Assignment 1.

(By Monu(t18002))

Q1.
Answer. `timescale 1ns / 1ps
module fab_series(clk,x3,rst);
input clk;
input rst;
output reg[5:0]x3;
reg [5:0]x1;
reg [5:0]x2;
parameter n=28;
always @(rst)
begin
if(rst==1)
begin
x2=1;
x1=0;
end
end
always @(posedge clk)
begin
if(x1<=28)
begin
x3=x2+x1;
x1<=x3;
x2=x1;
end
else
x2=x2;
end
endmodule

`timescale 1ns / 1ps

module series_test;
reg clk;
reg rst;
wire [5:0]x3;
fab_series DUT(clk,x3,rst);
initial
begin
clk=0;
rst=1;
end
always #50 clk=~clk;
endmodule
Assignment 1.(By Monu(t18002))

b=6'b00000101;
end
endmodule

Q2.
Answer. `timescale 1ns / 1ps
module matrix_mult(a,b,c);
input [5:0]a;
input [5:0]b;
output [8:0]c;
reg[1:0] a1[0:2];
reg[2:0] b1[0:1];
reg[2:0] c1[0:2];
always @(a or b)
begin
{a1[0][0],a1[0][1],a1[1][0],a1[1][1],a1[2]
[0],a1[2][1]}=a;
{b1[0][0],b1[0][1],b1[0][2],b1[1][0],b1[1]
[1],b1[1][2]}=b;
c1[0][0]=(a1[0][0]*b1[0][0])+(a1[0][1]*b1[1] Q4.
[0]); Answer.
c1[0][1]=(a1[0][0]*b1[0][1])+(a1[0][1]*b1[1] timescale 1ns / 1ps
[1]); module vending(F,W,E,clk,R,C1,C2,C3);
c1[0][2]=(a1[0][0]*b1[0][2])+(a1[0][1]*b1[1] input [3:0]F,W,E;
[2]); input clk;
output reg [3:0]R,C1,C2,C3;
c1[1][0]=(a1[1][0]*b1[0][0])+(a1[1][1]*b1[1] reg [1:0]i;
[0]); reg [2:0]j;
c1[1][1]=(a1[1][0]*b1[0][1])+(a1[1][1]*b1[1] reg [2:0]k;
[1]); always @(F or W or E)
c1[1][2]=(a1[1][0]*b1[0][2])+(a1[1][1]*b1[1] begin
[2]); C3=0;
C2=0;
c1[2][0]=(a1[2][0]*b1[0][0])+(a1[2][1]*b1[1] end
[0]); always @(posedge clk)
c1[2][1]=(a1[2][0]*b1[0][1])+(a1[2][1]*b1[1] begin
[1]); if(F[0]+F[1]+F[2]+F[3]==1)
c1[2][2]=(a1[2][0]*b1[0][2])+(a1[2][1]*b1[1] i=1; // one 50 rupee note.
[2]); else if(F[0]+F[1]+F[2]+F[3]==2)
end i=2; // two 50 rupees notes.
assign c={c1[0][0],c1[0][1],c1[0][2],c1[1] else
[0],c1[1][1],c1[1][2],c1[2][0],c1[2][1],c1[2] i=0;
[2]};
endmodule if(W[0]+W[1]+W[2]+F[3]==1)
j=1; // one 20 rupee note.
Testbench. `timescale 1ns / 1ps else if(W[0]+W[1]+W[2]+F[3]==2)
module matrix_mult_test; j=2; // two 20 rupees notes.
reg [5:0]a,b; else if(W[0]+W[1]+W[2]+F[3]==3)
wire [8:0]c; j=3; // three 20 rupees notes.
matrix_mult DUT(a,b,c); else if(W[0]+W[1]+W[2]+F[3]==4)
initial j=4; // four 20 rupees notes.
begin else
a=6'b00000101; j=0;
Assignment 1.(By Monu(t18002))

wire [3:0]R,C1,C2,C3;
if(E[0]+E[1]+E[2]+E[3]==1) vending DUT(F,W,E,clk,R,C1,C2,C3);
k=1; // one 10 rupee initial
note. begin
else if(E[0]+E[1]+E[2]+E[3]==2) clk=0;
k=2; // two 10 rupee F[0]=0; F[1]=1; F[2]=0; F[3]=0; W[0]=0;
note. W[1]=0; W[2]=0; W[3]=0; E[0]=0; E[1]=0;
else if(E[0]+E[1]+E[2]+E[3]==3) E[2]=0; E[3]=0;
#50 F={F[3],F[2],F[1],F[0]};
k=3; // three 10 rupee #60 W={W[3],W[2],W[1],W[0]}; W[2]=1;
note. #50 E={E[3],E[2],E[1],E[0]}; E[1]=1; E[2]=1;
else if(E[0]+E[1]+E[2]+E[3]==4) E[3]=1;
k=4; // four 10 rupee end
note. always #50 clk=~clk;
else endmodule
k=0;

if(i+j+k>1);
begin
if(i==2)
begin
C1=0;
R=1; Q.5
end Answer.
else if(i+j+k==4) module summation(clk,a0,a1,a2,a3,an,x,c);
begin output reg [7:0]c;
C1=0; input clk;
R=1; input [2:0]a0,a1,a2,a3,an;
end input [2:0]x;
else if(i+j+k==5) always @(posedge clk)
begin begin
C1=0; c= (a0*x**0)+(a1*x**1)+(a2*x**2)+
R=1; (a3*x**3)+(an*x**4);
end end
else if(i+j==4) endmodule
begin
C1=1; Testbench:
R=1; module summation_test;
end reg [2:0]a0,a1,a2,a3,an,x;
else if(j+k==6) reg clk;
begin wire [7:0]c;
C1=0; summation DUT(clk,a0,a1,a2,a3,an,x,c);
R=1; integer i;
end initial
else begin
begin clk=0;
C1=3'bx; for(i=0; i<=2; i=i+1)
R=0; begin
end #200 a0=i; a1=i; a2=i; a3=i; an=i; x=i;
end end
end end
TESTBENCH: always #100 clk=~clk;
module vending_testbench; endmodule
reg [3:0]F,W,E;
reg clk;
Assignment 1.(By Monu(t18002))

Q.6
Answer.
module polynomial(clk,a0,a1,a2,a3,an,x,c);
output reg [7:0]c;
input clk;
input [2:0]a0,a1,a2,a3,an;
input [2:0]x;
always @(posedge clk)
begin
c= ((((an*x)+a3)*x+a2)*x+a1)*x+a0;
end
endmodule

Testbench:
module polynomial_test;
reg [2:0]a0,a1,a2,a3,an,x;
reg clk;
wire [7:0]c;
polynomial DUT(clk,a0,a1,a2,a3,an,x,c);
integer i;
initial
begin
clk=0;
for(i=0; i<=2; i=i+1)
begin
#200 a0=i; a1=i; a2=i; a3=i; an=i; x=i;
end
end
always #100 clk=~clk;
endmodule