Author: Ramesh Kankanala very low voltages are required. In the Intermediate Bus
Microchip Technology Inc. Architecture (IBA), the IBC generates 12V/5V. Further,
these voltages are stepped down to the required load
voltages by Point of Loads (PoLs).
Isolation Barrier
Load
DC/DC Brick 3.3 VDC
Converter
Load
Load
24V/48V Bus DC/DC Brick 2.5 VDC
AC/DC Power
Supply Converter
Load
Load
DC/DC Brick 1.8 VDC
Converter
Load
1.3 VDC
PoL Load
1.8 VDC
PoL Load
1.0 VDC
PoL Load
0.8 VDC
PoL Load
TOPOLOGY SELECTION
VIN  VOUT
The bus converter specifications are standardized, and
are used or assembled as one of the components in the
final system. The user must consider the endsystem Isolated Forward Converter
characteristics such as reliability, efficiency, foot prints
and cost. There is no universally accepted topology for In the Forward Converter, the energy from the input to
the bus converters. However, the following sections the output is transferred when the switch Q1 is ON.
describe a few topologies that are commonly used for During this time, diode D1 is forward biased and diode
DC/DC converter applications with their pros and cons. D2 is reverse biased. The power flow is from D1 and L1
to output. During the switch Q1 OFF time, the
A fundamental distinction among the PWM switching transformer (T1) primary voltages reverse its polarity
topologies is hard switching and soft switching/ due to change in primary current. This also forces the
resonant topologies. Typically, high frequency secondary of T1 to reverse polarity. Now, the secondary
switching power converters reduce the size and weight diode, D2 is forward biased and freewheels the energy
of the converter by using small magnetics and filters. stored in the inductor during switch Q1 ON time. This
This in turn increases the power density of the simple topology can be used for power levels of 100W.
converter. However, high frequency switching causes Some of the commonly used variations in Forward
Q1
VOUT
FullBridge Converter
VIN
The FullBridge Converter is configured using the four
switches: Q1, Q2, Q3 and Q4. The diagonal switches
PushPull Converter Q1, Q4 and Q2, Q3 are switched ON simultaneously.
This provides full input voltage (VIN) across the primary
The PushPull Converter is a two transistor topology winding of the transformer. During each half cycle of
that uses a tapped primary on the converter the converter, the diagonal switches Q1, Q4 and Q2,
transformer T1. The switches Q1 and Q2 conduct their Q3 are turned ON, and the polarity of the transformer
respective duty cycles and the current in the primary reverses in each half cycle. In the FullBridge
changes, resulting in a bipolar secondary current Converter, at a given power compared to the Half
waveform. This converter is preferred in low input Bridge Converter, the switch current and primary
voltage applications because the voltage stress is twice current will be half. This makes the FullBridge
the input voltage due to the tapped primary Converter suitable for highpower levels.
transformer.
FIGURE 8: FULLBRIDGE CONVERTER
FIGURE 6: PUSHPULL CONVERTER
VIN +
Q1 D1 L1 VOUT +
T1 L1 Q1 Q3
D1 VOUT +
T1
 + C1
VIN
C1
Q2 Q4
VOUT 
VOUT 
D2 D2
VIN 
Q2
TXVPRI
t
PWM
PWML PWML
t PWMH
Q2 Q4 Q5
Synchronous Rectification
This configuration involves complexity and cost to an
In synchronous rectification, the secondary diodes, D1 extent because a gate drive circuit is required to control
and D2 are replaced with MOSFETs. This yields lower the synchronous MOSFET. The efficiency of this
rectification losses because a MOSFET will have configuration can be further increased by designing the
minimum DC losses compared to the Schottky complex gate drive signals, which are discussed in the
rectifiers. The forward DC losses of a Schottky rectifier section “Digital Nonlinear Implementations”.
diode will be forward voltage drop multiplied by the
forward current. The power dissipation by a conducting Many topologies are available and one of them can be
MOSFET will be RDS(ON) multiplied by the square of chosen depending on the given power level, efficiency
the forward current. The loss comparison will be of the converter, input voltage variations, output voltage
significant at considerably higher current >15A and levels, availability of the components, cost, reliability of
lower output voltages. the design, and good performance characteristics.
This application note discusses the design
considerations of FullBridge topology for Quarter Brick
DC/DC converter design.
VIN + VOUT +
VIN  VOUT 
Driver
Current TX
Drive TX Driver
dsPIC®
DSC
Drive TX Driver
Communication
Remote Control
OPTO
VINOV
VINUV 3.3V Reg
3.8V
NCP 1031 Auxiliary TX
12V To Driver’s VCC
VOUT+
VIN+
VIN
VOUT 
Current TX
Driver1 Driver2
OPTO
Communication
Q1 Q3
Q6
PWMH PWML
TX
PWML
Q2 Q4
Q5
PWMH
PWML PWMH
Q1
Q2
Q3
Q4
VPRI
IPRI
Q5
Q6
T1 T2 T3
T0
D
I SRMS = I MAX ×  = 4.53A where:
2
For all four FullBridge MOSFETs = 0.504W
Because the maximum input voltage is 76 VDC, select Bias voltage to the gate drive, VDD = 12V
a MOSFET voltage rating that is higher than 76V and MOSFET total gate charge, QG = 70 ns
the current rating higher than IMAX at 36 VDC.
The device selected is Renesas HAT2173 (LFPAK),
and has VDS 100V, ID 25A, RDS(ON) 0.015E.
14.90 mm
(0.59'')
• VIN = 36V Champs Technologies
• Frequency = 150 kHz MCHP045V311
• TP = 6.667 x 106
The intended output voltage was meant to supply a
typical bus voltage for distributed power applications
and the output voltage. VO = 12.00V and the maximum
output load current, IO = 25A 16.90''
(0.67 mm)
No substitute exists for the necessary work to perform
calculations sufficient to evaluate a particular core size, 9.80 mm (0.39'')
turns, and core and copper losses. These must be
5.90 mm
iterated for each design. One of the design
(0.23'')
considerations is to maximize the duty cycle, but the
limitation of resolution offered by integer turns will
quickly lead to the turn ratio of NP = 5 and NS = 2.
In the design of the magnetics, users must select the
minimum number of turns. There is a cost or penalty to
placing realworld turns on a magnetic structure such This core shape is a tooled core and is available from
as, resistance, voltage drop and power loss. Therefore, Champs Technologies. In general, a power material in
use the least number of integer turns possible. the frequency range of interest must be considered.
Thereafter, a reasonable assessment for turn ratio, Materials such as 2M, 3H from Nicera™, the PC95
duty cycle, peak flux density, and core loss can be done from TDK™, or the 3C96, 3C95 from Ferroxcube™ are
until a satisfactory point is reached for the designer. the most recommended options. The peaktopeak and
The duty cycle (more than each halfperiod) to produce rms flux densities arising from this core choice are
the desired output is as follows: shown in Equation 10.
• TON = 2.89 µs
EQUATION 10:
• D = TON/TP = 0.434
8
Over a full period, the duty cycle is 86.8% at a VIN of ( V IN × t ON ) × 10
B PKPK = 

36 VDC. NP × AC
In this design, the following regulation drops are used: 3
B PKPK = 4.624 × 10 Gauss
• Secondary MOSFET drop, VFETSEC = 0.1V
• Total trace drops, VDROP = 0.2V t ON
8 2
2 ( V IN × t ON ) × 10
• Primary MOSFET drop, VFETPRI = 0.6V B RMS = 
TP
× ∫ 
2 × NP × AC
 dT
O
EQUATION 9: 3
B RMS = 2.153 × 10 Gauss
NS
VO = ( V IN – V FETPRI ) ×  – V FETSEC – V DROP × 2D
NP
= 12.03V
Core loss density can be approximated by the formula EQUATION 12: SECONDARY RMS
shown in Equation 11. The core constants are made CURRENT
available by Ferroxcube™. In this design:
I SEC = I O × D
• Temp = 50oC
• Frequency = 150000 Hz I SEC = 16.47A
• B = Brms * 104 = 0.2153 Tesla
• x =1.72 Primary rms current is calculated as shown in
• y = 2.80 Equation 13:
• Ct2 = 1.83 * 104
• Ct1 = 3.66 * 102 EQUATION 13: PRIMARY RMS CURRENT
• Ct0 = 2.83 NS
I PRI = I O × 2D × 
• Cm = 8.27 * 102 NP
I PRI = 9.317A
EQUATION 11: CORE LOSS DENSITY
The DCR values are computed from the CAD
Core Loss Density Pcore
drawings:
2
C m × Freq × B × ⎛ C t0 – C t1 × Temp + C t2 × Temp ⎞
x y
⎝ ⎠ • Secondary DCR: SecDCR = 0.0023E
= 
1000 • Primary DCR: PriDCR = 0.025E
3
P = 1.307 × 10 mW/Cm3 Secondary copper loss is multiplied by two because it
–3 is a center tapped winding.
CoreLoss = P × V E × 10
FIGURE 17: FULLBRIDGE CONVERTER WITH CENTER TAPPED FULL WAVE SYNCHRONOUS
RECTIFIER
Q1 Q3
TX Q6
LL
VPK2
IPRI L0
VPRI
C0 V0
Q2 Q4
Q5
12.00 mm
Champs Technologies
(0.47'')
MCHP1825V311
EQUATION 15:
N
S
V = (V –V ) ×  – V –V × 2D
O IN FETPRI N FETSEC DROP
P
15.0 mm
V O = 12.03V (0.59'')
9.80 mm (0.39'')
inductance value at the maximum off time. This occurs
5.40 mm
(0.21'')
in PWM regulated DC/DC converters at the maximum
input voltage, VINMAX = 76V, and the feedback loop
adjusts the switch ON time accordingly.
TONMIN = 1.415 µs
The duty cycle is as follows:
D_MIN = TONMIN/TP = 1.3689 µs This core is also a tooled core as the main
The peak voltage at the transformer secondary is as transformer, TX1. It is available from Champs
shown in Equation 16. Technologies as PN MCHP1825V311. Materials such
as 7H from Nicera™, the PC95 from TDK™, or the
3C94, 3C92 from Ferroxcube™ are the recommended
EQUATION 16:
choices.
NS • Core cross section, AC = 0.4 cm2
V PK2 = ( V INMAX – V FETPRI ) ×  – V FETSEC – V DROP
NP • Core path length, LCORE = 3.09 cm
V PK2 = 28.26V • Rated output current: IRATED = 17A
• Defined saturation current: ISAT = 20A
The process of inductor design involves iterating the
Maximum output load current, IO = 25A. A ripple cur number of turns possible and solving for a core air gap.
rent of 25% of the total output current is considered in The air gap is checked for operating the flux below
this design. maximum rated flux in the core material at the two
operating current values that is rated current and
EQUATION 17: saturation current.
In this design, if the 18 layers are available, these
I MIN = I O × 0.25 = 6.5A layers can be split into balanced integer turns. This is a
practical method and the number of turns, Nt = 6.
In this design, a fringing flux factor assumption of 15%
EQUATION 18: OUTPUT INDUCTANCE is done, which is FFF = 1.15.
(LOMIN)
The iterative process begins by calculating the air gap
equation. The air gap is calculated using Equation 19.
( V PK2 – V O ) × T ONMIN
L OMIN = 
 = 3.54μH EQUATION 19:
I MIN
2 –8
⎛ 0.4 × π × Nt × A C × 10 ⎞
L GAP = ⎜ ⎟ × FFF
In this design, the core window height and its adequacy ⎝ L OMIN ⎠
in terms of accommodating the 18 layer PCB stack is to = 0.058cm
be assessed since the windings/turns for the inductor
are also embedded. L GAP
L GAPIN = 
 = 0.023inch
2.54
V IN × T ON
The peak flux density is shown in Equation 27, which di = 

yields a voltµs rating of (VIN * TON) = 37.7. This is well LM
below the typical saturation curves for 3F3 of 3000 di = 0.362A
Gauss at 85ºC operational ambient temperature.
However, potential saturation is not a design concern.
Assuming the worst case, the distributed capacitance
is taken is as follows: CD = 50 * 1012 Farad.
EQUATION 27: PEAK FLUX DENSITY
Any ringing on the gate drive waveforms due to the
8
( V IN × T ON ) × 10 transformer will possess a frequency of 2.3 MHz.
B PK = 

2 × NP × AC
EQUATION 31:
3
B PK = 1.534 × 10 Gauss
1
F R = 

2 × π × ( LM × CD )
The rms flux density is calculated, as shown in
Equation 28. F R = 2.3MHz
3
B RMS = 1.363 × 10 Gauss
I MAX
Current Sense Transformer Design V PKSECY =  × R B
NS
The current sense transformer selected is a V PKSECY = 1V
conventional standalone magnetic device. The
decision was made earlier to have a 1:100 current
transformation ratio. Therefore, it is difficult to Therefore, the rating is 0.1 V/amp.
implement this device as an embedded structure.
We repeat some aspects of the TX1 main transformer EQUATION 36:
design such as switching frequency.
8
( V PKSECY × T ON ) × 10
B PK = 
EQUATION 32: NS × AC
F SW = 150 × 10 HZ
3 B PK = 109.886Gauss
EQUATION 39:
x y 2
C m × F × ( B RMS ) × ( C t0 – Ct1 × Temp + C t2 × Temp )
CoreLossDensity, P = 

1000
3
P = 0.048 mW/cm
–6
CoreLoss = 1.592 × 10 W
5.3 mm
(0.21'')
3
= 0.173W 7 + 8
4.9 mm
(0.19'')
0.25 mm
Priloss = Primary copper losses (0.010'')
PriDCR = 0.002E
SecDCR = 6.6E
EQUATION 41:
2 –9
L AL = ( N S ) × A L × 10
–3
L AL = 3 × 10 ~ 3mH
0.006 0.15
where:
Ns = 100 6.8 mm
(0.27'')
AL = 300 nH
X EFF = 9.953E
EQUATION 44: The turns ratio for 12V and 3.3V output is shown in
Equation 50.
3
F SW = 250 × 10 Hz
EQUATION 50:
N P [ V IN – ( I PPK × R DS ( ON ) ) ] × D
 ≥ 
Total period, TP = 4 µs NS ( V OUT + V fD1 ) × ( 0.8 – D )
On period, TON = 1.6 µs
NP
 = 2.60

EQUATION 45: N S12
InputPower NP
AverageCurrent, I AVE = 
  = 7.828

MinimumInputVoltage N S 3.3
7.5W where:
=  = 0.234A
32V Voltage drop on the diode, VFD1 = 0.7V
Peak current of a Discontinuous mode Flyback RDS(ON) = 4E
Converter, IPPK, is shown in Equation 46.
A quick check of the available standard core structures
EQUATION 46: indicates that there was a distinct possibility to use a
standard size RM4 core.
I AVE An important feature of this core for this design is, it
I PPK = 2 ×  = 1.17A consists of a core window with nominal 4.3 mm that clears
D
the 4.0 mm PCB thickness. The overall height of this core
is 7.8 mm, so its height is < 10 mm of the DC/DC
Primary rms current, IrmsPRIM is shown in Equation 47: Converter mechanical height.
EQUATION 48:
V INMIN × D
PrimaryInduc tan ceL P = 

F SW × I PPK
32 × 0.4
=  = 43.6μH
250000 × 1.17
A L = 164.063nH
1 2 5
6
EQUATION 54:
7
0.4 × π × N PRI × I PPK
B PK = 

4 L GAP
8
3
3
B PK = 1.959 × 10 Gauss
Inner Layer Top Points
where:
The rms flux density is calculated, as shown in
BMAX = 2200Gauss
Equation 57.
The required center post air gap based on the formula
is shown in Equation 52:
EQUATION 57:
T ON
EQUATION 52: 8 2
1 ( V IN × T ON ) × 10
0.4 × π × ( N PRI ) × A E × 10
2 –8 B RMS = 
TP
× ∫ 
2 × N PRI × A E
 dTp
L GAP =  × FFF O
LP
B RMS = 771.454Gauss
L GAP = 0.012cm
The core loss equation parameters are used for
L GAP Ferroxcube “3C92” material at 40ºC rise in
L GAPIN = 

2.54 temperature.
–3
L GAPIN = 4.591 × 10 in
CoreLoss = 0.076W
EQUATION 61:
2 2
CopperLoss = ( I rmsPRI × DCR PRI ) + ( I rmsSEC × DCR SEC )
CopperLoss = 0.067W
All the real world feedback signals are continuous The conversion speed plays an important role to
signals, and should be digitized to process in the DSC. replicate the sampled signal. As per Nyquist criterion,
A builtin ADC performs this process. The ADC the sampling frequency must be greater than twice the
bandwidth of the input signal (Nyquist frequency). As a
requires a voltage signal that is to be provided as an
guideline in SMPS applications, sampling of the analog
input. The input signals are scaled down to the ADC
signal at a frequency greater than 10x of the signal
reference voltage. These voltages are typically 3.3V
bandwidth is required to maintain fidelity.
and 5V.
FullBridge Converter
+
Input Voltage
Output Voltage
Synchronous Rectifier
36V DC– 75V DC
+
CT
12V DC/ 7A
 
Drive TX
Drive IC
Drive IC
Drive TX
Drive IC
Opto
Remote ON/OFF RB5 dsPIC33FJ16GS502
Isolator
Ext Communication
DCR Compensation
VO* IL *
+ VERROR + + VO
PI Control P Control Phase/Duty Plant
 
+
VO IL
VO Decouple
Compensation
ITX
ADC Sensor
ADC Sensor
Digital Signal Controller (DSC)
IL
D * VIN VL
LM DCR
VX
Buck Inductor
ESR
IC IO
Output
VIN VO Load
Capacitor
Based on Figure 25, and applying Kirchhoff's laws The current reference (IL*) is generated using the outer
results in the expressions and equations shown in voltage loop.
Equation 67. [IL* = (VO*  VO) * G] (because current loop performs the
function of differential gain in the voltage loop, the outer
EQUATION 67: voltage loop will have only proportional and integral
gain).
(A) IC = IL – IO From the physical capacitor system, IC = IL  IO. In the
equation, IO is made as constant and analyzed the
(B) V O = D × V IN – V L relation between VO and VO*. Therefore, IL = SCVO.
V VL VL V EQUATION 69:
(C) I L = L =   = L
 = 
XL 2πfL JωL sL K
(F) ( I L )∗ = ( V O∗ – V O ) × ⎛ K P + I⎞
Ic IC IC ⎝ s⎠
(D) V O = I C × X c =  = 
 = 

2πfC JωC sC
( Ra + sL ) KI
I L ×  = [ ( V O∗ ) – V O ] × K P + ⎛ ⎞
Ra ⎝ s⎠
The current compensator proportional gain is denoted
as RA, and it has a dimension of resistance. The value Equation 69 is rearranged to find VO*/VO and the
of RA can be determined from the system characteristic results are shown in Equation 70.
equation. Higher value of RA implies higher current
loop bandwidth. With the current mode control, the ‘D’
EQUATION 70:
term performance in the voltage PID can be achieved.
Ki
EQUATION 68: ( K P × R A ) + ⎛  × R A⎞
VO ⎝s ⎠
 = 
VX = VO + VL VO ∗ KI
s LC + ( sC × R A ) + ( K P × R A ) + ⎛ ⎞ × R A
2
⎝ s⎠
V X = V O + sLI L = R A × [ ( I L∗ ) – I L ] + [ V X – sLI L ]
(E) [ R A × ( I L∗ ) ]
I L = 
R A + sL
Because ‘s’ is 2πf1(ω1), 2πf2 (ω2) and 2πf3 (ω3), • VINS = VIN/turns ratio = 30.4V
which are the roots of the characteristic equation and • Output inductor L = 3.4e6 Henry
should make the equation equal to zero after • DC resistance of the inductor and tracks is
substituting for ‘s’. The three unknown coefficients KP, considered as DCR = 0.05E
KI and RA can be obtained by solving the following • Output capacitance, C = 4576e6F (4400 µF
three equations shown in Equation 71: external to converter)
• Equivalent series resistance of the capacitor,
ESR = 0.0012E
EQUATION 71:
• Switching frequency of the converter,
2 3
ω1 CR A + ω1 K P R A + K I R A = – ω1 LC FSW = 150000 Hz
• Control loop frequency TS is 1/2 of the FSW that is:
2 3
ω2 CR A + ω2 K P R A + K I R A = – ω2 LC 1 
T S = 
2 3 F SW ⁄ 2
ω3 CR A + ω3 K P R A + K I R A = – ω3 LC
• Integral voltage BW, f3 = 1000 * 2 * π
These coefficients can be solved by using the matrix • Proportional voltage BW, f2 = 2000 * 2 * π
method shown in Equation 72 and is made equivalent • Proportional current loop BW, f1 = 4000 * 2 * π
to A * Y = B for simplicity purposes. The characteristic equation is solved using the above
three bandwidths.
EQUATION 72:
• RA = 0.1495
ω1
2
ω1 1 – ω1 LC
3 • KP = 57.5037
CRa
• KI = 2.0646e + 005
ω2 1 × K P R A = – ω2 LC
2 3
ω2
2 KI RA 3
ω3 ω3 1 – ω3 LC
+
+ VERROR IREF (IL*) + IERROR VX
VL
Compensator Compensator Phase/Duty
+
VO*  
+ VO
IL
VO
FIGURE 27: SINGLE WIRE LOAD SHARE COMPENSATOR DESIGN BLOCK DIAGRAM
Outer Voltage Loop Compensator Inner Current Loop Compensator (IL * DCR)
VERROR
+ IREF(IL*) + IERROR VL + VX
Compensator Compensator Phase/Duty
+ +
VO*  
IL1 +
VO VO
(IL1 + IL2)/2
Load Share
Outer Voltage Loop Compensator
Inner Current Loop Compensator
(IL * DCR)
+ IL2 +
+ V ERROR I REF(I L*) +  IERROR VL Vx
Compensator Compensator Phase/Duty
VO * +
 +
VO
VO
ZeroOrder
Quantizer2 Hold2
Quantizer1 ZeroOrder
Hold1
VO
IL
Phifactor Phifactor
12 VO* LC Voltage 1
VIN_PHIFACTOR
VIN
VO * IL1 IL1
Control System VIN
VO1
ZVT Modulation VO2
L1 iLoad
13.6
Scope1
C
VIN
Pulse Generator
Variables_FB.h
ISHARE
IO
Reset Soft Start
Load Sharing
PI Controller
Voltage PI
Controller
PWM Duty
Current
P
Controller IREF VDC 12V
IO
Q1 Q3
Q6
TX
LO
TXVPRI
Q2 Q4
CO
Q5
Q1
Q2
Q3
Q4
VPRI
Q5
Q6
Zero States
Note: In Zero States Q5, Q6 MOSFETs freewheeling body diodes will be conducting. The forward drop
of body diode will be much higher than the MOSFET RDS(ON).
Q1 Q3
Q6
TX
L LO
TXVPRI
Q2 Q4
CO
Q5
Q1
Q2
Q3
Q4
TXVPRI
Q5
Q6
Zero States
FIGURE 50: REMOTE ON/OFF, OUTPUT VOLTAGE RISE TIME: 17A AT 53V
FIGURE B1: FullBridge Quarter Brick DC/DC Converter Board Layout (Bottom View)
DT1
Main Transformer (TX1)
Output Inductor (L2)
VIN +ve
VO +ve
Q2
Q5
Remote ON/OFF
U5
VO ve
VIN ve
AN1369
DT2
DS01369Apage 67
3.3V Regulator (U8) dsPIC33FJ16GS502 (U1) Auxiliary Transformer (TX3) U7 Auxiliary Controller (U9)
Q6
Note: This view lists a few key components. Refer to the Bottom Silk drawing in Figure B2, which lists all board components.
FIGURE B2: FB Quarter Brick DC/DC Converter Board Layout (Bottom Silk)
DS01369Apage 68
AN1369
C47
Q1
C10
C11
R5 R1
C7 Q5 C1
Q6
D1
C9
Q2
R41 R33 D25
R35
R44
R46
C21 R80 C14 C28
R81
U5 C46 D2
R2
C19 R31 D18 U7 C31
R6 R62
R54 R55
C48
C22
C30 C32
C39
R73
R58
C13 R34
C20
L4
U1 U9 C36 R59
© 2011 Microchip Technology Inc.
C29 L3 R43
C23
C41 R57
C26 C37
C3 R40
R47
C40
C33
C27 D16 R61
C25 D15 R66
R48 U8 C24
FIGURE B3: FB Quarter Brick DC/DC Converter Board Layout (Top View)
© 2011 Microchip Technology Inc.
DT1
Q4
J4
TX2
U4
DT2
U6
AN1369
DS01369Apage 69
J1
TX3 U3 U2
Note: This view lists a few key components. Refer to the Top Silk drawing in Figure B4, which lists all board components.
FIGURE B4: FB Quarter Brick DC/DC Converter Board Layout (Top Silk)
DS01369Apage 70
AN1369
C4
Q3
M
C5
C6
C2 Q4 R7
R3 Q13 C8
Q14 R11
D3 J4
R10
D27
D28
R8 R4
R13
R39 R52 R50
D8 D7 R49
TX2 C42 R12
R51
D4 C44 R26
C18
R22 U4
D26 U3 U2
R28
D17
C17
C15 R36
R21 C43
R19
© 2011 Microchip Technology Inc.
R20
R23 R69
C33
C16
C45
C34 R17 U6 R64
R56 R16
R18
R65
D14
C12
R15 R14 R66 C38 R63 R68
J1
FIGURE B5: FB Quarter Brick DC/DC Converter Board Dimensions
© 2011 Microchip Technology Inc.
VO+
VIN+
ON/OFF
VIN
VO
AN1369
DS01369Apage 71
FIGURE B6: FB Quarter Brick DC/DC Converter Schematic (Sheet 1 of 4)
DS01369Apage 72
AN1369
+12V
ANA_GND
U2
1 8 C42 .1uF DT1
Vdd Vdd
PWM1H 2 IN OUT 7 1 5
3 N/C OUT 6
R26 4 GND GND 5
10K +12V
TC4422ASOIC 4 6 S1
7
GATE4
R39
ANA_GND
8 10
ANA_GND
U4
1 NC NC1 8
PWM3H 2 IN/A OUT/A 7 GATE5
3 GND VDD 6
PWM3L 4 IN/B OUT/B 5 GATE6
SECY side Components. Require 2250Vdc Isolation. R34
R36 MCP1404SO8
10K
10K
C18
2.2uF
+12V ANA_GND
R28 10 C17 2.2uF
ANA_GND
GATE3
U3
1 8 C44 .1uF DT2
Vdd Vdd
PWM1L 2 IN OUT 7 1 5
3 N/C OUT 6
4 GND GND 5
R31
10K TC4422ASOIC 4 6 S3
7 GATE2
© 2011 Microchip Technology Inc.
ANA_GND 8 U5 +3.3V_ANA
ANA_GND
1 NC NC1 5
2 VSS
TEMP 3 VOUT VDD 4
MCP9700SC70 C19
2.2uF
ANA_GND
SECY side Components. Require 2250Vdc Isolation. ANA_GND
FIGURE B7: FB Quarter Brick DC/DC Converter Schematic (Sheet 2 of 4)
© 2011 Microchip Technology Inc.
Pin #1
Q5
INPUT VOLTAGE+ Q1 Q3
HAT2173H
5
HAT2173H HAT2173H TX1 R10 4.7
5
C49 .1uF C50 .1uF 1 7 4 GATE6
4 4
Q13 R11
3
2
1
5
R5 5 CT
1
2
3
1
2
3
10K D29 R7 D30 4 10K
R1 BAT54
R3
10K BAT54
Pin #6
10.0 10.0 9 HAT2173H
S1
3
2
1
S3 VO+
GATE3
GATE1 C4 C5 C6 C7 C8 C9 C10 C11
C1 C2 L2a 3.5uH
11 2uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
2.2uF 2.2uF
VAux
Q2 Q4
D18 eSMP
Pin #5 VO
8
HAT2173H HAT2173H TX2 L2b
5
5
C51 .1uF C52 .1uF C45 R73
4 4 47uF 0.0
R4
1
R2 R6 R8
1
2
3
1
2
3
10.0 D32 D31
10K 10.0
BAT54 10K BAT54 ANA_GND DIG_GND
INPUT VOLTAGE GATE4 R13
GATE2 Q14
3
2
1
Q6 10k R12 4.7
3
2
1
4 GATE5
4
Pin #4
5
HAT2173H
5
C46 470pF
HAT2173H
R80 150K
Pin #2 CT
Remote ON/OFF R81 4.99K
D7 3 3 D8 DIG_GND
BAS40 BAS40
C13 VSecy
8
R69 MCP6022TSSOP 5 MCP6022TSSOP
+
7 3 R20 47
LOAD SHARE 100 +
6 1 TX CURRENT
C43 47  R68 R18
R14 2 C14
.1uF 2K C12 2K  R21
C38
4
.1uF 4.7K
4
470pF 11.3 470pF
ANA_GND TX OVER CURRENT
ANA_GND ANA_GND ANA_GND ANA_GND
R22 C15
ANA_GND
R64 R65 4.7K 470pF
AN1369
ANA_GND
ANA_GND
DS01369Apage 73
ANA_GND
FIGURE B8: FB Quarter Brick DC/DC Converter Schematic (Sheet 3 of 4)
DS01369Apage 74
AN1369
+3.3V_DIG MCLR
R33 10 R48 4.7K J1
1
VO+ REMOTE+ MCLR
R44 2
Vdd
5.23K C22 2.2uF
C26 3
+3.3V_ANA Vss
.1uF
OUTPUT FEEDBACK 4
C48 PGD2 PGD
ANA_GND 5
R46 C21 DIG_GND
2200pF 2200pF PGC2 PGC
1.5K
6
N/C
REMOTE VO MCLR PWM1L
ICSP_6_HDR
R35 10 TX CURRENT PWM1H
28
27
26
25
24
23
22
OUTPUT FEEDBACK
U1
PWM1L
MCLR
AVss
PWM1H
AN1
AN0
AVdd
VO+
LOAD SHARE 1 AN2 PWM2L 21
R41 2 20
VSecy AN3 PWM2H
7.5K OUTPUT OVER VOLTAGE 3 CMP2C PWM3L 19 PWM3L
TEMP 4 RP10 PWM3H 18 PWM3H
5 Vss Vcap 17
OUTPUT OVER VOLTAGE TX OVER CURRENT 6 CMP4a Vss 16
EXTSYNCI1 7 RP2 SDA1 15
PGD2
PGC2
R43 C20
RB15
SCL1
GND
RB8
RB5
Vdd
1K 470pF C23
2.2uF
DSPIC33FJ16GS502QFN28
8
9
10
11
12
13
14
29
DIG_GND
C24
2.2uF
R49 R50
DIG_GND 4.99K
4.99K
COM3
J4.1
R51 220
COM1 14 15 COM2
EXTSYNCI1 12 13 DIG_GND
COM4 10 11
R52 220
LOAD SHARE 8 9 N/C
REMOTE ON/OFFI/P
REMOTE+ 6 7 REMOTE
© 2011 Microchip Technology Inc.
R62 +3.3V_ANA
1.6K
1
U7
2801
REMOTE ON/OFF
2
R47 C25
470pF
6.8K
DIG_GND
PRI side Components. DIG_GND
Require 2250Vdc Isolation.
FIGURE B9: FB Quarter Brick DC/DC Converter Schematic (Sheet 4 of 4)
© 2011 Microchip Technology Inc.
VAux
+12V
D15
L4
TX3 XPL2010
2 5 C41 C30
eSMP 47uF 47uF
INPUT VOLTAGE +
1 6 ANA_GND
3 7
R53 C33 R56
2200pF 1K +3.3V_DIG +3.3V_ANA
1Meg D14 U8 LP3961LLP6
4 8 L3
2
2 VIN VOUT 1
C3
7 GND1
D17 eSMP 3 XPL2010
4 GND
VOUTSEN
MURA110 15uF 6 VEN BYPASS 5
C40 15uF C39 C28
C29
D16
1
R57 47
10000pF 15uF
2 1 15uF
BAT54XV
C31 R54 DIG_GND ANA_GND
10000pF 45.3K R58 10 R59 4.7K R60 1.43K
8 VDRAIN VSS 1
7 2 +3.3V_ANA
VCC CT
6 UV FB 3
5 OV COMP 4
INPUT VOLTAGE 
AN1369
DS01369Apage 75
AN1369
TABLE B1: FB Quarter Brick DC/DC Converter Pin Out Details
Pin Number Pin Designation Function
1 VIN+ Input Voltage Plus
2 Remote Remote ON/OFF
ON/OFF
3 VIN Input Voltage Minus
4 V0 Output Voltage Minus
5 V0+ Output Voltage Plus
J46 Remote+ Remote Sense Plus
J47 Remote Remote Sense Minus
J48 Load Share Single Wire Load Share
J49 NC Not Connected
J410 COM 4 Serial Clock Input/Output
J411 COM 3 Serial Data Input/Output
J412 EXTSYNCI 1 External Synchronization Signal
J413 DIG_GND Digital Ground
J414 COM 1 PORTB  8
J415 COM 2 PORTB  15
J11 MCLR Master Clear
J12 +3.3V Supply
J13 DIG_GND Digital Ground
J14 PGD2 Data I/O Pin for Programming/Debugging
J15 PGC2 Clock Input Pin for Programming/Debugging
Red U1 Red
10
6
7
8
9
TP4 TP6
GND
MCLR
+3.3V
PGC
PGD
1 4
VI+ VO+
2.2 µF/100V P1
C2C7 Orange C8 C9 C11 C12 1
1
C1 DCDC C13 C14
C2 C3 C4 C5 C6 C7 TP5 2
P2 2 2200 µF 2200 µF 47 µF 100 µF 22 µF 22 µF
5
180 µF/100V ON/OFF
2 D1
1 1
LOADSHARE
EXTSYNCI1
3.3V
REMOTE+
J1 J2
REMOTE
2
COM1
COM2
COM3
COM4
3
GND
N/C
VI VO
5
TP3 TP7
11
12
13
14
15
16
17
18
19
20
Black Black
TP1 TP2 TP8 TP9
White White White White
Fan circuitry
U2
1
7 BST C17
VIN L1
LX
8 0.1 µF
R3 D2 220 µH
1M J6
C15 5 50SQ100 C16 1
ON/OFF
15 µF
68 µF R4 FB
4 2
SGND
Fan Header
GND
139K VD
2
C18
3
4
MAX5035
3
0.1 µF
J3 J5
Input Power Selection for Fan
1
MCLR J4 1
AN1369
1
Auxiliary Fan Input 2
VDD 2
DS01369Apage 77
2
J7 S1 3
VSS 3
1 3
1 4
3 PGD 4
4
5 5
PGC
2
2 6
4 N.C. 6
RJ11 PMBUS
FIGURE C2: BASE BOARD LAYOUT (TOP VIEW)
DS01369Apage 78
AN1369
R1 R5
C7 C8 C5 C4 C3 C2 D1 C10
C12 C14
D3 C18
U5
D5
C17
© 2011 Microchip Technology Inc.
R3 C19
R4
AN1369
BASE BOARD LAYOUT (BOTTOM VIEW)
FIGURE C3:
© 2011 Microchip Technology Inc. DS01369Apage 79
AN1369
C.1 Efficiency Improvement Proposals
The following proposals can be implemented to
improve the efficiency of the converter.
1. Improving the rise and fall times of the
MOSFETs.
2. Investigating the feasibility of using a single gate
drive transformer in the FullBridge reference
design.
3. Investigating the feasibility of using highside
and lowside drivers.
4. Using 3+3 synchronous MOSFETs in the
secondary rectifications.
5. Investigating the feasibility of using fractional
turns in the main transformer.
In the present design, some of the layers were made
using 2 oz. copper. As an improvement, these layers
could be made using 4 oz. copper.
FIGURE D2: FRONT VIEW OF THE QUARTER BRICK DC/DC CONVERTER REFERENCE DESIGN
Note: The check mark on the front of the enclosure identifies the reference design model.
FB = FullBridge Quarter Brick DC/DC Converter (to be discussed in a future application note)
PSFB = PhaseShifted FullBridge DC/DC Converter
FIGURE D3: LEFT SIDE VIEW OF THE FIGURE D4: RIGHT SIDE VIEW OF THE
QUARTER BRICK DC/DC QUARTER BRICK DC/DC
CONVERTER REFERENCE CONVERTER REFERENCE
DESIGN DESIGN
FIGURE D10: CONNECTING THE OSCILLOSCOPE PROBE FOR REMOTE ON/OFF TESTING
Use the following procedure to power up the reference Typically, the unit may enter into the
design. regulation range at around 35 VDC,
undervoltage lockout at approximately 33.5
1. Turn the DC source ON and measure the input VDC, and overvoltage lockout at
voltage with DMM, as illustrated in Figure D7. approximately 81 VDC.
This voltage should be in the range of 36 VDC 
76 VDC. Check to see that the fans are 2. No load power.
circulating air into the enclosure. a) Set the input voltage at 53 VDC and
2. Ensure that the connected DC load is in the disconnect or turn OFF the load from the
range of 0A17A. The output load current mea converter and record the input power.
surement resistor provides a value in the range This value will be the product of input
of 0 mV85 mV when measuring with DMM, as voltage and input current measured using
illustrated in Figure D6. the DMM illustrated in Figure D5 and
3. Ensure that the output voltage read by DMM Figure D7.
(see Figure D8) is in the range of 11.88 VDC to 3. Input power when remote ON/OFF is active.
12.12 VDC.
Remote ON/OFF will be used to turn OFF the
converter by applying a 3.3 VDC signal on the
D.6 Test Procedure pin illustrated in Figure D10. A high signal (3.3
The following two sections provide detailed procedures VDC) will turn OFF the converter and there is no
for each test. output. When a high signal is sensed by the
dsPIC DSC, all of the PWM generators are
D.6.1 INPUT CHARACTERISTICS shutdown. When the dsPIC DSC detects a low
remote ON/OFF signal, the converter will be
1. Input undervoltage/overvoltage.
turned ON.
The Quarter Brick DC/DC Converter is rated to
a) Turn ON the converter with 53 VDC input at
operate with regulation between the input
8.5A output load. Connect an oscilloscope
voltage ranges 36 VDC76 VDC. The converter
voltage probe to measure the output
features input undervoltage and overvoltage
voltage and a differential voltage probe to
protection. This feature will not allow the
measure the external 3.3 VDC supply, as
converter to startup unless the input voltage
illustrated in Figure D10.
exceeds the turnon voltage threshold and shuts
down the converter when the input voltage b) Turn ON the external 3.3 VDC supply and
exceeds the overvoltage threshold. the system will shut down (there will be no
voltage at the output of the converter).
Record the input voltage and input current
to calculate the input power.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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ISBN: 9781609328238
08/04/10
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