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Clocking
and the
Dynamic Discipline
D Q is like a toll-gate
Level-sensitive: if G is high then
G value of D flows through to Q
D Q is like a air-lock
Edge-triggered: Q value updated
on rising transition of clock.
No direct path from D to Q
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6004 Spring 1998: L10
Inputs Outputs
Acyclic
Combinational
Logic
Current Next
State State
Q1 D1
Q2 D2
Memory element:
CLK Latch or Flip-Flop
in every feedback loop
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6004 Spring 1998: L10
≥ ts Setup time = ts
≥ th Hold time = th
CLK
D
D Q
old Q
Q
tpd CLK-Q
tcd CLK-Q
5
1 2 7
I O CLK
CL
3 4
Q
Q D
5 6
CLK
D
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6004 Spring 1998: L10
1 2 7
CLK
3 4
Q
5 6
D Q D Q D Q
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6004 Spring 1998: L10
D Q Setup time = ts
≥ ts Hold time = th
Flow
through
G ≥ th
old Q
Q
1 2 7
I O CLK
CL
3 4
Q
Q D
5 6
CLK G
D
10
5
6004 Spring 1998: L10
1 2 7 8
CLK
3 4
Q
Need t25 > 0 to
9 5 6 avoid race
D condition
11
1 2 7 8
CLK
3 4
Q
ts
9 5 6
D
ts Assume
same as
Clock period = t28 = t96 tpd C-Q
t96 = (t94 + t46) ≥ tpd D-Q + tpd C.L.
assuming all other timing rules are satisfied!
12
6
6004 Spring 1998: L10
Clock Skew
D Q D Q
CL
CLKA
CLK
CLKB
wire delay w
CLKA
CLKB
Input D Q D Q
CL
CLK
14
7
6004 Spring 1998: L10
Coordinates
15