MINDBENDERS

When a puzzle is found to contain a major flaw - when the answer is wrong,
when there is no answer, or when, contrary to claims, there is more than one
answer or a better answer - the puzzle is said to be ‘cooked’
BEWARE: These questions are nicely cooked!!!

LEVEL I
[Q1] Identify the circuit below, and its limitation.

A
B
C

D
E Y

[Q2] Implement a NAND3 gate using minimum number of only NAND2 gates.

[Q3] Implement a NOR3 gate using minimum number of only NOR2 gates.

[Q4] Implement a XOR3 gate using minimum number of only XOR2 gates.

[Q5] What is the output Y, given A and B are as in waveform? (Tp’i’ is the gate delay)
Tp1 = 1ns

A
Tp3 = 5ns
B

Tp2 = 4ns

0 2.5 5 7.5 10 12.5 15 17.5

ns

B
[Q6] Briefly explain what will happen if the propagation delay of the clock signal in path
B is much too high compared to path A. How do we solve this problem if the propagation
delay in path B can not be reduced?

Path A
Path B

[Q7] What is the purpose of the buffer in the circuit below? Is it necessary / redundant to
have a buffer?

[Q8] Why are most interrupts active low?

[Q9] Implement a comparator that compares two 2-bit numbers A and B. The comparator
should have 3 outputs: A > B, A < B, A = B. Do it using combinational logic.

[Q10] Implement above design using multiplexers.

[Q11] Describe a finite state machine using state diagram that will detect three
consecutive coin tosses (of one coin) that results in heads

LEVEL II
[Q1] Your company is pretty tight on budget this year and it happens to have only 2:1
muxes to design with. You are required to design a negative edge triggered TFF using 2:1
muxes only.

[Q2] Generate a divide by two clock using DFF

[Q3] Design a simple circuit based on combinational logic to double the output
frequency.
 LEVEL III
[Q1] We have a FIFO which clocks data in at 100 MHz and clocks data out at 80 MHz.
On the input there are only 80 data bits in any order during each 100 clocks. In other
words, a 100 input clock will carry only 80 data bits, and the other twenty clocks carry no
data (data is scattered in any order).

How big the FIFO needs to be to avoid data over/under-run?

[Q2] Given an SRAM of depth N and some arbitrary width K, which is filled with 2n+1
non-zero values (for completeness – the rest of the 2^N – (2n+1) are all zeroes). n
elements appear twice – in different places in the SRAM, while a single value appears
only once.

Design a circuit with the minimum amount of hardware to find the value which appears
only once

[Q3] MinMax2 is a component with 2 inputs – A and B, and 2 outputs – Max and Min.
You guessed it, you connect the 2 n-bit numbers at the inputs and the component drives
the Max output with the bigger of the two and the Min output with the smaller of the two.

Your job is to design a component – MinMax4, with 4 inputs and 4 outputs which sorts
the 4 numbers using only MinMax2 components. Try to use as little as possible MinMax2
components.

Then try for MinMax6 using minimum number of MinMax2 and MinMax4.

[Q4] Assuming you have an n-bit binary counter, made of n identical cascaded cells,
which hold the corresponding bit value. Each of the binary cells dissipates a power of P
units only when it toggles. You also have an n-bit Gray counter made of n cascaded cells,
which dissipates 3P units of power per cell when it toggles.

You now let the counters run through an entire cycle (2^n different values) until they
return to their starting position. Which counter burns more power?

[Q5] In the diagram below both X and Y are n-bit wide registers. With each clock cycle
you could select a bit-wise basic operation between X and Y and load it to either X or Y,
while the other register keeps its value.

The problem is to exchange the contents of X and Y. Describe the values of the “Select
logic op” and “Load XnotY” signals for each clock cycle.
[Q6] An FSM receives an endless stream of “0″s and “1″s. Is it possible to build a state
machine, which at any given moment outputs whether there were more 0–>1 or 1–>0
transitions so far? If yes, describe briefly the FSM. If no, give a short proof.

[Q7] We are dealing with the recession hit engineers in the land of Logicia. For some sort
of fancy circuitry, a 3-bit binary input is received. As a result it should give the amount of
“1″s present in this vector. For example, for the inputs 110 and 101 the result should be
the same and equal to 010 (2 in binary). This time however, the only components they
have on their hands are 1-bit Full Adders.
Describe the circuit with minimum amount of parts.

[Q8] The engineers at Logicia are very happy with the above design. Now they want to
extract more out of you. You cannot protest against them as they have the right to
exploitation as well. So you cannot escape from their clutches. You will get freedom only
when you to implement the logic for a 7-bit binary input.
Describe the circuit with minimum amount of Full Adders.
[Q9] Blocks X and Y with their truth tables are shown below.

A A
X out Y out
B B

A B out A B out

0 0 1 0 0 z

0 1 z 0 1 z

1 0 z 1 0 z

1 1 z 1 1 0

Truth Table for X Truth Table for Y

Implement all the AOI gates (and, or, inv) using blocks X and Y only.