PROJECT- LITERATURE SURVEY FORM

BATCH NUMBER-16
TITLE: DESIGN AND IMPLEMENTATION OF LOW POWER AND
HIGH SPEED PHASE LOCKED LOOP.
S.No. NAME ROLL NO. PHONE NO. EMAIL

1 K.RITWIK 15071A04K1 7396873855 k.ritwikreddy9@gmail.com

REDDY
2 P.DEEPAK 15071A04L5 8328032265 datthureddy36@gmail.com
DUTT

3 P.PRADEEPTHI 15071A04L9 9550962275 pradeepthipamba@gmail.com

4 T.V.S.LALIT 15071A04N8 9348599935 Lalit.talluri0000@gmail.com

SRIHARSHA

1. Problem Statement: The Phase Detector circuit is one of the basic building
blocks of the Phase Locked Loop module. This occupies a large area, long
latency and consumes considerable power. Therefore the problem is formulated
to design the phase comparators with reduced power dissipation, number of
transistors and delay.
Block Diagram
2. Deliverables:
S.NO NAME OF THE TYPE OF THE OUR PROJECT WORK WHERE IT IS
INDUSTRY INDUSTRY USEFUL&HOW IT IS USEFUL TO
THAT PARTICULAR INDUSTRY

1 Multimedia, Information Low power design has become one of

Communication And the primary focuses in digital VLSI
.Pvt.Lmt Entertainment circuits. Optimization of several
devices for speed and power is a
significant
issue in low voltage and low-power
applications.

3. Review of status of Research and Development in the subject

3.1International Status:
S.NO NAME OF THE WORK ADVANTAGES &
RESEARCHER CONTRIBUTED DISADVANTAGES OF
WORK
1 Serkan YAKUT the classical phase-locked How the synchronization is obtained
loop (PLL) and Costas loop by the carrier recovery from the
are investigated together sinusoidal reference signal is
mathematically shown with some
assumptions and presented. It is
concluded that Costas loop
produces about half of the error
signal produced by the PLL in the
locked-stateoperation.
2 Noushin Ghaderi A Low Noise, Low Power A very simple, low power, high
Phase-Locked Loop, Using speed, and open loop phase
Optimization Methods detector is proposed which operates
in a wide frequency range from 1
MHz to 5 GHz. Due to the extra
simplicity of the circuit, the power
consumption is very low and is about
0.3 mW at the highest operational
frequency

3.2 National Status:

S.NO NAME OF THE WORK ADVANTAGES &
RESEARCHER CONTRIBUTED DISADVANTAGES OF
WORK
Suraj Kumar Phase locked loop conclude that we found that the
Digital phased locked loop have
1 result in good phase noise
performance with low power
consumption with improved tuning
range as compared to other
phased locked loop circuits.

2 John H. Lee An On-Chip All-Digital An on-chip, all-digital state

Measurement Circuit to machine can be used to accurately
Characterize Phase-Locked estimate PLL bandwidth and
Loop Response in 45-nm SOI peaking with potentially large
savings in tester time. This flexible
circuit may be used from wafer
level to product level, minimizing
die/package waste and allowing for
adaptive PLL loop calibration.
3.3 Importance of the proposed project in the context of current status.
Phase Detector is a fundamental unit in designing the Phase Locked Loops and in Servo
mechanisms. Phase Detectors have large area, long latency and they consume considerable
power. Therefore, a low-power phase detector design has become an important part in low
power VLSI system design. Of late, there has been extensive work on low-power phase detectors
at technological, physical, circuit and logic levels.

4. Work Plan:
4.1 Project Steps:
PROJECT STEPS PROJECT STEPS DESCRIPTION

STEP 1 Problem Statement identification.

STEP 2 Understanding PLL in detail.

STEP 3 Identification of different modules in PLL.

STEP 4 Choosing different techniques to enhance the performance of PLL

modules. i.e, using CMOS, GDI, MOD-GDI.
STEP 5 Designing and Simulating phase detector block in CMOS logic.

STEP 6 Designing and Simulating phase detector block in GDI logic.

STEP 7 Designing and Simulating phase detector block in MOD-GDI logic.

STEP 8 Designing and Simulating phase frequency detector block in CMOS

logic.
STEP 9 Designing and Simulating phase frequency detector block in CMOS
logic.
STEP 10 Designing and Simulating phase frequency detector block in CMOS
logic.
STEP 11 Comparing different parameters of PLL through different techniques.
4.2 Time Schedule of activities giving milestones through Table.
S.NO TASK TENTATIVE DATES& NO.OF.DAYS
DURATION REQUIRED
1 Abstract Preparation 05-01-2019 to 06-01-2019 2
2 Block Diagram Preparation 10-01-2019 to 13-01-2019 4
3 Literature survey 20-01-2019 to 21-01-2019 2
4 STEP1 23-01-2019 to 25-01-2019 3
5 STEP2 27-01-2019 to 28-01-2019 2
6 STEP3 05-02-2019 to 06-02-2019 2
7 STEP4 15-02-2019 to 17-02-2019 2
8 STEP5 20-02-2019 1
9 STEP6 23-02-2019 to 26-02-2019 3
10 STEP7 5-03-2019 1
11 STEP8 7-03-2019 to 9-03-2019 2
12 STEP9 12-03-2019 to 15-03-2019 2
13 STEP10 18-03-2019 1
14 STEP 11 20-03-2019 1
14 Documentation/Thesis 25-03-2019 to 26-03-2019 2
Presentation
15 Final slides preparation 30-03-2019 to 31-03-2019 2

4.3 Software’s/Technologies/Tools used in this Project Work:

S.NO Software’s/Technologies/Tools Application/Usage
1 MENTOR GRAPHICS WITH FOR SIMULATION
PYXIS TOOL.
5. Expertise:
5.1 Expertise available with the investigators in executing the project:
S.NO Name and Type of Help/assistance
Designation taken
of the mentor
1 P.kishore Helped in understanding
concepts of PLL and
techniques like GDI and
MOD- GDI.

5.2 Summary of roles/responsibilities for all batch mates:

S. No Name of the Student Roles/Responsibilities

1 K.RITWIK REDDY Literature review.

2 P.DEEPAK DUTT Implementing base paper designs.
3 P.PRADEEPTHI Transient analysis and computing certain parameters.
4 T.LALIT Implementing prerequisites required for the project.

5.3 Bibliography:
5.3.1: References: Pinninti Kishore, P. V. Sridevi, K. Babulu, K.S. Pradeep Chandra, ―A Novel
Low Power and Area Efficient Carry-Lookahead Adder using Mod-GDI Technique‖,
International Journal of Scientific and Research, vol.4, no. 5, May 2015.
5.3.2 Websites: https://www.electronics-notes.com/articles/radio/pll-phase-locked-loop/tutorial-
primer-basics.php
http://www.delroy.com/PLL_dir/CICC09_slides19.3_PLL_loop_measurement.

5.3.3 Youtube Links: https://youtu.be/A9qt0JYdvFU

6.0 Outcome of the project :
In this project the primitive gates were designed using those techniques to achieve a minimal
transistor count with low power consumption and maintaining the functionality. This is achieved
through the MOD-GDI technique. By using the MOD-GDI technique the design of the Phase
Detector is achieved. As per the analysis the proposed Phase Detector was more efficient in terms
of total power dissipation and also the transistor count when compared with the CMOS and GDI
based Phase Detectors. An effective Phase Frequency Detector is also implemented using the
MOD-GDI technique. In order to have a reference to check the functionality and also to compare
the other parameters like the number of transistors used and the Total power dissipation, the
circuit is designed in CMOS. After the analysis and comparison of the readings of the parameters
obtained, it is proven that MOD-GDI technique is the best technique to implement the complex
sequential logic circuits.

6.1 Social/Societal Impact of the Project

. The phase discriminator is the basic building block for the complex Phase Locked Loops, Radar
and Tele-communications system and in other Servo mechanisms.