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ABSTRACT

In 2005 power line communication (PLC) in integrated circuits (ICs) has proposed by Dr. Ha’s
group. Their motive was to utilize the power dispersion mesh for data transmissions as well as
delivery of power, so that the routing smash can be avoided and the count of pins in the chip can
be reduced. After some again research has done with the equivalent group in 2016, in this time
the helper Jebreel M. Salem of Dr. Ha’s group and demonstrated done measurements the
existence of pass-bands in the power dispersion mesh and the feasibleness of power line
transmissions in ICs.Earlier lots of PLC receiver were developed to recover the data from the
power line of an IC based PLC receiver. This thesis research worked on a new PLC receiver to
improve flaws of previous PLC CMOS receivers, specifically work to improve the dependability
on power orwe can say reducing power dissipation.

In the proposed work the PLC receiver, has received of data with layering power lines.
The basic objective to design this PLC receiver is to be unique and work properly under mutants
and droops of the supply voltage with high data speed. In our PLC receiver we prefer an
amplitude shift keying (ASK) modulation technique with power dispersion network. The
proposed PLC receiver circuit consists of mainly three sub-blocks. The first sub-block is a level
translator, which shifted the offset voltage of the supply to lower value approximately 0.5VDD.
The second sub-block is a signal separator, which detects a data signal modulated with the power
line. The signal separator is a mixer cum differential amplifier. The signal separator amplifies the
data signal while removing the dc offset voltage and also has design to overcoming of hysteresis.
Therefore, the signal can extenuate the fluctuations and droops of the supply voltage. The third
sub-block is the logic renovator, which converts the differential output of the second sub-block
to a logic value of the modulated data with the power line according to the Schmitt trigger. The
hysteresis of the Schmitt trigger improves the noise exemption of the receiver.

In this paper we use 0.18 μm CMOS technology for designing of PLC receiver and the
supply voltage is 1.8 V and the simulation results of the receiver shows that the receiver is
capable to send data of 1Gb/s. The receiver can dissipate total static power is 1.302mW under
1.8 V supply. The threshold value is set to 0.55 mV (or 2.5% of the supply voltage) and the sign

M.TECH THESIS 1
values are taken as logic 0 (1) if it is lowering (greater) than -0.083 (1.717 V) under the supply
voltage of 1.8 V. Note with the comparison of tolerance to the supply voltage that range of
±46%. The area of layout is also less as of it covers 100.3µm × 23.4 µm.

M.TECH THESIS 2
Chapter 1
Introduction
1.1 Motivation
Advancement of silicon processing technologies pushes the limit of consolidation for
today's integrated circuits (ICs). For example, an Intel Itanium® processor in 22 nm CMOS with
12 copper metal layers contains 6.2 billion transistors [2]. A major restraint for a high level of
consolidation stems from the package due to restricting factors such as I/O pin counting,
preparation of static power supply with large power consumption, and thermal heat removal. A
limited number of I/O pins for IC packages such as those for microprocessors poses a major
challenge to IC designers, who push to integrate an ever increment number of works in a single
chip.
As the consolidation level of an IC increases, the number of sensors to monitor internal
state of the chip such as the temperature and the supply voltage also increases. The increased
need to monitor the internal state is mainly due to two factors, increment system complexity and
decreasing reliability in deep sub-micron silicon technologies. The increased system complexity
simply has more nodes to monitor. The decreased reliability due to PVT (Process Voltage
Temperature) mutants makes the process status of blocks and circuits less predictable, which
necessitates deployment of more sensors. Control of those individual sensors necessitates
consecrated pins and routings. Consecrated pins are expensive for packages with complex ICs,
and routings cost expensive design hours.
A power dispersion network (PDN) is ubiquitous to inner nodes of a chip. In other term, a power pin reaches any
inner node through a PDN. Thus, a dual use of power pins and the PDN for data communicatings as well as
distribution of power is extremely alluring. It saves pins, and routing of the data signal to the inner nodes. It is
particularly alluring to restraint a huge number of sensor nodes, which does not require a high data rate. Further, it
provides the flexibility on placements of sensor nodes without thoughtful preplanning due to no necessity for routing.
The ability to communicate with inner nodes without routing data paths also opens up a option for fault diagnosis,
supervise ephemeral logic values during built-in self-test and for on-line/off-line testing.
1.2 Power Line Communicating Systems in VLSI Circuits
Power line communicating (PLC) in VLSI circuits was proposed by et. Al. Jabreel Salem to
control internal nodes of an IC [4] - [8]. A PLC system achieves communicating between an external
control module and one or multiple internal nodes of an IC through the power dispersion network.
The main objective of this research work is to reduce the cost of complex ICs of receiver through
decresing of the number of pins required to control internal nodes. The external transmitter of our

M.TECH THESIS 3
PLC system superimposes the data on the power supply and sends the data through a power pin(s)
and the power dispersion network of the IC to an internal node(s) without affecting the performance
of the chip. The PLC receiver at an intended node extracts the data from the power dispersion
network. Each receiving node has a pre-assigned unique identification code, which enables the data
to be delivered to the intended node(s).
Figure 1.1 shows a PLC receiver in a VLSI circuit environment. The Test/Control module
sends data lay overed on a power line of the system board. The sign travels through a power pin(s),
power planes of a package, and the power dispersion network and reaches at the intended node(s).
The channel characteristics of the power dispersion network of a target IC are important to select
proper frequency bands, and measured results on channel characteristics of Intel processors are
available in [8].

M.TECH THESIS 4
Figure 1.1: Power line communicating system in a VLSI circuit

1.3 Review of PLC Receivers in Integrated Circuits


The proposed subject of the thesis researches is to develop a PLC receiver in CMOS
technology. A few of PLC receivers in CMOS technology were designed by Dr. Dong S. Ha’s and
Jabreel Salem team [10]- [12]. The PLC receivers demonstrate feasibility of power line
communicating in ICs. The PLC receiver proposed by Thirugnanam et al. in [9] is composed of a
sensing circuit, a differential amplifier with an offset cancellation, and a positive feedback latch. The
offset cancellation, which removes the DC voltage from the input signal, which is according to fixed
bias voltage, and is susceptible to the fluctuations of the supply voltage. The PLC receiver was
designed in CMOS 0.18 µm technology. The PLC receiver’s design given by Chawla et al. in [10]
adopts a coherent detection for ultra wideband (UWB) data signals and with this concept, he achieves
a higher susceptibility than its predecessor owing to the coherent detection, on the cost of the more
power dissipation on the circuit due to higher complexity in the circuit designing. Like its precursor,
his receiver’s design also depends on a fixed bias voltage for removing the DC voltage from the
input signal and hence endure the same shortcoming. The PLC receiver was designated in CMOS
0.18 μm technology initially, and was also improved in 0.13 μm CMOS technology latter [12].

M.TECH THESIS 5
1.4 Technical Contributions of the Previous Proposed Researches
The research work of this thesis is to improve previously designed PLC receivers by Dr. Ha’s
group and other researcher’s group. The three major design objectives of the PLC receiver are to
extenuate supply voltage fluctuations and droops, to improve the noise exemption, and reduce power
dissipation. The main research contributions of this thesis work are as follows.
First, we designed a PLC receiver, which can extenuate supply voltage fluctuations and droops. A
differential amplifier but without a low-pass filter in our PLC receiver, which improves resilience to
low frequency voltage fluctuations and is effective for voltage droops.
Second, a Schmitt trigger with hysteresis is adopted to increase the noise exemption. The switching
voltages of the Schmitt trigger are in synchronous with the clock, which changes the two threshold
voltages to further improve the noise immunity. Third, a non-coherent is adopted for the PLC
receiver, which reduces the circuit complexity to lower power dissipation. Fourth, the proposed PLC
receiver was designed in CMOS 0.18 μm technology, and simulation results on a microwind software
are reported in this thesis.

1.5 Organization of the Thesis


The organization of the thesis is as follows. Chapter 2 provides background and preliminaries
for the proposed research work. The requirements for PLC receivers in ICs are discussed, and two
PLC receivers in ICs designed by Dr. Ha’s former students are briefly reviewed. Binary amplitude
shift keying (ASK) modulation, which is adopted for our PLC system, and its probability of symbol
error and energy per bit noise ratio are covered. Finally process of two building blocks of the
proposed PLC receiver is discussed. Chapter 3 presents the proposed PLC receiver consisting of
three building blocks, a level translator, a sign separator, and a logic reformer. Design of the three
blocks in CMOS 0.18 μm is described and simulation results to verify the process of the logic
restorer are presented. Chapter 4 presents post-layout simulation and measurement results of a test
chip. Measurements were performed with three individual building blocks first followed the entire
receiver, and the results on individual blocks as well as the entire chip are presented. The
performance of the receiver at different operating conditions and power consumption of individual
blocks are also reported. Lastly, Chapter 5 draws a conclusion on the proposed PLC receiver design
and suggests a few areas to improve as future research.

M.TECH THESIS 6
Chapter 2
Literature Review
In the part of hardware designing many designers has given their design concept on the
PLC based CMOS receiver. In this follows the precedent work has done on same technology
CMOS 180nm in which the results show that the receiver can bear a voltage dissipation of up to
0.423 V for a data rate of 10 Mb/s. The receiver dissipated power is 3.26mW @ 1.8V supply and
the used core area for receiver is 74.9µm× 72.2µm. According to our knowledge and gathered
information, PLC receiver was exclusively described in [1] Fig. 1 shows the theoretical and
practical PLC system under the IC environment which is taken for their research work [7]. On
the same track A superimposed data signal on the power supply of a system is send through a test
instrument [3]. The signal travels through a power pin(s), the power area of a package, and the
PDN, and then it reached at the intended node(s) [10]. The use power lines to simultaneously
carry data signals while delivering its power. A direct superposition of a data signal on a power
line would fail because of an inherent larger noise on power lines and precludes the possibility
for multiple data channel. To address the problem, we suggest adoption of the direct sequence-
code division multiple access (DS-CDMA) and UWB (Ultra Wideband) communication
technologies [11].
This chapter provides literature reviews topics and the previous research activities that
are necessary to interpret the proposed Power line communication (PLC) receiver and the
contributions of this thesis research. Section 2.1 provides the characteristics of power supply
voltage at ICs and gives a set of typical target requirements as a reference for the proposed PLC
receiver. Section 2.3 reviews the previous PLC receivers. Section 2.3 describes amplitude shift
keying (ASK) modulation scheme adopted for the proposed PLC. Section 2.4 briefly describes a
Schmitt trigger circuit, which is a major building block of our PLC receiver. Section 2.5 explains
the Supply voltage rejection ratio (SVRR) of amplifiers, and the property of SVRR is exploited
for our design. Section 2.6 summarizes the chapter.

M.TECH THESIS 7
2.1 Requirements
The supply voltage of an IC changes spatially across the IC as well as in time. Supply
voltage may change because of the non-ideal voltage regulator, IR drop, Ldi/dt noise, and
changing power consumption of blocks connected to the same power line. Figure
2.1 shows a supply voltage map pointing to the worst case voltage droop on a chip [13]. The map
shows that the supply voltage droop ranges from 3 to 15% of VDD across the chip area. The
problem could be worsened for devices powered by batteries as the battery voltage drops over
the operating period. Therefore, supply voltage unsteadiness is critical issue for IC design.
Superposition of the data sign on power lines should not affect the integrity of the supply
voltage, and difference of the supply voltage for ICs should remain less than ±10% of the voltage
supply [14]. Like any communication system, the bit-error-rate is an important guideline for the
proposed receiver. A low bit-error-rate (BER), desirably less than 10-6, would be necessary to
apply our receiver for simulating and diagnosis purpose of ICs, and adoption of an error coding
layout may be necessary in addition to a high performance PLC receiver. The above needed
thing combined with a high level of noise on power lines in ICs makes a PLC receiver design
challenging ‘‘Full Chip Leakage Estimation Considering Power Supply and Temperature Mutants,’’
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003,
pp. 78–83. Used under fair use, 2012.

Figure 2.1: A power supply voltage graph of, H. Su, F. Liu, A. Devgan, E. Acar, and S. R. Nassif

M.TECH THESIS 8
2.2 Previous PLC Receivers in ICs
Design of a strong PLC receiver in a CMOS 0.18 µm technology was examined closely in this thesis.
Their proposed PLC system adopts an ASK modulation layout, and the PLC receiver consists of
three sub-blocks. The first sub-block was a level shifter, which limited the offset voltage of the
supply voltage near about 0.5VDD. The second sub-block was a signal extractor, which detected a
data signal value which covered on the power line. The signal extractor was a differential amplifier,
in which one input was connected through an RC low-pass filter. The DC voltage of the data signal
varies according to the supply voltage’s fluctuations and droops. The low-pass filter allows to pass
only the DC values of the data signal. Since the DC voltage is common for both inputs of the
differential amplifier, it is removed from the data signal through the common mode rejection of the
differential amplifier. Therefore, the signal extractor could extenuate supply voltage fluctuations and
droops. The last sub-block was the logic restorer, which converts the differential signal to a logic
value based on a Schmitt trigger. The hysteresis of the Schmitt trigger improved the noise exemption
of the receiver.
Their proposed PLC receiver was designed in CMOS 0.18 μm technology. Measured results of the
three sub-blocks and the entire PLC receiver were presented and compared with the simulation
results. The data rate is set to 10.0 Mbps (the maximum simulated data rate can reach as high as
250.0 Mbps), and the ASK modulation scheme adopts VDD (= 1.8 V) for logic 0 and 90 mV above
VDD for logic 1. The measurements show that the PLC receiver can tolerate the supply voltage drop
by 0.423 V or 23.0%. The power dissipation for the receiver is 3.2 mW under 1.8 V supply. The core
area of the receiver is 72.2 μm x 74.9 μm. Although a fair comparison was difficult due to different
technologies used and design objectives and restraints, their proposed receiver had lower power
dissipation compared with previous PLC receivers.

Figure 2.2: Block diagram of their proposed PLC receiver

M.TECH THESIS 9
Measurement results in the frequency response of power dispersion networks performed by
Dr. Ha’s group show the existence of pass-bands for Intel processors [8]. A couple of PLC receivers
were proposed by Dr. Ha’s former students, Rajesh Thirugnanam and Vipul Chawla, and their
designs are reviewed in the this section [8]- [9].

2.2.1 Thirugnanam PLC Receiver


The PLC receiver proposed by R. Thirugnanam in [7] is shown in Figure 2.2. It consists
of a sensing circuit, a differential amplifier, and a latch. The sensing circuit, which is simply a
common source with diode connected load, detects the transmitted sign in the power line and
shifts the DC level of the sign down. The output of the sensing circuit, which is single ended, is
applied to a differential amplifier. One input of the differential amplifier is connected to a
constant reference voltage, and the other input to the drains of M3 and M4 whose gates are
connected to the clock sign. When the clock sign is low, the output of the sensing circuit is
connected to the input of the differential amplifier, and the amplifier amplifies the sensed sign
and compares it with the reference sign. When the clock is high, M3 is off and M4 is on. The
amplifier is disconnected from the sensing circuit, and the M5 acts as diode with resistance 1/gm.
The output of the differential amplifier is connected a latch, consisting of back-to back inverters.
The latch converts the output of the differential amplifier to the supply rails, i.e., logic values.
The transistor M9 enables the latch to sample at the falling edge.

Figure 2.2: PLC receiver proposed by R. Thirugnanam, “The dual use of power dispersion networks
for data communication in high speed integrated circuits,” Ph.D. dissertation, Department of
Electrical and Computer Engineering, Virginia Tech, 2006. Used under fair use, 2012.

M.TECH THESIS 10
A shortcoming of the PLC receiver is that the offset voltage at the output of a differential
amplifier is directly affected by the fluctuation of the supply voltage. The offset voltage may pull
up or down the latch according the fluctuation of the supply voltage to disrupt the process.
Also, the turn-on resistance associated with M3 weakens the strength of the output sign to reduce the
sensitivity of the receiver.

2.2.2 Chawla PLC Receiver


The block diagram of V. Chawla’s receiver is shown in Figure 2.3. The receiver consists of a sensing
and amplifying circuit, a merged mixer integrator, and a comparator. The sensing circuit senses and
amplifies impulse data on the power line, while shifting down its DC level. A merged mixer-
integrated circuit correlates the received sign with a template sign generated by a template generator.
The output of the merged mixer-integrator is applied to a comparator, which translates the sensed
pulses to logic values.

Figure 2.3: PLC receiver proposed by V. Chawla, “power line communicatings in


microprocessors - system level study and circuit design,” M.S. thesis, Department of Electrical
and Computer Engineering, Virginia Tech, 2009. Used under fair use, 2012.
The sensing and amplifying circuit is shown in Figure 2.4. It is simply a down-flowing
two stage of the differential amplifier. One of the inputs of the first amplifier is connected to the
supply voltage, and the other one connected to a RC filter tied to the supply voltage. The filter
extracts the DC voltage of the sudden desire signs lay overed on the power line.

M.TECH THESIS 11
Figure 2.4: Sensing and amplifying circuit proposed by V. Chawla, “power line communicatings in
microprocessors - system level study and circuit design,” M.S. thesis, Department of Electrical and
Computer Engineering, Virginia Tech, 2009. Used under fair use, 2012.

The merged mixer-integrator circuit is shown in Figure 2.5. The lower part of the circuit
consists of two single-balanced mixers with cross-coupled outputs. The mixer outputs are loaded
with capacitors C1 and C2. The transconductors (M15 and M16) at the bottom of the two single-
balanced mixers are driven by two almost the same, but time separated, example signs. The template
signs are digital impulses created by Template Generator.

Figure 2.5: A merged mixer- integrator circuit proposed by V. Chawla, “power line
communicatings in microprocessors - system level study and circuit design,” M.S. thesis, Department
of Electrical and Computer Engineering, Virginia Tech, 2009. Used under fair use, 2012.

The comparator circuit shown in Figure 2.6 (a) converts the impulses into digital. It has
an input gain stage and a regenerative latch stage. The input stage consists of M17 – M21, where
M17 and M18 are input transistors and M19 and M20 are included to minimize static current of
M.TECH THESIS 12
the input stage. A regenerative latch is back-to-back inverter pairs. The template generator circuit
diagram is illustrated in Figure 2.6 (b). One of the inputs to the NOR gate is inverted with respect
to the other by introducing an inverter. Every time the input switches from Vdd to 0, a glitch is
generated at the output (Vtmp), which serves as the template waveform for the correlation. The
glitch duration is adjusted by controlling the delay between the two inputs of the NOR gate with
the aid of switched capacitor bank 2. A template is generated at every clock transition from 0 to
Vdd. The switched capacitor bank 1 synchronizes the template waveform with the received
impulse by controlling the delay.

Figure 2.6: (a) A comparator circuit and (b) A template generator circuit proposed by V.
Chawla, “power line communicatings in microprocessors - system level study and circuit
design,” M.S. thesis, Department of Electrical and Computer Engineering, Virginia Tech, 2009.
Used under fair use, 2012.

The main advantage of the PLC receiver is that it can extenuate the voltage fluctuation
effectively. However, the receiver is complex to consume large power, notably use of two
differential amplifiers for the sensing stage and the merged mixer-integrated in the second stage.
M.TECH THESIS 13
Also, the large number of transistor for the PLC contributes more noise on the input of the
comparator, which is rather sensitive to the noise due to adoption of one threshold voltage.
2.3 ASK Modulation
Binary amplitude shift keying (ASK) modulation is adopted for our PLC receiver. Binary
ASK is attractive for low data rate systems due to simple modulation and demodulation schemes,
which lead to low power consumption. Figure 2.7 shows the relationship between probability of
symbol error and energy per bit to noise ratio (Eb/No). To achieve the bit error rate of 10-6, the
binary ASK (in which M=2) necessitates more than 11.0 dB of Eb/No . Note that the symbol rate
is equal to the bit rate for binary ASK. At the same time, the data sign should not be excessive to
maintain the integrity of power supply. Adoption of an error correction scheme is a solution to
meet the both requirements.
An ASK demodulator consists of three stages, an envelope detector, an average detector,
and a comparator. ASK demodulator circuits can be classified into voltage-mode, current-mode,
and mixed-mode, and three different types of circuits are illustrated in Figure 2.8. The data for a
voltage-mode ASK demodulator is represented as the nodal voltage and is shown in Figure 2.8
2.8 (a) [14] An inverting amplifier amplifies the voltage of the received sign, and the modulated
sign is reconstructed by the OR gate. The low-pass filter removes the noise and extracts the
envelope from the carrier, and the comparator recovers the digital data based on the threshold
voltage. A voltage-mode ASK demodulator has a lower circuit complexity compared with the
other two modes as it does not require a conversion between voltage and current. The data is
represented as the branch current for a current-mode ASK demodulator and is illustrated in
Figure 2.8 (b) [15]. The modulated sign is rectified by the current mode squarer with a small
impedance, and the carrier sign is eliminated using a 3rd-order Gm-C lowpass filter. A level
detector extracts the digital data from the envelope information. The data for a mixed-mode ASK
demodulator is represented in both nodal voltage and branch current, which intends to benefit the
advantages of both modes. An example of mixed-mode demodulator is shown in Figure 2.8 (c) [16].
The processal transconductance amplifier (OTA) converts the input voltage into current, and the
current mode envelope detector. The current level detector translates the current into digital values.

M.TECH THESIS 14
Figure 2.7: Probability of symbol error for M-ASK modulation, H. Nguyen and E. Shwedyk, A First
Course in Digital Communicatings. Cambridge University Press, 2009.. Used under fair use, 2012.

Figure 2.8: Three different types of ASK demodulator, (a) A voltage-mode ASK demodulator (b) A
current-mode ASK demodulator (c) A mix-mode demodulator.

A voltage-mode demodulator is chosen for our PLC receiver due to its simplicity to have a
smaller die area. It is suitable to our application since the transmitted sign is a voltage sign. Our PLC

M.TECH THESIS 15
receiver adopts a Schmitt trigger with two threshold voltages instead of a comparator with one
threshold voltage, which increase the noise exemption.

2.4 Schmitt Trigger


A Schmitt trigger produces a bi-static state with two diverse limit esteems or activating voltages and
is generally used to improve the exclusion to clamor and unsettling influences. A Schmitt trigger
decides the level of the sign rather than a comparator. A comparator has one edge voltage to change
from one rail to the next, and its limit voltage is controlled by the reference voltage. Dissimilar to

Figure 2.9: An example of hysteresis of a Schmitt trigger


Comparators , Schmitt triggers have hysteresis which has two limit voltages to change from rail to
the next. The lower limit voltage, VTL, at which the Schmitt trigger change from high to low, and
the higher edge voltage, VTH, at which the yield of the Schmitt trigger change from low to high.
Figure 2.9 demonstrates a case of a Schmitt trigger hysteresis. The primary favorable position of
having two edge voltages is circuit ends up resistant to clamor variety, and this is the thing that
makes a Schmitt trigger better than a comparator. The benefit of hysteresis in clamor condition is
shown in Figure 2.10. In this figure, the comparator yield change when the information surpasses or
falls behind the edge voltage (the blue line). Then again, the yield of the Schmitt trigger changes
from low to high when the information sources surpasses the higher edge voltage, and change from
high to low when the information falls behind the lower edge voltage which is well underneath the
high limit voltage.

M.TECH THESIS 16
Figure 2.10: A comparison between a comparator and a Schmitt trigger output

Their PLC embraces a differential Schmitt trigger with tunable hysteresis exhibited in [17] and is
appeared in Figure 2.11. Transistors M1 and M2 change over info voltages vin+ and vin-to streams
I1 and I2, individually. The hysteresis of the Schmitt trigger is created utilizing regenerative input
which set up by a cross-coupled inverter match, M7 – M10, and balanced by the heap control voltage
Vtune. M5 and M6 are voltage-controlled current sources. The width of M3 and M4 is set to be
substantially littler than that of M5 and M6, with the goal that current of M5 and M6 is considerably
more noteworthy than M3 and M4. M12 and M13 pull the hub yield of the Schmitt trigger up to
VDD or down to ground contingent upon the condition of hub A.
The procedure of the differential Schmitt trigger is clarified as takes after [17]. M1, M2, and M11
with two load transistors, M3 and M4, frame a differential speaker (DA). Let voltage Vin-be settled
to Vref all through the whole procedure and Vtune is associated with an inclination voltage so M5
and M6 are in immersion. Assume the inverter match M7-M10 is inert. The exchanging voltage of
the DA is Vin+ = Vin-= Vref and the streams ID1, ID2, ID5, and ID6 are a similar when current I3
and I4 are overlooked. Presently, assume Vin+ < Vref and the inverter match is dynamic with voltage
VA high and VB low. For this situation, M7 and M10 are turned on. Two current sources, M6 and
M10, pull up the hub A to high voltage while M1 and M7 sink the current I5 and draw down the hub
B to low voltage. I1 = I5 + I9 and I2 = I6 - I8. At the point when voltage vin+ increment more
present will be sunk through M2 and the voltage at hub A begins to diminish. At the same time,
voltage at hub B begins to increment. At the point when the voltage vin+ ends up break even with to

M.TECH THESIS 17
Vref, M10 is on and endeavoring to pull up the hub An and M7 attempting to pull down hub B. For
this situation there won't be a change at Vref in light of the fact that M7 and M10 are still on. At the
point when vin+ increments far above Vref (Vref+ΔV), the greater part of the current, I11,
experiences M1 bringing down the voltage at hub A further which in turns switches the M8 and M9
on and M7 and M10 off. For this situation, VA is low, and VB is high. The yield voltage, vout
changes from low to high. A similar situation happens when the voltage vin+ diminishes back. The
progress happens when vin+ well beneath (Vref-ΔV).

Figure 2.11: A differential Schmitt trigger with the tunable hysteresis, F. Yuan, "Differential CMOS
Schmitt Trigger with Tunable Hysteresis," Analog Integrated Circuits and Sign Processing
(Springer). Vol.62, No.2, pp.245 - 248, Feb. 2010. Used in fair use, 2012.

To evaluate the exchanging voltages of the circuit at state advances with Vin+ > Vin-, it is seen that
when the VA is at low voltage and VB is at high voltage exchanging, transistor M1, M2, M7, and
M10 are in immersion. Since M8 and M9 will turn off toward the finish of state progress, they can be
spoken to by open switches.

2.5 Power Supply Rejection Ratio


The SVRR is defined as the ratio of the output gain from the input to the output gain from the supply
voltage [18]. Consider a common source amplifier with a diode-connected load shown in Figure
2.12.

M.TECH THESIS 18
Figure 2.12: A common source amplifier
A plan target of an ordinary simple circuit is to segregate the circuit yield from supply voltage
mutants, which is spoken to as supply voltage rejection ratio (SVRR), and a large SVRR is desired
for typical circuits.

2.6 Chapter summary


In this part, a few subjects identified with the proposed work were explored. Right off the bat, a
diagram of an electrical cable conveying framework in VLSI circuits was exhibited. At that point, the
necessities and the difficulties were talked about. It was talked about that the voltage variance, sign
honesty and commotion impacts are the real difficulties of the collector. This part additionally looked
into the past PLC recipients, particularly those by Dr. Ha's and Jabreel Salem. Binary amplitude shift
keying (ASK) modulation and the relationship between probability of symbol error and energy per
bit to noise ratio were described. Circuit designs of ASK demodulators were likewise talked about.
At long last, two circuits, a Schmitt trigger and a common source amplifier, which were embraced for
the proposed PLC receiver, were covered. A Schmitt trigger in terms of its process and a common
source amplifier with respect to power supply rejection ratio were described.

Chapter 3
M.TECH THESIS 19
Proposed PLC Receiver
The proposed PLC receiver intends to control internal logic values of ICs for applications such
as simulation and diagnosis. Subsequently, a high information rate isn't an outline concern.
Rather, a reliable process under supply voltage ups and downs, droops, and noise, along with low
power wasting, are the primary design goals. The chapter describes circuit design of the
proposed PLC receiver, specifically three building blocks, a level shifter, a sign extractor, and a
logic restorer. The proposed PLC receiver is designed and simulated in CMOS 0.18 μm
technology under 1.8 V supply.

3.1 Block Diagram


The proposed PLC receiver adopts the binary amplitude shift keying (ASK), in which level of
signal is higher than VDD + Vth represents logic (1) and a lower than VDD + Vtl represents
logic (0), where Vth and Vtl are preset high and low threshold voltages, accordingly. A block
diagram of the proposed PLC receiver is shown in Figure 3.1. The PLC receiver mainly consists
of three different blocks. The first block is a level translator, which lowers the DC level of the sign
lay overed on the supply voltage, so that the level-translated signal can be processed by the following
signal separator. The subsequent block, a signal separator, first extract the superimpose signals then
amplifies the signals and converts it to a differential sign. The logic reformer, which is a Schmitt
trigger, retreats logic levels from the analog signal. The logic reformer has a derivative input and
converts the sensed analog sign into a logic value based on the threshold of its hysteresis.

Figure 3.1: Block diagram of the proposed Dual PLC receiver

3.2 Level Translator

M.TECH THESIS 20
The level translator shown in Fig. 1 can be behaved as a common source amplifier where PMOS
behaves diode connected load as, in which input is fixed to a bias voltage Vbias. In the proposed
configuration for mixing of VDD + V(D) where VDD is supply voltage and V(D) transient
response based message signal.

Figure 3.1: Level Translator

Figure 3.2: Layout diagram of Level Translator

For the superimposing of these two signal in a single power line we have used OR logic. The
level translator propagates the data signal imposed on the supply voltage VDD to the output

M.TECH THESIS 21
while lowering the dc voltage level of the signal to VDD/2 [7]. When Vbias is offering low
voltage MN2 gate is opened and signal will pass a common source amplifier to the output
section. To propagate the data signal superimposed on the supply voltage to the output, the
output should be sensitive to supply voltage variations and the respective layout of level
translator is given in Fig. 3.2. This proposed configuration also works for supply voltage
rejection ratio (SVRR) of respective amplifier circuit. Here we also kept the W/L ratio of M1
transistor is two time larger than M2 transistor.
𝐴𝑉
PSRR = (3.1)
𝐴𝑉𝑑𝑑

Thus, the PSRR of a common source amplifier is expressed as


𝑤
𝑔𝑚1 𝜇𝑛 ( 𝐿 )1 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )1
𝑆𝑉𝑅𝑅 = − =− (3.2)
𝑔𝑚2 𝑊
𝜇𝑃 ( 𝐿 ) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2
2

So the equation 3.2 is telling for lower SVRR the gm1 smaller than the gm2. This means that the
bias voltage and the W/L ratio of MP1 should be set to small, while operating MP1 in saturation.
Since the desired dc voltage level at the output of the sensing circuit is VDD/2, the condition sets
the overdrive voltage of MN2. A large W/L ratio for MN2 increases the current ID, and so it is a
compromise between low-power dissipation and low SVRR [5].
The bias voltage and the W/L ratio of the M1 are calculated to ensure that M1 remains in saturation.
The overdrive voltage (VGS -VTH) for the level translator is set to a near minimal (= 0.05 V), (W/L)M1
relatively large (=30), and (W/L)M2 relatively small (=15). The level translator is designed in CMOS
0.18 μm technology under 1.8 V supply. The parameter values of M 1 are, VGS = 0.5 V, and Vth = 0.75
V.

3.3 Signal Separator


As the proposing of differential amplifier as a balanced topology and also act as a mixer for dual
input over a single power line. This design supports low power designing for RF, UWB and IR
range communication device. Here one clock signal (clk 3) provided as a reference voltage of
two grounded NMOS (M9 & M10). This clock pulse will be inverse switching mode to the
Vbias cause will be given the lower additive noise figure and more linear output waveform. The
input signal of the signal separator (differential amplifier & mixer) is the data signal offset with
VDD/2, and the signal separator amplifies the data signal while removing the dc offset voltage
and also has design to overcoming of hysteresis. The signal separator shown in Fig. 3.3 is a
M.TECH THESIS 22
differential amplifier designed by fully NMOS, which reducing the space consumes by PMOS
and other passive components. The design stands for extract the dc value of the signal without
requiring of filter. The differential amplifier rejects the common-mode rejection signal of the two
inputs or the dc value. It also converts a dual mixed input into dual separated outputs and Fig 3.4
showing layout diagram of signal separator.

Figure 3.3: Signal Separator

Figure 3.4: Layout diagram of Signal Separator

The voltage gain of the differential amplifier is expressed as below.


𝐴𝑉 = −𝑔𝑚2/3 𝑅𝐷 (3.3)

M.TECH THESIS 23
Where 𝑔𝑚2 = 𝑔𝑚3 and can be expressed as 𝑔𝑚 = 𝜇𝑛 𝐶𝑂𝑋 (𝑊/𝐿) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) . It can be seen
from (3.3) that the gain increases by increment the transconductance, which in turns increases by
increment W/L or by increment RD. By concentrating of new design and reducing the parasitic
device like filter network we also reduce the static power consumption as well as reducing size
of device.

3.4 Logic Restorer


The logic restorer translates the data in analog differential sign form into logic values. It is based on
the Schmitt trigger described in Section 2.5. The logic restorer and its transistor sizes are shown in
Figure 3.5. A key aspect of the Schmitt trigger is the hysteresis through the regenerative feedback
circuit, which is a cross-coupled inverter pair. In fig 3.5, four stacked parallel input Mosfets M11-M14 and
their respective gate electrodes are coupled to the trigger input IN. Depending on the transition of IN, both MOS
transistors, signals are generated Which are controlled by the transistor size ratio M15/M11 and M16/M13. M15 and
M16 makes an inverter to provide a sharp transition at OUT. MP1 and MN1 form a feedback structure to control the
switching of the transistors in the circuit.
If IN is low then M15 is off and M16 is on, OUT is low. As IN increases, M11 begins to turn on and VN
starts to decrease. The trip point is defined When IN=Vtn2+VN that is When M13 turns on. When M3 turns on,
drain of M3 starts decreasing and turns NMOS MN1 off. Once M13 is on, the transition is very fast. If the transistor
size of M13 is large compared to M14 and M16 then trip point (VIH) is accurately decided by the ratio of M15/
M14. Similarly VIL is decided by the ratio of M15/M11. This proposed configuration has two parallel connections
and each one is working vice versa for final result. At low supply voltage this circuit provides considerable
hysteresis values, given in Fig. 3.6 showing the final layout diagram of proposed logic restorer circuit as compare
with the base paper [1].

M.TECH THESIS 24
Figure 3.5: A Schmitt trigger with the lower tunable hysteresis

Figure 3.6: A layout of logic restorer (Schmitt trigger)

We confirmed procedure of the rationale restorer through reenactments. We settled Vin-to a


specific reference voltage called Vref for our recreations. Let the cross-coupled inverter match be
deactivated. On the off chance that Vin+ is equivalent to Vref, at that point VA is equivalent to VB.
The voltage exchange trademark for the circuit under Vref = 1.1V is appeared in Figure 3.7. Note
that the exchanging voltage is Vin+ is equivalent to Vref = Vin-= 1.1 V. Assume that the inverter
combine ends up dynamic right now. The inverter combine can take a state subjectively, and thus the

M.TECH THESIS 25
yield can be either esteem 1 or 0. So Vref is in fact the exchanging voltage. We set Vref to 1.1 V for
our all simulation depicted beneath.

Figure 3.7: DC response for the Schmitt trigger with the inverter pair being inactive
Assume that Vin+ is 0 V, while Vin-is set to Vref = 1.1 V and the clock to 1.8 V. At that
point, VA is at a high voltage and VB at a low voltage, which turns on M7 and M10 and turns off M8
and M9. The output voltage Vout of the Schmitt trigger is low. As Vin+ increments from 0 V, M1
steadily swings on to diminishes VA, and M2 bit by bit kills to build VB. At the point when Vin+
progresses toward becoming Vin+= Vref, the hub voltage VA is as yet higher than VB because of
M7 and M10. So the exchanging does not happen at the point. At the point when Vin-surpasses Vref,
VA winds up equivalent to VB in the long run and an exchanging happens. M7 and M10 kill and M8
and M9 turn on. For this situation, the changing from high to low happens. Fig 3.8 showing final
proposed circuit of receiver with the subsequent of fig 3.9 layout diagram of finaliesd proposed dual
PLC receiver.

M.TECH THESIS 26
Figure 3.8: Final circuit representation of CMOS Dual PLC receiver

Figure 3.9: Final layout representation of CMOS Dual PLC receiver

3.5 Chapter Summary


The section portrays usage of three noteworthy building blocks, the level translator, the
signal separator, and the logic restorer, of the proposed PLC receiver in CMOS 0.18 µm process. It
clarifies measuring of key transistors for each block and gives the layouts of the three blocks. It
finally gives simulation results of the logic restorer to verify the lower hysteresis process of the
Schmitt trigger, which is a major function.

M.TECH THESIS 27
Chapter 4
Simulation Results
This chapter describes the simulation environment for the proposed PLC receiver first. Next, post-
layout simulation results for each sub-block, specifically the level translator, the signal separator, and
the logic restorer, are presented and then the results for the entire dual PLC receiver are presented.
The performance of the proposed PLC receiver is compared with previous PLC receivers developed
by Dr. Ha’s group.

4.1 Simulation Environment


The proposed PLC receiver is designed in CMOS 0.18-μm technology with a supply voltage of 1.8 V. The threshold
value is set to 0.55 mV (or 2.5% of the supply voltage). This means that a signal value is interpreted as logic 0 (1) if
it is lowering (greater) than -0.083 (1.717 V) under the supply voltage of 1.8 V. Note that the threshold value is well
below the tolerable range of ±46% of the supply voltage. The area of layout is also less as of it covers 100.3µm ×
23.4 µm.

4.2 Post-layout Simulation Results


4.2.1 Level Translator
4.2.1.1 Post-layout Simulations
The level translator is a common source amplifier whose input is fixed to a bias voltage.
Figure 4.1 shows the post-layout simulation of the level translator. The data rate is set to 10.0 Mbps,
and the ASK has 1.8 V for logic 1 and 0 V for logic 0. The simulation results show that the DC level
of the output is shifted down to 0 V, when VDD goes down. The simulated power consumption for
this sub-block was 28.856 μW.

M.TECH THESIS 28
Figure 4.1: Simulation results of Level Translator when the offset of the input sign is 1.8V

4.2.2 Sign Extractor

The signal separator is a differential amplifier, in which one of the inputs is connected to an inverter.
The one input of the inverter and the other input of the differential amplifier are connected together,
i.e., one signal is applied to the signal separator. The two differential outputs are observed for
simulations.
4.2.2.1 Post-layout Simulations
Figure 4.2 shows simulation results for the signal separator. The topmost waveform is the
input sign with any noise, which varies between 0 V and 2.0 V. The second waveform shows the
clock signal of differential amplifier, which changes slowly . The third waveform shows the positive
output (Vout+), which it varies between 1.1V and 1.25V. The last one is the negative output voltage
(Vout-) varying between 1.2V and 1.35V. This signal separator draws 105 μA under the supply
voltage of 1.8 V and dissipates 0.998mW.

M.TECH THESIS 29
Figure 4.2: Simulation results of signal separator
4.2.3 Logic Reformer
4.2.3.1 Post-layout Simulations
A ramp sign with 1.8V peak-to-peak is applied to the positive input Vin+ of the Schmitt trigger, while
the negative input Vin- is fixed at 1.0 V and the clock signal fixed at 1.8 V. Figure 4.3 shows the
simulation results on of the logic reformer. The output switches at 1.08 V when the input rises and
switches at 0.83 V when the input falls, which exhibits the hysteresis. In comparison with the
simulation result shows that this type of configuration reducing hysteresis comparative previous one.
The middle waveform shows the applied input signal to represent 1.8 V for logic 1 and 0 V for logic
0. The bottom wave is the output of the logic reformer, which shows a successful recovery of the
input data sign. The logic reformer draws 1.301 mA under the supply voltage of 1.8 V and dissipates
1.302 mW.

M.TECH THESIS 30
Figure 4.3: Simulation results of Logic Reformer when input sign is 1.8V

4.3 Layouts
The layout of the entire circuit diagrams is shown in Figure 4.4, the core size is 100.0 μm x
23.4 μm.

Figure 4.3: Final layout diagram of Dual PLC receiver circuit

4.4 Performance Comparison

M.TECH THESIS 31
Table 4.1 shows a comparison of the proposed receiver with earlier PLC receivers developed by
Jabreel Salem and his group. Although a fair comparison is difficult due to same technology used and
design objectives and restraints, the proposed receiver has the lowest power dissipation among all the
PLC receivers. Although not compared directly, we believe that the proposed one can tolerate a far
larger voltage droop than previous ones. It should be noted that proposed design has a much lower
data rate than its predecessors, and the above advantages of the proposed design may attribute to the
low data rate.
Table 4-1: Comparison of Performance with PLC Receivers for ICs
This work Previous Work
Technology 0.18 μm 0.18 μm
Supply Voltage 1.8V 1.8 V
Pulse amplitude 0.5V 90.0 mV
Pulse duration 4ns 8 ns
Power consumption 1.302mW 2.4 mW
Data Rate 1 Gbps 250Mbps

4.6 Chapter Summary


The proposed PLC receiver is designed in CMOS 0.18-μm technology with a supply voltage of 1.8 V. The
threshold value is set to 0.55 mV (or 2.5% of the supply voltage). This means that a signal value is interpreted as
logic 0 (1) if it is lowering (greater) than -0.083 (1.717 V) under the supply voltage of 1.8 V. Note that the threshold
value is well below the tolerable range of ±46% of the supply voltage. The area of layout is also less as of it covers
100.3µm × 23.4 µm.

M.TECH THESIS 32
Chapter 5
5.1 Conclusion
A receiver for Power line communication, which can be applicable to high data rate
communications, such as UWB applications, scan design, system debugging, and fault diagnosis,
was investigated in this paper. The proposed PLC system adopts a binary Amplitude shift key
modulation scheme , and the receiver consists of three basic building blocks. In that the level
translator shifts the dc level of the data signal to a half of the supply voltage. The signal
separator, based of a mixer and differential amplifier, removes the dc voltage from the data
signal, which mitigates supply voltage fluctuations and sinks. The logic renovator, based on a
differential Schmitt trigger, extracts logic values from the data signal while improving the noise
immunity and removing of all hysteresis of the receiver . By the calculation for data rate:
Data rate ≤ 2× Bandwidth
Data rate = 2 × BW × log2 M
Here the range of frequencies we got that 0.25 GHz and M are 2 bits values so by the above
formula
= 2 × 0.25 × 109 × 2
= 1 Gbps

few future research areas to improve the PLC receiver and to make the PLC in ICs feasible are
suggested below.
 The most power hungry piece of the proposed PLC recipient is the logic reformer or a
Schmitt trigger. Outline of a power proficient Schmitt trigger is recommended to lessen the
general power dissemination of the recipient.

 The proposed PLC can endure supply voltage hang by 0.423 V or 24% under supply voltage
of 1.8 V. It is conceivable to build the resilience level of the voltage hang through cautious
update of sub-squares.

The current PLC framework is expected to control interior hubs, and henceforth an
instrument can be utilized as a transmitter. To screen inside hubs, a PLC transmitter ought to be
outlined, and the achievability of PLC from an inward hub to an outer stick ought to be researched.
5.2 Future Work
M.TECH THESIS 33
In future the data rate of the PLC can be increased relatively easily through resizing and
matching of transistors. In future it can also design by different transistor level with reduce internal
nodes. The minimization of transistor should to be reducing static power of the future device. In
future also be increased the device performance in term of area, parasitic capacitance and the W/L
ratio.

Bibliography
M.TECH THESIS 34
[1] R. J. Riedlinger et al., “A 32nm 3.1 billion transistor 12-wide-issue Itanium; processor for
mission-critical servers,” in ISSCC ’11, Feb. 2011,pp. 84 –86.

[2] W. C. Chung, D. S. Ha, and H. J. Lee, “Dual use of power lines for data communicatings in a
system-on-chip environment,” Proceedings of IEEE International Symposium on Circuits and
Systems, Vol. 4, pp. 3355-3358, May 2005.

[3] W. C. Chung, and D. S. Ha, “A new approach for massive parallel scan design,” Proceedings of
IEEE International Test Conference, pp. 497-506, November 2005.

[4] R. Thirugnanam, D.S. Ha, and T. M. Mak, “On Channel Modeling for Impulse-Based
Communicatings over a Microprocessor's Power Despersion Network,” International Symposium on
Power Line Communicatings, pp. 355-359, March 2007.

[5] V. Chawla and D. S. Ha, "On feasibility study for power line communicatings in
microprocessors", TBD journal, manuscript submitted on xxxx date.

[6] R. Thirugnanam, “The dual use of power despersion networks for data communicatings in high
speed integrated circuits,” Ph.D. dissertation, Department of Electrical and Computer Engineering,
Virginia Tech, 2006.

[7] V. Chawla, “power line communicatings in microprocessors - system level study and circuit
design,” M.S. thesis, Department of Electrical and Computer Engineering, Virginia Tech, 2009.

[8] R. Thirugnanam, D.S. Ha, and T. M. Mak, "Data Recovery Block Design for Impulse Modulated
Power Line Communicatings in a Microprocessor," IEEE Computer Society Annual Symposium on
VLSI, pp. 153 - 158, May 2007.

[9] V. Chawla, R. Thirugnanam, D.S. Ha, and T.M. Mak, "Design of a Data Recovery Block for
Communicatings over Power Despersion Networks of Microprocessors,” International Conference
on Circuits & Systems for Communicatings, 5 pages, May 2008.

[10] V. Chawla and D.S. Ha, "Dual Use of Power Lines for Data Communicatings in
56

M.TECH THESIS 35
Microprocessors" IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems,
pp. 23-28, April 2011.

[11] H. Su, F. Liu, A. Devgan, E. Acar, and S. R. Nassif, ‘‘Full Chip Leakage Estimation
Considering Power Supply and Temperature Mutants,’’ Proceedings of the International Symposium
on Low Power Electronics and Design (ISLPED), 2003, pp. 78–83.

[12] N. Weste and D. Harris, CMOS VLSI design: A circuit and systems perspective. 4th ed.
Addison-Wesley, 2011.

[13] H. H. Nguyen and E. Shwedyk, A First Course in Digital Communicatings. Cambridge


University Press, 2009.

[14] S. Lee and S. Lee. “An implantable wireless bidirectional communicating microstimulator for
neuromuscular stimulation”. IEEE Trans. on Circuits and Systems I.,52(12):2526–2538, December
2005.

[15] G. Gudnason. “A lowpower ASK demodulator for inductively coupled implantable electronics”.
In Proc. European Solid State Circuits Conf., pages 385–388, September 2000.

[16] J. Alegre, S. Celma, B. Calvo, and J. Pozo. “Design of a novel envelope detector for fastsettling
circuits ”. IEEE Trans. on Instrumentation and Measurement, 57(1):4–9, January 2008.

[17] F. Yuan, "Differential CMOS Schmitt Trigger with Tunable Hysteresis," Analog Integrated
Circuits and Sign Processing (Springer). Vol.62, No.2, pp.245 - 248, Feb. 2010.

[18] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 4th ed. New York, NY: Wiley, 2001.

[19] Phillip E Allen, Douglas R Holberg. CMOS Analog Circuit Design, 2nd Edition. Oxford:Oxford
University Press, 2002.

[20] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.

[21] E. Alon, V. Stojanovic´, and M. A. Horowitz, “Circuits and techniques for high-
57

M.TECH THESIS 36
resolution measurement of on-chip power supply noise,” IEEE J. Solid-State Circuits, vol. 40, no. 4,
pp. 820–828, Apr. 2005.

M.TECH THESIS 37