SIGNAL ENGINEERING GUIDELINE No 14

Issue 1.0 Date 22 February 2006

TOPIC: Microlok II Relay Output PCBs

The recommendations of Microlok II Service Manual SM6800 G, Table 3-3 I/O Processing, Item 3.3.2 must be
implemented throughout all current and future project design.

For points outputs this recommendation will require the introduction of an independent locking bit (typically a LW)
for customers that have not previously specified external point locking bits in their systems.

The normal and reverse points control bits (typically a NW and RW) shall be allocated consecutively on the same
output PCB. However, the locking bit shall be allocated on another output PCB.

If customers specify the controls to be placed in the locking bit then no additional logic changes will be required.
However, the location of the functions controlling the locking bit shall be analysed and arranged to ensure they will
deliver the maximum possible level of protection to the points.

If customers do not specify the controls to be placed in the locking function then the locking bit shall be set if either
the normal or reverse control bit is set and the dead locking track circuit/s over the points is clear at time of setting
the locking bit. Subsequently, track circuit occupancy after the points have commenced to move shall not prevent
the move from being completed. This application logic shall be provided in the cardfile from which the points are
directly controlled (typical via a NWR and RWR) and the dead locking track circuit/s must be inputted to
the same cardfile.

The form of the LW equation shall be:

ASSIGN (NW + RW) * (ATP * BTP + LW) TO LW;

For other outputs, for example that drive latched relays, similar safeguards must be considered and
implemented.

Any issues regarding the implementation of this guideline should be raised with the Director of Engineering -
Signalling.

Howard J Revell,
Director of Engineering – Signalling