FacultyMember: Engr Arshad Nazir Date: 3rd April, 2018

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Semester: 2nd Section: BESE-8A
EE221 – Digital Logic Design
Lab7: Part (a): Design of 2-out-of-5 to BCD Code Converter with Display
Part (b): Gate-level Modeling in Verilog

S. No. Student Name Reg. No. Total Marks

S1 Muhammad Shaharyar 211690

S2 Muhammad Usama
S3 Taimoor Khan Mahsud
S4
Method: Viva, Lab report and instructor observation during lab session.
Outcome Assessed:
a. Ability to conduct experiments, as well as to analyze and interpret data (P).
b. Ability to function in a team (A).
c. Ability to use the techniques, skills and modern engineering tools necessary for engineering
practice (P).
Exceeds expectation Meets expectation
Performance
(10--8)/(5--4)
Selects relevant equipment
to the experiment, develops
1.Realization Of
setup diagrams of
Experiment [c]
equipment connections or
10
wiring.
Actively engages and
2. Teamwork [b] cooperateswith other group
5 members in an effective
manner.
Does proper calibration of
3.Conducting equipment, carefully
Experiment [a] examines equipment and
5 wiring components, and
ensures smooth operation
and process.
4. Laboratory Respectfully and carefully
Safety Rules [a] observes safety rules and
5 procedures.
Plans data collection to
5. Data achieve experimental
Collection[a] objectives, and conducts an
10 orderlyand a complete data
collection.
212622
212573
Group No. 7
Does not meet Marks
expectation
(7--5)/(3)
(4--1)/(2--1) S1 S2 S3 S4
Needs guidance to
Incapable ofselecting
select relevant
relevant equipment to
equipment to the
conduct the experiment,
experiment and to
equipment connection or
develop equipment
wiring diagrams are
connection or
unrecognizable.
wiringdiagrams.
Cooperates with other Distracts or discourages
group members in a other group members from
reasonable manner. conducting the experiment.
Calibrates equipment,
Unable to
examines
calibrateappropriate
equipmentand wiring
equipmentand wiring, and
of components and
equipment operation is
operates theequipment
substantially wrong.
with minorerror.
Observes safety rules
Disregards safety rules and
and procedures
procedures.
Withminor deviation.
Plans data collectionto Does not know how to Plan
achieve experimental data collection toachieve
objectives, and collects experimental goals; data
complete data with collected is incomplete and
minor error. contain errors.

EE-221: Digital Logic Design Page 1

Lab7: Part (a): Design of 2-out-of-5 to BCD Code Converter with
Display

This Lab Activity has been designed to familiarize the student with design and working of a 2-out-
of-5 to BCD Code Converter with numeric Display circuit. Psychomotor Level P-4

Objectives:

 Simplification of output Boolean functions using Five-Variable map from truth table.
 Design of Code Converter block using Two-Level NAND gates.
 System integration with BCD-to-Seven-Segment Decoder and Numeric readout for decimal
display.
 Understand the difference between common cathode and common anode displays

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to
the lab and deposit it with teacher/lab engineer for necessary evaluation.
 The students will start lab task and demonstrate design steps separately for step-
wise evaluation (course instructor/lab engineer will sign each step after ascertaining
functional verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely
patched circuit will simplify trouble-shooting process.

 After the lab, students are expected to unwire the circuit and deposit back
components before leaving.
 The Total duration for the lab is 3 hrs. The students are expected to complete
lab within specified time.
 A lab with in-complete lab tasks will not be accepted.
 The students will complete lab task and submit complete report to Lab Engineer
before leaving lab.
 There are related questions at the end of this activity. Give complete answers.
 This lab is OBE compliant.

EE-221: Digital Logic Design Page 2

Pre-Lab Tasks:
1. What do you mean by non-weighted codes? Give any two examples. (1 Mark)
Answer:
The codes which have no positional weights are called non-weighted codes. In other
words, the codes which are not given any weights, such as:

Gray code, 2 out of 5 code, XS-3 code etc. In gray code 3 is represented as 0010 then
actually it would have been 0010 it represents 3.

2. What are de-generate forms? List any five. What are the applications of these forms in
digital design? (2 Marks)
Answer:
In a two level circuit those combinations which are reduced to a single operation are
called degenerate forms.
1. AND-AND
2. OR-OR
3. AND-NAND
4. OR-NOR
5. NAND-OR

3. 7-Segment LED Displays are commonly used for displaying decimal Numbers (0 to 9). It
can also be used for displaying alphabets. A 7-Segment LED Displays essentially
consist of 7 LEDs configured as shown below to display numbers. It comes in two
configurations. Common Cathode and Common Anode. Draw the diagram showing
connections to drivers and power source and ground for both configurations and
highlight differences between the two. Also give signal logic level required to light up the
LEDs in the segment in each configuration: (2 Marks)

EE-221: Digital Logic Design Page 3

4. Complete the following table. (3 Marks)

Dec Inputs (2-out-of-5) Output(BCD)

A B C D E W x y z
0 1 1 0 0 0 0 0 0 0
1 0 0 0 1 1 0 0 0 1
2 0 0 1 0 1 0 0 1 0
3 0 0 1 1 0 0 0 1 1
4 0 1 0 0 1 0 1 0 0
5 0 1 0 1 0 0 1 0 1
6 0 1 1 0 0 0 1 1 0
7 1 0 0 0 1 0 1 1 1
8 1 0 0 1 0 1 0 0 0
9 1 0 1 0 0 1 0 0 1

∑d( )

5. Simplify the output functions w, x, y, and z using map method. Try to take maximum
advantage of don’t care conditions. (5 Marks)

W= DE + CE = [(DE)’.(CE)’]’

X= AE + BE + A’DE’ = [(AE)’.(BE)’.(A’DE’)’]’

Y= AB’ + BE = [(AB’)’.(BE)]’

Z= B’D + AB + BE = [(B’D)’.(AB)’.(BE)]’

EE-221: Digital Logic Design Page 4

Lab Tasks:

Lab Task 1

6. Give complete schematics for your design including 2-out-of-5 to BCD Code Converter
block, BCD-to-Seven-Segment driver IC and read out. A Schematic is a logic diagram
with pin numbering and IC Labeling on each gate. (3 Marks)

EE-221: Digital Logic Design Page 5

7. Implement the above circuit in hardware using minimum number of NAND gates at Two-
Level and show the results to Teacher/Lab-Instructor. (10 Marks)

8. Mention which configuration of 7-Segment Display did you use in Lab? If you were to
use the other configuration what change would you need in your circuit? (1 Mark)

Answer:

We used common anode display for the output as the values a, b, c… were
already in complemented form. If we used the common cathode display, it would be
needed to flip the 1’s and 0’s of the BCD to convert the complemented values back to
the original values.

Part (b): Gate-level Modeling in Verilog

Lab Task 2:

EE-221: Digital Logic Design Page 6

9. Design and simulate the gate-level model of the circuit you have patched. Give the code
in the space provided. (8 marks)
Code:

Output:

EE-221: Digital Logic Design Page 7

Observations/Comments:

It took us a lot of time to complete the lab as the decoder IC was faulty and after
long time we came to know that it was not working.

W could also be expressed as ((A’B’E)’). If we used this expression we din’t need

to use C and the circuit could be implemented using four switches only.

EE-221: Digital Logic Design Page 8