CMOS Analog Circuits

L20: Class
C AB amplifier
f (24.10.2013)

B. Mazhari
B
Dept. of EE, IIT Kanpur
56
G-Number
B. Mazhari, IITK
Output Stage

+3.3V

1 2 3 v0

vS
-3.3V
RL = 1K

Low output Resistance; Rail-to-Rail voltage swing

Low distortion; High efficiency

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B. Mazhari, IITK
CS Amplifier

VDD = 3.3V 3.3V

+3
Vbias2 (W/L)P
RD 0
-3 M2
vO
vO
1k (W/L)N
vS Vbias1 M1
vin VSS = -3.3V
-3.3V

VDD I DSQ  3mA

I DSQ   33mA
RD

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B. Mazhari, IITK
CD Amplifier

VDD = 3.3
VDD = 3
3.3
3

vO VBias1 m1
vO

RL = 1K VBias2
vin RS vin RL = 1K
m2

VSS =-3.3 VSS =-3.3

3.3
Ibias  ~ 33mA I Bias  3.3
3 3mA
A
100

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B. Mazhari, IITK
Class A amplifiers VDD
VBias2
3.3V
m2
vO
Vbias2
VBias1
M2 RL=1k
vO
m1
vin
1k VSS
vS Vbbias1
as M1

-3.3V

In both CS and CD amplifiers,

amplifiers the transistor remains ON and conducting
throughout out the ac cycle. To achieve this the bias current must be larger than
the ac drain current.
Ids d  I Bias  ids
I ds d d  I Bias iL  ids
ids d  I Bias

vo  VDD PL  0.5vo  iL  0.5VDD I Bias

ids
IBias
1T
Pss    VSS  I ds dt  Vss I Bias Pdd  VDD  I Bias
T0
PL
t   0.25
B. Mazhari, IITK Psup ply 60G-Number
Amplifiers with negligible stand-by power dissipation
Ids
VDD
VBias2
m2 ids Even when no input is
vO IBias applied,
pp power is drawn
p
VBias1
RL
from the supply.
m1
t
vin An efficient
A ffi i t amplifier
lifi will
ill take
t k power from
f th supply
the l
VSS
only when power is to be delivered to the load.

Bi currentt mustt be
Bias b zero !! Ids 2
1T 2 ids R
vO PL   ids dt  RL  max L
VBias1 T0 4
RL
m1
vin
VSS ids t

1T V i  ids max RL v
Pss    VSS  I ds dt  ss ds max    0.785
0 785  o max
T0  4 VSS VSS
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B. Mazhari, IITK
How do we reduce distortion? VDD = 3.3
VBias2
vO m2
vO
VBias1
RL
vin RL
m1
IL vin
VSS IL

t
t

VDD = 3.3
VBias2
m2
Each Transistor conducts for
vO only half the cycle resulting in
Class B operation
vin RL
VBias1 m1
62
B. Mazhari, IITK VSS G-Number
Class B push-pull amplifier

VDD = 3.3
VBias2
m2

vO
vin RL
VBias1 m1

VSS

During positive cycle, M2 pushes current into the load, while during the
negative cycle, M1 pull current from the load and hence the name Push-Pull
amplifier 63
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B. Mazhari, IITK
 VDD = 3.3
0V 700/1
m2 Symmetrical
y nmos and p pmos with identical
parameters and no body effect for nmos.
700/1 vO
vin RL
m1
0V
VSS

Cross-over distortion

64
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B. Mazhari, IITK
 Note the odd harmonics 65
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B. Mazhari, IITK
 VDD = 3.3
0.7V
m2

vO
vin RL
-0.7V m1

VSS

Psby~24
24 µW
W 2.14mW
  49.1% @ 2.3V
4.26mW

v
  0.785
0 785  o max
VSS

For output swing of

3V, efficiency
increase
c ease too 71.6%
6%

66
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B. Mazhari, IITK
 VDD = 3.3
0.8V
m2

vO
vin RL
-0.8V m1

VSS

Psby~2.92mW
2 92 W

2.14mW
  43.6% @ 2.2V
4.9mW

For output swing of

3V, efficiencyy
increase to 68%
67
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B. Mazhari, IITK
 VDD = 3.3
0V 700/1
m2

700/1 vO
vin RL
m1
0V
VSS

VDD = 3.3
0.7V
m2

vO
vin RL
-0.7V m1

VSS

VDD = 3.3
0.8V
m2

vO
vin RL
-0.8V m1
68
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B. Mazhari, IITK VSS
Distortion can also be reduced by employing negative feedback

3.3V

700/1
M2
vO
100 -100 700/1
vS 1k
M1

-3.3V
3 3V

69
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B. Mazhari, IITK
0.5um nmos and pmos Tr.
With body effect

VDD = 3.3
0V 700/1
m2

700/1 vO
vin RL
m1
0V
VSS

Not the strong second

harmonic distortion as
well resulting from
unequal swings in
positive and negative
p g
directions..

70
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B. Mazhari, IITK
 VDD = 3.3
0.7V
m2

vO
vin RL
-0.86V m1

VSS

Pstb~0
0

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B. Mazhari, IITK
 VDD = 3.3
1.0V
m2

vO
vin RL
-1.16V m1

VSS

Pstb ~0.6mW
06 W

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B. Mazhari, IITK
 VDD = 3.3
1.0V
m2

vO
vin RL
-1.16V m1

VSS

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B. Mazhari, IITK
Class AB Push-Pull amplifier using CS stage

VDD = 3.3
VBias2
m2

vO
vin RL
VBias1 m1

VSS

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B. Mazhari, IITK
Symmetrical nmos and pmos with identical parameters and no body effect for
nmos.

VDD = 3.3
2.6V 700/1
m2

700/1 vO
vin RL=1k
-2.6V m1

VSS

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 76
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B. Mazhari, IITK
 77
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B. Mazhari, IITK
 VDD = 3.3
VBias2
m2

vO
vin RL
VBias1 m1

VSS

VDD = 3.3
VDD = 3.3
VBias2
VBias2
Bi 2 m2
m2
vO
vO

RL
vin VBias1 m1
VBias1 m1
VSS
VSS
Need to address biasing 78
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B. Mazhari, IITK
Biasing Of Class AB Output Stage

VDD
~ VDD  0.7 VDD
m2
VBias2
m2
vin vO VBias3
vin vO
RL
VBias1 m1 VBias4
~ VSS  0.7 VSS
m1

VSS
VBias2 m2

vO

vin VBias1 m1

VSS 79
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B. Mazhari, IITK
 VDD VDD
m2
m2
VBias3
as3
vin vO
VBias4 vin
VBias3
m1 vO
VSS VBias4

m1

VBias2 m2
VSS

vO

vin VBias1 m1

VSS 80
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B. Mazhari, IITK
 VDD

VDD
m2
m2

vin
VBias3 VBias3
vO vO
VBias4 vin
VBias4
m1

VSS
m1

VSS

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B. Mazhari, IITK
 VDD

m6 m14

VBias3
vO
VBias4

m7 m15

VSS

CS gain
i Stage
St Class AB Output Stage

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B. Mazhari, IITK
Class AB Buffer Amplifier

C.W. Lu,” High-Speed Class AB Buffer Amplifiers with Accurate

Quiescent
B. Mazhari, IITK
Current Control 83
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 84
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B. Mazhari, IITK
 85
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B. Mazhari, IITK
Class AB CMOS Pseudo-Source Buffer Amplifier

VDD

VDD
M6
M6
A1
+
_ Vb1
Vin Vout
Vin Vout

RL
+ RL
A2
_ Vb2

M6A M6A
VSS VSS

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B. Mazhari, IITK
 VDD

VBias2 M5A
Folded cascode Load M6

M1A M2A

VSS
Vout
VDD
Vin
M1 M2

M6A
Folded cascode Load
VBias1
M5

VSS

(a)

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B. Mazhari, IITK
Positive error amplifier

M44 M45

M52

M54
Vin+ Vin-

M42 M43

Ibn

M55 M56

M40 M41
VBIAS

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B. Mazhari, IITK