Chapter

10

FIELD EFFECT
TRANSISTORS:
MOSFET

The following overview gures describe important issues related to the most important electronic
device.
 MOORE'S LAW

Gordon Moore, co-founder of Intel:

1st law: Complexity (number of active devices) of a chip doubles every 18

months.
2nd law: Cost of a fabrication facility grows on a semi-log scale with time.

• Complexity increases at ~59% per year!

• At current pace, semiconductor fabrication facilities will cost $250 billion
by 2010!

108

107
NUMBER OF ACTIVE DEVICES/CHIPS

106

105

104

103

102

101
1960 1970 1980 1990 2000 2010
YEAR

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 AN OVERVIEW OF THE MOSFET STURCTURE

Polysilicon
or metal
idth, Z
Gate w Oxide
n-type
semiconductor

D
n-source
L
Gate
n-drain
p-substrate G B

S
(a)
STRUCTURE Schematic symbol

Metal source Gate, G Deposited Metal source

contact n-type insulator drain
S polysilicon D

}
SiO2 n+ n+ SiO2
dox
Source Drain
Field oxide Channel p+
region L Silicon dioxide
Channel length L

p-type body, B

(b)
CROSS-SECTIONAL VIEW

Modern MOSFETs are enormously complex devices with great care taken to reduce
parasitic elements.

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 A SIMPLE SCHEMATIC OF PROCESSES IN A MOSFET FABRICATION

n+ source and
drain are produced
Coat the entire wafer by ion

AAAAAAA AA
with Si3N4. Si3N4 is G implantation.

AAAAAAA
impervious to dopants. Si3N4

p-Si
n+ p+
p-Si

(a) (d)

SiO2 is deposited on the entire structure.

A mask is used to open windows for
First mask: Define contacts. Al is evaporated.
transistor area and B S G D

AAAA AA
remove Si3N4. Implant
SiO2
p+ regions to serve as

AAAA
device isolation. Grow
thick field oxide.
p+

(b) (e)
Top view of
Etch Si3N4 and grow the device

AA
thin gate oxide. On the polysilicon gate
gate oxide, grow

AA
SiO2
polysilicon and define G
the gate via a mask.
p+

B S D
p-Si

(c) (f)

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 BAND PROFILES IN A METAL, OXIDE, SEMICONDUCTOR, AND A MOS

Metal

Oxide (insulator)

p-type semiconductor

(a)

Evac Evac Evac

Band profiles in Ec (oxide)
a metal, SiO2, eχs
and p-Si. eφs

eφm Ec

dox EF
Ev
EF Semi-conductor
Metal Oxide

(b)

eVfb
Band profile in a
MOS structure Evac
eχs
eφm
eVfb = eφm – eφs
Ec
eφs
EF EF
Metal Ev
Oxide
Semiconductor

(c)

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 BAND PROFILES AND CARRIER DENSITY IN ACCUMULATION,
DEPLETION AND INVERSION

Electric field F
Accumulation
VGS < 0

ρ
p
p0
Carrier

AAAAAA
Ec
EF density

AAAA
eVGS n0
EFi
EF n
+
++ z
Ev
M O S W
(a)

Electric field F
Depletion

Na p0
Ec
p Carrier
VGS > 0

AAAA
AA AA n density
EFi

eVGS
AA EF
Ev
z
EF W
M O S (b)

Electric field F
Inversion
n (interface) > po
Ec ρ
VGS >> 0

AAA
A
AAA AA EFi
Na
p
p0
Carrier

AAA
EF n density
Ev n0
eVGS

EF z
M O S
(c) W

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 AN MOS STRUCTURE UNDER INVERSION

V >> 0 W

Ec

AAAAA
AAA
d
Ei

AA
AA
EF

AA
eVGS Ev

O Semiconductor
EF
z
M
Qm Q (charge per unit area)

Charge
density

W
z

Qd: charge from background dopants

Qn: free carrier charge

Fox
Electric
field

Fs
W
z

V(x)

Electrostatic Vox
V
potential VGS = Vfb + V
Vs = Vfb + Vox + Vs
z
W

4εs φF 1/2
Wmax = ( | |
eNa ( ; φF = EF – EFi
1 Q
VT = Vfb – 2φF + [2eεsNa |– 2φF + VSB |]1/2 C – C ss
ox ox
Qss = interface areal charge density

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 CAPACITANCE-VOLTAGE RELATION IN A MOS CAPACITOR

A typical C-V curve

Oxide Semiconductor Low frequency

AAA AA
(~1Hz)
C = Cox C

AAAA
C = Cox

AAA
(i)
Cmos(fb)
Accumulation
High frequency

AAA
(103 Hz)
Cmos(min)
(ii)

Inversion

Vfb 0 VT
Cox Cs
VGS

Flat band
Accumulation Depletion Weak Strong
region inversion inversion

Once the MOS is in inversion, the

sheet charge density increases 10–5
rapidly with bias.
AREAL CHARGE DENSITY, |Qs| (C/cm2)

10–6

2φF
10–7

10–8

10–9
–0.2 –1.0 0 1.0 0.2 0.3 0.4
SURFACE VOLTAGE, Vs (volt)

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 CURRENT VOLTAGE RELATIONS IN A MOSFET

A SCHEMATIC OF THE STRUCTURE

th
id Source, Gate, Drain,
w ce

in
te Z ur S

AAAAAAA
Gate
ra
G D
Ga So
L D
Oxide
p-semiconductor AAAAAAA
n+ n-channel
x=0 x=L
n+

p-substrate
z

y B

VDS = VDS(sat)

A
µZCox
Linear Saturated region: ID (VGS – VT)2 k=

AA
A
region L
LINEAR REGIME:

AA
A
AA
ID = k[VGS – VT]VDS

SATURATION REGIME:

AAAA
DRAIN CURRENT ID

k
ID(sat) = (VGS – VT)2

AAAA
2

AA
AA
AA
AA DRAIN TO SOURCE BIAS VDS

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 EFFECT OF BODY BIAS ON MOSFET PROPERTIES
VGS
VDS
S G D
n-MOSFET
n+ n+ with VSB bias
p-substrate

(a) VSB

Ιnversion condition
Ec when VSB = 0

AA
AA AAAAA
AAA A AAA
A A
AAA
EFi

AA
eVs = –2eφF EF
Ev

(b) Wmax

W(VSB) Ιnversion condition

Ec when VSB > 0

AAAA
AAAAA AAAAA
AAAA AA
AA A EFi

AAAAA
AAAA A
AA
A
EF
eVs = e(–2φF + VSB) Ev

AAAAA AAA
AAAAAAAA
AAAAAAA A
AA
AAAAA
EFn
Electron quasi-
Fermi level

(c)

Shift in threshold voltage

2eεsNa
∆VT = –2φF +VSB – 2φF
Cox

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 DEPLETION AND ENHANCEMENT MOSFET

Source Gate Drain

Oxide
n-channel
n+ n+

p-substrate
(a)

A typical n-channel
Ohmic depletion-mode

AA
region device
Depletion FET: Saturated region

AA
Device is ON at
zero gate bias. D VGS = +2.0 volts

A A
A
substrate
VGS = +1.0

A
G S

AA
A
VGS = 0.0
Drain current ID

AA
AA
VGS = –1.0

A
AA A VGS = –2.0

VGS = –3.0
(b)
Drain bias VDS

AA
A typical n-channel
Enhancement FET: enhancement-mode

A
AA
Device is OFF at D Ohmic Saturated region device
region

A
AA
zero gate bias. VGS = +7.0 Volts
substrate

G S
A VGS = +6.0

AA
A
Drain current ID

AA
VGS = +5.0

AA
AA
VGS = +4.0

AA
VGS = +3.0
(c) Drain bias VDS

Ion implantation of the channel is used to fabricate depletion mode MOSFETs.

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 COMLIMENTARY MOSFET: LOW POWER FET
By combining an NMOS and a PMOS a CMOS is constructed. Since only one device
(NMOS or PMOS) conducts for any gate bias the CMOS does not draw any current
and is very useful for low power applications.

PMOS NMOS
Output
Source + Gate Drain Drain Gate Source

SiO2 p+ + + ++ p+ SiO2 n+ – ––– n+ SiO2

p well
Hole conduction Electron conduction

(a) n-type body

+VDD

PMOS

NMOS

(b) SCHEMATIC SYMBOL

(a) A cross-section of a CMOS device. (b) Symbol representing the CMOS.

+V
Vin
t S
p-channel
Vout D
Vin Vout
t D
n-channel
ID S
(a) t (b)
(a) A complimentary MOS structure shown to function as an inverter. The circuit
draws current only during the input voltage switching. (b) A schematic of the
CMOS structure.

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 LATCHUP PROBLEM IN CMOS TECHNOLOGY

The presence of npn, pnp bipolar pathways in a CMOS can lead to parasitic transistor
action and unintentional current flows.

AAAAAAAAAAAAAAA
A A A B

AA A AAA
AAAAAAAAAAAAAAA
AAA
AAA AAAAAA
+ V –

AA
AAAAAAAAAAAAAAA
AAA
AAA AAAAAAAA
I
D S S D

AAAAAAAAAAA AAAAA
p+ p+ n+ p+ n+ n+
R1
R2 p well
npn
R4
n substrate pnp

R3
(a)

Slope = 1
CURRENT, I

R3||R4

VL
(b) VOLTAGE, V

(a) A schematic of the parasitic effects that lead to CMOS latch-up problems.
(b) Current versus voltage effect. The onset of latch-up is represented by a
sharp rise in the parasitic current.

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 CAPACITANCES OF IMPORTANCE IN A MOSFET
Gate Oxide Channel

AAAAAAA
A
CGC
Source Drain
CGSO CGDO
n+ +n+ n n n n n n+ n+
n n+
n+ n + p– p– p– p– n +
p–CBC1 CGB CBD1
p– CBS1 p– – p–
p – p p– p–
p– p– p –
– – –
p Bulk (substrate) p p p–
(a)

d2
LD LD
Z
Source Drain

d1

(b) Gate

Region

Cutoff Ohmic Saturation

CGD Cox Z LD Cox Z LD + 1/2 ZL Cox Cox Z LD

CGS Cox Z LD Cox Z LD + 1/2 Z LCox Cox Z LD + 2/3 Z LCox

CBG Cox Z L 0 0
CBC1
CBD CBD1 CBD1 + CBD1
2
CBS CBS1 CBS1 + CBC1 CBS1 + 2/3 CBC1
2
(c)

A CIRUIT MODEL FOR A MOSFET Miller capacitance:

Total gate capacitance Gate-drain capacitance CM + CGD(1+gmRL)
includes overlay effects includes parasitic effects
(CGS) (CGD) Cutoff frequency:
gm
S G D fT =
2π(CGS+CM)

Source-body n+ RS RD n+
'
gmVGS Self-aligned gate
capacitance CBS CBD Drain-body technology to minimize
p-substrate capacitance CM or CGD.

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 SCALING ISSUES IN MOSFET TECHNOLOGY

PARAMETER FULL SCALING CONSTANT-VOLTAGE SCALING

Gate width, Z 1/S 1/S

Gate length, L
Oxide thickness, dox

Drain bias, VDS 1/S 1

Threshold bias, VT

Oxide capacitance 1/S 1/S

for the device

Drain current, ID ~1/S ~S

DC power consumption ~1/S2 ~S

Device switching time ~1/S ~1/S2

Power-delay product ~1/S3 ~1/S

© Prof. Jasprit Singh www.eecs.umich.edu/~singh

 SEMICONDUCTOR INDUSTRY ASSOCIATES ROADMAP

YEAR 1997 1999 2001 2003 2006 2009 2012

DRAM cell 250 180 150 130 100 70 50

half-pitch
(nm)

Gate length 200 140 120 100 70 50 35

for MPU
(nm)

Maximum 200 300 300 300 300 450 450

substrate
diameter (mm)

Acceptable 2080 1455 1310 1040 735 520 370

defect density
at 60% yield
for DRAM

Defect density 1940 1710 1510 1355 1120 940 775

for MPU

Power supply 1.8-2.5 1.5-1.8 1.2-1.5 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6

(V)

Power dissipation 70 90 110 130 160 170 175

with heat sink
(W)

Power dissipation 1.2 1.4 1.7 2.0 2.4 2.8 3.2

without heat sink
(for portable electronics)
(W)

Cost per function 120 60 30 15 5.3 1.9 0.66

DRAM (µcents/function)

Cost per function 3000 1735 1000 580 255 110 49

MPU (µcents/function)

KEY ISSUES: Gate tunneling current

Defect density
Interconnect delays will dominate

© Prof. Jasprit Singh www.eecs.umich.edu/~singh