Documente Academic
Documente Profesional
Documente Cultură
William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 3
A Top-Level View of Computer
Function and Interconnection
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Computer Components
Hardware
and Software Instruction Instruction
codes
Approaches interpreter
Control
signals
General-purpose
Data arithmetic Results
and logic
functions
Major components:
• CPU I/O
• Instruction interpreter
Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
• Input module
+ • Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
MAR
I/O address I/O buffer
register (I/OAR) register (I/OBR)
• Specifies a • Used for the
particular I/O exchange of data
+ device between an I/O
module and the
CPU
MBR
I/O AR
Data
Execution
unit Data
I/O BR
Data
Data
PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Processor- Processor-
memory I/O
Data
Control processin
g
• An instruction may • The processor may
specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data
0 1 15
S Magnitude
4. The data at address 941 are added to the AC and the PC is incremented
Multiple Multiple
operands results
Table 3.1
Classes of Interrupts
i
Interrupt
occurs here i+1
1 4 1 4 1 4
Interrupt Interrupt
2b Handler Handler
END END
3a
3 3
3b
(a) No interrupts (b) Interrupts; short I/O wait (c) Interrupts; long I/O wait
1 1
4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing
5 5
2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5
5 3b
1 1
4 4
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
Interrupts
Disabled
Check for
Fetch Next Execute
START Interrupt;
Instruction Instruction Interrupts Process Interrupt
Enabled
HALT
Multiple Multiple
operands results
No
Instruction complete, Return for string interrupt
fetch next instruction or vector data
Interrupt
handler Y
Interrupt
User program handler X
Interrupt
handler Y
15
0 t=
t =1
t = 25
t= t = 25 Disk
40 interrupt service routine
t=
35
Data N–1
External
Address M Ports Data
Internal
Data Interrupt
Signals
External
Data
Instructions Address
Control
Data CPU Signals
Interrupt Data
Signals
An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
Control lines
Data lines
I/O device
I/O Hub
DRAM
DRAM
Core Core
A B
DRAM
DRAM
Core Core
C D
I/O device
I/O device
I/O Hub
Routing Routing
Flits
Link Link
Rcv Clk
Transmission Lanes Reception Lanes
Fwd Clk
Rcv Clk
The flits can be considered as a bit stream that is distributed across the
data lanes in a round-robin fashion (first bit to first lane, second bit to
second lane, etc.)
Gigabit PCIe
Memory
Ethernet
Chipset
PCIe–PCI PCIe
Memory
Bridge
PCIe
PCIe PCIe
Switch
PCIe PCIe
Physical Physical
At each physical lane data are buffered and processed 16 bytes (128
bits) at a time
Each block is encoded into a 130 bit code word for transmission
The extra 2 bits ensure that in a long sequence of 1’s there are at least
some 0’s to provide these transitions
128b/ PCIe
B6 B2
130b lane 2
128b/ PCIe
B7 B3
130b lane 3
The data link layer sends packets between two devices that are
concerned with “bookkeeping” between the two devices.
The data link layer also adds error checking and address bits to
each TLP to ensure they arrive at the correct device
Configuration Message
This address space enables This address space is for
the TL to read/write control signals related to
configuration registers interrupts, error handling,
associated with I/O devices and power management
Appended by PL
2 Sequence number
DLLP
Created
by DLL
4
2 CRC
12 or 16 Header 1 End
0 or 4 ECRC
4 LCRC
1 STP framing