MCP6022 PDF

MCP6021/1R/2/3/4
Rail-to-Rail Input/Output, 10 MHz Op Amps

Features Description
• Rail-to-Rail Input/Output The MCP6021, MCP6021R, MCP6022, MCP6023 and
• Wide Bandwidth: 10 MHz (typical) MCP6024 from Microchip Technology Inc. are rail-to-
• Low Noise: 8.7 nV/Hz at 10 kHz (typical) rail input and output operational amplifiers with high
performance. Key specifications include: wide band-
• Low Offset Voltage:
width (10 MHz), low noise (8.7 nV/Hz), low input offset
- Industrial Temperature: ±500 µV (max.) voltage and low distortion (0.00053% THD+N). The
- Extended Temperature: ±250 µV (max.) MCP6023 also offers a Chip Select pin (CS) that gives
• Mid-Supply VREF: MCP6021 and MCP6023 power savings when the part is not in use.
• Low Supply Current: 1 mA (typical) The single MCP6021 and MCP6021R are available in
• Total Harmonic Distortion: SOT-23-5 packages. The single MCP6021, single
- 0.00053% (typical, G = 1 V/V) MCP6023 and dual MCP6022 are available in 8-lead
PDIP, SOIC and TSSOP packages. The Extended
• Unity Gain Stable
Temperature single MCP6021 is available in 8-lead
• Power Supply Range: 2.5V to 5.5V MSOP. The quad MCP6024 is offered in 14-lead PDIP,
• Temperature Range: SOIC and TSSOP packages.
- Industrial: -40°C to +85°C The MCP6021/1R/2/3/4 family is available in Industrial
- Extended: -40°C to +125°C and Extended temperature ranges. It has a power
supply range of 2.5V to 5.5V.
Applications
• Automotive
Package Types
• Multi-Pole Active Filters MCP6021 MCP6022
SOT-23-5 PDIP, SOIC, TSSOP
• Audio Processing
• DAC Buffer VOUT 1 5 VDD VOUTA 1 8 VDD
• Test Equipment VSS 2 VINA- 2 7 VOUTB
• Medical Instrumentation VIN+ 3 4 VIN- VINA+ 3 6 VINB-
VSS 4 5 VINB+
Design Aids MCP6021R
SOT-23-5 MCP6023
• SPICE Macro Models
PDIP, SOIC, TSSOP
• FilterLab® Software VOUT 1 5 VSS
• MPLAB® Mindi™ Analog Simulator VDD 2 NC 1 8 CS
• Microchip Advanced Part Selector (MAPS) VIN+ 3 4 VIN- VIN- 2 7 VDD
• Analog Demonstration and Evaluation Boards VIN+ 3 6 VOUT
• Application Notes MCP6021 VSS 4 5 VREF
PDIP, SOIC,
MSOP, TSSOP MCP6024
Typical Application PDIP, SOIC, TSSOP
5.6 pF
NC 1 8 NC
7 VDD VOUTA 1 14 VOUTD
Photo
Detector
VIN- 2
100 k VIN+ 3 6 VOUT VINA- 2 13 VIND-
VSS 4 5 V VINA+ 3 12 VIND+
REF
100 pF VDD 4 11 VSS
MCP6021 VINB+ 5 10 VINC+
VDD/2 VINB- 6 9 VINC-
Transimpedance Amplifier VOUTB 7 8 VOUTC
 2001-2017 Microchip Technology Inc. DS20001685E-page 1

MCP6021/1R/2/3/4
NOTES:
DS20001685E-page 2  2001-2017 Microchip Technology Inc.

MCP6021/1R/2/3/4
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
CHARACTERISTICS device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings† indicated in the operational listings of this specification is not
VDD – VSS ........................................................................7.0V implied. Exposure to maximum rating conditions for extended
Current Analog Input Pins (VIN+, VIN-)..........................±2 mA periods may affect device reliability.
Analog Inputs (VIN+, VIN-) ††......... VSS – 1.0V to VDD + 1.0V †† See Section 4.1.2, Input Voltage Limits.
All Other Inputs and Outputs.......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short-Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature ................................. +150°C
ESD Protection on All Pins (HBM; MM)   2 kV; 200V
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2
and RL = 10 kto VDD/2.
Parameters Sym. Min. Typ. Max. Units Conditions
Input Offset
Input Offset Voltage:
Industrial Temperature Parts VOS -500 — +500 µV VCM = 0V
Extended Temperature Parts VOS -250 — +250 µV VCM = 0V, VDD = 5.0V
Extended Temperature Parts VOS -2.5 — +2.5 mV VCM = 0V, VDD = 5.0V,
TA = -40°C to +125°C
Input Offset Voltage Temperature Drift VOS/TA — ±3.5 — µV/°C TA = -40°C to +125°C
Power Supply Rejection Ratio PSRR 74 90 — dB VCM = 0V
Input Current and Impedance
Input Bias Current: IB — 1 — pA
Industrial Temperature Parts IB — 30 150 pA TA = +85°C
Extended Temperature Parts IB — 640 5,000 pA TA = +125°C
Input Offset Current IOS — ±1 — pA
Common-Mode Input Impedance ZCM — 1013||6 — ||pF
Differential Input Impedance ZDIFF — 1013||3 — ||pF
Common-Mode
Common-Mode Input Range VCMR VSS – 0.3 — VDD + 0.3 V
Common-Mode Rejection Ratio CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 5.3V
CMRR 70 85 — dB VDD = 5V, VCM = 3.0V to 5.3V
CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 3.0V
Voltage Reference (MCP6021 and MCP6023 only)
VREF Accuracy (VREF – VDD/2) VREF_ACC -50 — +50 mV
VREF Temperature Drift VREF/TA — ±100 — µV/°C TA = -40°C to +125°C
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VCM = 0V,
VOUT = VSS + 0.3V to VDD – 0.3V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 20 mV 0.5V input overdrive
Output Short Circuit Current ISC — ±30 — mA VDD = 2.5V
ISC — ±22 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 2.5 — 5.5 V
Quiescent Current per Amplifier IQ 0.5 1.0 1.35 mA IO = 0

MCP6021/1R/2/3/4
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
RL = 10 kto VDD/2 and CL = 60 pF.
AC Response
Gain Bandwidth Product GBWP — 10 — MHz
Phase Margin PM — 65 — ° G = +1 V/V
Settling Time, 0.2% tSETTLE — 250 — ns G = +1 V/V, VOUT = 100 mVp-p
Slew Rate SR — 7.0 — V/µs
Total Harmonic Distortion Plus Noise
f = 1 kHz, G = +1 V/V THD + N — 0.00053 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),
VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +1 V/V, RL = 600 THD + N — 0.00064 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK),
VDD = 5.0V, BW = 22 kHz
f = 1 kHz, G = +1 V/V THD + N — 0.0014 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz
Noise
Input Noise Voltage Eni — 2.9 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 8.7 — nV/Hz f = 10 kHz
Input Noise Current Density ini — 3 — fA/Hz f = 1 kHz
MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, RL = 10 kto VDD/2 and CL = 60 pF.
CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2 VDD V
CS Input Current, Low ICSL -1.0 0.01 — µA CS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD — VDD V
CS Input Current, High ICSH — 0.01 2.0 µA CS = VDD
GND Current ISS -2 -0.05 — µA CS = VDD
Amplifier Output Leakage IO(LEAK) — 0.01 — µA CS = VDD
CS Dynamic Specifications
CS Low to Amplifier Output Turn-on Time tON — 2 10 µs G = +1, VIN = VSS,
CS = 0.2 VDD to VOUT = 0.45 VDD time
CS High to Amplifier Output High-Z Time tOFF — 0.01 — µs G = +1, VIN = VSS,
CS = 0.8 VDD to VOUT = 0.05 VDD time
Hysteresis VHYST — 0.6 — V VDD = 5.0V, internal switch

MCP6021/1R/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Temperature Ranges
Industrial Temperature Range TA -40 — +85 °C
Extended Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C (Note 1)
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W
Thermal Resistance, 8L-PDIP JA — 85 — °C/W
Thermal Resistance, 8L-SOIC JA — 163 — °C/W
Thermal Resistance, 8L-MSOP JA — 206 — °C/W
Thermal Resistance, 8L-TSSOP JA — 124 — °C/W
Thermal Resistance, 14L-PDIP JA — 70 — °C/W
Thermal Resistance, 14L-SOIC JA — 120 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note 1: The industrial temperature devices operate over this Extended temperature range, but with reduced performance. In any
case, the internal Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C.
1.1 Test Circuits

CS The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
tON tOFF capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.
VOUT High-Z Amplifier On High-Z
-1 mA VDD
ISS -50 nA (typical) VIN RN 0.1 µF 1 µF
-50 nA
(typical) (typical) CB1 CB2 VOUT
ICS 1 k:
MCP6021
10 nA 10 nA 10 nA
(typical) (typical) (typical) CL RL
60 pF 10 k:
VDD/2 RG RF
FIGURE 1-1: Timing Diagram for the CS VL
2 k: 2 k:
Pin on the MCP6023.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
VDD/2 RN 0.1 µF 1 µF
CB1 CB2 VOUT
1 k:
MCP6021
CL RL
60 pF 10 k:
VIN RG RF
VL
2 k: 2 k:
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.

MCP6021/1R/2/3/4
NOTES:

MCP6021/1R/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
RL = 10 k to VDD/2 and CL = 60 pF.
16%
24%
Percentage of Occurances
I-Temp 1192 Samples

14% Parts VCM = 0V 22% 1192 Samples
TA = +25°C 20% I-Temp VCM = 0V
12% 18% Parts TA = -40°C to +85°C
10% 16%
14%
8% 12%
6% 10%
8%
4% 6%
2% 4%
2%
0% 0%
100
200
300
400
500
-500
-400
-300
-200
-100
-8
-4
8
-20
-16
-12
12
16
20
Input Offset Voltage (µV) Input Offset Voltage Drift (µV/°C)
FIGURE 2-1: Input Offset Voltage FIGURE 2-4: Input Offset Voltage Drift
(Industrial Temperature Parts). (Industrial Temperature Parts).
24%
24%
22% 438 Samples

22% E-Temp 438 Samples
E-Temp VCM = 0V
Parts VDD = 5.0V 20% Parts
20% TA = -40°C to +125°C
VCM = 0V 18%
18% TA = +25°C
16% 16%
14% 14%
12% 12%
10% 10%
8% 8%
6% 6%
4% 4%
2% 2%
0%
0%
120
160
200
240
-80
-40
-240
-200
-160
-120
0
40
80
-20
-16
-12
-8
-4
12
16
20
Input Offset Voltage (µV) Input Offset Voltage Drift (µV/°C)
FIGURE 2-2: Input Offset Voltage FIGURE 2-5: Input Offset Voltage Drift
(Extended Temperature Parts). (Extended Temperature Parts).
500 500
-40°C
400 VDD = 2.5V
Input Offset Voltage (µV)
400
VDD = 5.5V +25°C

-40°C 300 +85°C
300 +25°C +125°C
200 +85°C 200
100 +125°C 100
0 0
-100 -100
-200 -200
-300 -300
-400
-400
-500
-500
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.5
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

Common Mode Input Voltage (V) Common Mode Input Voltage (V)
FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs.
Common-Mode Input Voltage with VDD = 2.5V. Common-Mode Input Voltage with VDD = 5.5V.

MCP6021/1R/2/3/4
100 200
VCM = VDD/2

50 150
0 100
-50 VDD = 5.5V
50
-100 0
-150 -50 VDD = 2.5V
-200 -100
VDD = 5.0V
-250 VCM = 0V -150
-300 -200
-50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ambient Temperature (°C) Output Voltage (V)
FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Offset Voltage vs.
Temperature. Output Voltage.
1,000 24
Input Noise Voltage Density

Input Noise Voltage Density
22 VDD = 5.0V
20
18
100 16
(nV/√Hz)
(nV/√Hz)
14 f = 1 kHz
12
10
8
10 6 f = 10 kHz
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-0.5
1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
0.1 1 10 100 1k 10k 100k 1M

Common Mode Input Voltage (V)
Frequency (Hz)
FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density
vs. Frequency. vs. Common-Mode Input Voltage.
110
100
PSRR+ 105
90 PSRR-
CMRR
PSRR, CMRR (dB)
CMRR, PSRR (dB)
80 100
70 95
60 90
CMRR 85 PSRR (VCM = 0V)
50
40 80
30 75
20 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

70
100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: CMRR, PSRR vs.
Frequency. Temperature.

MCP6021/1R/2/3/4
10,000
Input Bias, Offset Currents
Input Bias, Offset Currents (pA)

10,000
VDD = 5.5V IB, TA = +125°C VCM = VDD
VDD = 5.5V
1,000 IOS, TA = +125°C
1,000
(pA)
IB, TA = +85°C
100 100 IB
10 10 IOS
IOS, TA = +85°C
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1
Common Mode Input Voltage (V) 25 35 45 55 65 75 85 95 105 115 125
FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Input Bias, Offset Currents
vs. Common-Mode Input Voltage. vs. Temperature.
1.2
1.2
1.1
1.1
1.0 1.0 VDD = 5.5V
Quiescent Current
Quiescent Current
0.9 0.9
(mA/amplifier)
(mA/amplifier)
0.8 0.8 VDD = 2.5V

0.7 +125°C 0.7
0.6 +85°C 0.6
0.5 +25°C 0.5
-40°C
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1 VCM = VDD - 0.5V
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125
Power Supply Voltage (V) Ambient Temperature (°C)
FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: Quiescent Current vs.
Supply Voltage. Temperature.
35 120 0
110 -15
Output ShortCircuit Current
30 100 -30
Open-Loop Phase (°)

Open-Loop Gain (dB)
90 -45
25 80 -60
70 Phase -75
20 60 -90
(mA)
50 -105
15 40 -120
+125°C
+85°C 30 -135
10 Gain
+25°C 20 -150
-40°C 10 -165
5 0 -180
-10 -195
0 -20 1.E+00 1.E+01 1.E+02 1.E+03 -210
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1k 10k 100k 1M 10M 100M
Supply Voltage (V) Frequency (Hz)
FIGURE 2-15: Output Short-Circuit Current FIGURE 2-18: Open-Loop Gain, Phase vs.
vs. Supply Voltage. Frequency.

MCP6021/1R/2/3/4
130 120
DC Open-Loop Gain (dB)

VDD = 5.5V
115
120 VDD = 5.5V
110
110
VDD = 2.5V
105
100 VDD = 2.5V
100
90
95
80 1.E+02 1.E+03 1.E+04 1.E+05
90
100 1k 10k 100k
Ω)
Load Resistance (Ω -50 -25 0 25 50 75 100 125
FIGURE 2-19: DC Open-Loop Gain vs. FIGURE 2-22: DC Open-Loop Gain vs.
Load Resistance. Temperature.
120 14 105
VCM = VDD/2
Gain Bandwidth Product (MHz)
Phase Margin, G = +1 (°)

12 Gain Bandwidth Product 90
110
VDD = 5.5V 10 75
100
8 60
90 6 Phase Margin, G = +1 45
VDD = 2.5V
80 4 30
2 15
70 VDD = 5.0V
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 0
Output Voltage Headroom (V); 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD - VOH or VOL - VSS Common Mode Input Voltage (V)
FIGURE 2-20: Small Signal DC Open-Loop FIGURE 2-23: Gain Bandwidth Product,
Gain vs. Output Voltage Headroom. Phase Margin vs. Common-Mode Input Voltage.
10 100 14 105
9 90

12 Gain Bandwidth Product 90

8 80
7 70 10 75
6 60 8 60
Phase Margin, G = +1
5 50
GBWP, VDD = 5.5V 6 45
4 40
GBWP, VDD = 2.5V
3 30 4 30
PM, VDD = 2.5V
2 PM, VDD = 5.5V
20 VDD = 5.0V
2 VCM = VDD/2 15
1 10
0 0 0 0
-50 -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Ambient Temperature (°C) Output Voltage (V)
FIGURE 2-21: Gain Bandwidth Product, FIGURE 2-24: Gain Bandwidth Product,
Phase Margin vs. Temperature. Phase Margin vs. Output Voltage.

MCP6021/1R/2/3/4
11 10
10 Falling, VDD = 5.5V
Maximum Output Voltage

Rising, VDD = 5.5V
9 VDD = 5.5V
Slew Rate (V/µs)
Swing (VP-P)
7 VDD = 2.5V
6
5 1
4 Falling, VDD = 2.5V
3 Rising, VDD = 2.5V
2
1
0
-50 -25 0 25 50 75 100 125 0.1 1.E+04 1.E+05 1.E+06 1.E+07
10k 100k 1M 10M

Ambient Temperature (°C) Frequency (Hz)
FIGURE 2-25: Slew Rate vs. Temperature. FIGURE 2-28: Maximum Output Voltage
Swing vs. Frequency.
0.1000% 0.1000%
f = 1 kHz G = +100 V/V
BWMeas = 22 kHz
VDD = 5.0V
THD+N (%)
0.0100% G = +10 V/V
THD+N (%)
G = +100 V/V 0.0100%
G = +10 V/V
0.0010% 0.0010% G = +1 V/V
f = 20 kHz
BWMeas = 80 kHz
VDD = 5.0V
G = +1 V/V
0.0001%
0.0001%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (VP-P)
Output Voltage (VP-P)
FIGURE 2-26: Total Harmonic Distortion FIGURE 2-29: Total Harmonic Distortion
plus Noise vs. Output Voltage with f = 1 kHz. plus Noise vs. Output Voltage with f = 20 kHz.
6
135
Channel-to-Channel Separation
VDD = 5.0V
VOUT G = +2 V/V
Input, Output Voltage (V)
5
130
4 VIN
125
3
(dB)
120
2
115
1
110
0 G = +1 V/V
105 1.E+03 1.E+04 1.E+05 1.E+06
-1 1k 10k 100k 1M
Frequency (Hz)
0 10 20 Time
30 (10
40 µs/div)
50 60 70 80 90 100
FIGURE 2-27: The MCP6021/1R/2/3/4 FIGURE 2-30: Channel-to-Channel

Family Shows No Phase Reversal Under Separation vs. Frequency (MCP6022 and
Overdrive. MCP6024 only).

MCP6021/1R/2/3/4
1,000 10
VDD – VOH or VOL – VSS (mV)

Output Voltage Headroom
VDD – VOH or VOL – VSS (mV)
Output Voltage Headroom;
9 VOL – VSS
8
100 7
6
VDD – VOH
5
4
10 VOL – VSS 3
2
VDD – VOH 1
1 0
0.01 0.1 1 10 -50 -25 0 25 50 75 100 125
Output Current Magnitude (mA) Ambient Temperature (°C)
FIGURE 2-31: Output Voltage Headroom FIGURE 2-34: Output Voltage Headroom
vs. Output Current. vs. Temperature.
6.E-02
6.E-02
5.E-02
G = +1 V/V 5.E-02
G = -1 V/V
Output Voltage (10 mV/div)
RF = 1 kΩ
Output Voltage (10 mV/div)

4.E-02 4.E-02
3.E-02 3.E-02
2.E-02
2.E-02
1.E-02
1.E-02
0.E+00
0.E+00
-1.E-02
-1.E-02
-2.E-02
-2.E-02
-3.E-02
-3.E-02
-4.E-02
-4.E-02
-5.E-02
-5.E-02
-6.E-02
0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06
-6.E-02
0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06
Time (200 ns/div)
Time (200 ns/div)
FIGURE 2-32: Small Signal Non-Inverting FIGURE 2-35: Small Signal Inverting Pulse
Pulse Response. Response.
5.0 5.0
G = +1 V/V G = -1 V/V
4.5 4.5 RF = 1 kΩ
4.0 4.0
Output Voltage (V)
Output Voltage (V)
3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5
1.0
1.0
0.5
0.5
0.0 0.E+00 5.E-07 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06
0.0 0.E+00 5.E-07 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06
Time (500 ns/div)
Time (500 ns/div)
FIGURE 2-33: Large Signal Non-Inverting FIGURE 2-36: Large Signal Inverting Pulse
Pulse Response. Response.

MCP6021/1R/2/3/4
50 50
40 40 Representative Part
30 30
VREF – VDD/2 (mV)
VREF – VDD/2 (mV)

VREF Accuracy;
VREF Accuracy;
20 20 VDD = 5.5V
10 10
0 0
-10 -10 VDD = 2.5V
-20 -20
-30 -30
-40 -40
-50 -50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125
Power Supply Voltage (V) Ambient Temperature (°C)
FIGURE 2-37: VREF Accuracy vs. Supply FIGURE 2-40: VREF Accuracy vs.
Voltage (MCP6021 and MCP6023 only). Temperature (MCP6021 and MCP6023 only).
1.6 1.6
Op Amp Op Amp
1.4 Op Amp Op Amp
shuts off here 1.4 turns on here
turns on here shuts off here
Quiescent Current
1.2
(mA/amplifier)
1.2
Quiescent Current
(mA/amplifier)
1.0 Hysteresis
CS swept Hysteresis 1.0
0.8 high to low CS swept
0.8
0.6 high to low CS swept
CS swept 0.6 low to high
0.4 VDD = 2.5V low to high
G = +1 V/V 0.4 VDD = 5.5V
0.2 VIN = 1.25V G = +1 V/V
0.2 VIN = 2.75V
0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0
Chip Select Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
FIGURE 2-38: Chip Select (CS) Hysteresis FIGURE 2-41: Chip Select (CS) Hysteresis
(MCP6023 only) with VDD = 2.5V. (MCP6023 only) with VDD = 5.5V.
5.5
5.0 VDD = 5.0V 10m
1.E-02
Input Current Magnitude (A)
G = +1 V/V 1m
4.5 CS Voltage
VIN = VSS
1.E-03
Chip Select Voltage,
Output Voltage (V)
4.0 100µ
1.E-04
3.5 10µ
1.E-05
3.0 VOUT 1µ
1.E-06
2.5 100n
1.E-07
2.0
10n
1.E-08
1.5 Output Output High-Z Output
1n +125°C
1.0 on on 1.E-09
+85°C
0.5 100p
1.E-10 +25°C
0.0 10p -40°C
1.E-11
-0.5 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05
1p
1.E-12
Time (5 µs/div)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-39: Chip Select (CS) to
Amplifier Output Response Time (MCP6023 FIGURE 2-42: Measured Input Current vs.
Only). Input Voltage (Below VSS)

MCP6021/1R/2/3/4
NOTES:

MCP6021/1R/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE

MCP6021 MCP6021 MCP6022 MCP6023 MCP6024
PDIP, SOIC, Symbol Description

PDIP, SOIC, PDIP, SOIC, PDIP, SOIC,
MSOP, SOT-23-5 SOT-23-5(2)
TSSOP TSSOP TSSOP
TSSOP(1)
6 1 1 1 6 1 VOUT, VOUTA Analog Output (Op Amp A)

2 4 4 2 2 2 VIN-, VINA- Inverting Input (Op Amp A)
3 3 3 3 3 3 VIN+, VINA+ Non-Inverting Input (Op Amp A)
7 5 2 8 7 4 VDD Positive Power Supply
— — — 5 — 5 VINB+ Non-Inverting Input (Op Amp B)
— — — 6 — 6 VINB– Inverting Input (Op Amp B)
— — — 7 — 7 VOUTB Analog Output (Op Amp B)
— — — — — 8 VOUTC Analog Output (Op Amp C)
— — — — — 9 VINC– Inverting Input (Op Amp C)
— — — — — 10 VINC+ Non-Inverting Input (Op Amp C)
4 2 5 4 4 11 VSS Negative Power Supply
— — — — — 12 VIND+ Non-Inverting Input (Op Amp D)
— — — — — 13 VIND– Inverting Input (Op Amp D)
— — — — — 14 VOUTD Analog Output (Op Amp D)
5 — — — 5 — VREF Reference Voltage
— — — — 8 — CS Chip Select
1, 8 — — — 1 — NC No Internal Connection
Note 1: The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts.
2: The MCP6021R is only available in the 5-pin SOT-23 package and for E-temp (Extended Temperature) parts.
3.1 Analog Outputs 3.4 Chip Select Digital Input (CS)

The operational amplifier output pins are low-impedance This is a CMOS, Schmitt triggered input that places the
voltage sources. part into a Low-Power mode of operation.
3.2 Analog Inputs 3.5 Power Supply (VSS and VDD)

The operational amplifier non-inverting and inverting The positive power supply pin (VDD) is 2.5V to 5.5V
inputs are high-impedance CMOS inputs with low bias higher than the negative power supply pin (VSS). For
currents. normal operation, the other pins are at voltages
between VSS and VDD.
3.3 Reference Voltage (VREF) Typically, these parts are used in a single (positive)
MCP6021 and MCP6023 supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
Mid-supply reference voltage is provided by the single need a bypass capacitor.
operational amplifiers (except in the SOT-23-5
package). This is an unbuffered, resistor voltage divider
internal to the part.

MCP6021/1R/2/3/4
NOTES:

MCP6021/1R/2/3/4
4.0 APPLICATIONS INFORMATION
VDD
The MCP6021/1R/2/3/4 family of operational amplifiers
is fabricated on Microchip’s state-of-the-art CMOS
process. The amplifiers are unity-gain stable and suitable D1 D2 U1
for a wide range of general purpose applications.
V1
4.1 Rail-to-Rail Input MCP602X VOUT
V2
4.1.1 PHASE REVERSAL
The MCP6021/1R/2/3/4 operational amplifiers are FIGURE 4-2: Protecting the Analog Inputs.
designed to prevent phase reversal when the input pins
exceed the supply voltages. Figure 2-42 shows the 4.1.3 INPUT CURRENT LIMITS
input voltage exceeding the supply voltage without any
phase reversal. In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
4.1.2 INPUT VOLTAGE LIMITS the input pins. See the Absolute Maximum Ratings†
section. Figure 4-3 shows one approach to protecting
In order to prevent damage and/or improper operation these inputs. The resistors, R1 and R2, limit the pos-
of these amplifiers, the circuit must limit the voltages at sible currents in or out of the input pins (and the ESD
the input pins. See the Absolute Maximum Ratings† diodes, D1 and D2). The diode currents will go through
section. either VDD or VSS.
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize Input Bias VDD
(IB) current.
D1 D2 U1
Bond V1
VDD VOUT
Pad R1
MCP602X
V2
R2
Bond Input Bond
VIN+ VIN
Pad Stage Pad VSS – min (V1,V2)
min(R1,R2) >
2 mA
max(V1,V2) – VDD
min(R1,R2) >
VSS Bond 2 mA
Pad
FIGURE 4-3: Protecting the Analog Inputs.
FIGURE 4-1: Simplified Analog Input ESD
4.1.4 NORMAL OPERATION
Structures.
The input stage of the MCP6021/1R/2/3/4 operational
The input ESD diodes clamp the inputs when they try amplifiers uses two differential CMOS input stages in
to go more than one diode drop below VSS. They also parallel. One operates at a low Common-Mode Voltage
clamp any voltages that go well above VDD. Their (VCM) input, while the other operates at high VCM. With
breakdown voltage is high enough to allow normal this topology, the device operates with VCM up to 0.3V
operation, but not low enough to protect against slow above VDD and 0.3V below VSS.
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the specifications) are limited so that
damage does not occur. In some applications, it may
4.2 Rail-to-Rail Output
be necessary to prevent excessive voltages from The maximum output voltage swing is the maximum
reaching the operational amplifier inputs. Figure 4-2 swing possible under a particular output load. According
shows one approach to protecting these inputs. to the specification table, the output can reach within
A significant amount of current can flow out of the 20 mV of either supply rail when RL = 10 k. See
inputs when the Common-Mode Voltage (VCM) is below Figure 2-31 and Figure 2-34 for more information
ground (VSS). See Figure 2-42. concerning typical performance.

MCP6021/1R/2/3/4
4.3 Capacitive Loads 4.4 Gain Peaking
Driving large capacitive loads can cause stability Figure 2-35 and Figure 2-36 use RF = 1 k to avoid
problems for voltage feedback operational amplifiers. (frequency response) gain peaking and (step response)
As the load capacitance increases, the feedback loop’s overshoot. The capacitance to ground at the inverting
phase margin decreases and the closed loop input (CG) is the op amp’s Common-mode input capaci-
bandwidth is reduced. This produces gain peaking in tance plus board parasitic capacitance. CG is in parallel
the frequency response, with overshoot and ringing in with RG, which causes an increase in gain at high frequen-
the step response. cies for non-inverting gains greater than 1 V/V (unity
When driving large capacitive loads with these opera- gain). CG also reduces the phase margin of the feedback
tional amplifiers (e.g., > 60 pF when G = +1), a small loop for both non-inverting and inverting gains.
series resistor at the output (RISO in Figure 4-4)
improves the feedback loop’s phase margin (stability) VIN
by making the load resistive at higher frequencies. The VOUT
bandwidth will be generally lower than the bandwidth
with no capacitive load.
RF
CG
VIN RISO RG
MCP602X VOUT
CL
FIGURE 4-6: Non-Inverting Gain Circuit
with Parasitic Capacitance.
FIGURE 4-4: Output Resistor, RISO, The largest value of RF in Figure 4-6 that should be
Stabilizes Large Capacitive Loads. used is a function of noise gain (see GN in Section 4.3
“Capacitive Loads”) and CG. Figure 4-7 shows results
Figure 4-5 gives recommended RISO values for for various conditions. Other compensation techniques
different capacitive loads and gains. The x-axis is the may be used, but they tend to be more complicated to
normalized load capacitance (CL/GN), where GN is the design.
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is 1.E+05
100k
GN > +1 V/V
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
Maximum RF (W)
1,000 1.E+04
10k CG = 7 pF
CG = 20 pF
GN ≥ +1
Recommended RISO (Ω)
1.E+03
1k
CG = 50 pF
100 CG = 100 pF
1.E+02
100
1 10
Noise Gain; GN (V/V)
10 FIGURE 4-7: Non-Inverting Gain Circuit

10 100 1,000 10,000
Normalized Capacitance; CL/GN (pF)
with Parasitic Capacitance.
FIGURE 4-5: Recommended RISO Values 4.5 MCP6023 Chip Select (CS)
for Capacitive Loads. The MCP6023 is a single amplifier with Chip Select
After selecting RISO for your circuit, double-check the (CS). When CS is pulled high, the supply current drops
resulting frequency response peaking and step to 10 nA (typical) and flows through the CS pin to VSS.
response overshoot. Modify RISO’s value until the When this happens, the amplifier output is put into a
response is reasonable. Evaluation on the bench and high-impedance state. By pulling CS low, the amplifier
simulations with the MCP6021/1R/2/3/4 Spice macro is enabled. The CS pin has an internal 5 MΩ (typical)
model are helpful. pull-down resistor connected to VSS, so it will go low if
the CS pin is left floating. Figure 1-1 and Figure 2-39
show the output voltage and supply current response to
a CS pulse.

MCP6021/1R/2/3/4
4.6 MCP6021 and MCP6023 Reference
Voltage RG RF
VIN VOUT
The single operational amplifiers (MCP6021 and
MCP6023), not in the SOT-23-5 package, have an
internal mid-supply reference voltage connected to the
VREF pin (see Figure 4-8). The MCP6021 has CS inter- VREF
nally tied to VSS, which always keeps the operational
amplifier on and always provides a mid-supply refer-
CB
ence. With the MCP6023, taking the CS pin high
conserves power by shutting down both the operational
amplifier and the VREF circuitry. Taking the CS pin low
turns on the operational amplifier and VREF circuitry. FIGURE 4-10: Inverting Gain Circuit Using
VREF (MCP6021 and MCP6023 only).
VDD If you don’t need the mid-supply reference, leave the
VREF pin open.
50 k
4.7 Supply Bypass
VREF With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
50 k bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
CS
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
5 M
4.8 Unused Operational Amplifiers
An unused operational amplifier in a quad package
VSS (MCP6024) should be configured as shown in
Figure 4-11. These circuits prevent the output from tog-
(CS tied internally to VSS for MCP6021) gling and causing crosstalk. Circuit A sets the opera-
tional amplifier at its minimum noise gain. The resistor
FIGURE 4-8: Simplified Internal VREF divider produces any desired reference voltage within
Circuit (MCP6021 and MCP6023 only). the output voltage range of the operational amplifier.
The operational amplifier buffers that reference
See Figure 4-9 for a non-inverting gain circuit using the
voltage. Circuit B uses the minimum number of compo-
internal mid-supply reference. The DC Blocking nents and operates as a comparator, but it may draw
Capacitor (CB) also reduces noise by coupling the more current.
operational amplifier input to the source.
¼ MCP6024 (A) ¼ MCP6024 (B)

RG RF
VDD VDD
VDD
VOUT R1
CB VREF
VREF
VIN R2
FIGURE 4-9: Non-Inverting Gain Circuit

Using VREF (MCP6021 and MCP6023 only). R2
V REF = V DD + --------------------
R1 + R2
To use the internal mid-supply reference for an
inverting gain circuit, connect the VREF pin to the
non-inverting input, as shown in Figure 4-10. The FIGURE 4-11: Unused Operational
capacitor, CB, helps reduce power supply noise on the Amplifiers.
output.

MCP6021/1R/2/3/4
4.9 PCB Surface Leakage Use a solid ground plane and connect the bypass local
capacitor(s) to this plane with minimal length traces.
In applications where low input bias current is critical, This cuts down inductive and capacitive crosstalk.
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by Separate digital from analog, low speed from high
humidity, dust or other contamination on the board. speed and low power from high power. This will reduce
Under low humidity conditions, a typical resistance interference.
between nearby traces is 1012. A 5V difference would Keep sensitive traces short and straight. Separate
cause 5 pA of current to flow, which is greater than the them from interfering components and traces. This is
MCP6021/1R/2/3/4 family’s bias current at +25°C especially important for high-frequency (low rise time)
(1 pA, typical). signals.
The easiest way to reduce surface leakage is to use a Sometimes it helps to place guard traces next to victim
guard ring around sensitive pins (or traces). The guard traces. They should be on both sides of the victim trace
ring is biased at the same voltage as the sensitive pin. and as close as possible. Connect the guard trace to
Figure 4-12 shows an example of this type of layout. the ground plane at both ends and in the middle for long
traces.
Guard Ring VIN- VIN+ Use coax cables (or low-inductance wiring) to route
signal and power to and from the PCB.
4.11 Typical Applications

4.11.1 A/D CONVERTER DRIVER AND
ANTI-ALIASING FILTER
FIGURE 4-12: Example Guard Ring Layout.
Figure 4-13 shows a third-order Butterworth filter that
can be used as an A/D Converter driver. It has a band-
1. Non-Inverting Gain and Unity Gain Buffer.
width of 20 kHz and a reasonable step response. It will
a) Connect the guard ring to the inverting input work well for conversion rates of 80 ksps and greater (it
pin (VIN-); this biases the guard ring to the has 29 dB attenuation at 60 kHz).
Common-mode input voltage.
b) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the 1.0 nF
PCB surface.
8.45 k 14.7 k 33.2 k MCP602X
2. Inverting (Figure 4-12) and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors). 1.2 nF 100 pF
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the FIGURE 4-13: A/D Converter Driver and
operational amplifier’s input (e.g., VDD/2 or Anti-Aliasing Filter with a 20 kHz Cutoff
ground). Frequency.
b) Connect the inverting pin (VIN-) to the input
with a wire that does not touch the PCB This filter can easily be adjusted to another bandwidth
surface. by multiplying all capacitors by the same factor.
Alternatively, the resistors can all be scaled by another
common factor to adjust the bandwidth.
4.10 High-Speed PCB Layout
Due to their speed capabilities, a little extra care in the
PCB (Printed Circuit Board) layout can make a signifi-
cant difference in the performance of these operational
amplifiers. Good PC board layout techniques will help
you achieve the performance shown in Section 1.0
“Electrical Characteristics” and Section 2.0 “Typical
Performance Curves”, while also helping you minimize
EMC (Electro-Magnetic Compatibility) issues.

MCP6021/1R/2/3/4
4.11.2 OPTICAL DETECTOR AMPLIFIER
Figure 4-14 shows the MCP6021 operational amplifier 5.6 pF
Photo
used as a transimpedance amplifier in a photo detector Detector
circuit. The photo detector looks like a capacitive 100 k
current source, so the 100 k resistor gains the input
signal to a reasonable level. The 5.6 pF capacitor
stabilizes this circuit and produces a flat frequency 100 pF
response with a bandwidth of 370 kHz.
MCP6021
VDD/2
FIGURE 4-14: Transimpedance Amplifier

for an Optical Detector.

MCP6021/1R/2/3/4
NOTES:

MCP6021/1R/2/3/4
5.0 DESIGN AIDS 5.5 Analog Demonstration and
Evaluation Boards
Microchip provides the basic design tools needed for
the MCP6021/1R/2/3/4 family of operational amplifiers. Microchip offers a broad spectrum of analog demon-
stration and evaluation boards that are designed to
5.1 SPICE Macro Model help you achieve faster time to market. For a complete
listing of these boards, and their corresponding user’s
The latest SPICE macro model available for the guides and technical information, visit the Microchip
MCP6021/1R/2/3/4 operational amplifiers is on web site at www.microchip.com/analogtools.
Microchip’s web site at www.microchip.com. This
model is intended as an initial design tool that works Some boards that are especially useful are:
well in the operational amplifier’s linear region of oper- • MCP6XXX Amplifier Evaluation Board 1
ation at room temperature. There is information on its • MCP6XXX Amplifier Evaluation Board 2
capabilities within the macro model file. • MCP6XXX Amplifier Evaluation Board 3
Bench testing is a very important part of any design and • MCP6XXX Amplifier Evaluation Board 4
cannot be replaced with simulations. Also, simulation • Active Filter Demo Board Kit
results using this macro model need to be validated by
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
comparing them to the data sheet specifications and
P/N: SOIC8EV
characteristic curves.
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N: SOIC14EV
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative software 5.6 Application Notes
tool that simplifies analog active filter (using operational
amplifiers) design. Available at no cost from the The following Microchip Application Notes are
Microchip web site at www.microchip.com/filterlab, the available on the Microchip web site at www.microchip.
FilterLab design tool provides full schematic diagrams of com/appnotes and are recommended as supplemental
the filter circuit with component values. It also outputs reference resources.
the filter circuit in SPICE format, which can be used with • ADN003, “Select the Right Operational Amplifier
the macro model to simulate actual filter performance. for your Filtering Circuits” (DS21821)
• AN722, “Operational Amplifier Topologies and DC
5.3 MPLAB® Mindi™ Analog Specifications” (DS00722)
Simulator • AN723, “Operational Amplifier AC Specifications
and Applications” (DS00723)
Microchip’s Mindi™ circuit designer and simulator aids
in the design of various circuits useful for active filter, • AN884, “Driving Capacitive Loads With Op Amps”
amplifier and power management applications. It is a (DS00884)
free online circuit designer and simulator available from • AN990, “Analog Sensor Conditioning Circuits –
the Microchip web site at www.microchip.com/mindi. An Overview” (DS00990)
This interactive circuit designer and simulator enables • AN1177, “Op Amp Precision Design: DC Errors”
designers to quickly generate circuit diagrams and (DS01177)
simulate circuits. Circuits developed using the MPLAB • AN1228, “Op Amp Precision Design: Random
Mindi analog simulator can be downloaded to a Noise” (DS01228)
personal computer or workstation.
These application notes and others are listed in the
design guide: “Signal Chain Design Guide” (DS21825).
5.4 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor pro-
fessionals efficiently identify Microchip devices that fit a
particular design requirement. Available at no cost from
the Microchip web site at www.microchip.com/maps,
the MAPS is an overall selection tool for Microchip’s
product portfolio, that includes analog, memory, MCUs
and DSCs. Using this tool you can define a filter to sort
features for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchasing and
sampling of Microchip parts.

MCP6021/1R/2/3/4
NOTES:

MCP6021/1R/2/3/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
5-Lead SOT-23 (MCP6021/MCP6021R) Example:
Device E-Temp Code

MCP6021 EYNN EY25
MCP6021R EZNN
Note: Applies to 5-Lead SOT-23.
8-Lead PDIP (300 mil) Example:
MCP6021 MCP6021
OR
I/P256 E/P e3 256
1603 1603
8-Lead SOIC (150 mil) Example:
MCP6021 OR MCP6021E
I/SN1603 SN e3 1603
256 256
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP6021/1R/2/3/4
Package Marking Information (Continued)
8-Lead MSOP Example:
6021E
903256
8-Lead TSSOP Example:
6021
E903
256
14-Lead PDIP (300 mil) (MCP6024) Example:
MCP6024-I/P
0903256
OR
MCP6024-E/P e3
0903256

MCP6021/1R/2/3/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6024) Example:
MCP6024-I/SL
1603256
OR
MCP6024
E/SL e3
1603256
14-Lead TSSOP (MCP6024) Example:
6024E
1603
256

MCP6021/1R/2/3/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A D
E/2
E1/2
E1 E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1 1 2
B NX b
0.20 C A-B D
TOP VIEW
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2 C
A1
SIDE VIEW
Microchip Technology Drawing C04-028D [OT] Sheet 1 of

MCP6021/1R/2/3/4
T
L
L1
VIEW A-A
SHEET 1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 6
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 - 1.30
Standoff A1 - - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 - 0.60
Footprint L1 0.60 REF
Foot Angle I 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091D [OT] Sheet 2 of

MCP6021/1R/2/3/4
5 SILK SCREEN
Z C G
1 2
E
GX
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X5) X 0.60
Contact Pad Length (X5) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90
Notes:
Microchip Technology Drawing No. C04-2091A [OT]

MCP6021/1R/2/3/4
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
D A
N B
E1
NOTE 1
1 2
TOP VIEW
C A A2
PLANE
L c
A1
e eB
8X b1
8X b
.010 C
SIDE VIEW END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2

MCP6021/1R/2/3/4
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)
DATUM A DATUM A
b b
e e
2 2
e e
Units INCHES
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2

MCP6021/1R/2/3/4

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NOTES:

MCP6021/1R/2/3/4
APPENDIX A: REVISION HISTORY Revision B (November 2003)
• Second Release of this Document
Revision E (January 2017)
The following is the list of modifications: Revision A (November 2001)
1. Updated the AC Electrical Characteristics table. • Original Release of this Document
2. Added Section 4.1.2, Input Voltage Limits and
Section 4.1.3, Input Current Limits.
3. Added package information for 8-pin TSSOP.
4. Various typographical edits.
Revision D (February 2009)

The following is the list of modifications:
1. Changed all references to 6.0V back to 5.5V
throughout document.
2. Design Aids: Name change for Mindi Simulation
Tool.
3. Section 1.0, Electrical Characteristics, Section
“”: Corrected “Maximum Output Voltage Swing”
condition from 0.9V Input Overdrive to 0.5V
Input Overdrive.
“AC Electrical Characteristics”: Changed
Phase Margin condition from G = +1 to G= +1 V/V.
“AC Electrical Characteristics”: Changed
Settling Time, 0.2% condition from G = +1 to
G = +1 V/V.
6. Section 1.0, Electrical Characteristics: Added
Section 1.1, Test Circuits
7. Section 5.0, Design Aids: Name change for
Mindi Simulation Tool. Added new boards to
Section 5.5, Analog Demonstration and Evalua-
tion Boards and new application notes to
Section 5.6, Application Notes.
8. Updates Appendix A: “Revision History”
Revision C (December 2005)

The following is the list of modifications:
1. Added SOT-23-5 package option for single op
amps MCP6021 and MCP6021R (E-temp only).
2. Added MSOP-8 package option for E-temp
single op amp (MCP6021).
3. Corrected package drawing on front page for
dual op amp (MCP6022).
4. Clarified spec conditions (ISC, PM and THD+N)
in Section 2.0, Typical Performance Curves.
5. Added Section 3.0, Pin Descriptions.
6. Updated Section 4.0, Applications Information
for THD+N, unused op amps, and gain peaking
discussions.
7. Corrected and updated package marking infor-
mation in Section 6.0, Packaging Information.
8. Added Appendix A: “Revision History”.

MCP6021/1R/2/3/4
NOTES:

MCP6021/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) X /XX Examples:

a) MCP6021T-E/OT: Tape and Reel,
Device Tape and Reel Temperature Package Extended temperature,
Option Range 5LD SOT-23.
b) MCP6021-E/P: Extended temperature,
8LD PDIP.
Device: MCP6021 Single Op Amp c) MCP6021-E/SN: Extended temperature,
8LD SOIC.
MCP6021T Single Op Amp
(Tape and Reel for SOT-23, SOIC, TSSOP, a) MCP6021RT-E/OT: Tape and Reel,
MSOP) Extended temperature,
MCP6021R Single Op Amp 5LD SOT-23.
MCP6021RT Single Op Amp
(Tape and Reel for SOT-23) a) MCP6022-I/P: Industrial temperature,
8LD PDIP.
MCP6022 Dual Op Amp
b) MCP6022-E/P: Extended temperature,
MCP6022T Dual Op Amp
8LD PDIP.
(Tape and Reel for SOIC and TSSOP)
c) MCP6022T-E/ST: Tape and Reel,
MCP6023 Single Op Amp w/CS
Extended temperature,
MCP6023T Single Op Amp w/CS 8LD TSSOP.
(Tape and Reel for SOIC and TSSOP)
MCP6024 Quad Op Amp a) MCP6023-I/P: Industrial temperature,
MCP6024T Quad Op Amp 8LD PDIP.
(Tape and Reel for SOIC and TSSOP) b) MCP6023-E/P: Extended temperature,
8LD PDIP.
c) MCP6023-E/SN: Extended temperature,
Tape and Reel Blank = Standard packaging (tube or tray) 8LD SOIC.
Option: T = Tape and Reel(1)
a) MCP6024-I/SL: Industrial temperature,
14LD SOIC.
Temperature I = -40C to +85C (Industrial) b) MCP6024-E/SL: Extended temperature,
Range: E = -40C to +125C (Extended) 14LD SOIC.
c) MCP6024T-E/ST: Tape and Reel,
Extended temperature,
Package: OT = Plastic Small Outline Transistor (SOT-23), 5-Lead 14LD TSSOP.
(MCP6021, E-Temp; MCP6021R, E-Temp)
MS = Plastic MSOP, 8-Lead (MCP6021, E-Temp)
Note 1: Tape and Reel identifier only appears in the
P = Plastic DIP (300 mil Body), 8-Lead, 14-Lead catalog part number description. This identi-
SN = Plastic SOIC (150 mil Body), 8-Lead fier is used for ordering purposes and is not
SL = Plastic SOIC (150 mil Body), 14-Lead printed on the device package. Check with
ST = Plastic TSSOP, 8-Lead (MCP6021, I-Temp; MCP6022, your Microchip Sales Office for package
I-Temp, E-Temp; MCP6023, I-Temp, E-Temp) availability with the Tape and Reel option.
ST = Plastic TSSOP, 14-Lead

MCP6021/1R/2/3/4
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A.
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip
and India. The Company’s quality system processes and procedures Technology Inc. in other countries.
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
and manufacture of development systems is ISO 9001:2000 certified.
Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.

© 2001-2017, Microchip Technology Incorporated, All Rights
CERTIFIED BY DNV Reserved.
ISBN: 978-1-5224-1278-6
== ISO/TS 16949 ==

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11/07/16

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MCP6021/1R/2/3/4

Rail-to-Rail Input/Output, 10 MHz Op Amps

 2001-2017 Microchip Technology Inc. DS20001685E-page 1

DS20001685E-page 2  2001-2017 Microchip Technology Inc.

 2001-2017 Microchip Technology Inc. DS20001685E-page 3

MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS

DS20001685E-page 4  2001-2017 Microchip Technology Inc.

1.1 Test Circuits

 2001-2017 Microchip Technology Inc. DS20001685E-page 5

DS20001685E-page 6  2001-2017 Microchip Technology Inc.

I-Temp 1192 Samples

22% 438 Samples

VDD = 5.5V +25°C

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

 2001-2017 Microchip Technology Inc. DS20001685E-page 7

Input Offset Voltage (µV)

Input Noise Voltage Density

1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

0.1 1 10 100 1k 10k 100k 1M

20 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

DS20001685E-page 8  2001-2017 Microchip Technology Inc.

Input Bias, Offset Currents (pA)

0.8 0.8 VDD = 2.5V

Open-Loop Phase (°)

 2001-2017 Microchip Technology Inc. DS20001685E-page 9

DC Open-Loop Gain (dB)

80 1.E+02 1.E+03 1.E+04 1.E+05

Gain Bandwidth Product (MHz)

Phase Margin, G = +1 (°)

Phase Margin, G = +1 (°)

Phase Margin, G = +1 (°)

12 Gain Bandwidth Product 90

DS20001685E-page 10  2001-2017 Microchip Technology Inc.

Maximum Output Voltage

10k 100k 1M 10M

0.0100% G = +10 V/V

FIGURE 2-27: The MCP6021/1R/2/3/4 FIGURE 2-30: Channel-to-Channel

 2001-2017 Microchip Technology Inc. DS20001685E-page 11

VDD – VOH or VOL – VSS (mV)

Output Voltage (10 mV/div)

Output Voltage (V)

DS20001685E-page 12  2001-2017 Microchip Technology Inc.

VREF – VDD/2 (mV)

 2001-2017 Microchip Technology Inc. DS20001685E-page 13

DS20001685E-page 14  2001-2017 Microchip Technology Inc.

TABLE 3-1: PIN FUNCTION TABLE

PDIP, SOIC, Symbol Description

6 1 1 1 6 1 VOUT, VOUTA Analog Output (Op Amp A)

3.1 Analog Outputs 3.4 Chip Select Digital Input (CS)

3.2 Analog Inputs 3.5 Power Supply (VSS and VDD)

 2001-2017 Microchip Technology Inc. DS20001685E-page 15

DS20001685E-page 16  2001-2017 Microchip Technology Inc.

 2001-2017 Microchip Technology Inc. DS20001685E-page 17

10 FIGURE 4-7: Non-Inverting Gain Circuit

DS20001685E-page 18  2001-2017 Microchip Technology Inc.

¼ MCP6024 (A) ¼ MCP6024 (B)

FIGURE 4-9: Non-Inverting Gain Circuit

 2001-2017 Microchip Technology Inc. DS20001685E-page 19

4.11 Typical Applications

DS20001685E-page 20  2001-2017 Microchip Technology Inc.

FIGURE 4-14: Transimpedance Amplifier

 2001-2017 Microchip Technology Inc. DS20001685E-page 21

DS20001685E-page 22  2001-2017 Microchip Technology Inc.

Microchip Technology Drawing C04-028D [OT] Sheet 1 of

Microchip Technology Drawing C04-091D [OT] Sheet 2 of

@" AA8 8

A A ; J ;