Sunteți pe pagina 1din 5

DESIGN OF A IPHASE, MOSFET INVERTER AND ASSOCIATED GATEDRrvE CIRCUIT

H.C. Lovatt, M.L. M‘Clelland


Department of Electrical and Eledronic Engineering,The University of Lecds, Lccds, UK.
MJ. Turner
Switched Reluctance Drives Ltd., Springfield House, Hyde Terrace, Lecds,UK.

Aachen 1989 Absmf. The paper discuses, with particular reference to the gate-drive circuit, the design of an inverter to reproduce a stored current
waveform with a hgh degree of accuracy for use in a motor drive system. The gate-drive circuit combines low cost with individual over-
current protection for each switch, thus providing shoot-through and short-circuit protection without the need or expense of a d.c link
choke. In addition to the gate-drive circuit design, the reasons for choosing MOSFETs as the main power devices, alternative gate-drive
circuit confiations and inverter protection techniques are discussed. Although designed for a standard bridge configuration, MOSFET
inverter, the gate-drivc circuit presented is applicable to other MOS input devices and to other power circuit configurations.
Keywords. MOSFETs, inverters, gate-drive circuits

the drive system is given below.


(i)
INTRODUCTION
This paper describes (with particular reference to the gate-drive circuit) the
design of an inverter to reproduce a stored current waveform with a high degree
of accuracy, for use as part of a Sphase motor drive system. The spedfication of

The inverter needs to reproduce a stored current waveform with a high


degree of accuracy. This implies the use of a high modulation fre-
quency for a switching amplifier or the use of a linear amplifer.
m D.C. link

Rerurn-
current
diode
(i) The inverter is to provide an output waveform with a fundamental fre-
quency in the range 0 to ux)Hz.
(i) The d.c. link voltage is variable between 50 and 400 V. Fig. 1: Standard 3-phase bridge configuration
(iv) Protection is to be provided against shoot-through faults and short-
circuits on the inverter’s outputs. me of switching device
(v) The maximum continuous output current is lOA/phase. The specification requires a DC link voltage of up to 400 V and a maximum con-
(vi) The peak output current is 33 A/phase. tinuous output current of 10 A/phase. In addition, a modulation frequency of
(vii) The control and power eledronics are to be electrically isolated from 20 kHz has been chosen. A good choice of power switch to meet these require-
each other. ments is the MOSFET whose advantages and characteristics are outlined below. -
In the following sections the power circuit codiiration, the reasons for choos- (i) They switch between states quickly, thus reducing switching losses and
ing MOSFETs as the main power devices, the gate-drive circuit, inverter protec- allowing a higher switching frequency. A higher switching frequency
tion and practical implementations of the design are discussed. The section on gives better control of the output current waveform.
the gate-drive circuits presents ‘circuit fragments’ without explanation as to how (i) They are easy to drive (seegate-drive circuit options below).
they operate, since they are well known configurations. in each case, reference is
(i) They are economically pried.
made to a description of their operation.
(iv) They require no snubber network, which leads to higher efficiency,
lower cost and a lower component count.
POWER SWITCH CONSIDERATIONS
(vi) They have good overload capabilities which allows the inverter to pro-
Gmif configurofionand modulation strategy duce the specified peak current rating for a short period of time.
The specification demands an accurate reprodudion of a stored current W h e n the decision to use MOSFETs for the main switching dcviccs was taken
waveform to reduce the undesired harmonics present in the current supplied to (early in 1988), the ‘state-of-the-art’ devices were the IRF [International
the motor. The inverter has a maximum continuous peak current rating of Rectifier, 1985) range of MOSFETs. As with all power MOSFETs, IRF devices
10 A/phase and a maximum d.c. link voltage of 400 V and at these voltage and have an anti-parallel diode (often referred to as a ‘parasitic’ diode) bctwcen their
current levels it is not economical to use a linear power amplifer, since the source and drain connections ( f i e 2 ) . This diode is in parallel with the
power dissipation (losses) would be too large. For example, if full current was return-current diode (see f i w e l ) and therefore conducts when the energy
supplied at a maximum d.c. link voltage to an indudive load a linear power stored in the motor windigs is returned to the supply. Since the ‘parasitic’
amplifer would be required to dissipate 4 kW (full current in one phase. and half diode turns off slowly, relative to the turn-on time of the MOSFET, there is a
current in the other two with half the d.c. link voltage across each conducting period of time equal to the difference in these two switching times when there is
device). To reduce the dissipation and hence the device rating and heatsinking a short-circuit acros the d.c. link. This leads to a large instantaneous power dis-
requirements, a switchg type power amplifier using a standard >phase bridge sipation in both the MOSFET and ‘parasitic’ diode. To prevent this, the ‘parasi-
configurationhas been adopted (see f i e 1). tic’ diode must be prevented from conducting. Two possible ways of doing this
There are many ways of modulating the incoming signal to produce a series of are suggested below.
pulses suitable for ampWication by the power electronics. A pulse-width- (i) Use a return-current diode with a lower ‘on’state voltage drop at full
modulation (PWM) strategy has been chosen on the grounds that it can be current than the voltage drop at zero current of the ‘parasitic’diode.
operated at a fiied frequency (which helps in control Imp analysis) and is easily
implemented. (fi) Put a diode in series with the MOSFET (and ‘parasitic’ diode) to
prevent reverse. currents flowing ( f i i e 3).
The choice of modulation frequency inevitably involves a compromise between The fiist approach of using a return-current diode with a low ‘on’state voltage
reducing the unwanted harmonics at the output (which implies as high a switch- would be ideal, since it would also reduce the inverter losses when compared to
ing frequency as possible) and reducing the losses in the power electronics the sccond option. Unfortunately, no diodes are readily available with low ‘on’
(some of which are proportional to switching frequency). As a compromise state voltage drops and suffiaent reverse blocking voltage to ‘hold off the
between the conflicting requirements of a ‘good quality‘ output and low power specified d.c link voltage of 400V. Therefore the approach of preventing
dissipation, a modulation frequency of 20 kHz has been chosen. This modulation reverse currents with a series diode and suffering the cxtra ‘on-state’losses ((i)
frequency has the added benefit of beiig ultra-sonic and hence reduces the audi- above), has been chasen.
ble noise produced by the motor drive system.

c
Series
d 1 ode
-7 * Rmturn-
currmnt
diode

Fig, 2: MOSFET and ‘parasitic’diode


FiP.3: MOSFET. return current din& mracitir A i d e mnd
Mininun II i n i n u n
o f f - tinm o n - t ine
n o n 0 st 8 b 1e l nonos t a b I
+ S
1
T

r a q u i r e hish
dVldt innunitu
I

Protection
over-ride
nonostabla -
-> Q
+ a-
- t!

Fig. 4 Block diagram ofone channel of the complete gate-drive circuit

Power &if layout SWITCH STATUS SIGNALLING AND


THE PROTECTION CIRCUITRY
MOSFETs are capable of operating without any snubber network since they do
not require the rate of voltage rise at turn-off to be limited and they have a The spedfication requires that the inverter be protected against short-circuits on
‘square’ safe-operating area (International Rectifier, 1985). However, like all the outputs and shoot-through faults. The Same circuitry is used to protect
power electronic devices, there is a limit to the voltage a MOSFET can with- against both fault conditions.
stand. Thus a snubber network may be desirable to reduce the voltage overshoot A common method of providing short-circuit protcdion is to measure the d.c.
at turn-off due to any ‘stray’ inductance resulting from the circuit layout. When link current and signal to the control electronics to turn the power switches off
assessing the need for a snubber network, the fault current (which is much when a preset level of current is exceeded. Since the control electronics are iso-
higher than the nominal peak current) should be taken into account in the lated from both the d.c. link and the power switches, the delays assodated with
design. In the m e of the inverter described here, the nominal peak current is these two isolation barriers must be accounted for. To prevent the current rising
33 A and the fault current is lu)A (see section on testing below). The need for to a harmful level in the time it takes the turn-off signal to cross these two isola-
a snubber network in this application is avoided by carefully designing the circuit tion barriers, it is usual to insert an inductor in the d.c link to h i t the rate of
layout and fitting a decoupling capacitor to each limb of the inverter (see section rise of current. Apart from the additional cost incurred, this inductor has the
on testing below). undesirable effect of increasing the turn-off-voltage overshoots in the power elec-
tronics. This method of p r o t d o n is not suitable for use with a generator, since
GATEDRIVE CIRCUIT OPTIONS a switch fault current can be sustained from the generated current and not from
To meet the specification, all the gate-drive circuits require isolation from the the d.c. link.
control electronics, but the three top switches shown in f w e 1 also require An alternative technique is to use the gate-drive circuit to directly measure the
immunity from any eledrical noise resulting from the high dV/dt (up to current through each power switch and turn the switch off when a preset current
l3 GV/s) between these power switches and the control electronics. There are level is exceeded. In addition, the gate-drive circuit can (if required) signal back
many possible gate-drive circuit configurations but most fall into one of the ten to the control electronics (via a second optical isolator for example) that an
categories shown in table 1. over-current condition in the power switch has been detected.
The final gate-drive circuit shown in table1 (an optical system with dV/dt Since an optically isolated gate-drive circuit with individual power supplies for
suppressionlogic) has many desirable features, see below. each channel has been adopted, it is easy to provide individual protection of each
(i) The MOSFET can be switched on or off quickly. power switch. Current fbw through the MOSFET is monitored by measuring
the voltage drop across the device and turning the MOSFET off should this vol-
(i) The MOSFET is actively held on or off, without the risk of the gate tage exceed a preset value. A block diagram of the complete gate-drive circuit
voltage ‘ddihg‘ due to currents fbwing in stray capaatancw. including the switch status signalling and the protection circuitry is shown in
(i) Shoot-through and short-circuit protection can be provided cconomi- f w e 4.
d y (see the section on protcdion below).
(iv) Switch status signalling can easily bc provided (see the section on sip-
n a h g below and Barret, 1988).
(vi) The source impedance of the gate-drive circuit can be easily controlled,
which can reduce device losses (Presto& 1987).
By implementing this optical circuit using CMOS design techniques throughout,
the power consumption can be made very small (150mW/gate-drive circuit),
thus reducing the cost and complexity of the power supplies.

Fio 6. Six channel natedrive board m r e d from an external mains Fig. 5 A self-pornred hvo-channel gatedrive
Cmfimtioa Circuit DrantRlCkS

Level shifter (Sil- Requires pchannel

bG
iconix, 1988). MOSFETs (which are
costly and have large 'on'
state losses).
I The MOSFET switches

slowly (which incrreases its


resistor
DHoIuoehr dissipation).
High power resistors are
required.

I
* I
I
I Fast high-voltage transis-
tors are costly.

Improved level Requires pchannel


shifter (Siconix, MOSFJZTs (which are
1988). costly and have large 'on'
state losses).
Fast high-voltage transis-
tors are costly.

L ~ 0 . r not
reouiro hish
dVldt lnnunitu

Pulse transformer A bi-dircetional high


ON& 1985). current drive is required.
The maximum on-
time/off-time is limited by
the volt-second produd of
the transformer.
The ratio of on-time to
. I off-time can at most equal
the ratio of positive vol-
tage to negative voltage
applied to the transformer.
Pulse transformer 0 The capaator charges via
with steering logic currents fbwing through
the drain-gate capacitance
(Wood, 1985).
m e
J
I& of the MOSFET.
Charge on the capaator
will 'leak' away.

4t-I I

n
A.C. coupled (
&? The HF (approximatel)
(Siemens, 1985). 1 MHz) d t o r required
to drive the transformer is
costly (due to the higk
current requirements).
The MOSFET turns-08
slowly since the gate ir
discharged by a high value
resistor (relative to the
output impedance of an
active driver).
4.c. Coupled drivw 0 The HF (approximately
vith additional 1MHz) d a t o r required
pulse amplifier to drive the transformer is
(Siemens,1985). costly (due to the high
current requirements).
-,,-
i u e when
8r~li.d
l l l L

Bootstrap (Sil- Charge on the capacitor


Iconix, 1983). will 'leak' away.
0 Fast high-voltage transis-

tors are costly.


0 The turn-off transistor's

load resistor will need a


large power rating if the
MOSFET is to be turned
off quickly.

Improved bootstrap Charge on the capacitor


(Siliconix, 1983). will 'leak' away.
0 Fast high-voltage trwis-

tors are costly.

Active
IOU
++Ad isolator

I I
I
II
II

3ptically isolated
An external power supply
rate drive is needed for each MOS-
:Clemente, 1987).
FET switch.
Optical isolators with
sflicient
are costly. dV/dt rejection

Re4wir.s hiah
dV/dt innuni tu
o n t O D Switches

IpticaUy isolated An external power supply


pte drive circuit Pu1.a
is needed for each MOS-
vith dV/dt suppres- FET switch.
ion using mono-
tables (For an
llternative dV/dt
uppression circuit
ce Matsuda, 1983).

Duos not I I I I
reauire hieh
dWldt Lnnunitu M in inun Mini nun
off-tine on-tine
nonostable nonostable

Tabk 1: Comparison of diflerent MOSFET gatedrive circuits


IMPLEMENTATION AND TESTING CONCLUSIONS
Many variations on the above basic circuit are possible and a particular variation The design of the critical features of a 400 V, 10 A, MOSFET inverter have been
would be chosen to suit the application. For example figure 5 shows a photo- described, in particular the design of the gate-drive circuit has been discussed.
graph of a two-channel gate-drive board that derives its power supply wing The power circuit presented here uscs a series diode to prevent the 'parasitic'
'bleed' resistors from the high voltage acIos5 the MOSFET when the MOSFET diode assodated with the MOSFET from conduding. Power electronic devices
is in the 'off' state (unlike the six channel board desoibed below, the two- are improving all the time and the latest devices from Siemens (1987/88) and
channel board docs not signal an over-current condition back to the control elec- Phillips (1988) have fast 'parasitic' diodes, eliminating the need for both the
tronics). The specificationfor the inverter described here requires a variable d.c. series diode and a separate retum-current diode (the 'parasitic' diode is used
link voltage between 50 and 400 V, therefore it is not possible to use 'bleed' instead).
resistors. Instead, two spccidy built transformers, both with three sccnndaries h k h g further into the future, new bipolar-junction transistor based power
and low inter-winding capacitance, have been uscd. Figure 6 shows a photo- elcdronic devices like Easy-To-Drive transistors (Thomson, 1987) and
graph of a six channel gate-drive board. A striking feature of both these desigos Insulated-Gate-Bipolar transistors (Toshiba, 1988) are offering some of the
is how economical they are in terms of device count and cost. advantages of MOSFETs: they are easy to drive and they have fast switching
The worst case conditions for both the gate-drive circuitry and the power elcc- s e .
tronics are during the clearing of either short-circuit or shoot-through faults. As The choice of gate-drive configuration is application dependent and the design
previously noted, a shoot-through fault is a type of short-circuit fault and there- presented here is suitable for inverters requiring a high quality output and good
fore only short-circuits need be tested for. F i e s 7 and 8 show osdograms of protcdion with low device count and uxt. Different forms of the basic circuit
the current in the MOSFET (bottom traces) and voltage amoss the MOSFET have been tried in various applications and have been found to work reliably. In
(top traces) under the conditions of turning on into a short-circuit and a short- applications not r q u i r i i shoot-through and short-circuit protection, one of the
circuit Kig applied with full rated current (10 A) in the switch, respectively.
n other gate-drive confiiations discussed may well provide a small cost savkg,
From figures 7 and 8, it can be sccn that proteaion is provided against short- but the added reliability and freedom from 'nuisance tripping' due to noise may
circuit conditions by the gate-drive circuit. Due to the minimum-on-timemono- well justify the small extra cost of the circuit descnid. Although intended for
stable (figure 4), the MOSFET remains conducting for a longer pcriod of time MOSFETs this circuit is applicable to other MOS input devices.
when turning-on into a short-circuit ( f i e 7), therefore this is the worst case
condition. To obtain the oscillograms shown in figures7 and 8 a shunt was
inserted in series with the MOSFET. The resulting additional inductance associ- ACKh'OWLEDGEhiENTS
ated with the shunt and its leads increased the voltage overshoot at turn-off by The work described in this paper was carried out under a research contract
almost 100 V, hence the oscillograms are taken with a d.c. link of 300 V instead jointly funded by the LJK, Science and Engineering Research Council and
of the maximum 400 V link.As the MOSFET turns off and the current flowing Switched Reluctye Dews Limited of Lceds,UK.The authors would also like
in the load transfers to the return-current diode the energy stored in the 'stray to thank tGre coheagues at Lecds University (UK) and Switched Reluctance
inductance (resulting from the circuit layout) transfers to the de-coupling hpaci- Drives Limited for many thoughtful criticisms and suggestions, in particular Dr.
tors (and the main input rectifier capacitors), giving rise to the 'ringing' of the MA.Lahoud and Dr. J.M. Stephenson.
voltage across the MOSFET shown in both oscillograms.

REFERENCES
Bmet, J. (l988)."Interadin Switching in Bridge Arms,"Ewmwt Ind (Waf
Gu7nUny) VOL 19,no.2,105-110.
Qemente, S. (19sr). 'Gate Drive CharacteriStia and Requirements for Power
m s , ' I m m a f h a J Rrctfim ILEWET Power MOSFET Lh?sipcrs
M M L67-1.74.
div h X M t i o d Rcctifer (1985). HEXFETdoln book
M&uda, Y, F W H, Ammo, H, Okuda, H, Watanabe, S. and Ishibashi, A.
(1983). P m l O p m c n t - O f PWM Invtrter EmploYing GTO,"IEEE Tmn~.011
w1.IA-19, no. 3,335-342
Philips (1988). Tahnicpl-H VOL 1 (Semiamductor~Dcviccs),no. If
ov - (P- MOS tmnsistm).
Preston, MA., Edwards,JD.and Williams, G. (1987). *A N m l PWh4 Inverter
U b g Trdormer-Isolated P m r MOSFETs,' phn. qf 2nd EPE confer-
.V
m c Gmrob4
~ F m u , voL 1,105-110.
Siemens AG (1985). SIPMOS P o w T n m & m : & M m -@.
OA -
Sicmens AG (1987/88). SIPMOS componmrS data bode
Sioonix Incorporated (1983). "Driving Power MOSWWER =%" MOS-
Fig.% MOSFET drainaoum voltage (top) and current
P O m R h p -c, 6.16-6.19.
(bottom) -den turning-on into a short-circuit
Siconix Incorporated (1988). WOSPOWER Gate Driw,' MOSPOVER Data
Book, 9.18-9.24.
Tho- Semiumducteurs(1987), BUF 410 1BUF 41M data sheet
+O .50s /div Toshiba (1988).Applicption Notes: GTR M~niules,BiporOr GMOS IGBT.
Wood,P. (1985). Transformer-Isolated HEXFET Driver Provides Very Large
Duty cyde Ratios," InfnnntioruJ M f i e r HEXFET Power MOSFET
Lksignm Manual, A.141-A.143.
t100V/div

ov

t 40A/div

OA

Fig.8 MOSFET drain-soum voltage (top) and current

S-ar putea să vă placă și