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 Global Process Variation (PVT Corner) On-Chip Process Variation
Global Process Variation. Also called inter-die variation, refers to the process effect that impact all Local Process variation. Also called intra-die variation, refers to the variations in the process
device on the same die/chip. The different process corner (operation condition) models this global which can affect the devices differently on a given die. On-chip variation can be systematic
variation. or randam.
 Timing Path - A Cascaded Statistical Events

Spatial Effect -> Distance Based

Paths comprised of cells in close proximity are correlated and exhibit less variation relative to one another.
Timing Path - A Cascaded Statistical Events

Statistical Cancellation -> Logic Depth Based

Uncorrelated random variation will die out over logic stages.
 Cell Delay Interconnection Delay

Arrival Timing Window

Since both cell delay and wire delay are statistical in nature, signal arrival time is also not
deterministic. Timing window can also be modelled statistically when calculating crosstalk.

Path Slack
SSTA reports the mean, standard deviation (ẟ) and the quantile values of the slack for each
path. The passing or failing can be determined based upon the required statistical confidence.
Derating
A scaling factor could be applied to both cell and wire delay,
which is called a derating factor.

Worst-Case Variation
Global OCV use a single flat derating factor across the entire chip,
which guard bands the worst situation that could happen to a chip.

Spatial Variation Unawareness

Regardless of the physical location of the cell/wire, they could have
very large variation swing. Even cells next to each other could have
been derated completely.

Logic Depth Unawareness

The path with more stages (logic depth) are derated the same
way as the path with less stages.
AOCV table
Derating value is acquired through Monte Carlo Spice simulation

Spatial Effect
The closer the distance, the less the variation (derating)

Statistical Cancellation
The deeper the path, the less the variation.
Advantage Advantage
1) Natural to think Constraints of different operational modes are combined to be consolidated
2) Can exclude path from specific functional mode precisely into a single super mode.
1) Reduce number of analysis mode significantly
2) Reduce runtime and timing closure difficulty

Disadvantage
Disadvantage
1) Can result in too many modes if functionality is very complex.
1) Would be pessimistic compared with MCMM since it has to be conservative
2) Can be very runtime intensive and designers may not get a
not under-constrain any mode.
meaningful result in a reasonable time
2) Additional constraints (e.g. new generated clocks) may be needed to
3) Can increase timing closure iterations.
modelling exclusive relation between merged clocks.
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