DPT and Color conflict in Physical design

mantravlsi.blogspot.in/2017

Multiple patterning lithography (MPL) techniques have been used to extend the 193nm lithography
to 22nm/14nm nodes.
Possibly further due to the delay of extreme ultra violet lithography and electric beam lithography
(EBL) Generally speaking, the MPL consists of double patterning lithography (DPL) and triple
patterning lithography (TPL).
There are two main types of DPL with different manufacturing processes:
                 litho-etch-litho-etch (LELE) and
                self-align double patterning (SADP).
Both of them can be extended for triple patterning. The most important issue for multiple
patterning technique is how to successfully decompose the layout into several masks that can be
manufactured under current 193nm optical lithography.
When the pitch between two patterns is less than the lithography threshold, the patterns have to
be separated into different masks. This process is called layout decomposition, or coloring. There
are many studies on MPL layout decompositions at the mask synthesis stage to resolve the coloring
conflicts, minimize the stitches, balance the mask density, or even mitigate the undesirable overlay
effects

Meanwhile, there are studies showing that it is very important to consider the multiple patterning
implications at earlier physical design stages so that the overall design and manufacturing closure
can be reached.
Both multiple patterning aware standard cell library design and multiple patterning aware physical
design flow are necessary to avoid undecomposable patterns in final layout.

For example, if placement/routing techniques are not multiple patterning friendly, the final layout
may introduce some conflicts.
Since redesigning indecomposable patterns in the final layout requires high ECO efforts.

we propose a unified physical design flow for standard cell compliance, pin access, routing, and
placement to bridge the gap from mask/layout decomposition to physical design. With further
scaling of feature size into very deep sub-wavelength, the mask-level manipulation will be limited if
the final layout after physical design is not lithography friendly. Therefore, it is necessary to
integrate lithography awareness into nanometer physical design flow. Our preliminary results from
such a unified flow are very promising. As multiple patterning lithography is being actively adopted
by industry and it can also be used together with EUV, e-beam lithography, DSA, etc., we expect to
see more research activies to bridge such gap. 

The double-patterning technology (DPT) that means we can continue to use 193nm lithography to
produce features at a 64nm pitch in 20nm processes is a breakthrough for manufacturing but an
added complication for design. In double patterning, features that are too close together to be
resolved with conventional lithography are separated onto two masks, which are exposed
sequentially, with an etch step in between, to form the necessary densely packed features.
Designers must create layouts that can be split (‘decomposed’) into two layers, a process known as
coloring, after map-coloring theory. Achieving such layouts means following new design rules that
encapsulate the limitations of the lithographic process and prohibit two polygons of the same color
from having particular geometric relationships

Physical designers have to work with these new rules during placement and routing, considering the
costs of decomposability alongside other costs such as timing, power and area. The physical
verification process also has to change, so that it can show that an entire layout can be successfully
split onto two masks in a way that meets the foundry’s specifications.
Achieving decomposability

Although foundries will often decompose a layout themselves so that they can optimise the
resultant masks for manufacturability, producing decomposable designs means being able to show
that applying the foundry rules to a layout can result in successful mask assignments.

The essence of the coloring problem is to create layouts made up of closed loops of polygons (so-
called ‘cycles’) that can be given alternating colors along the whole length of the loop. Physical
verification tools such as Synopsys’s IC Validator include analysis engines that enable users to
define complex geometric relationships, such as the minimum spacing between polygon edges and
the corners of facing sides or line ends assigned to the same mask, and then apply them to a
candidate design. More elaborate rules allow single polygons to be subdivided on to two masks (a
process known as ‘stitching’), which enables greater design freedom by offering a way to avoid
some coloring violations.
Meeting DPT requirements in library development

Double-patterning requirements have to be taken into account in both the design and placement
of 20nm cell libraries.
Cell designers must ensure that their cell layouts can be safely decomposed into two colors, using
physical verification tools to check that their work will meet this requirement and to suggest
possible adjustments if it doesn’t. Cell designers also need to think about possible interactions
between the cells they design when they are placed adjacent to each other. One way to overcome
this issue is to build enough space into every cell that they can’t create coloring violations. The
other is to design cells without this margin and rely on the placer to avoid any potential violations
caused by cell adjacencies. Both approaches are supported by In-Design technology, which
seamlessly couples signoff-quality analysis in IC Validator to the placement engine in IC Compiler.

Here’s an example of a 20nm cell library in which the designer has created an XOR gate and wants
to know whether it can be successfully decomposed and its properties in placement.

The cell is first decomposed according to some basic conditions: both power rails must be assigned
to the same color and polygons must not be stitched. This approach results in DPT conflicts