Sai Madhan. K: Mca - Semester 1 REGISTER NO: 190951144

SAI MADHAN.
K
MCA | SEMESTER 1
REGISTER NO: 190951144
January – 2019
MCS- 012
Computer Organisation and Assembly Language Programing
Assignment Code:
MCA (1)/012/Assignment/2018-19
MCS-012: Computer Organisation and Assembly Language
Question 1
A. 1. Fixed Point Numbers:
i. What is a fixed point number?
A number representation which is a real data type for a number
that has fixed number of digits before or after the radix point. A
fixed point data type is defined by the word length in bits, the
position of radix point and stating whether the umber is signed or
unsigned.
ii. Why are negative numbers represented in complements?

Negative fixed point numbers are always represented in
complements for a scaling factor whose exponents is negative, the
number represented is smaller than the integer number that was
stored and the number being represented has a functional
component so it has to be complemented. In other words to
differentiate between possitive and negative numbers. Thus,
Negative numbers are always complemented.
iii. Example of fixed point number

Let’s assume the numbers ‘+9’ and ‘-9’
Representations can be made in 3 forms as:
1. Sign Magnitude Representation
Representation in 8 bits
Decimal Number Sign bit Magnitude bits
+9 0 000 1001
As Negative numbers has to be complemented we could only

represent positive numbers in this form
2. Signed 1’s complement:
Decimal Numbers Representation in 8 bitsSi

Sign bit Magnitude bits
+9 0 000 1001
-9 1 111 0110
3. Signed 2’s complement
Decimal Numbers Representation in 8 bits

Sign bit Magnitude bits
+9 0 000 1001
-9 1 111 11
A) 2. Perform arithmetic operations:
i. Add -30 and -98 using signed 2’s complement
Deriving 2’s complement of -30 and -98
Decimal Number Signed magnitude

Sign bit Magnitude
-30 1 110 0010
-98 1 001 1110
Decimal Number Signed 2’s complement

Carry Sign bit Magnitude bits
-30 - 1 110 0010
-98 - 1 001 1110
-128 1 1 000 0000
There is carry in to the sign bit and carry out from the sign bit.
Therefore, No overflow and hence carry out will be discarded.
ii. Subtract -79 from 45
Derive 2’s complement of -79 and 45
Decimal Number Signed Magnitude

Sign bit Magnitude
45 0 010 1101
79 0 100 1111
Decimal Signed 2’s complement

number Carry Sign bit Magnitude
45 - 0 101 0011
79 - 0 011 0001
- 1 000 0100
Hence, There is an overflow at the carry into the sign bit is not
equal to the carry of the sign bit.
B. Conversion of Numbers
i. Decimal to binary
Given D10 = (56789123)10
B2 = 11 01100010 10001000 10000011
Decimal to HexaDecimal
Given D10 = (56789123)10
Hex = (362 8883)H
ii. HexaDecimal to Octal
Given = (ABCDEF)H
Octal = (1257157360)8
iii. ASCII to UTF-8
Given string = “Subject: Computer %$ Sc.”
Given ASCII UTF-8 UTF-8

(Unicode (Hex)
code point)
S 83 U-0053 53
u 117 U-0075 75
b 98 U-0062 62
j 106 U-006A 6A
e 101 U-0065 65
c 99 U-0063 63
t 116 U-0074 74
: 58 U-003A 3A
<space> 32 U-0020 20
C 67 U-0043 43
o 111 U-006F 6F
m 109 U-006D 6D
p 112 U-0070 70
u 117 U-0075 75
t 116 U-0074 74
e 101 U-0065 65
r 114 U-002 72
<space> 32 U-0020 20
% 37 U-0025 25
$ 36 U-0024 24
<space> 32 U-0020 20
S 83 U-0053 53
c 99 U-0063 63
. 46 U-002E 2E
iv. Octal to Decimal
Given octal= (345123)o

Decimal = (117331)10
C. Circuit diagram for given function
Given F(A,B,C,D)=∑(2,3,4,5,10,11,12,13)
Truth Table
Decimal A B C D Output F
0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 0
7 0 1 1 1 0
A8 1 0 0 0 0
9 1 0 0 1 0
10 1 0 1 0 1
11 1 0 1 1 1
12 1 0 0 0 1
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 0
K-Map
CD 00 01 11 10
AB
00 1 1
01 1 1
10 1 1
11 1 1
On solving the K-map we get
𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷
→ 𝐴𝐵𝐶(𝐷 + 𝐷) + 𝐴𝐵𝐶(𝐷 + 𝐷) + 𝐴𝐵𝐶(𝐷 + 𝐷) + 𝐴𝐵𝐶(𝐷 + 𝐷)
→ 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶
→ (𝐴 + 𝐴)𝐵𝐶 + (𝐴 + 𝐴)𝐵𝐶
→ 𝐵𝐶 + 𝐵𝐶
Logic Diagram
𝐵𝐶 and 𝐵𝐶 are passed through AND gates and the output will be
𝐵𝐶 + 𝐵𝐶
(P.S. This arguments passed an output are mentioned separate as the tool I
use does not support adding these type of comments to the diagram)
D. Parity bit
1. Need for Parity bit:
Parity bit is used to keep a count of 1’s in the data and marks wether
the count is even or odd and is added to the data. It is used for error
detection and is majorly useful for detecting errors on data
transmission
Example
Assume a 7bit data 011 0101 is transmitted.
For error checking we add an eighth bit which is the parity bit
If an even parity method is adapted then a parity bit 0 which is an
even parity bit is added. Whereas if an odd parity method is adapted
then an odd parity 1 is added.
2. Number of parity bits required
Given equation
2i – 1 >= n + i
This equation is used to find number of error correction bits
Were n is 8 and assume i =3
→ 23-1 >= 8+3

→ 7 >= 11
(Is false)
So, assume i=4
→ 24-1 >= 8+4
→15 >= 12
Therefore for an 8 bit data atleast 4bits of error correction code is

required in a single bit transaction.
3. correction of single bit error
Assume 4 bits binary data 1101 is the source
Source Data Add parity bits at source

B1 B2 B3 B4 P 1 (B1 P2 P3 P4 (B1,
, B2 , (B2, (B3, B2, B3,
B3) B3, B4) B4, B1) B4)
1 1 0 1 1 1 0 0
If suppose the source data is received as 1001
B1 B2 B3 B4 P1 P2 (B2, P3 P4(B1,
(B1, B3,B4) (B3, B2, B3,
B2, B4, B4)
B3) B1)
1 0 0 1 1 1 0 0
Here P1-B1, P2-B2, P3-B3, P4-B4 pairs differ. Thus B3 hass error and
we could correct it by complementing it in order to obtain he correct
data 1101.
E. 2Bit down counter
State Table
Present State Input Next State Flip Input

Flop
A B X A B Da Db
1 1 0 1 1 1 1
1 1 1 0 0 0 0
1 0 0 1 0 1 0
1 0 1 1 1 1 10
1 0 0 1 0 1 0
1 1 1 0 1 0 0
0 0 0 0 0 0 0
0 1 0 1 0 1 0
0 0 0 0 0 0 1
0 0 1 0 1 0 1
-State diagram
K Map
Da
BX
A 𝐵𝑋 𝐵𝑋 𝐵𝑋 𝐵𝑋
𝐴 1
A 1 1 1
Db
BX
A 𝐵𝑋 𝐵𝑋 𝐵𝑋 𝐵𝑋
𝐴 1 1
A 1 1
𝐷𝐴 = 𝐴𝐵 + 𝐴𝑋 + 𝐴𝐵𝑋
Thus 2 flip flop equations are
𝐷𝐴 = 𝐴𝐵 + 𝐴𝑋 + 𝐴𝐵𝑋
𝐷𝐵 = 𝐵𝑋 + 𝐵𝑋
Logic Circuit
Where the outputs will be 𝐴 𝑎𝑛𝑑 𝐴 from first flip flop and 𝐵 𝑎𝑛𝑑 𝐵 from the
second flip flop respectively.
F. Floating point Number

1. Floating point numbers
Floating point numbers have two parts the first part has a signed
fixed point number which is called as mantissa and the second part
specifies the decimal or binary position and is called as exponents
The mantissa can contain integer or a fraction. Hence, the position of
the decimal or binary part are assumed and is not a physical point.
Example
A decimal +12.34 can be represented as

Mantissa (Fractional) Exponent
Sign Sign
0 1234 0 02
Difference between single precision and double precision Floating

point Number
In floating point number precision is the trade-off between the range

and accuracy of the numbers. Major difference between the single
precision and double precision of floating point is the range and
accuracy of the numbers. In single precision floating point numbers,
32 bits are used to represent the numbers. And as double precision
uses more bits range and precision increase significantly.
Representation of 0 in single precision
IEEE 754 single precision standard specifies +0 and -0 are special

charecters.
For denoting +0, sign bit is set to ‘0’, all bits of exponent are ‘0’and all
bits of significand as ‘0’.
Similarly for -0, sign bit is set to ‘1’, and all of exponents to ‘0’ and all
significands to ‘0’.
Therefore IEEE 754 standard notation of +0 in single precision is

Sign Bit Exponent Significand
0 0000 0000 0000 0000 0000 0000
0000 0000
Similarly for -0 is
Sign Bit Exponent Significand
1 0000 0000 0000 0000 0000 0000
0000 0000
Representation of (-23456.05)10 in IEEE 754 single precision format
As the number is negative sign bit becomes ‘1'

Binary is 101101110100000 .000011001
Exponent = 114+127= (147)10= (10001101)2
Significand = 011 0111 0100 0000 0001 1001
Therefore the IEEE 754 single precision notation f givennumber is:
1 1000 1101 0110 111 0100 000 0000 11001
Representation of (0.00025)10 in IEEE 754 single precision format

sign bit =0
Binary = 0.00000000000100000110001001001101110
= 1.00000110001001001101110x2-12
Exponent = -12+127= 115=011100112
Significand = 00000110001001001101110
Therefore representation in IEEE754 single precision format is

0 01 1100 1100 0001 10001 0010 0110 1110
Question 2
A. RAM memory
i. Data input and output lines
Given 1M with 16 cells
Therefore, word size =16
Hence, given RAM needs 16 Data input lines and 16 Data output lines?
ii. Capacity of the RAM

Capacity = 1*1024*1024*16 bytes
Therefore, Capacity of ram in bytes is = 16777216 bytes
iii. Adress lines

Given Ram has 1M words
So, 1M=220
Therefore, the given Ram will need 20 address lines
B. Ram Memory
i. Direct cache memory is needed
Given Ram 1MB =220 words
Word size of ram =16 bits
Cache memory size= 8 blocks
Cache memory block size=32 bits
=> 1 block of cache= 2 words of RAM
Given main memory address= 0001 1001 1110 1101 0001
Here, index= 3 and tag =17
Address mapping in direct memory

Memory 0001 1001 1110 Mem add
Address 1101 0 001 =106193
Block Address 0001 1001 1110 1 Block Add =
1101 000 53096
Block offset= 1
Cache 0001 1001 000 1 Tag= 13274
Address 1110 1101 Index set no= 0
Block offset= 1
ii. Associate cache mapping is used

In associate cache mapping the values can be anywhere in
the cache
iii. Two way set cache memory is used

Address mapping for 2 way set cache mapping is
Memory Address 0001 1001 1110 Mem add
1101 0 001 =106193
Block Address 0001 1001 1110 1 Block Add =
1101 000 53096
Block offset= 1
Cache Address 0001 1001 00 1 Tag= 13274
1110 1101 Index set no= 0
Block offset= 1
C. DMA
Need for DMA

Direct memory access issued when a large amount of data is to be
transferred form I/O device to the memory DMA is more efficient
technique to overcome drawbacks of both interrupt driven.
How DMA differs from I/O.

The processor is busy with executing Input/ Output instructions
and the I/O transfer rates limited by the speed with which the
processor can test and service a device.
Whereas, in DMA it acts as if it has taken over control from the
processor
Witch I/O technique is most suitable

DMA is more suitable for building a new computer that supports
for few bytes of input from multiple users as DMA acts as if it has
taken over the processor with this, the CPU interruption is
minimized in DMA. The DMA transfers entire block of data, one
word at a time, directly to or from memory without going through
the processor. Hence, DMA is more suitable in the case.
D. Memory
Given
Total No. of tracks= 1000
Size of each sector= 512k
File size= 16M
Size of four free continuous clusters of 8sectors each
= 4*8*512k
=16384k
=16M
Therefore the given file will be stored in 4 free continuous clusters

of 8 sectors each.
E. Explain the following

i. Memory interleaving
The main memory is divided into ‘n’ equal size modules and
the CPU has separate memory address register and memory
and register for each memory module. It is used for adding
high equal memory segments.
ii. RAID
RAID stands for Redundant array of independent disks.. A
basic scenario to use RAID is to replace the large capacity
disk multiple smaller capacity disks. It improves overall I/O
performance as data is distributed along disks to provide
stimulator.
iii. IDE in interface

Integrated disk electronic interface is one of the drive
interface standards. It is an interface between the disk
controller and an adapter localized on the mother board
and it is the most widely used interface.
iv. CAV and CLV in the context of disk

CAV stands for Constant angular velocity. The technique is
used in the disk drives for accessing data off rotating disks.
CLV stands for Constant linear velocity technology makes
the speed reduces the speed or rotation of the disk as we

move further from the centre as it ensures constant reading
of sectors and it is used in CD-ROM’s
v. Passive and active matrix display

In a passive matrix display LCD had a horizontal grid and
vertical conductors and each pixel is located at an
intersection. This technology is more commonly used.
Active matrix display technology is also called Thin film
Transistor- TFT in this there is a transistor at every pixel
acting as a relay receiving a small amount and image is
much bigger to activate the pixel. Since the amount is
smaller it can travel faster and have response faster
vi. Advantages and disadvantages of ink-jet printers

Ink jet printers are non-impact printers.
Advantages of inkjet printers include
 speed of printing
 improved quality over impact printers
Disadvantages include
 Low quality compared to laser jet printer
 Higher the quality output depend on paper quality
Question 3
A.
i. Design instruction formats
Register type used for arithmetic interactions
OP RS RT RD Stamt Funct
6Bytes 5Bytes 5Bytes 5Bytes 5Bytes 5Bytes
Where,
OP - Operations code or operand
RS - The first register source operand
RT - Designation operand, stores result of operation
Shamt – used in case of self-operations
Funct – This field selects specific variable out of the operation in the
opcode field, and is sometimes referred as function code
Total 26 = 32 operations can be called on this machine as opcode
size is 6bit.
i. Demonstrate different addressing modes
Indirect and Direct Addressing modes can be used in the
machine
When addressing mode bit is ‘0’thenindirect addressing is
used
Example
LOAD I
500
500 50A
50A 0111
Insertion
Address
↓
Address of
operand
↓
Operand
If addressing bit is “1” then direct mode is used

Example: LOAD D500
200 LOAD D 500

500 …0111
Main Memory
Instruction
Address
↓
Operand
ii. Micro operation and instruction cycle

Sequence of micro operation will be
IR <- DR will be done as
MAR <- PC
Above instruction will transfer PC to MAR
DR<- (MAR), PC<- PC+1
MAR puts its contents in the address bus for main memory location
selection.
IR <- DR
The function so obtained is transformed from data register to
instruction register for further processing.
ADD AC DR
The DR and AC values are added and shared in register AC.
iii. Subtract R2 from R1with borrow

Given
R1= 0111 1011
R2= 1000 0100
S3 S2 S1 S0 C F Macro Name
Operati
on
0 0 1 0 0 𝑓 R<-R2-R1 Subtra
=𝑥 ct with
+ (𝑦 borrow
+ 1)
0 1 1 0 - F= R<-R1+R2 Exclusi
x+y ve OR
of R1
and R2
1 0 - - - F= R<- Shift
shl(x Shl(R1) Left
)
1 0 - - - F= R<- Shift
shl(x Shl(R2) Left
) twice
0 0 0 0 1 f- R<- R1+1 Increm
x+1 ent
A. Structure of CPU
A control unit has a set of input values on the basis of which it produces
on output control signals which in turn performs micro operations. These
input signals control the execution of a program
The master clock signal:

This signal causes micro operations to be performed in a square. In a
single clean cycle either a single or set of instructions or micro o
operations can be performed.
The instruction Register:

It contains the operation code and addressing mode bits of the
instruction. It helps in determining the words cycle to be performed and
the hence determines the related micro operations which are to be
performed
Flags: flags are used by the control unit for determining the states of the
CPU and the outcomes of a previous micro operations.
Control signals which are required within the CPU:
Some of the control signals are provided to the control unit through the
control bus. These signals are occurred from outside the CPU, some of the
signals are independent signals and acknowledgement signals.
Role of control signals in instruction execution:
The control signals are applied directly as the binary signals to the logic
gates of the logic which are applied to select a circuit or a path or any
other operation in the logic circuits
A program execution consists of a sequence of instruction cycles. Each
instruction cycle is made up of a number of sub cycles. One such simple
subdivision includes fetch, indirect, execute and interrupt cycle with only
fetch and execute cycle always occurring each sets cycle includes one or
more micro operations
Reading complexity in RISC machine

RISC stands for reduced instruction set computers. In the 1980’s a new
philosophy evolved having optimizing computers that could be used to
compile “normal” programing languages down to instructions and that
were as simple as micro operators in a large vessel address square. This
made the instruction cycle time as fast as technology would permit. The
machines should have simple instructions such that it can harness the
potential of simple instruction executioner one cycle that having reduced
instruction sets
Advantages of using large file in RISC
Use of large set of registers will lead to fewer memory access. Some most
operational resources are to lead variables of a function in C they are the
obvious choice for storing the registers. RISC register file produces a
support for such cell returns which the help of register windows. Register
files are broken into multiple small sets of registers and assigned to a
difficult function. A function call automatically changes each of these sets.
The use from fixed size window of registers to another, rather than saving
registers in memory or done in CISC. Windows for adjacent procedures
are often piped. This feature allows parameter passing without moving
the variables at all.
Difference between RISC and other machine instruction passing:

Interaction pipelining is often used to enhance performance. In RISC
machines most of the operations are register to register.
Therefore, the instructions can be executed in two phases:
F- Instruction fetch to get the instruction
E-instruction execute on register operands and store the results in
register.
In general, the memory access in RISC is performed through LOAD and
STORE operations for each instructions the following may be needed
F- Instruction fetch to get the instruction
E- Effective address calculation for the decimal memory operand.
D- Memory to register or register to memory data transfer through bus.
B. Levels of cells supported
Given
No. of registers reserved for global variables = 32
No of registers reserved for interaction between bits =32
No of registers received from string 2i/p parameters =8
Register Used for

No
0-31 Global Function A Function B Function
variables C
32-63 Instruction
related
token
64-98 Unused
99-102 Used by Temprory
(ou parameters variables
registers) of F that of
may be function
parallel to C
next cell
103-106 Used for Local
(ou local variables
register) variables of of
F(C) function
c
111-114 Local Local
(ou variables of variable of
register) f (B) function B
115-118 Parameter Temprory Parameters
(ou that are variables of of function
registers) passed function A B
from f(A)to
F(B)
119-123 Local Local
(ou variable of variable of
registers) function a function A
124-127 Functions Parameters
(ou passed to of function
registers) F(A) A
This type of RISC machine can support 7 levels of calls all together.
Question 4
A. Assembly program
Source Code
DATA SEGMENT
IN_1 DB 0
IN_10 DB 0
IN_100 DB 0
IN_1000 DB 0
MSG1 DB “ENER NUMBER: $”

MSG2 DB “ENTERED VALUE IS $”
MSG3 DB “NOT A NUMBER! $”
MSG4 DB “NOT A 4 DIGIT VALUE $”
MSG5 DB “RESULT $”
CODE
MAIN PROC
; READ INPUT
MOV AX, @DATA ; SETS UP DATA
MOV DS, AX
LDA DX, MSG1
MOV AH, 091
INT 21H
;READ FIRST CHARACTER

MOV AH, 1
INT 21H
MOV IN_1, AL
; CHECK IF NUMBER
CMP INT_1, 304
JB ERROR
CMP IN_1, 57
JA ERROR
; GET SECOND DIGIT

MOV AH, 1
INT 21H
MOV IN_10, AL
; COMPARE AL VALUE TO ASCII

CMP IN_10,48
JB ERROR
CMP IN_10, 57
JA ERROR
; GET THIRD DIGIT

MOV AH, 1
INT 21H
MOV IN_100, AH
CMP IN_100, 48
JB ERROR
CMP IN_100, 57
JA ERROR
; GET FOURTH DIGIT

MOV AH, 1
INT 21H
MOV IN_1000, AH
CMP IN_1000, 48
JB ERROR
CMP IN_1000, 57
JA ERROR
;IF NO ERROR COMPUTE VALUE

JNA COMPUTE
MOV MSG5, DX
LDA DX, MSG5
MOV AH, 094
INT 21H
END;
MOV AX, 4COOH

INT 21H
MAIN ENDS
END MAIN
; END OF PROGRAM
OUTPUT
ENTER NUMBER: 123C
NOT NUMBER!
ENTER NUMBER: 1235
RESULT: 4D3
ERROR
; IF NOT NUMBER EROR MAY OCCOUR
LDA DX, MSG3
MOV AH, 09H
INT 21H
JMP P_END
COMPUTE:
MOV AX, 0000H
MOV AL, IN_1
MOV DI, 3E8H
MOV DI
MOV DH, 00H
MOV DL, IN_10000

ADD DX, AX
MOV AX, 0064H
MUL IN_10
ADD DX, AH
MOV AX, 0004H
MUL IN_1000
ADD DX, AX
B. Program to that possess AL register value as parameter to a near procedure
Source code
.DOSSEG
.MODEL SMALL
.STACK 11H
.DATA
.CODE
MAIN PROC
MOV AL, 31H
CALL DIVZERO
MOV AH, 9
INT 21H
MAIN ENDP
; ENDS MAIN PROC
DIVZERO PROC NEAR
CMP AL, 60H
JNE L1
MOV AH, 9
INT 21H
L1:
RET
DIVZERO ENDP
END MAIN
; END OF PROGRAM
C. Explain following
i. The sequential memory in 8086 is 1 MB where instruction offset is 16its
Given
Sequential memory = 1MB
Instruction offset = 16 Bits
Sequential memory is related to the address bus of 8086 micro processor
The address bus has total 20 bits address bus thus, the microprocessor can access upto
220 i.e. 1MB ram directly.
The address bus of 8086has 16 bit lines. Thus, the instruction offset is only 16 Bits.
ii. Processing interrupts
8086 recognizes two types of interrupts
1. Hardware Intrust:
The interrupts are general which a peripheral interrupt source program requests for some
service
2. Software interrupt
It makes a call to the operating system and usually it is the input –output route.
In 8086, software interrupts instruction processing is done using the interrupt vector table.
The IVT is located in the first 1k of memory and has a total of 256 entities each of 4 bytes. An
entity in the interrupt vector table is defined by the number given in the interrupt
instruction. The entry states the address of the operating system subroutine that is used to
process the interrupt. This address may be different for different machines.
Interrupt is processed as
Step 1:
The number field in IVT instruction is multiplied by 4 to find the entry in the interrupt vector
table.
Step 2:
The CPU locates the interrupt secondary routine whose address is stored at IVT entry
Of the interrupt.
Step 3:
The Cupolas the CS register and the IP register with this new address in the IVT and
transfers the control to that address just like a for call.
Step 4:
IRET causes the program to resume execution at the next interaction in the calling program
iii. Indirect addressing modes
In indirect addressing mode operands are registers to point to locations on memory
Type of indirect memory dressing in 8086
1. Register indirect mode

In this addressing mode the effective address is in SI, DI or BX.
2. Based indexed mode
In this the effective address is sum of base register and index register.
3. Indexed indirect
In indexed interrupt addressing mode the contents of a register are added to a displacement
to generate an effective address
4. Based indexed displacement mode

In this type of addressing mode the effective address is the sum of index register,
base register and displacement.

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SAI MADHAN.

ii. Why are negative numbers represented in complements?

iii. Example of fixed point number

Representations can be made in 3 forms as:

1. Sign Magnitude Representation

As Negative numbers has to be complemented we could only

2. Signed 1’s complement:

Decimal Numbers Representation in 8 bitsSi

3. Signed 2’s complement

Decimal Numbers Representation in 8 bits

A) 2. Perform arithmetic operations:

i. Add -30 and -98 using signed 2’s complement

Deriving 2’s complement of -30 and -98

Decimal Number Signed magnitude

Decimal Number Signed 2’s complement

ii. Subtract -79 from 45

Derive 2’s complement of -79 and 45

Decimal Number Signed Magnitude

Decimal Signed 2’s complement

Given D10 = (56789123)10

B2 = 11 01100010 10001000 10000011

Given D10 = (56789123)10

Hex = (362 8883)H

ii. HexaDecimal to Octal

iii. ASCII to UTF-8

Given string = “Subject: Computer %$ Sc.”

Given ASCII UTF-8 UTF-8

iv. Octal to Decimal

Given octal= (345123)o

C. Circuit diagram for given function

On solving the K-map we get

𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷 + 𝐴𝐵𝐶𝐷

→ 𝐴𝐵𝐶(𝐷 + 𝐷) + 𝐴𝐵𝐶(𝐷 + 𝐷) + 𝐴𝐵𝐶(𝐷 + 𝐷) + 𝐴𝐵𝐶(𝐷 + 𝐷)

→ 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶

2. Number of parity bits required

Were n is 8 and assume i =3

→ 23-1 >= 8+3

Therefore for an 8 bit data atleast 4bits of error correction code is

3. correction of single bit error

Assume 4 bits binary data 1101 is the source

Source Data Add parity bits at source

If suppose the source data is received as 1001

E. 2Bit down counter

Present State Input Next State Flip Input

F. Floating point Number

A decimal +12.34 can be represented as

Difference between single precision and double precision Floating

In floating point number precision is the trade-off between the range

Representation of 0 in single precision

IEEE 754 single precision standard specifies +0 and -0 are special

Therefore IEEE 754 standard notation of +0 in single precision is

Representation of (-23456.05)10 in IEEE 754 single precision format

As the number is negative sign bit becomes ‘1'

Representation of (0.00025)10 in IEEE 754 single precision format

Therefore representation in IEEE754 single precision format is

ii. Capacity of the RAM

iii. Adress lines

Address mapping in direct memory

ii. Associate cache mapping is used

iii. Two way set cache memory is used

Need for DMA

How DMA differs from I/O.

Witch I/O technique is most suitable