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29/12/2018 Trying to constrain I2C interface

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FPGA DESIGN TOOLS (/s/topic/0TO0P000000MWKAWA4)

Altera Forum (/s/profile/0050P000008ARVLQA4) (Intel) asked a question.


September 21, 2011 at 3:54 PM (/s/question/0D50P00003yyNG9SAM/trying-to-constrain-
i2c-interface)

Trying to constrain I2C interface


I am designing an I2C serial interface, but I'm running into confusion setting up the timing
constraints for it. 
 

1 module Test
2 (
3 input wire scl_in,
4 input wire sda_in,
5 output reg sda_out
6 );
7 reg start_det;
8 reg stop_det;
9 reg sreg;
10 always @(negedge sda_in)
11 start_det <= scl_in;
12
13 always @(posedge sda_in)
14 stop_det <= scl_in;
15 always @(posedge scl_in)

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29/12/2018 Trying to constrain I2C interface

16 sreg <= { sreg, sda_in };


17
18 always @(negedge scl_in)
19 sda_out <= (sreg == 8'hA5);
20 endmodule

 
 
The basic period is 1uS, and in general SDA will transition near the middle of the SCL low time.
The only time this isn't true is when SDA is driven low at the falling edge of SCL 
 

1 create_clock -name "scl" -period 1000.000ns -waveform {0.000 500.000}


2 create_clock -name "sda" -period 1000.000ns -waveform {250.000
750.000}

 
 
For a repeated start condition, SCL is high a minimum of 260nS before the falling edge of SDA.
(Tsu;sta) 
For a start condition, SCL is held high at least 260nS after the falling edge of SDA. (Thd;sta) 
For a stop condition, SCL is high a minimum of 260nS before the rising edge of SDA. (Tsu;sto) 
 

1 set_input_delay -clock "sda" -max 740ns


2 set_input_delay -clock "sda" -max 740ns -clock_fall
3 set_input_delay -clock "sda" -min 260.000ns -clock_fall

 
 
For data input, SDA must be valid 50nS before the rising edge of SCL (Tsu;dat) and held for 0nS
after the falling edge of SCL. 
 

1 set_input_delay -clock "scl" -max 950ns


2 set_input_delay -clock "scl" -max 550ns -clock_fall

 
 
So, does this look right? 
 

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29/12/2018 Trying to constrain I2C interface

Also, (at the risk of tldr) the second attachment (tsu.jpg) shows th measured from the rising edge
of the clock, but tsu measured back from the Falling edge of the clock. Shouldn't both of them be
measured from the same clock edge? 
 
Thanks
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Altera Forum (/s/profile/0050P000008ARVLQA4) (Intel)


7 years ago

From my experience, when you are doing I2C, it is much better to over sample the inputs
rather than use them as a clock. We have seen multiple clocks due to the slow rise rate of
IIC lines. In the past we got around that by using a schmidt trigger on the inputs to get rid
of the bounce, but currently we are just using oversampling. 
 
But, if you are to do it this way, and it isn't just an assignment to figure it out but real world
application, all of the timing values are so slow you can just cut the paths and not worry
about it.
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Altera Forum (/s/profile/0050P000008ARVLQA4) (Intel)


7 years ago
 
--- Quote Start ---  
From my experience, when you are doing I2C, it is much better to over sample the inputs
rather than use them as a clock. We have seen multiple clocks due to the slow rise rate of

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29/12/2018 Trying to constrain I2C interface

IIC lines. In the past we got around that by using a schmidt trigger on the inputs to get rid
of the bounce, but currently we are just using oversampling. 
 
--- Quote End ---  
 
 
The goal is to turn off the clock when the FPGA isn't used, so I need an asynchronous I2C
interface. I've never had a problem with bouncing on the inputs, but I'm coming from an
ASIC background so we always had schmitt inputs with the 50nS glitch filter available. I'll
definitely add it to the list of things to check for this project. 
 
 
--- Quote Start ---  
 
But, if you are to do it this way, and it isn't just an assignment to figure it out but real world
application, all of the timing values are so slow you can just cut the paths and not worry
about it. 
--- Quote End ---  
 
 
You are probably right, but I've got the time to do it now and incomplete specs for the rest
so it seems like a good project to work on.
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