Elements of

1
Physical Design
Lecture# 13
VLSI Design
2
Layout Editors
 n+ (ndiff) is formed when Active is surrounded by nSelect
 p+ (pdiff) is formed when Active is surrounded by pSelect (and
nWell)
 An nMOS is formed when Poly cuts an n+ region in to two
segments
 An pMOS is formed when Poly cuts a p+ region in to two
segments
 No electrical path exists between conducting layer
 n+, p+, Poly, Metal etc.

 Unless a contact cut is used

 Active Contact, Poly Contact or Via

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 3
Layout Editors
 Layout Drawings

 A layout editor visually distinguishes among the layers

 By defining different colors or fill patterns for each layer
 A layout editor also provides
 Drawing layer using polygons, by first selecting appropriate layer
 To create any shape

 A background grid, the difference between each point is a specified

distance
 Layers can be drawn in any order
 Creation of layer mask using the layout pattern for the layer
 Observing the drawn dimensions

 Check and ensures that no design rules are violated

 Polygons on each layer may touch or overlap to form any share
 GDS output file after layout completion (sent to foundry called tape-out)
 Contains mask for each layer

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 4
Cell Concepts
 Introduction

 VLSI chips are design in a hierarchical manner.

 Individual transistor build gates
 Gates are cascaded to build complex logic and functional blocks
 And so on.
 The building blocks in physical design are called cells
 Try to remember creating sub modules in lab and instantiating them
 You can also create cells of NOT, NAND2, NOR2, NOR3 etc.
 Cell based designs are straightforward to visualize
 Input and output terminals are called ports

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 5
Cell Concepts
 Introduction

 Consider we have cells NOT (𝑋 ), NAND2 (𝑋 )&

NOR2 (𝑋 )

 Implement the logic function 𝑓 𝑎⋅𝑏

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 6
Cell Concepts
 Placement of Power Lines

 Consider a placement of powerlines

 𝐷 is the edge-to-edge distance between VDD and VSS

 And pitch 𝑃 𝐷 𝑤
 Where 𝑤 is width of 𝑉 and 𝑉 lines
 𝐷 is and important factor in drawing circuit layout

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 7
Cell Concepts
 Placement of Transistors

 After placement of power lines, we can start placing transistors

 There can be two different orientations for each MOSFET
 Can be vertically or horizontally

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 8
Cell Concepts
 MOSFET Widths
 MOSFETs widths are limited by 𝐷
 However orientation can be changed to allow
incorporating larger MOSFETs
 𝑊 is width of nMOS and 𝑊 is width of pMOS

Horizontal orientation
◦ Requires larger 𝐷
◦ But smaller 𝑋

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 9
Cell Concepts
 Fitting Cells Together

 The cells are combined to make complex units

 Shape of the cells affects how they can be fit together
 Placing the cells together is called tiling, where each cell is a tile
 Consider two complex cells made with individual cells
 Of large and small 𝐷

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 10
Cell Concepts
 Interconnect Routing
 Another task to be carried-out alongside placement
 Is routing of the interconnects which can be complicated

One approach is to place

logic cells in parallel, and
◦ Allocate space in between for
routing

As metal1 is used within cells

◦ We can use it parallel in
between logic cells

While metal2 lines goes

perpendicular
◦ Can cross logic cells safely

Often used in ASIC, but can be used otherwise

◦ May not offer best packing density
Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad
11
Class Exercise 1
 First make three cells of XOR, AND and OR Gate with proper
scale. Design a Full Adder layout using cell concept

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

12
Cell Concepts
 Weinberger Image
 An alternate approach uses alternate VDD and VSS powerlines
 Results in the Weinberger image
 Alternate logic cells are inverted
 No space reserved for routing
 Need to used Metal2 or higher
 Offers high packing density

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

13
Cell Concepts
 Port Placement
 I/O of a cells must be placed at convenient points
 To ensure smooth and convenient interconnect wiring
 Consider an example, where input is placed on the left
 Outputs on the right
 Poly gates are extended for connections with other cells
 There is no generic constraints on port placement
 Can be placed within a cells
 What needs to be ensured is that
 Cells can be wired together in a complex arrangement
 Which requires proper port placement
 when designing a cell

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

14
MOSFET Sizing
 MOSFETs are specified by aspect ratios (𝑊/𝐿)
 It defines 𝐴 𝐿 𝑊 and 𝐶 𝐶 𝑊𝐿
 We can say 𝐼 𝐼 , drain and source currents are approximately
equal
 Channel resistance (which impedes current flow), in a simplistic
form
 𝑅 𝑅 , , between source and drain regions

 Where 𝑅 , is sheet resistance

 Channel resistance is
 Inversely proportional to channel width

 𝑅 ∝

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

15
MOSFET Sizing cont.
 We are aware that 𝜇 𝜇
 The difference between carrier mobilities in nMOS and pMOS
 So, we can say that 𝑅 𝑅

 Mobility ratio 𝑟 , where 𝑟 1 between 2 and 3

 In order to design symmetric CMOS

 𝑟

 Results in 𝐶 𝑟𝐶

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

16
Unit Transistor
 In order to smoothly build-up a CMOS ICs
 We can define a unit transistor with specified 𝑊/𝐿
 Which is replicated
 Whose electrical characteristics are known, makes analysis easy
 Often unit transistor is defined to be minimum-size MOSFET
 Defined by design rules
 minimum width of poly and minimum width of Active mask

 We will get

 Also 𝐶 𝐶 𝑤 𝑤

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

17 Minimum Size FET with Active
Contact Features

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

18
Scaling of Unit Transistor

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

19 Scaling of Series Connected FET
Chain

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

20

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

21 Physical Design of Logic Gates
 The NOT Gate

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

22 Physical Design of Logic Gates
 The NOT Gate Rotated 90 Degrees

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

 23 Physical Design of Logic Gates
 The NOT Gate
 pFET Mobility higher than nFET
 r = 2.5
 Known as Symmetric Inverter
 Because resistance is equal

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

24
Assignment No 2 Q. No. 3
 Design a Full Adder layout using cell concept and using
minimum space

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad

25
Home Task
 Read about NAND and NOR Layout Cells and importance of
Vertical and Horizontal placement (Page 181 – 183)

Dr. Sohaib Ayyaz Qazi | COMSATS University Islamabad