Dear students,

Those who got less than 25 marks out of 50 marks in CAT1, you should submit
this slow learner assignment on or before 25th Feb 2019. (Note: I took questions from last
year CAT2 Paper)

1. Determine the Elmore’s delay for the given circuit when input changes from A=0, B=1 & C=0 to
A=1, B=0 & C=1 and vice versa. (Assume: Mobility of the nmos is thrice of mobility of pmos).

2. Calculate the propagation delay for the following circuit from A to output (dotted line).

A
4
B 5 5
9
4 50
C

3. Find-out the input capacitance and width of pmos and nmos of gates when the circuit gives
minimum possible propagation delay.

A
4
B ? ?
?
? 50
C

4. An IC is operated with 1 V, 180 nm process, which has 5 billion transistors, of which 20% are in
logic gates and the remainder in memory arrays. The average logic transistor width is 1080nm and the
average memory transistor width is 360nm. The memory arrays are divided into banks and only the
necessary bank is activated so the memory activity factor is 0.05. The static CMOS logic gates have
an average activity factor of 0.3. Assume each transistor contributes 0.01fF/nm of gate capacitance
and 0.08fF/nm of diffusion capacitance. Neglect wire capacitance for now (Though it could account
for a large fraction of total power). Estimate the switching power when operating at 1 MHz.

5. Draw the layout of a two input XNOR gate

6. Identify the output expression of the following layout?

7. Draw the schematic and stick diagram for the following function (using shared diffusion nodes)

E  A  B  C [ D  ( F  G)]  H

8. Suppose we wish to implement the two logic functions given by F = A + B + C and G = A + B +

C + D. Assume both true and complementary signals are available.
a) Dynamic CMOS b)n-p logic

9. Draw the schematic of 4 input NAND gate in a) Static CMOS b) Domino logic

10. Draw the schematic of 4input NAND and AND gate in CVSL