Documente Academic
Documente Profesional
Documente Cultură
16F84A
Chapter 2
Sections 1‐8
Dr. Iyad Jafar
Outline
y Overview of the PIC 16 Series
y An Architecture Overview of the 16F84A
y The 16F84A Memory Organization
y Memory Addressing
y Some Issues of Timing
Some Issues of Timing
y Power
Power‐up
up and Reset
and Reset
y The 16F84A On‐chip Reset Circuit
2
Overview of the PIC 16 Series
y The PIC 16 series is classified as a mid range
microcontroller
ll
y The series has different members all built around
,
the same core and instruction set, but with
different memory, I/O features, and package size
3
4
An Architecture Overview of the
16F84A
y 18 Pins / DC to 20MHz / 1K program Memory/ 68 Bytes of RAM / 64
Bytes of EEPROM / 1 8‐bit Timer / 1 5‐bit Parallel Port / 1 8‐bit Parallel
5 Port
An Architecture Overview of the 16F84A
6
The PIC 16F84A Memory and Registers
y g
y Program Related
7
The PIC 16F84A Memory and Registers
y g
y Program Memory
y 1K x 14 Bits
y Address range 0000H – 03FFH
y Flash (nonvolatile)
y 10000 erase/write cycles
10000 erase/write cycles
y Location 0000H is reserved for the reset vector
y Location 0004H is reserved for the Interrupt Vector
y Program Counter
y Holds the address of the next instruction to be executed
y Stack
y 8 levels (each is 13 bits)
y SRAM (volatile)
SRAM (volatile)
y Used to store the return address with instruction like CALL,
RETURN,RETFIE, and RETLW (interrupts and procedures)
y Instruction Register
8
y Holds the instruction being executed
The PIC 16F84A Memory and Registers
y g
y The Configuration Word
y A special part of the program memory
p p p g y
y Allows the user to configure different features of the microcontroller at
the time of program download
y Is not accessible within the program or while it is running
I t ibl ithi th hil it i i
9
The PIC 16F84A Memory and Registers
y g
Data Memory and Special Function
Registers (SFRs)
g ( )
y SRAM (volatile)
y Banked addressing to reduce
g
address bus size
y Special
Special Function Registers SFRs
Function Registers SFRs
y Locations 01H‐0BH in bank 0 and 81H‐
8BH in bank 1
y Used to communicate with I/O and
control the microcontroller operation
y General Purpose Registers
y Addresses 0CH – 4FH (68 Bytes)
y Used for storing general data
10
The PIC 16F84A Memory and Registers
y g
Special Function Registers (SFRs)
11
The PIC 16F84A Memory and Registers
y g
y Special Function Registers (SFRs) interacting with
peripherals
peripherals
12
The PIC 16F84A Memory and Registers
y g
y The Working Register
y Inside the CPU
I id th CPU
y Holds the result of the last instruction executed by the CPU
13
The PIC 16F84A Memory and Registers
y g
y Data Memory Addressing
y For PIC 16F84A, we need to select one of two banks (1‐bit)
F PIC 16F84A dt l t f t b k (1 bit)
and 7‐bits to select on of the locations
y Bank selection is done through using bits 5 and 6 of the
STATUS registers (RP0 and RP1)
STATUS registers (RP0 and RP1)
y For the 16F84A, only RP0 is needed since we have two
, y
banks
y In general, two forms to address the RAM (File Registers)
y Direct addressing – the 7‐bit address is part of the instruction
y Indirect addressing – the 7‐bit address is loaded in File Select
14 Register (FSR , 04H)
The PIC 16F84A Memory and Registers
y g
y Data Memory Addressing
15
The PIC 16F84A Memory and Registers
y g
y The STATUS Register (03H, 83H)
16
The PIC 16F84A Memory and Registers
y g
y Data Related
y EEPRM Data Memory
y 64 bytes Non‐volatile
y 10 000 000 erase/write cycles
y Used to store data that is likely to be needed for long term
U d d h i lik l b d df l
y Operation is controlled through EEDATA (08H), EEADR (09H), EECON1
(
(88H), and EECON2 (89H)
) ( ) SFRs
y To read a location
y store the address in EEADR and set the RD bit in EECON1
y data is copied to EEDATA register
d d
y To write to a location
y data and address are placed in EEDATA and EEADR, respectively
data and address are placed in EEDATA and EEADR, respectively
y enable writing by setting the WREN bit in EECON1 SFR
y store 55H then AAH in EECON2
y commit writing by enabling the WR bit
17
y Once the write is done, the EEIF flag is set in EECON1.
The PIC 16F84A Memory and Registers
y g
y The EECON1 Register (88H)
18
Some Issues of Timing
y The Clock
y The microcontroller is made up of combinational and sequential logic.
Thus, it requires a clock !
y Clock – a continuously running fixed frequency logic square wave
y Timers counters serial communication functions are also dependent
Timers, counters, serial communication functions are also dependent
on the clock
y Operating frequency has direct impact on power consumption
y Every microcontroller has a range for its clock
19
Some Issues of Timing
y Instruction Cycle
y The main clock is divided by a fixed value ( 4 in the 16
series) into a lower‐frequency signal
y The cycle time of this signal is called the instruction cycle
y The primary unit of time in the action of processor
20
Some Issues of Timing
y Pipelining
y Every instruction in the computer has to be fetched from memory and
Every instruction in the computer has to be fetched from memory and
then executed. These steps are usually performed one after another
y The CPU can be designed to fetch the next instruction while executing
th
the current instruction. This improves performance significantly!
t i t ti Thi i f i ifi tl !
y This is called Pipelining
y All PIC microcontrollers implement pipelining (RISC
All PIC microcontrollers implement pipelining (RISC+Harvard
Harvard make it
make it
easy)
21
Power‐up and Reset
y On power‐up, the microcontroller must start to execute program
stored in the program memory from its beginning (address 0000H)
y A specialized circuit inside the microcontroller detects this and is
responsible for putting the microcontroller in the reset state:
y the program counter is set to zero
h
y the SFRs are set such that the peripherals are in safe and disabled
y Another way to put the microcontroller in the reset state is to apply
Another way to put the microcontroller in the reset state is to apply
logic zero to the Master Clear input (MCLR)
y Some reset circuit configurations
g
22
The 16F84A on‐Chip Reset Circuit
Logic
L i ‘1’ on
this activates
the Reset
Signal
Logic
L i ‘1’ on thi
this iinputt
deactivates the Reset
Signal and causes the
microcontroller to exit
th resett state
the t t
23
The 16F84A on‐Chip Reset Circuit
Example on reset timing when MCLR is connected to VDD
24
Summary
y The PIC 16F84A series is a diverse and cost effective
family of microcontrollers
family of microcontrollers
y The PIC 16F84A is pipelined RISC processor with
Harvard architecture
Harvard architecture
y The PIC 16F84A has three different memory types
y An important memory area is the Special Function
Register area which act as link between the CPU and
peripherals
y Reset operation must be understood for proper
p p p
operation of the microcontroller
25