2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)
Design of QCA Circuits Using New 1D Clocking
Scheme
Suman Rani
School of VLSI Design and embedded system
Design,
National Institute of Technology
Kurukshetra, India
sumanbhukal23@gmail.com
Abstract— This paper considers the proposed clocking scheme
for Quantum-dot Cellular Automata (QCA) designs; this scheme
utilizes only single or regular (900) cells for circuit design. Based
on the analysis of previous schemes, use of single (regular) cells
rather than both regular and rotated cells is believed to be an
important idea for the QCA designs. According to the previous
clocking schemes there are no such schemes exist where only
single phase cells are used for circuit design. The main drawback
of the previous schemes is that during the fabrication, there is a
possibility of “cross-coupling” between the two wires of 900 and
450, when arrangement of any cells is misaligned. But there is no
misalignment when only single cells are used. The proposed
scheme is based on 1D clocking scheme and aim is to provide
crossing and information flow with only single or regular cells.
Some Combinational circuits such as Adders Half adder, Full
adder, 2-Bit adder and 4-Bit adder are designed using proposed
1D clocking scheme with only regular cells (900). It is observed
that the circuits designed using this proposed clocking scheme
achieves same results in comparisions to the best previous
relavant works. Simulation and Verification are carried out by
QCADesigner.
Keywords— quantum-dot cellular automata, emerging
technology, half adder, full adder, 2-bit adder, 4-bit ripple carry
adder
I. INTRODUCTION
After the past few decades, the devices based on the
CMOS technology have been continually scaled down in size.
There are many critical issues have arrived in CMOS design
i.e. leakage current and power consumption. To overcome
these issues some new technologies have arrived, Quantum-
dot Cellular Automata is one of the suitable new technologies
that was introduced in 1993 [1]-[3]. QCA is a nano-electronic
platform having advantages of high speed computation, small
area requirement and extremely low power dissipation. So
that, for the design of efficient arithmetic circuits in QCA
many efforts have been concentrated, for example adders and
multipliers etc.
In this paper, we acknowledge the issues related to timing
and clocking of QCA systems for high performance
computing. Firstly, as we studied various clocking schemes
Trilokaya Nath Sasamal
Department of Electronics and Communication
Engineering,
National Institute of Technology
Kurukshetra, India
tnsasamal.ece@nitkkr.ac.in
(1D, 2D and 2D-wave clocking schemes) which are used to
solve these issues. These schemes are uses both rotated cells
and regular cells for data transformation and crossing but to
solve these issues we can also use only regular cells. The new
clocking scheme proposed, using only regular cells for signal
propagation as well as crossing, is based on 1D
characterization of data propagation and crossing also. In
previous paper which is introduced by S. Rani et al [9], some
combinational circuits were designed. And some more
combinational circuits (high level circuits) are designed such
as half adder, full adder, 2-bit adder, 4-bit ripple carry adder
and 16-bit ripple carry adder using proposed clocking scheme.
Simulation results indicate that our designs with new clocking
scheme achieve same results in comparison to the best
previous relevant works. Simulation and verification are
carried out by QCADesigner [8].
Remainder of this paper is organized as follows. Section II
represents the overview of QCA in which we discuss about
QCA cell, wire, operation of QCA cell, QCA logic and
clocking scheme. Section III presents the related works
(different clocking schemes). Section IV discuss about
proposed clocking scheme based on 1D scheme with only
regular cells. Section V presents detailed simulation results
using QCADesigner. Section VI addresses the conclusion and
future directions.
II. QCA OVERVIEW
A. QCA Cell and Wire
The basic element in QCA device is QCA cell, which is in
a square shaped nanostructure with four quantum dots one in
each corner. Here we have to use four-dot cell model, In
which two electrons are placed at diagonal site within the cell
due to coulombic repulsive force.
Fig. 1. Representation of QCA cell and wire.
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)
Due to tunneling action occurs in cell, two ground states of
charge configuration in cells can be used to represent binary
states i.e. “1” and “0” with polarizations of +1 and -1
respectively [3]-[6].
QCA cells are of two types one is Regular and another is
Rotated cell. For coplanar crossings rotated cells are used.
QCA wire is a set of cells and these cells are arranged adjacent
to each other in a chain as shown in Fig. 1.
B. QCA Operation and Logic Gates
The main feature of QCA designs is that the data stored in
QCA is based on the position of each electron in the cells,
can’t be stored in “voltage or current levels” as in CMOS
technology. The basic principle of how to operate QCA is
“columbic interaction” that connects the state of one cell to the
state of another cell in [3] and [6]. Majority voter and Inverter
are also the fundamental element like QCA cell and wire.
Inverter and three input majority gate is shown in Fig. 2 in [1]-
[3].
Fig 2 Representation of Inverter and majority gate.
A three input majority gate consists of five QCA cells and
the output of majority gate will be decided by the majority of
its inputs states. In that case if the inputs of majority voter
(gate) are A, B and C, then the output OUT of majority voter
(gate) is shown in the equation
OUT= AB + BC + AC (1)
C. QCA Clocking Scheme
Clocking is the concept of giving direction to data flow in
QCA circuits. In QCADesigner four-phase zone clocking
scheme [5] is used, and there is a phase shift of 900 between
each clocking zone as shown in Fig. 3. There are four phases
in a QCA cell; called Switch, Hold, Release and Relax in [4],
[6] and [7]. During the Switch phase, QCA cells are starts to
unpolarized and the inter-dot barriers of cell are low.
According to the state of the input cells, the potential barriers
are raising and the cells become polarized. The actual
switching appears in this phase. At the end of this phase, the
electron tunneling is to suppress due to higher the barriers and
the states of cell are fixed. the next stage. In the Release phase,
due to lowered potential barriers the states of cells become
unpolarized again. In the final phase (relax), the barriers of the
cells remains lowered and the state of cells remains
unpolarized
During the Hold phase, the potential barriers are high,
due to which the sub-array outputs are used as the inputs of.
III. RELATED WORK
fig-3 Representation of four-phase of QCA clock and Clock
zones
signal.
This section will discuss about the various clocking
schemes in which both regular and rotated cells are used. As
we know that clocking is used to give the direction of
information flow and will help in improving the logic
computation. The clocking schemes which are discussed in
this section provide another easy physical implementation as
compared to other clock schemes and freedom to information
flow in all directions.
A. 1D Clocking Scheme
1D clocking scheme is firstly introduced by Lent et al. [6].
In this scheme a design is divided into multiple regular zones
of different clock phase in single dimension. The data
propagate in this scheme is only in one direction, it means the
partitioning of circuit into regular columns of cell because it
makes easy to lay CMOS wires beneath for clocking. But the
limitation of this scheme is that it requires long wires in single
direction even for circuits of moderate complexity in [6].
Fig 4 Representation of 1D Clock Scheme and 4:1 multiplexer using 1D
clocking scheme.
B. 2D Clocking Scheme
This scheme is introduced by vankamamidi et al. [6]. To
remove the limitation of 1D clock scheme, every column is
again divided into small clock zones due to which the length
of the long wire will be reduced
Fig. 5 Representation of 2D clock scheme and 4:1 mux using 2D clock
scheme.
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

C. 2D Wave Clocking Scheme

This scheme is also introduced by vankamamidi et al. [6].
This is an effective scheme in which data processing and
execution is done in parallel way within a different timing
framework. The clock zones which are diagonally placed are
switched simultaneously in [6] and [7].

Fig 7 Representation of Proposed clocking scheme.

Fig 6 Representation of 2D wave clocking scheme and 4:1 mux using 2D

wave clocking scheme.

The logic propagate in horizontal and vertical direction

because of the diagonal switching, which limits the data
propagate in only two directions at any time in a given zone.
One other limitation is that when SWITCH a particular zone
with right data two other clock zone “one placed above and
one placed to the left” should be kept in the HOLD state.

However, as we studied such schemes we analysed that

these clocking schemes are based on both regular and rotated
cells, in which need of rotated cell is due to occurrence of
crossing because of long feedback wire consumes more delay.

IV. PROPOSED CLOCKING SCHEME

According to the previous clocking schemes there are no such
schemes in existing works, in which only single phase cells
are used for crossing as well as data propagation. In previous
coplanar crossover schemes both cells (900 and 450) are used
for circuit design. The main limitation of these schemes is that
there is a possibility of cross coupling between the two wires
(one of 900 and another is 450) during fabrication, when
placement of any cells is misaligned. In the new scheme only
single phase cells are used, so there is no misalignment of
cells. For significant improvement of crossing as well as data
propagation can be achieved by new proposed clocking
scheme.
The principle of the new proposed clocking scheme is
based on using only regular cells not on rotated cells. As we
know rotated cells are used when crossing occurs and also to
reduce the long wires, because there is no interference
between regular cell and rotated cell in same phase zone. But
in the new scheme we propose an area shown in Fig. 7 for
clocking in which crossing as well as information propagation
is possible with only single cells (regular cell). For example 4-
bit ripple carry adder under the proposed clock scheme as
shown in Fig. 8.
Fig 8 Representation of 4-bit ripple carry adder using proposed clocking
scheme.
In this scheme design is divided into multiple regular clock
zones of different clock phase in a single direction similar to
1D clock scheme as shown in Fig. 4. The boxes in each clock
zones is the set of cells arranged in series (either from top side
or from bottom side) phase for example (0, 1, 2), (2, 3, 0) and
(1, 2, 3) and so on. In previous paper [9] some combinational
circuits were designed such as 2:1, 4:1 and 8:1 multiplexers.
These boxes should be used for both information flow as
well as crossings. Consider an example with 4-bit ripple carry
adder as shown in Fig. 8 under proposed clock scheme, in
which design is divided into four clock zone (0, 1, 2 and 3).
Under the new scheme 4-bit ripple carry adder take twelve
complete clock cycles.
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)
V. SIMULATION RESULT
QCADesigner 2.0.3 is used for QCA circuits. In this
section, we represent the simulation waveforms of half adder,
full adder and 2-bit adder under the proposed clocking scheme
in Fig. 10, Fig. 12 and Fig. 14 respectively. For all the circuit
simulations, the dimension of cell and size of a dot used in
QCA is 18×18 nm2 and 5×5 nm2 respectively. For results,
coherence vector engine of the QCADesigner is used.
A. Half Adder
The design of half adder is shown in Fig. 8, which is the
basic block for any adder (i.e. full adder, 4-bit ripple carry
adder etc.). In this Fig. 9 the three AND gates are sum up in an
OR gate. Simulation results are shown in Fig. 10. Input A is
defined by (01010101)2 and input B is defined by
(00110011)2. Resulted output sum is given as bit strings
(0110011)2 and carry output is given as bit strings (0001000)2
as per the logic behavior of a half adder.
When input A and B is 0 the output sum and carry both 0.
When input A and B is 1 than output sum and carry will be 0
and 1as shown in Fig. 10. The equation of the half adder
outputs can be expressed as bellow:
Sum = A⊕B
Carry = AB
Fig 9 Representation of Half adder using proposed clocking scheme.
Fig 10 Representation of waveform of 4-bit ripple carry adder using proposed
clocking scheme.
There is a delay of “Five Clock periods” because it takes five
clock periods for the inputs to reach the output.
B. Full Adder
The design of Full adder is shown in Fig. 11, and
simulations results are shown in Fig. 12 for inputs and outputs.
Input A is given by the bit string (0000111100001111)2, B is
defined as (0011001100110011)2 and C is defined as
(0101010101010101)2. Resulted output Sum and carry is
defined by (0110100101101001)2 and (0001011100010111)2
as per the logic behavior [10] of a full adder. The equation of
the full adder outputs can be expressed as bellow:
Sum = A ⊕ B ⊕ Cin (4)
Carry = AB + BCin + ACin (5)
When input A is 0, input B is 0 and input C is 0 then the
output Sum and carry will be 0. If input A is 1, B is 1 and
input C is 1 then the outputs Sum and carry will be 1
respectively as shown in Fig. 12.
(2)
(3)
Fig 11 Representation of Full adder using proposed clocking scheme.
Delay of “Three Clock cycle or twelve clock periods” has
been occurred here for the inputs to reach the output.
Fig 12 Representation of the waveform of Full adder using proposed clocking
scheme.
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

C. 2-Bit Adder The proposed general structure of 16-Bit Ripple carry

adder as shown in Fig. 15 is realized from the proposed 4-Bit
Ripple carry adder using new proposed 1D clocking scheme.
The 16-Bit Ripple carry adder uses 16 no. of Full adder as
shown in Fig. 15. There is a delay of “48 Clock cycles”
because it takes 48 complete clock cycless for the inputs to
reach the output.

For n-bit ripple carry adder, the number of majority

voters and inverters are 3n and 3n, respectively. The delay of
an n-bit ripple carry adder is “n×3”, which can be deduced
from its layout.
fig 13 Representation of 2-Bit adder using proposed clocking scheme.
The area information of all the adders is listed in TABLE I.
below:

TABLE I. COMPARISION RESULTS

Adder n-Bit Cell Area Delay Cross-

count (um2) (clock over
phase) Type

HA _ 72 0.14 5 Coplanar
(proposed) (clocking
based)

Fig 14 Representation of waveform of 2-bit adder using proposed clocking FA 1 264 0.58 12 Coplanar
scheme. (proposed) (clocking
based)

The design of 2-bit adder is shown in Fig. 13 and

FA 2 756 2.77 24 Coplanar
simulations results are shown in Fig. 14 for inputs and outputs. (proposed) (clocking
When input Ain [1:0] is given by (13103)10 , Bin [1:0] is defined based)
as (21203)10 and Cin is defined as (00000)2 in red cicles
respectively, than the resulted output sum [2:0] is defined by FA 4 1556 5.53 48 Coplanar
(34306)10 in red box. When input Ain [1:0] is given by (proposed) (clocking
(13103)10 , Bin [1:0] is defined as (21203)10 and Cin is defined based)
as (11111)2 in green circles respectively, than the resulted
output sum [2:0] is defined by (45417)10 in green box. There is FA 16 20298 74.68 192 Coplanar
a delay of “Six Clock periods” because it takes six clock (proposed) (clocking
based)
periods for the inputs to reach the output.
[11] CLA 16 4489 3.65 17 Coplanar
D. 16-Bit Ripple carry Adder (Rotated
cells)

[11] BKA 8 1462 1.06 10 Coplanar

(Rotated
cells)

[12] RCA 4 558 0.85 20 Coplanar

(Rotated
cells)

VI. CONCLUSION
fig 15 Representation of 16-bit Ripple carry adder using proposed clocking
scheme. In this paper, we have considered a new clocking scheme
for QCA designs circuits based on single or regular cells. The
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

designs of half adder, full adder, 2-bit adder and 4-bit ripple
carry adder using proposed scheme achieves same results in
comparison to the best previous relevant works. The proposed
clocking scheme is based on 1D technique and aim is to
provide crossing and information flow with only regular cells.
Simulation and verification are carried out by QCADesigner.

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