Top-Down Analog Design Methodology Using Matlab and Simulink
Naveen Chandra and Gordon W. Roberts
Microelectronics And Computer Systems Laboratory, McGill University
3480 University Street, Montreal, Quebec, Canada H3A 2A7
{ naveen,roberts) @macs.ece.mcgill.ch
Tel: 1-514-398-6029. Fax: 1-514-398-4470
ABSTRACT
This paper presents a new design methodology, featuring top-down
design techniques iri cor~jurictioriwith an optirnicatioii process for
the creatiori of arialog or nii.red signal iiitegrated circuits. As a re-
sult, the requirements of the building blocks will be specified prior
to the undertaking of traiisistor lewl siniulations. saving valrred de-
sign time. This method has the advaritage that designs can be imple-
merited with cui-rently used, arid available tools. A design featuring
a switched capacitor delta-sigma niodulator will be presented.
1. Introduction
Design of an analog system primarily consists of three obstacles:
( 1 ) Selection of an architecture.
( 2 ) Determining the specifications of the analog building blocks
necessary to implement the chosen architecture.
(3) Minimization of the effects of circuit non-idealities.
These are usually done separately, and more often than not, most
of the building block specifications and non-idealities are
explored at the transistor level using circuit simulation programs.
To verify the circuit with respect to changes in passive component
and transistor characteristics requires simulation over the full
range of these variations. Obtaining performance curves when
considering a single architecture, let alone multiple architectures,
also requires multiple simulations. Attempting to perform this
type of analysis at a low level can be problematic due to long
simulation times. As a result, the design cycle will take too long to
practically meet the market demands for the technology. In
addition, the entire procedure must be carried out for each
architecture selected, which forces the designer to be very careful
for fear of losing much valued time.
Based
Parameters
Values
Results
+
Results
(a) (b)
Figure I Design Using (a)Prevalent (6) Proposed Methods
V-3 19
0-7803-6685-910 1/$10.000200 I IEEE
To reduce the number of design iterations and better explore the
design options, it is beneficial to perform an analysis at the system
architectural level before starting transistor level design. This
allows for a feasibility analysis in which all the design
considerations are treated at the highest level of abstraction. The
ultimate goal is to have the low level circuit parameters dictated
by the selected architecture and desired performance.
In section 2, the motivation for the design methodology is
discussed. We continue in section 3 with a design example
featuring a AZ modulator. This is followed by simulation results in
section 4, and wrapped up with concluding remarks in section 5.
2. Design Methodology Motivation
Choosing the specifications for an analog circuit given a set of
design objectives such as minimal area and power, is potentially a
very complicated and time consuming process. This task is further
made difficult by the fact that the number of specifications to deal
with is usually very large. and vary over wide ranges from one
application to another.
There exist tools aimed at fully automating the design process.
however they are limited to a small number of fixed schematics [I,
21. These tools, .which are not designed to be reproduced, remove
the designer from the process, and do nothing to increase the
designer’s knowledge. Furthermore, the techniques used in these
programs are hidden and cannot be applied to other designs.
Due to the uncertainty that arises with a change in technology. it is
more amenable to consider a design process that can begin without
a complete dependence on a specific technology. High level
optimization geared design avoids this reliance the longest, and
provides the designers with values for familiar parameters (i.e. g,,,
and rol,, for an OTA), which provide excellent guidelines for the
construction of a device. A comparison of this method and the
currently used methods can be seen in Figure 1 .
The main focus is to provide a means of tackling the design
problem by presenting a simple to implement methodology that
mnkes use of widely used and available tools. This allows the
procedure to be implemented and reused with little difficulty or
expense [3].In short, SIMULINK is used to implement the system
architecture and model non-idealities, while MATLAB [4] is used
to create routines to optimize the circuit parameters.
2.1. Optimization Procedure
Optimization concerns the minimization or maximization of a
function. In the case of analog systems, the objective is to
maximize or minimize a given set of performance criterion (such
as SNDR, power. area or settling time).
 Circuit w OPTZMIZATION
Dcsired
Propcrtv
Figure 2 Optimization Procedure
In order to do so, one must establish a trackable set of variables
(g,Jl,ro, Ibias or C,oad)that can be used to model the system while
simultaneously providing a link to the performance criteria. An
illustrative flow of this procedure can be seen in Figure 2. The
property measurement block detects particular attributes of the
output signal from the circuit and compares it with the desired
behaviour. The error signal is then used to adjust the key
parameters such that the error is minimized. It is using this very
simple principle that the proposed top-down methodology is
executed.
2.2. Isolating the Key Parameters
A set of guidelines that clarify the MATLAB design space will be
presented to carry out the design methodology. Familiarity with
the MATLAB optimization toolbox will be assumed.
The optimizer is split into three parts, and is illustrated in Figure 3:
(1) The MATLAB Optimizer Block, which receives an error value
and accordingly adjusts the key parameters given to it in order to
minimize any further error. On the first run, the optimizer begins
by using the initial conditions supplied to it for the key parameters.
(2) The SIMULINK System, with its built in nonidealities. This is
called by the optimizer so that data for property measurements can
be obtained (e.g. getting data to produce SNDR calculations)
through transient simulations.
( 3 ) The MATLAB Evaluation Block. This block receives data
from the SIMULINK System, evaluates the results based on
constraints (bounds) on the key parameters, and produces a value
for the error based on the designer's criteria. When the error is
low enough the process will stop and deliver its results.
As a result. for each design it is necessary to identify the key
parameters along with the error measurement criteria and
constraints.
2.2. I . Initial coiiditioiis
A good set of initial conditions or an adequate bounding of the
variables are needed for improved Optimization efficiency, and to
increase the chances of obtaining a convergent solution.
The best set of initial conditions and bounds will usually come
from the designer, as a designer usually has a better intuitive
understanding, and more knowledge concerning the feasibility of
certain values. In addition. the knowledge of transistor parameters
such as ro and gn,can help to obtain all of the information needed
V-330
SIMULINK
SYSTEM
EVALUATION
Exit if error
low enough
Figure 3 Optimization Setup
for setting bounds on variables. Preliminary simulations in SPICE
can solve this problem quickly and efficiently.
For example, the measurement of ro for a single transistor is a
trivial matter, and based on this value a range of values for rolctof
an OTA can be constructed. This process is very simple, and only
need be done once for each new technol'ogy.
Bounds can also be created based on the designer's preference.
For example, if a capacitance is desired, then upper and loRer
bounds can be set so that no solution will contain too low or 030
high a capacitance for the designer's liking. Once bounds have
been chosen for each of the key parameters, choosing the initial
conditions is not so arduous a task, as values within those bounds
can be taken as a starting point.
2.2.2. Additional Factors
There are additional factors that can alter the behaviour of the
system. As examples, the input and output capacitances of an
amplifier along with the loading capacitance of the common-mode
feedback circuit can affect the settling times of integrators. Tht:se
parameters can be accounted for by including them in with other
key parameters. For example, the load capacitance parameter, CL,
can be altered to reflect this. The inclusion of these additional
factors can be left to the discretion of the designer, or can be part
of a larger iterative design procedure.
3. EA Design Example
To best explain the procedure, this methodology will be explained
using a Delta-Sigma (AX) analog to digital converter (ADC),
which despite a high tolerance for non-idealities is still governed
by the limitations of its analog building blocks, especially at the
input stage where no noise-shaping has taken place.
3.1. Isolating the Key Parameters
In order to best utilize the optimization procedure, it is first
necessary to isolate the key parameters that influence
performance. For a high resolution switched-capacitor AZ
modulator. it can appear that there is a large set of parameters to
optimize. However, if one examines its building blocks carefully,
most of the factors that affect the system's performance can be
related to a small set of parameters, which will now be explored
3.1.1. kT/C Noise
A critical source of noise in the system, is the kT/C noise injected
into the first stage integrator of the modulator. As a result, the
input capacitors must be large enough to counter the additive noise
effect that results. Therefore the first key parameter is the input
 Table 1: OTA Non-idealities

Non-ideality I Result
-7
Random Zero-Order

Saturation
kT/C noisel

1 /Supply-factor
Sum1
~

Slew Rate Limiting Noise due to incomplete settling (1)

and harmonic distortion %(ti Product3

Thermal Noise 1 Added white noise Figure 4 kT/C Noise Model in SIMULI"

Table 2: Key Parameters for Modeling (1>

Kint

Cascode
1
I

Two-Stage Class A
I

I Two-Stage
ClassAB
Random ZerQ-Order Gain
Number Hold

Figure 5 OTA Noise Model in Simuliiik

sampling capacitor of the first integrator (Cs).
3.1.2. OTA Parameters
The OTA is the most critical component of the modulator, as its
non-idealities causes an incomplete transfer of charge, leading to
nonlinearities. The key parameters that govern its behaviour are
isolated and examined in Table 1.
There are three OTA topologies commonly used in the design of
A I modulators. From Table 3. we can see that the main sources
for non-idealities can be related to a few OTA parameters. It is
important to note that roI refers to the output resistance of the fist-
stage, I,,,f to the current in the second stage, C, to the load
capacitance, and C, to the compensation capacitance.
3.2. Modeling in Siinuliitk
In order to perform behavioural simulations of AX modulators
while taking into account the non-idealities, it is necessary to
create models. A set of models have been proposed that attempt to
simulate the non-idealities in SIMULINK [5]. The following work
is intended as modifications and extensions to them, for the
purpose of providing reference to the key parameters in Table 2.
This makes them more suitable for an optimization environment.
3.2.1. Switch Tlzerinal Noise
The thermal noise associated with the switching due to input
sampling onto the first integrator can be modeled as follows:
y(t) = ki,lt:k[x(tj +nswitc~i(t)l
number with unity standard deviation. This has been implemented
in a SIMULINK, and can be seen in Figure 4.
It is important to note that the formula used in theflu) block with
its input ki,,f, implements the nsn,ifc,,(t)formula. A Sirppl)~fncror
block is present for simulations in which it is desired to normalize
the supply voltage. If no such normalization is desired, then
SupplyJictor should be set to I.
3.2.2. OTA Noise
The input referred noise of an OTA can be modeled as follows:
y( t ) = k.~ n r [x(t) +nOTA(t)l (2)
where n O T A ( r ) = V I ?. R N ( t ) , kirlr is the integrator gain, Vn is
the OTA RMS noise voltage. and RN(r) is a Gaussian random
number with unity standard deviation. The model can be seen in
Figure 5 [ 5 ] .
3.2.3. SC Integrator Non-Idealities
The diagram in Figure 6, incorporates the finite gain, the
saturation levels. the finite bandwidth and the slew rate limiting of
the OTA. The formulas used here depend on the type of OTA used.
From the diagram, it can be noticed that a Slew & Bandwidth
MATLAB function block exists that interfaces with a multiplexer.
The slew and bandwidth behaviour of the OTA were modeled
based on analysis in which their effects in a switched capacitor
integrator are interpreted as a nonlinear gain [6]. There are three
basic conditional states that can occur: complete bandwidth
(1)

where E'
I I ~ ~ , , , ~ ~ ~=, , ( ~ ) RN(r) and where kirlf is the
limiting, complete slew rate limiting, or first slew rate followed by
bandwidth limiting. These are all mutually exclusive, and are
selected based on the present input voltage and the previous output
voltage. Due to this conditional nature, the modeling was much
integrator gain. Cs is the input sampling capacitor, k is Boltzman's easier accomplished through the use of a MATLAB function.
constant. T i s temperature, and RN(r) is a Gaussian random

V-32 1
 Figure 6 Non-Ideal Integrator Model in SIMULINK
3.3. Optirnizatioii Setup
For this specific case, the folded cascode OTA was chosen, and as
a result, the key parameters that necessitated optimization were
Cs, gm,ro. and Ibias. Therefore, the next step is to define both the
error measurement criteria and the constraints.
3.3.1. Error Measureinent Criteria arid Coiistraiiits
It is important to note that these criteria can be as simple or as
complicated as the designer wishes. The more criteria that are
given translates into a longer optimization routine, but a final
result that is closer to the overall goal. In this case these were
formulated based on the following three criterion:
( I ) Minimization of Area. Since the capacitance required in single
loop modulators usually accounts for at least half of its area, the
area constraint placed an emphasis on minimizing the capacitance.
(2) Minimization of Power. The main power consumption in the
modulator comes from the OTA used in the first stage. As a result,
constraints were placed on the bias current in order to place an
upper bound on power consumption by minimizing the current.
( 3 ) Maximization of SNDR. Since SNDR is a dominant measure
of a modulator’s performance, lower limits were placed on its
value, with an emphasis placed on its maximization. The
SIMULINK system was used in order to get the data for the
SNDR measurements.
4. Simulation Results
This optimization procedure was applied to the design of a 16 bit,
3rd order AX ADC, in which the primary objective was to design a
lowpass, audioband, single bit, modulator. with an oversampling
ratio of 128.
In the ideal case the SIMULINK simulation of this modulator
yields peak SNDR of 105.72 dB, and a dynamic range of I12 dB,
which can be seen in Figure 7(a). After the addition of the models
that were presented in section 3, the SIMULINK diagram was
constructed (Figure 8). and the optimization routine was run.
The process resulted in feasible design values (g, = 3.3 m A N , ro
= 960 162. Ibias = 450 PA, and C s = 4.5 pF, for a load of 8.2 pF).
An SNDR curve which reflected the modeled nonidealities and
can be seen in Figure 7(b). The SIMULINK simulation of the
nonideal modulator yields peak SNDR of 99.45 dB, and a
dynamic range of 102 dB. A chip has been sent for fabrication in a
0.25 pm process.
v-323
(a) Ideal (b) Nonideal
Figure 7 SNDR Plots f o r 3rd Order Modulator in SIMULINK
Figure 8 Nonideal System in SIMULINK
5. Conclusion
A new design methodology for analog or mixed signal integrated
circuit components was presented. The benefits of the top-down
optimization were presented, which featured a shorter design
cycle, along with ease of implementation and reproducibility. The
design of a A 2 modulator was presented to illustrate the benefits
of this methodology.
Acknowledgments
This work was supported by NSERC, the Canadian Microelectron-
ics Corporation, and Micronet. a Canadian network of centers of e.K-
cellence dealing with microelectronic devices, circuits, and systems.
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