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In the following, d, s, and t are general purpose registers. Register d receives the result of
operation between the contents of registers s and t .
branch if s == t
beq s,t,addr
A branch delay slot follows the instruction.
branch if s != t
bne s,t,addr
A branch delay slot follows the instruction.
lw d,off(b)
d <-- Word from memory address b+off
off is 16-bit two's complement.
or d,s,$0 d <-- s
if s < t
d <-- 1
else
slt d,s,t
d <-- 0
if s < imm
d <-- 1
else
slti d,s,imm
d <-- 0
if s < imm
d <-- 1
else
sltiu d,s,imm
d <-- 0
unsigned operands
if s < t
d <-- 1
else
sltu d,s,t
d <-- 0
unsigned operands
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