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High-Performance Polymer-Small Molecule Blend
Organic Transistors
By Richard Hamilton,* Jeremy Smith, Simon Ogier, Martin Heeney,
John E. Anthony, Iain McCulloch, Janos Veres, Donal D. C. Bradley, and
Thomas D. Anthopoulos*
Solution-deposited alternatives to amorphous silicon have been
pursued commercially for over a decade.[1–3] Introduction of an
economically viable technology that enables large area flexible
displays[4,5] as well as ubiquitous cheap electronics such as
radio-frequency identification tags[6,7] is expected to be highly
disruptive to the silicon-dominated market.[8,9] Solution-
deposited semiconducting organic small molecules[10–14] and
polymers[15–17] are viable approaches that promise to meet the
challenge. To date, small molecules have provided the highest
headline field-effect mobilities,[18,19] but device-to-device varia-
tion due to morphology anisotropies makes large area deposition
via printing difficult,[20,21] while the high solubility of small
molecules makes finding orthogonal solvents for further solution
processing a considerable constraint. Polymers, however,
demonstrate excellent device uniformity[22] and solution rheology,
which makes them good candidates for large area printing,[5] but
have not yet demonstrated the high mobility to make them truly
useful in commercial devices.[23]
Combining the high mobility of crystalline small molecules
with the device uniformity of polymers is very attractive and has
been approached in a number of ways. These include increasing
the crystallinity of a polymer such as poly-3-hexylthiophene
(P3HT)[16] by introducing more rigid units into the polymer
back-bone reducing conformational freedom and creating
regiosymmetric monomers. Polymer-small molecule blends have
[*] Dr. R. Hamilton, Prof. I. McCulloch
Department of Chemistry, Imperial College London
South Kensington, SW7 2AZ (UK)
E-mail: R.Hamilton@Imperial.ac.uk
Dr. T. D. Anthopoulos, J. Smith, Prof. D. D. C. Bradley
Department of Physics, Imperial College London
South Kensington, SW7 2AZ (UK)
E-mail: Thomas.Anthopoulos@Imperial.ac.uk
Dr. S. Ogier
UKPETEC, NETPark, Sedgefield
County Durham TS21 3FD (UK)
Dr. M. Heeney
Department of Materials, Queen Mary, University of London
Mile End Road, E1 4NS (UK)
Dr. J. E. Anthony
Department of Chemistry, University of Kentucky
Lexington, KY 40506-0055 (USA)
Dr. J. Veres
Eastman Kodak, 1999 Lake Avenue
Rochester, NY 146500 (USA)
DOI: 10.1002/adma.200801725
1166 ß 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
previously been investigated[24,25] in an attempt to produce
ambipolar devices but rather than enhancing performance, the
blending in these investigations appeared to diminish the peak
electron and hole mobility of each component. Using a blend of
small molecules and polymer to enhance the performance and
improve deposition has been described in the patent litera-
ture.[26,27] By blending a soluble, highly crystalline p-type small
molecule organic semiconductor (OSC) with an inert or
field-effect active polymer significant enhancement in perfor-
mance is claimed.
Here, two acene semiconductors first described by Anthony
and co-workers, 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-
pentacene)[28] and 2,8-difluoro-5,11-bis(triethylsilylethynyl)an-
thradithiophene (diF-TESADT)[18,29] (Fig. 1), are blended with
both inert and semiconducting polymers with the expectation that
peak device performance will be maintained while device
uniformity is improved. OTFTs fabricated from soluble blends
of polymer and small molecule are deposited using spin-coating,
which we will show causes vertical-phase separation of the two
components. The small molecule migrates to the exposed
interface, allowing large crystals to form within the channel
region of the device.
To evaluate the effect of the blend morphology devices were
fabricated in a dual gate structure as well as a more conventional
top gate design. The processing conditions are documented in the
Experimental section, but Figure 1c shows a schematic of the
standard OTFT, whereas Figure 2b shows the dual gate device.
Constructing transistors that have a bottom and top gate within
the same device will elucidate differences in device performance
between the bottom and top OSC interfaces, but will not
differentiate between dielectric effects, channel injection, and
morphology changes. The leakage current between the two gates
was always found to be less than the lowest measured off current
thus allowing channels to be probed independently. Devices were
operated in dual gate mode by biasing one gate at a constant
voltage whilst sweeping the other to obtain transfer character-
istics. This produced a shift in the threshold voltage dependent on
the fixed gate voltage, which is consistent with dual gate
operation.
Figure 2a shows the transfer characteristics for top and bottom
channels within a single device, fabricated using a 1:1 by weight
blend of TIPS-pentacene and the insulating polymer poly(a-
methyl styrene) spin-coated onto the bottom gate dielectric. The
choice of an inert polymer matrix for the dual gate device
maximized any difference in mobility between top and bottom
gate which might be due to vertical phase separation.
Adv. Mater. 2009, 21, 1166–1171
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Figure 1. Chemical structures of a) diF-TESADT and b) TIPS-pentacene.
c) A schematic diagram of the standard device structure (PFBT ¼ penta-
pentafluorobenzene thiol).
Figure 2. Dual gate device using a TIPS-pentacene:poly(a-methyl styrene)
blend: a) transfer curves for the separate channels and b) a schematic of
the device structure (PFBT ¼ pentafluorobenzene thiol).
Adv. Mater. 2009, 21, 1166–1171 ß 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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Uniform semiconductor film formation was observed, whilst the
saturation mobility of holes within the bottom channel was
(0.10
0.05) cm2 V1 s1 increasing to (0.5
0.1) cm2 V1 s1 in
the top channel. Moving from bottom to top gate also showed an
improvement in on/off current ratios, reduced hysteresis and
threshold voltage shifts from greater than þ10 V to between –5 V
and –10 V. Processing issues, described in the Experimental
section, forced the use of different dielectric materials for the
bottom and top channel, which could account for the difference in
performance seen. However, devices were analyzed by a DSIMS
technique (results below) which indicate a higher concentration
of TIPS-pentacene in the top-channel. The maximum mobility
achieved using TIPS-pentacene:poly(a-methyl styrene) in a
top-gate-only device was found to be 0.69 cm2 V1 s1, which is
only slightly higher than measured in the dual gate transistors
showing that the altered structure does not adversely affect the top
channel operation.
In order to make an improvement in the mobility a change of
polymer matrix was carried out. It is suggested that lateral phase
segregation of TIPS-pentacene and poly(a-methyl styrene) causes
a reduction in the effective channel width and thus a lowering of
the measured mobility for devices based on insulating polymers.
Replacing poly(a-methyl styrene) with the amorphous p-type
polymer poly(triarylamine) (PTAA) increases carrier mobility
between crystalline pentacene-rich regions and improves the
performance of the OTFT.
Figure 3 shows typical transfer and output characteristics of top
gate devices (channel length (L) of 60 mm and width (W) of
1000 mm) made from a) TIPS-pentacene and b) diF-TESADT,
both blended with PTAA. The highest mobility devices using
TIPS-pentacene had a slight deviation from ideal square law
behavior at gate voltages greater than –50 V, due to the drain being
biased to –40 V. Charge injection appeared to be efficient, since
there is a good linear output at low drain voltages and despite the
higher currents within diF-TESADT based transistors no
injection problems were observed. There is also a clear
improvement in hole mobility over the devices made using
TIPS-pentacene:poly(a-methyl styrene) blends. The highest
mobility obtained was in a diF-TESADT:PTAA device which
had a saturation mobility of (2.41
0.05) cm2 V1 s1 and a linear
mobility of (1.88
0.04) cm2 V1 s1.
In addition to high mobilities the important characterization
parameters for the devices remained constant and reproducible
over the whole sample. A typical, non optimized sample (having
lower quality evaporated source-drain electrodes but more
transistors per sample) was tested and averages taken over 18
devices. The mean saturation mobility was found to be
(0.66
0.13) cm2 V1 s1 and the best device was
0.91 cm2 V1 s1. Similarly the mean threshold voltage was
(–7.2
2.2) V and the on/off current ratio was 10(4.51
0.32).
Generally it was found that over 80% of the devices on a sample
would show transistor behavior. Table 1 displays the mobilities
and on/off current ratios obtained for the various material and
device designs employed.
Devices fabricated in air using TIPS-pentacene blends had
much lower mobilities (0.1 cm2 V1 s1) compared to those
made in nitrogen. These results are consistent with the
degradation of pentacene OTFT performance due to H2O and
O2 acting as a charge trapping dopants introduced during
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diF-TESADT blend transistors showed

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excellent stability and maintained a satura-

Figure 3. Transfer and output curves of typical a) TIPS-pentacene and b) diF-TESADT blend
2 1 1 2 1 1
transistors with saturation mobilities of 1 cm V s and >2 cm V s , respectively.
annealing of the semiconductor layer.[30] However, after fabrica-
tion in nitrogen, exposure to air resulted in only a slow reduction
in device performance since the permeability of CYTOP to H2O
and O2 is low. Figure 4 shows how the mobility as well as on and
off currents varied over a period of four weeks for a diF-TESADT
and a TIPS-pentacene transistor. The TIPS-pentacene blend
showed a slight drop in mobility after several hours while
tion mobility above 1.2 cm2 V1 s1 for the
entire test. There was a gradual decrease in
the on/off ratio due to increasing off
current as bulk conduction in the channel
became more significant.
The lower performance of the bottom
gate in the dual gate device can be
attributed to two effects. Firstly, there will
be a larger number of charge trapping sites
on the BCB-semiconductor interface due to
the oxygen plasma treatment creating polar
groups on the surface. Secondly, we believe
that there is vertical separation of compo-
nents within the semiconductor layer.
During film formation phase separation
of the polymer and the small molecular
material occurs, and there is preferential
crystallization of the TIPS-pentacene (or
diF-TESADT) at the top semiconductor
interface. This therefore increases the
fraction of molecular solid within the
conducting channel of the transistor in
the top gate configuration.
Vertical profiling of the device structure
by dynamic secondary ion mass spectro-
metry (DSIMS) was used to confirm the
distribution of the blend components. Cs
ion bombardment was used to slowly
sputter material from the film, and the
resulting ejected ion species measured by
mass spectrometer. Figure 5 shows the first
signal to rise is the Si from the silyl group
on the TIPS-pentacene molecule. The
nitrogen signal (from the PTAA) can be
seen to rise to a maximum approximately
20–30nm beneath the top surface. When
scanned over the channel (a) the Si signal is
seen to rise at a probed depth of ca. 50 nm
indicating the glass substrate. When
scanned over the electrodes (b) the fluorine peak indicates the
position of the self-assembled monolayer of pentafluorobenzene
thiol (PFBT). The broadening in the F peak (which is a
monomolecular layer <1 nm thick) is due to a combination of
a variable rate of etch for different materials in the layer and a
slight spread in the energy density of the Cs ion beam. The gold
signal rises immediately afterwards as the profiling reached the

Table 1. Summary of the mobilities and on/off current ratios obtained for the various material and device designs employed.

TIPS-pentacene: TIPS-pentacene: poly(a-methyl styrene) TIPS-pentacene: PTAA diF-TESADT: PTAA

poly(a-methyl styrene)

Architecture DUAL GATE TOP GATE TOP GATE TOP GATE

Channel Bottom Top Top Top Top

2 –1 –1
msat [cm V s ] 0.10
0.05 0.5
0.1 0.7 1.1 2.41
mlin [cm2 V–1 s–1] – – 0.6 0.7 1.88
ION/IOFF 104.1 104.8 105.3 105.2 104.2

1168 ß 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim Adv. Mater. 2009, 21, 1166–1171
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Figure 4. Air stability of TIPS-pentacene and diF-TESADT (open and filled
symbols, respectively) measured over a period of four weeks.
source and drain electrodes, and finally the Si signal rises once
more indicating profiling into the glass substrate. A depth profile
of an area between the source and drain electrodes showed the
same distribution of the TIPS and PTAA, indicating that the
phase separation occurs over the entire area of the spin-coated
sample.
The TIPS-pentacene:PTAA system was chosen to illustrate the
suspected vertical phase separation, as each component contains
an element that identifies it as being located at a certain depth.
Using this analysis, it is apparent why a top-gate device may
Figure 5. DSIMS depth profile of TIPS-pentacene:PTAA film on silicon substrate with a PFBT-treated gold source and drain electrodes. The graphs show
the phase separation, a) in the channel and b) over the electrodes of the TIPS-pentacene material (as indicated by the Si signal), closer to the air interface
when compared with the PTAA (seen in the N signal).
Adv. Mater. 2009, 21, 1166–1171 ß 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
COMMUNICATION
perform better than a bottom-gate. Although there is sufficient
TIPS-pentacene in the bottom channel to allow a reasonable
field-effect mobility, the higher concentration in the top channel
promotes better charge percolation. The vertical phase separation
in this system is assumed to apply to all small molecule polymer
blends in this study.
The films were also studied using polarized light microscopy to
observe the morphology of the crystallites and atomic force
microscopy (AFM) to map the surface of the semiconductor
which forms the conducting channel within the OTFT. Figure 6
shows both diF-TESADT and TIPS-pentacene based blend films.
It is clear that some crystallization of the molecular material into
spherulitic-type structures has occurred. Crystallization occurs
over the whole sample when annealed for longer than 2 min at
100 8C, less than this quenches the sample, leaving some
amorphous regions which are not suitable for high performance
devices. The AFM image shows a clear difference between the
amorphous part of the film, with a r.m.s. surface roughness of
6.4 nm, and the crystallites with a surface roughness of 18 nm.
This increase in surface roughness and the change in appearance
of the film suggest that some of the TIPS-pentacene is forming on
the top surface during crystallization – optimal for good top gate
OTFT performance. The optical microscopy images also show the
effect of contact induced crystallization on PFBT-coated gold
contacts.[11] Much larger and more spherulitic crystals are
produced on the gold surfaces in the case of diF-TESADT blends
where it is suggested that fluorine interactions promote the
crystallization. In the case of TIPS-pentacene blends, the effect is
less pronounced as F–F interactions do not exist, which also
agrees with the better charge injection observed in the
diF-TESADT devices.
Further annealing of the diF-TESADT based transistors at
100 8C after fabrication resulted in a lowering of the off current,
for example after 1 hour the on/off current ratio typically
increased from approximately 103.5 to 104.2. This is also
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Figure 6. Polarized microscopy and AFM images of a) TIPS-pentacene:PTAA, b) diF- electrodes were approximately 40 nm thick with a
TESADT:PTAA, and c) partially crystallized films with A being the amorphous and B being the 60 mm channel length. Their surface was modified by
crystalline region. Scale bar upper left image: 100 mm, scale bars other images: 50 mm.
consistent with an improvement in vertical phase separation on
heating which would reduce bulk conduction through the
semiconductor film and thus lower the current in the off state
of the device.
Simple unipolar inverter circuits were constructed using
TIPS-pentacene and diF-TESADT blend transistors showing their
possibility for use in real devices. We have demonstrated that an
inverter gain of greater than 10 and good noise margins can be
achieved. Again with a view to commercial viability we have
shown that devices can be fabricated on poly(ethylene terephtha-
late) (PET) films with very little loss of performance. Using a
TIPS-pentacene:PTAA blend for the semiconductor, saturation
mobilities of up to (1.13
0.05) cm2 V1 s1 were measured and
threshold voltages and on/off current ratios remained the same as
for the devices made on glass. The key feature here was the
maximization of the substrate surface energy by oxygen plasma in
order to enhance uniform film formation and vertical phase
separation of the blend components.
In conclusion, we have shown a high peak device performance
and reduced device variability by combining the film-forming
properties of polymers and high mobility small molecules.[11] The
use of an insulating polymer matrix demonstrated the improved
film forming properties of the blend system, while use of the
1170 ß 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
www.advmat.de
semiconducting polymer matrix maintained
this and increased the mobility.
The dual gate device structure illustrated
improved top channel performance over bot-
tom channel within the same device. Although
this could be explained by the different
dielectrics and their respective interface proper-
ties, DSIMS measurements confirmed that
there was a higher fraction of small molecule at
the top surface.
The comparison of diF-TESADT and TIPS-
pentacene in identical blend systems shows
that diF-TESADT is more crystalline, air-stable,
and better performing. Optical microscopy
images show larger crystallite formation on
the electrodes which extend further into the
channel, appearing to correlate with the higher
performance observed, reaching a maximum
mobility of 2.4 cm2 V1 s1.
Experimental
Top-gate transistors were fabricated on glass
substrates (EAGLE 2000 from Corning) with evapo-
rated gold (Au) source and drain electrodes. A 900 nm
layer of the fluorocarbon polymer CYTOP (Asahi
Glass) was used as the dielectric and gate electrodes
were evaporated aluminium (Al). The substrates were
cleaned by sonication in detergent solution (DECON
90) and rinsed with deionized water. Source and drain
immersion in a 5  103 mol L1 solution of penta-
fluorobenzene thiol (PFBT) in isopropanol for 5 min
and then rinsed with pure isopropanol. The semi-
conducting layer was spin-coated from a solution of
either TIPS-pentacene or diF-TESADT plus the polymer matrix (poly-
a-methyl-styrene or polytriarylamine) 1:1 by weight at 4 wt % concentration
of solids in tetralin. Spin-coating was carried out at 500 rpm for 10 s then
2 000 rpm for 20 s and was followed by drying at 100 8C for 15 min in
nitrogen to obtain layers with a thickness of 70 nm. CYTOP was then
spin-coated at 2 000 rpm for 60 s and dried at 100 8C for 20 min before the
gate electrode was evaporated.
Dual gate devices were fabricated using ITO coated glass substrates.
Divinyltetramethyldisiloxane bis-benzocyclobutane (BCB) solution was
spin-coated at 1 500 rpm for 60 s before being UV cured and then heat
cured at 300 8C to form the bottom gate dielectric. The devices were then
completed as for the standard structure with Au source and drain, CYTOP
top gate dielectric and Al top gate contact. It was not possible to use
identical layers for both top and bottom gate dielectrics in the double gate
device. Although CYTOP uses a fluorinated solvent and will not dissolve the
small molecule when spun on top of the organic transistor blend layer, it
also has a very low surface energy and, when using it as a bottom gate
dielectric, wetting on top of CYTOP is very difficult. Conversely, the solvent
used with BCB will also dissolve the active layer, thus destroying the device.
Before PFBT treatment the samples were oxygen plasma treated for 2 min
at 80 W radio-frequency power in order to increase the surface energy of the
BCB layer from around 35 mJ m2 to 73 mJ m2. This increase is primarily
due to the introduction of a polar component to the surface energy not
present on pristine BCB.
The devices using PET films as the substrate were produced in a similar
fashion to the standard devices. Plastic films were cleaned by sonication in
Adv. Mater. 2009, 21, 1166–1171
www.advmat.de
acetone and isopropanol, and oxygen plasma treatment was used to
increase the substrate surface energy before PFBT treatment.
AFM was carried out in close-contact mode using a Pacific
Nanotechnology Nano-R2 machine and a Nikon Eclipse E600 POL was
used to image the films between crossed polarizers.
In order to examine the phase separation of the TIPS-pentacene and
polymer matrix, DSIMS was performed on the spin-coated TIPS-
pentacene:PTAA blend film using an ion time-of-flight ‘‘ToFSIMS IV’
instrument (analysis performed by Intertek MSG, Wilton, UK). During
DSIMS, ion bombardment is used to slowly sputter material from the film
and the ejected ion species are measured by a mass spectrometer. The
primary ion species used were Cs ions and elements were selected so as to
uniquely identify each component: Si in TIPS-pentacene; N in PTAA; F in
the PFBT monolayer; Au in the source-drain electrodes and Si in the bottom
layer was assumed to be from the glass substrate. The results were
normalized to their respective maxima, as there is a large variation in
sensitivity for different elements using this technique. Therefore, DSIMS
cannot be used to indicate relative concentrations between elements, but it
can show the concentration variation for a particular element throughout
the depth of a film. A thin layer of gold was sputtered onto the surface of the
semiconductor film to prevent charging of the sample. The depth of the
trench made by the ion beam was measured by profilometer (Dektak 8) and
used to convert the time signal from the DSIMS into a measure of depth.
Electrical characterization of the OTFTs was carried out in either a
nitrogen atmosphere (<0.1 ppm oxygen) or in air using a semiconductor
parameter analyzer. Mobilities were calculated in both the linear, mlin, and
saturation, msat, regimes from the transfer characteristics, using a standard
thin film field-effect transistor model:
L 1 @2 ID
msat ¼ (1)
W Ci @VG2
L 1 @ID
mlin ¼ (2)
W Ci VD @VG
In these expressions, L is the device channel length, W is the channel
width, VD is the drain voltage, VG is the gate voltage, ID is the drain current,
and Ci is the geometric capacitance of the dielectric layer. The capacitance
of the dielectric layer for CYTOP was measured to be (2.10
0.09) nF cm2
and 1.12 nF cm2 for BCB. This measurement was carried out using a
parallel-plate capacitor on a Solartron 1260 impedance analyzer. From Ci a
value of 2.14 was estimated for the dielectric constant of CYTOP, which is
only slightly higher than the value of 2.1 quoted by Asahi Glass Co.
Acknowledgements
We are grateful to the Engineering and Physical Sciences Research Council
(EPSRC) and Research Councils UK (RCUK) for financial support. TDA is
an EPSRC Advanced Fellow and an RCUK Fellow/Lecturer. This article has
been amended for print publication.
Received: June 20, 2008
Revised: September 15, 2008
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