Abstract

With the advance of technology and rapid growth of digital systems, low power high
speed analog-to-digital converters with great accuracy are in demand. To achieve
high effective number of bits Analog-to-Digital Converter(ADC)calibration as a time
consuming process is a potential bottleneck for designs. This dissertation presents
a fully digital background calibration algorithm for a 7-bit redundant flash ADC
using split structure and look-up table based correction.

Redundant comparators are used in the flash ADC design of this work in order
to tolerate large offset voltages while minimizing signal input capacitance. The split
ADC structure helps by eliminating the unknown input signal from the calibration
path. The flash ADC has been designed in 180nm IBM CMOS technology and
fabricated through MOSIS. This work was supported by Analog Devices, Wilming-
ton,MA.

While much research on ADC design has concentrated on increasing resolution

and sample rate, there are many applications (e.g. biomedical devices and sensor
networks) that do not require high performance but do require low power energy
efficient ADCs. This dissertation also explores on design of a low quiescent cur-
rent 100kS/s Successive Approximation (SAR) ADC that has been used as an error
detection ADC for an automotive application in 350nm CD (CMOS-DMOS) tech-
nology. This work was supported by ON Semiconductor Corp, East Greenwich,
RI.
 Acknowledgments

It has been a great experience for me to study at Worcester Polytechnic Insti-

tute and a great honor to be a student of Professor John McNeill for almost five
years. Over this period of time, I have gained experience in both teaching and do-
ing research. His special method of guiding his students without providing them
with immediate solutions for their problems helped me in becoming an independent
researcher. I also was a teaching assistant for the major analog courses that Profes-
sor McNeill teaches at WPI and I think I have learned a lot from him during that
time. His support for attending the International Solid-State Circuits Conference
(ISSCC) which is a great conference about leading edge research in analog IC design
has motivated me to pursue a high professional standard during my PhD research.
I would also like to thank my committee members, Professor Brown and Dr.
Wang, for their expertise and review of this work.
My special thanks go to ON Semiconductor, East Greenwich RI, for supporting
my PhD dissertation. I have been working at ON Semiconductor as an internship-
Co-op employee and have taped-out the ultra-low power SAR ADC under direct
supervision of Robert Davis, design manager in switching mode power supply group.
I would like to thank him for his significant help in explaining the application of this
ADC and all his help through implementation, tape-out and test chip evaluation.
I also had the experience of working at ON Semiconductor as an Analog DFT
validation Engineering Intern and have become familiar with various test methods
under supervision of Andrew Laidler which gave me much insight into making a
robust design. Many thanks to him for all his support on evaluating my test chip.
I must say thank you to my other colleagues who were available to help me to
manage this work. Thanks to: Shelby Raymond, Andrew Tarlan, Paul Gunaratnam,
Alpha Diallo for the analog design advice, Wai Yung for digital design advice, Jon
Buzzi for helping with the layout of SAR ADC, Justin Yerger for his help with
using a microscope with laser to remove passivation layer and burn trim fuses,
Betty Podgorski for bonding out the test chip, Marie Crowley for help with Mentor
graphic software maintenance, Jayson Busila for his advice on PCB design, and
Robert Cushing for his help with using the needle probes and all the test set up.
The Flash ADC part of this work was carried out with the support of the Analog
Devices and New England Center for Analog and Mixed Signal Design at WPI un-
der the direction of Professor McNeill. I would like to thank Professor Zain Navabi
for digital design advice. I am also thankful to my colleagues at the NECAMSID
lab, Christopher David and Tsai Chen, former PhD students who were always avail-
able to help me with Cadence tool maintenance, Anthony Crasso for his help on
MATLAB simulation for flash ADC calibration, Jianping Gong for his help with
layout the Flash ADC. I would like to thank Robert Brown and Siamak Najafi for
IT support and Robert Boisse for his help in soldering the flash ADC evaluation
board.
My family has been a great support throughout my entire education. I would like

i
to thank my husband Dr. Ali Kiapour, my dad Dr. Mohammad Majidi, my mom
Mina Farazdaghi who is my best teacher and support and my sister Dr. Fatemeh
Majidi, for all their love, support, advice, patience during my hard time. Without
their support this dissertation would not have been written.

ii
Contents

1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Background 4
2.1 ADC Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 ADC Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Quantization Error . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Offset and Gain Error . . . . . . . . . . . . . . . . . . . . . . 7
2.2.3 Nonlinearity Error . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.4 Timing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Figures of Merit and Performance Trends . . . . . . . . . . . . . . . . 14
2.4 ADC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 Flash ADC Structure . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2 Redundant Flash ADC . . . . . . . . . . . . . . . . . . . . . . 16
2.4.3 SAR ADC Structure . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Calibration Techniques Overview . . . . . . . . . . . . . . . . . . . . 20
2.5.1 Flash ADC Calibration . . . . . . . . . . . . . . . . . . . . . . 20
2.5.2 SAR ADC Calibration . . . . . . . . . . . . . . . . . . . . . . 21
2.5.3 The Split ADC Structure . . . . . . . . . . . . . . . . . . . . . 21
2.6 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.1 Flash ADC Research . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.2 SAR ADC Research . . . . . . . . . . . . . . . . . . . . . . . 24
2.6.3 Split ADC Research . . . . . . . . . . . . . . . . . . . . . . . 25
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 FLASH ADC Calibration 29

3.1 Using Split-ADC for calibration . . . . . . . . . . . . . . . . . . . . . 29
3.2 Digital Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 LMS Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 Behavioral Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

iii
 3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 FLASH ADC Chip Implementation 37

4.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 Analog Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.1 Dynamic Comparator Design . . . . . . . . . . . . . . . . . . 38
4.2.2 Reference Ladder . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.3 Analog Shift Design . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 Digital Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.1 Decoder Design . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.2 Output Buffer Design . . . . . . . . . . . . . . . . . . . . . . . 49
4.3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5 FLASH ADC Testing and Analysis 52

5.1 ADC Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1.1 PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 Flash ADC Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.2.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6 SAR ADC Chip Implementation 66

6.1 SAR ADC Proposed Algorithm . . . . . . . . . . . . . . . . . . . . . 66
6.2 SAR ADC Implementation . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3 ADC Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.1 Dynamic Comparator . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.2 DAC Capacitor Network . . . . . . . . . . . . . . . . . . . . . 69
6.3.3 Switching Logic Network . . . . . . . . . . . . . . . . . . . . . 71
6.3.4 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.5 Refference Volatges . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7 SAR ADC Testing and Analysis 75

7.1 PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.2 Static Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.3 Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.4 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8 Conculsions 81
8.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

iv
A Glossary 82
A.1 Acronym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
A.2 Flash ADC decoder design,verilog code . . . . . . . . . . . . . . . . . 83
A.3 Sampling jitter at different SNR and input frequency . . . . . . . . . 89
A.4 Flash ADC, DNL/INL plot, MATLAB code . . . . . . . . . . . . . . 90
A.5 SAR ADC, DNL/INL plot, MATLAB code . . . . . . . . . . . . . . . 91
A.6 SAR ADC, fft plot, SNR calculation MATLAB code . . . . . . . . . . 92

v
List of Figures

2.1 Ideal ADC transfer function . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Quantization Error as a function of input voltage [1] . . . . . . . . . 7
2.3 ADC Offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 ADC Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 DNL error in a 3-bit ADC with a missing Code . . . . . . . . . . . . 10
2.6 DNL error in a 3-bit ADC with missing Decision Levels . . . . . . . 10
2.7 INL error in a 3-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 Sampling Jitter at different SNR and input frequency [2] . . . . . . . 13
2.9 State-of-the-Art FoM Lines [3] . . . . . . . . . . . . . . . . . . . . . 15
2.10 Different ADC architectures comparison [4] . . . . . . . . . . . . . . . 15
2.11 Block diagram of a flash ADC . . . . . . . . . . . . . . . . . . . . . . 17
2.12 SAR ADC architecture . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.13 A 4-bit charge-redistribution SAR ADC [5] . . . . . . . . . . . . . . 19
2.14 Split ADC Architecture [6] . . . . . . . . . . . . . . . . . . . . . . . 22
2.15 The basic principle of redundancy method [7]. Selected comparators
are highlighted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.16 Survey of Flash ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.17 Survey of SAR ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.18 Survey of ADCs using “Split ADC” approach. . . . . . . . . . . . . . 26

3.1 Block diagram of split redundant flash ADC . . . . . . . . . . . . . . 30

3.2 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 Calibration block diagram . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Calibrated and Uncalibrated DNL . . . . . . . . . . . . . . . . . . . . 35
3.5 Calibrated and Uncalibrated INL . . . . . . . . . . . . . . . . . . . . 35
3.6 Calibration Convergence . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1 Block diagram of split redundant flash ADC . . . . . . . . . . . . . . 38

4.2 Block diagram of dynamic comparator . . . . . . . . . . . . . . . . . 39
4.3 Dynamic comparator simulation results . . . . . . . . . . . . . . . . . 40
4.4 Indication of comparator offset in flash ADC design [8] . . . . . . . . 41
4.5 MonteCarlo simulation of yield of ADC vs. σof f set of comparator [8] . 42
4.6 Flash ADC with unstable thermometer code as digital output [9] . . . 43
4.7 Regenerative latch structure [2] . . . . . . . . . . . . . . . . . . . . . 43

vi
4.8 Analog Shift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.9 Source Follower Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.10 Source Follower with cascode bias Circuit . . . . . . . . . . . . . . . . 47
4.11 Analog shift schematic view . . . . . . . . . . . . . . . . . . . . . . . 48
4.12 Analog shift: AC simulation result . . . . . . . . . . . . . . . . . . . 49
4.13 Analog shift simulation result: DC response . . . . . . . . . . . . . . 50
4.14 Digital block diagram of flash ADC . . . . . . . . . . . . . . . . . . . 50
4.15 Wallace tree decoder for a 7-bit flash ADC . . . . . . . . . . . . . . . 51
4.16 Block diagram of output buffers . . . . . . . . . . . . . . . . . . . . . 51

5.1 Flash ADC die photo . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.2 Flash ADCs Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3 Linear regulators with low dropout voltage . . . . . . . . . . . . . . . 55
5.4 Generating reference voltages . . . . . . . . . . . . . . . . . . . . . . 56
5.5 Generating differential input for each flash ADC . . . . . . . . . . . . 57
5.6 Connecting the Analog (AGND) and Digital Ground (DGND) Pins
of ADC to System Analog Ground . . . . . . . . . . . . . . . . . . . 58
5.7 PCB layout for flash ADC evaluation . . . . . . . . . . . . . . . . . 58
5.8 PCB board for flash ADC evaluation . . . . . . . . . . . . . . . . . . 59
5.9 Simulation results for redundant flash ADC evaluation . . . . . . . . 59
5.10 Procedure of Chip Failure Determination . . . . . . . . . . . . . . . 61
5.11 ESD test for flash ADC evaluation . . . . . . . . . . . . . . . . . . . 62
5.12 Test chip under optical microscope . . . . . . . . . . . . . . . . . . . 63
5.13 Closer view of ESD and bond pads . . . . . . . . . . . . . . . . . . . 64
5.14 Layout mistake on PMOS substrate contact . . . . . . . . . . . . . . 65
5.15 DNL result for redundant flash ADC . . . . . . . . . . . . . . . . . . 65

6.1 Proposed SA-ADC architecture . . . . . . . . . . . . . . . . . . . . . 68

6.2 Waveforms of proposed switching procedure: (a) MSB=1 (b) MSB=0 69
6.3 Dynamic Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4 Monte-Carlo simulation of comparator offset. σ = 2.26mV . . . . . . 70
6.5 Control logic switches and timing . . . . . . . . . . . . . . . . . . . . 71
6.6 Top level schematic of SAR ADC design . . . . . . . . . . . . . . . . 73
6.7 Analog buffer with tuning . . . . . . . . . . . . . . . . . . . . . . . . 74

7.1 Analog portion of SAR ADC layout, including buffers, switches, DAC
and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.2 SAR ADC bonding diagram . . . . . . . . . . . . . . . . . . . . . . . 77
7.3 Measure DNL and INL for Die1 . . . . . . . . . . . . . . . . . . . . . 78
7.4 Measured DNL and INL with ramp input for Die1 . . . . . . . . . . . 79
7.5 Measured DNL and INL with ramp input for Die2 . . . . . . . . . . . 79
7.6 Measured 4096-point FFT spectrum at 100 kS/s. . . . . . . . . . . . 80

vii
List of Tables

2.1 Comparison of different ADC Architectures . . . . . . . . . . . . . . . 16

2.2 Comparison of different flash ADCs in previous works . . . . . . . . . 27
2.3 Comparison of different SAR-ADCs in previous works . . . . . . . . . 28

3.1 System Simulation Parameters . . . . . . . . . . . . . . . . . . . . . . 34

7.1 System Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 76

7.2 SAR ADC performance analysis . . . . . . . . . . . . . . . . . . . . . 80

viii
Chapter 1

Introduction

1.1 Motivation
Analog-to-Digital Converters (ADCs) are employed to digitize continues analog
signals into digital form with a certain number of bits of resolution. With the fast
shrinking of CMOS process and rapid advance of digital integrated circuit technolo-
gies, high-performance low-cost ADCs are needed in many mixed-signal applications
such as communications, software radio, audio, video and sensors [10]. Particularly,
wireless receivers as well as high-density disk drives [11] require efficient, high speed,
low-to-moderate resolution (5-8 bits) data conversion with a low jitter sample clock.
Flash ADCs are typically excellent candidates for these types of applications [11] as
the simple analog structure of flash ADCs enhances the feasibility to data converter
design with technology scaling.
Designing in a deep submicron process enables high speed but at the price
of increasing variation and device mismatch, which leads to decreasing the ADC
effective number of bits (ENOB) and affecting the ADC accuracy. Increasing the
device size will help with recovering the ENOB by improving matching, at the cost
of increasing area and power consumption. Flash ADCs are composed of multiple
comparators working in parallel, and device mismatch can cause offset error in each
comparator and affect differential and integral nonlinearity (DNL and INL)of the
ADC. There are several techniques for calibration found in Flash converters in order
to mitigate the offset errors of comparators such as averaging and digitally controlled
trimming [11] and combinations of analog and digital techniques have been used to
calibrate and correct the output of the ADCs.
Technology scaling has a great impact on area and power consumption of
integrated circuits. The power consumption of ADCs is a function of the technology
node, the linearity and bandwidth [12]. In general, ADC design methods, that
preserve the signal-to-noise ratio with scaling will increase the power consumption
and area [12].Flash architectures with moderate resolutions are not challenged by
noise requirements due to their low resolution [12]. However, power consumption of
the multiple comparators and calibration circuits increase ADC power consumption

1
and on-chip error correction circuits increase the design complexity. This has lead
to a motivation of the first part of this research on calibration of flash ADCs and
improving the performance and accuracy of this type of data converter.
In some applications such as wireless sensor networks and biomedical devices
[13] and electronic features in modern vehicles, power consumption is the primary
concern while speed is of a secondary importance. The second half of this research
focuses on a portion of the SAR ADC design that has moderate resolution and speed,
but is ultra low power. This SAR ADC has been used as an error detection ADC
in a feedback loop. This work explores the opportunity for further improvement in
power with a new algorthim using capacitive DAC and area savings by eliminating
the differential approach in favor of a single-ended architecture.

1.2 Goals
The goal of the first part of this work is to develop a digital background cali-
bration algorithm applying a ”Split-ADC” calibration structure and lookup-table-
based correction. Traditional methods used for offset improvements in comparators
are based on increasing the size of the device according to Pelgrom matching for-
mula [14]; while in this work small, power efficient comparators are used to design
7-bit flash ADC in order to minimize the ADC input capacitance. Redundancy is
used to tolerate the large offset voltage of digital regenerative comparators. Digital
background calibration is used to reduce analog complexity. The background ap-
proach estimates the error iteratively using least mean squares procedure and can be
useful for any changes in threshold voltage of the comparators due to temperature
variations or device mismatch.
The goal of the second part of this work is to present the design of a 7-bit
SAR ADC that is used as a regulation ADC in a switching mode voltage regulator
that uses a digital algorithm. The ADC is used as an error detection in a feedback
loop. This design only has 4μA current budget for this ADC. The ADC has been
designed and fabricated at ON Semiconductor Corp.

1.3 Dissertation Organization

The remainder of this dissertation is organized as follows: Chapter 2 will describe
flash ADC, SAR ADC and split ADC structures and address ADC characterization
and nonidealities while summarizes some previous flash ADC calibration, SAR ADC
low power design methods and split ADC techniques. In chapter 3 digital calibration
of flash ADC will be discussed. Chapter 4 will present design aspects of the flash
ADC designed for the test chip. Evaluation board for the test chip and measurement
results are given in chapter 5. The proposed algorithm for the ultra low power
SAR ADC and details on implementation of SAR ADC are presented in chapter 6.
Testing and measurement results of the SAR ADC are shown in chapter 7. Chapter

2
8 summarizes and concludes this dissertation and proposes the directions for future
research.

3
Chapter 2

Background

2.1 ADC Characterization

An analog-to-digital converter (ADC) is used to convert a continuous-time signal
to a digital number that represents its discrete amplitude. Any method of digitizing
the analog signal introduces some error. The quantization error and ADC nonideal-
ities are discussed in section 2.2. ADC performs the conversion by sampling the real
world analog signal periodically. The number of conversions that ADC is needed
to convert analog input to the digital code within a specific time is called sampling
rate. For example, 100kS/sec ADC collects hundred thousand samples in a second
of time.
Resolution of an ADC is the number of output levels of quantizing an analog
signal and it is given in powers of 2 as the output of a ADC comes in binary format.
A 7-bit ADC represents the analog input using 27 or 128 quantization levels. ADC
needs a reference voltage to digitize the analog signal and divides the reference
voltage into small quantization levels. The smallest quantization level that ADC
can resolve called the least significant bit (LSB) and it is defined as [5]:

Vref
LSB = (2.1)
2N

For an ADCs with a differential voltage reference LSB is defined as [15]:

Vref (+) − Vref (−)

LSB = (2.2)
2N

where Vref (+) and Vref (−) are the non-inverting voltage reference and the inverting
voltage reference respectively. Full scale of an ADC is defined as:

VF S = Vref − 1LSB (2.3)

4
 Figure 2.1: Ideal ADC transfer function

Meaning that ADC input can get very close to Vref but it never reaches its reference

voltage [15]. The LSB in terms of F S using (2.1) and (2.3) is:

VF S
LSB = (2.4)
2N−1

An ideal ADC transfer function is illustrated in Fig 2.1. The Y-axis shows
the ADC digital output and X-axis is the analog input. The quantized value of the
analog input is represented by the diagonal staircase [16]. The distance between two
successive transition points is defined as 1LSB as shown in Fig 2.1.
The ADC is also characterized by its bandwidth and signal-to-noise ratio
(SNR). The former is the frequency range that ADC can measure and defines the
sampling rate of the ADC; the latter is the ratio of the measured signal to its
introduced noise. Accuracy and linearity limit how well the quantizatized output
can match the real world signal. The dynamic range of an ADC is specified by its

5
effective number of bits (ENOB). ENOB is equal to the ADC resolution in an ideal
condition. The ideal dynamic range can be defined as the ratio of the full scale
input to the smallest quantization level. Assuming most of the input signals are
sinusoidal, dynamic range for an ideal N-bit converter can be calculated as [5]:

Dynamic Range(dB) ≈ 6.02N + 1.76 (2.5)

More details on deriving (2.5) are presented in Section 2.2. Further details on
using this equation are outlined in [1].

2.2 ADC Nonidealities

The ideal ADC has a linear transfer function as shown in Fig 2.1. However, real
ADC performance is degraded by several error sources. Quantization, offset, gain,
timing and non-linearity are common type of those errors.

2.2.1 Quantization Error

If changes in the input signal applied to the ADC are very small (¡1LSB) and cannot
be detected by the converter, quantization error is occurred. Fig 2.2 illustrates the
quantization error of ideal N-bit ADC. This sawtooth waveform as error signal e(t) is
the difference between the analog input signal and the quantized output signal [16].
The maximum error an ideal ADC makes during the conversion is ± 12 LSB.
The root-mean-square quantization error is [1]:


q
rms quantization error = e2 (t) = √ (2.6)
12

From (2.6)and (2.7)the SNR for N-bit ADC can be calculated (assuming a full-
scale input sine wave) as:

q × 2N
f ull − scale sinewave = v(t) = sin(2πf t) (2.7)
2

   q2N 
√
rms f ull − scale input power 2 2
SN R = 20log10 = 20log10 (2.8)
rms quantization noise power √q
12

6
 Figure 2.2: Quantization Error as a function of input voltage [1]

SN R = 6.02N + 1.76dB (2.9)

It is important to know that in (2.9) rms quantization error is estimated over the
full Nyquist bandwidth, dc to f2s where fs is the sampling frequency. If the signal of
interest has a smaller bandwidth (BW)or any noise shaping method is used to filter
out the noise components, then a correction factor(called process gain) [1] needs to
be added to rms quantization error equation. Therefore this correction factor results
in increased SNR and we have [1]:

 
fs
SN R = 6.02N + 1.76dB + 10log10 (2.10)
2 × BW

ENOB can be calculated from (2.9) as:

SN R − 1.76 dB
EN OB = (2.11)
6.02

2.2.2 Offset and Gain Error

The fixed difference between input and output signals due to device mismatch or
other nonidealities of the components of the ADC shifts the transfer function and

7
 Figure 2.3: ADC Offset error

causes offset error. If the slope of the real ADC transfer function varies from the
slope of the ideal ADC transfer function, gain error has occured, as typically happens
when an on-chip reference is used. In an ideal ADC when the full-scale input is
applied the result of the conversion is all ones. In an ADC with gain error, all ones
is the result of applying a voltage greater than full-scale (negative gain error) or a
voltage less than full-scale (positive gain error). The ADC transfer function with
offset and gain errors is shown in Fig.2.3 and 2.4.
Offset and gain errors can be calibrated by shifting the x and y axes of the transfer
function to align the zero points of the real and ideal ADC transfer function and
that will remove the offset error and then by rotating the transfer function about
the new zero point the gain error can be adjusted.

2.2.3 Nonlinearity Error

Integral nonlinearity (INL) and differential nonlinearity (DNL) are two of the
accuracy parameters for testing ADC performance. DNL error reveals how far an
actual quantization step width is from the ideal value of 1LSB, as in an ideal ADC
each quantization step of a converter are spaced exactly 1LSB apart. The distance
between an actual step width and the ideal value is measured in a form of a change
in input-voltage magnitude and represents in LSB units after removing static gain

8
 Figure 2.4: ADC Gain error

errors,therefore for an ideal ADC DN L is equal to 0LSB. For example, if the

input signals increases only 78 LSB and the output changes levels, the DNL error is
− 18 LSB for this transition. Any DNL error of less than or equal to 1LSB guarantees
a monotonic transfer function with no missing codes. If DNL reaches −1LSB,
quantization step is skipped and a missing code (is also known as missing-transition
levels [17] (MTLs)is occured [1]. Positive DNL values gives rise to wide codes, or
missing-decision levels (MDLs). In an ideal case, for every 1LSB interval, only one
decision level (transition voltage) exists. Therefore a positive DNL resembles as one
or more decision level in the code’s input range [17]. Large values of DNL can limit
the ADC performance in terms of signal-to-noise ratio (SNR). The DNL for an N-bit
ADC is calculated as:

Vi+1 − Vi
DN L[i] = − 1, where 0 < i < 2N − 2 (2.12)
VLSB−Ideal

i corresponds to the quantization code level and VLSB−Ideal is the ideal distance
for two adjacent digital codes [1].
Integral nonlinearity (INL) error is defined as the summation of DNL errors and
appears as deviation in LSB or percent of full-scale range (FSR) of the real transfer

9
 Figure 2.5: DNL error in a 3-bit ADC with a missing Code

Figure 2.6: DNL error in a 3-bit ADC with missing Decision Levels

function from a straight line in two forms: “best straight-line INL” and “end-point
INL”. The former determines the closest linearity approximation to the ADC’s
actual transfer function and the latter is defined by the position of the all zeros
and all ones (full-scale) outputs. Fig 2.5, 2.6 and 2.7 show the DNL and INL error
examples for of 3-bit ADC respectively.
Best straight-line INL provides information about offset (intercept) and gain
(slope) error, plus the position of the transfer function. It determines, in the form

10
 Figure 2.7: INL error in a 3-bit ADC

of a straight line, the closest approximation to the ADC’s actual transfer function.
End-point INL passes the straight line through end points of the converter’s trans-
fer function, thereby defining a precise position for the line. Thus, the straight line
for an N-bit ADC is defined by its zero (all zeros) and its full-scale (all ones) out-
puts. The best straight-line approach produces lower peak error results and is often
preferred [1]. INL for an N-bit ADC is calculated as:


k
Vi − Vzero
IN L[k] = DN L[i] = − i, where 0 < i < 2N − 1 (2.13)
i=0
VLSB−Ideal

Vi is the analog value corresponding to the digital output code i, N is the ADC
resolution, Vzero is the minimum analog input representing the all-zero output code,
and VLSB−Ideal is the ideal distance between two adjacent output codes.

2.2.4 Timing Error

Timing errors also limit ADC performance. Sampling clock jitter, clock skew,
and input skew are known as typical timing erros whether from random sources or
deterministic sources like clock distribution layout [5].

11
 Sampling clock jitter also known as “aperture jitter” giving rise to sampling-time
uncertainty and this error is more significant at the maximum slope of the input
signal; meaning that a small Δt change in sampling time while the ΔV Δt
is large causes
a large ΔV error. Assuming a sinusoidal input waveform (a full-scale signal Vin )
with input frequency fin is applied to an N-bit ADC, the maximum slope is at the
zero crossing [2, 5]:

Vref
Vin = sin(2πfin t) (2.14)
2

ΔV
|max = πfin Vref (2.15)
Δt

If Δt represents the sampling time uncertainty, then in order to keep ΔV error

less than 1LSB the Δt has a upper bound limitation [2, 5], therefore:

1 LSB 1
Δt < = N (2.16)
πfin Vref 2 πfin

For example, a 7-bit ADC sampling a 200MHz full-scale sinusoidal signal must
keeps its aperture jitter under 12 ps to maintain 7-bit accuracy. In order to calculate
the signal-to-noise (SNR) ratio affected by jitter-induced noise, we need to calculate
the power of ΔV error at any point in time. For a sinusoidal input signal v(t) =
Asin(2πfin t) the ΔV error is:

ΔV (t) = A(2πfin )Δt cos(2πfin t) (2.17)

The power of the ΔV error is calculated as:

A2
ΔV (t)2  = [A(2πfin ) cos(2πfin t)]2 Δt2  = (2πfin )2 Δt2  (2.18)
2
The SNR from jitter-induced noise is expressed as:
A2
2 1
SN R = = (2.19)
A2
2
(2πfin )2 Δt2  (2πfin )2 Δt2 

12
 Figure 2.8: Sampling Jitter at different SNR and input frequency [2]

−SN RdB
10 20
SN RdB = −20log10 (2πfin Δt)orΔt = (2.20)
2πfin

This means that for a 200MHz sinusoidal input applied to an ADC, in order to
achieve 40dB SNR the aperture jitter must be less than 8 pS. Therefore a low jitter
clock is essential to proper ADC performance. Jitter versus the input frequency for
a specific SNR is shown in Fig 2.8. As is shown in the figure, at high frequencies in
order to achieve large SNR very low jitter clock in the order of ps is needed.
Clock signal path needs careful layout in order to avoid clock skew. Different
wiring passes near clock signal wires can affect the capacitance of the clock distri-
bution wires and causes unwanted delays. Random mismatch of transistor devices
in buffers on clock signal path can also create clock skew. Input skew happens
when input signal arrives with delay to the blocks. For example, in a case of flash
ADC design, the input signal to the comparators sees some delay between com-
parators. Therefore some errors will br associated with the sampled voltage. A
front-end sample and hold circuits (at the cost of power consumption and limited
input bandwidth) can solve this problem.

13
2.3 Figures of Merit and Performance Trends
When ADCs with different specifications are compared, figure-of-merit (FOM) can
combine the various parameters that are important for design [10]. Several FOM
has been defined so far [3]:

• Walden FOM

P
F OMW = (2.21)
fs × 2EN OB
• Schreier FOM (DR)

BW
F OMS−DR = DR + 10log( ) (2.22)
P

• Schreier FOM (SNDR)

fs
2
F OMS = SN DR + 10log( ) (2.23)
P

In Fig 2.9, the dashed line shows the schreier FOM which is the borderline for
high resolution ADCs [3], in 2014. For low resolution ADCs, it is still appropriate
to use the walden FOM (doted line in Fig 2.9 ) [3].

2.4 ADC Architectures

ADCs cover a wide range of resolutions and speed with different architectures.
There are two main types of analog-to-digital converters: Nyquist rate and oversam-
pling converters. In Nyquist rate converters like flash and Successive Approximation
ADCs, output values have a one-to-one correspondence with input values [5]. How-
ever, they are designed to operate at 1.5 to 10 times the input signal Nyquist rate in
order to have a reliable anti-aliasing and reconstruction filter [5]. Oversampling data
converters such as Delta-Sigma ADC typically operates 20 to 512 times the input
signal Nyquist rate. Fig 2.10 shows several ADC architures for different sampling
rates and resolutions [4].
Scaling of CMOS IC technology into nanometer area has noticeable improve-
ment in cost, performance, and system integration. Although scaling is very benefi-
cial for digital systems, analog functions are degraded with shrinking the transistor
sizes, and analog design is challenging in nanometer technologies. However, the

14
 Figure 2.9: State-of-the-Art FoM Lines [3]

Figure 2.10: Different ADC architectures comparison [4]

cost advantages of integrating systems with technology scaling has made analog and
mixed signal design attractive to the designers yet. In comparison to other types of
analog-to-digital converters, the simple analog structure of flash ADCs makes them
attractive in the speed-power-complexity trade off in deep submicron CMOS. This
work presents a redundant flash ADC using a “Split-ADC” calibration structure

15
and lookup-table-based correction and an ultra low power SAR-ADC design.

2.4.1 Flash ADC Structure

In nanometer scale CMOS high speed low power analog-to-digital converters with
high effective number of bits (ENOBs) are in demand. Wireless receivers and high
density disk drives are examples of applications that flash ADCs are typically used
in [18]. A flash ADC has a simple structure that includes an array of comparators,
a resistor ladder in order to generate the reference voltages, and a thermometer-to-
binary converter block. Fig 2.11 shows block digram of a simple flash ADC.
The high conversion rate of flash ADC comes at the cost of high number
of comparators. A basic flash ADC employs an individual comparator for every
quantization level in order to compare an input voltage with a series of reference
voltages. For an N-bit flash ADC, typically 2N − 1 comparators are needed. The
analog input signal is applied to the negative input of each comparator while the
reference voltage coming from a voltage divider resistor ladder is applied to the
positive comparator input. The results is a thermometer code output, since all
comparators connected to as resistor string will generate a 1 output if the reference
voltage is larger than input signal or generate a 0 output if input signal is greater
than the related reference voltage. A “2N − 1 to N” digital decoder can convert the
thermometer code into a binary weighted output code [5].
Although designing in in a deep submicron process gives us the advantage
of higher speed, increasing variation and device mismatch will decrease the ADC
effective number of bits (ENOB). Especially in flash ADCs, device mismatch results
in offset error in each comparator, affecting differential and integral nonlinearity
(DNL and INL) of the ADC and degrading ENOB performance.

2.4.2 Redundant Flash ADC

Redundancy has been shown to be a practical method of yield enhancement in
integrated circuit designs [7, 18–20]. In order to reduce the matching problem of
transistors, one can increase the device size [14]; however this approach results in
increased area and power consumption costs. In flash ADC design, comparator

Architecture Speed Accuracy

Flash High Low
SAR Low-Medium Medium-High
Folding-interpolating Medium-High Medium
Delta-Sigma Low High
Pipeline Medium-High Medium-High

Table 2.1: Comparison of different ADC Architectures

16
 Figure 2.11: Block diagram of a flash ADC

redundancy tolerates the large comparator offsets due to small device sizes essential
to reduce input capacitance and provides the high speed flash ADC with acceptable
fan-in.
In a traditional N-bit flash ADC, comparators with monotonically increasing,
trip-voltages have the responsibility of quantizing the analog input signal applied
to the ADC. In a redundant flash ADC, instead of 2N − 1 comparators, a bank
of R × (2N − 1) comparators are used to quantize the input signal; meaning that
each code are associated with R comparators [7]. More details on the application of
redundant flash ADC are addressed in 2.6.1.

17
 Figure 2.12: SAR ADC architecture

2.4.3 SAR ADC Structure

Successive approximation ADCs are widely used as medium-to-high resolution
and medium speed data converters. For high resolution SAR ADCs, fully differential
techniques provide the best common mode noise rejection and lowest distortion
[21]. For medium resolution ADCs in power-critical applications such as battery
management, the lower power consumption of simpler single-ended architectures
are attractive.
Unlike the flash ADC in previous section, Successive Approximation Regis-
ter(SAR) ADC does not use so many comparators for decision making, instead it
only has a single comparator that uses a binary search algorithm and a full resolution
DAC. Fig 2.12 shows the block diagram of a conventional SAR ADC, consisting of
control logic, comparator, and capacitive DAC (CDAC). The sampled analog input
voltage is compared with DAC voltage in an iterative process until an analog voltage
that is approximately equal to the input voltage is found. A binary weighted capac-
itor network is used for the DAC architecture in most SAR ADCs since capacitors
are better than resistors for device matching [22]. The conversion cycle begins when
the Most Significant Bit (MSB) is set to digital value 1 and the rest of the bits are
V
set to zero. The equivalent analog value of this digital code ref 2
at the output of
DAC is compared to original input voltage by the comparator. If the comparison
shows the analog output from the DAC is greater than the original sampled input,
the MSB will reset to digital value 0 as the comparator output is zero. Otherwise,
the MSB is left to 1. The binary search will continue for the rest of the bits and the
last digital code of control logic will be the the digital representation of the origi-
nal analog input [23]. Fig 2.13 shows the first three steps of conversion in a single
ended SAR ADC. During the sampling mode the top plates of all capacitors are
connected to ground and the bottom plates are connected to the input voltage Vin .
In the second step which is the “hold mode” the top palates are disconnected from
the ground while the bottom plates are connected to ground and due to the charge

18
 Figure 2.13: A 4-bit charge-redistribution SAR ADC [5]

conservation, the top plates voltage will be −Vin . In bit cycling step, the bottom
plate of the largest capacitor is connected to the reference voltage Vref . This makes

19
 Vref
the negative input to the comparator (Vx ) increase by 2
as:

Vref
Vx = −Vin + (2.24)
2
V
if the (Vx ) < 0 which corresponds to Vin > ref2
, the comparator output will set the
MSB to logic 1; otherwise the MSB will be reset to 0 which means the capacitor
corresponding to the MSB will be grounded again. To determine the next bit, the
V
next largest capacitor is connected to Vref and the related (Vx ) will increase by ref
4
.
This procedure is repeated until all of the bits are determined [23].

2.5 Calibration Techniques Overview

2.5.1 Flash ADC Calibration
Most calibration methods of flash ADCs are designed to correct the comparator
offsets which can be due to device mismatch inherent in the design [5]. Variations
in resistors value due to random mismatch along the reference ladder, temperature
variation or the variation in polysilicon thickness in polysilicon resistors can cause
error in reference voltages [2]. However,this error is not significant in flash ADC
design with less than 10 bit resolution [2]. Any input offset voltage of comparators
can lead to a shift in flash ADC’s linear transfer function and cause an nonlinear-
ity. Several foreground and background calibration methods have been proposed
in literature to deal with comparator’s offset in flash ADC design. Some of these
methods are:
• Auto-Zeroing: This method helps to reduce the offset of preamplifiers and
comparators by sampling the unwanted offset voltage and then subtracting
the amount of offset voltage from the input or output of the preamplifier [24].
• Averaging, Interpolation, and Folding: Averaging method connects the out-
puts of the preamplifier array of comparators with resistors and thus effectively
averages the offset of the central preamplifier with its neighbors and will im-
prove the DNL/INL [25].
Interpolation produces voltages that are in between two other voltages and
thus a new reference voltage will be created (interpolation factor of 2). This
method can reduce the number of preamplifiers required which is also beneficial
in terms of input capacitance of flash ADC, power and area [5].
Folding method also reduces the number of comparators needed in flash ADC
design by generating multiple zero crossing for each comparators [5, 26].
• Redundancy: Redundancy is the technique that deliberately uses an excess of
“cheap and imprecise comparators [27], selects the best ones, and deactivates
the others. More detail is explained in 2.6.1.

20
 • Digitally controlled and DAC based calibration: Digital calibration of the com-
parators is usually applied in the DAC. Input-referred offset of the comparators
is controlled with extra circuitry, which increases the power consumption and
area of ADC [28].
• Stochastic ADC: Random distribution of comparator offsets is used to create
reference voltages, and the ADC output is the sum of the comparator outputs
[29]. The cumulative distribution function (CDF) of the comparator offset
will generate the flash ADC transfer function [29]. More detail is explained in
2.6.1.

2.5.2 SAR ADC Calibration

Calibration methods of the SAR converters are mostly aimed to correct the errors
of DAC due to capacitive mismatch inside the capacitor network which is one of the
primary sources of power dissipation in this type of ADC. Some of these methods
are:

• Capacitor Splitting: In this method the MSB capacitor splits into two capaci-
tors of value C0 , and then switches down one of them when it is needed. Thus,
the capacitor splitting approach uses the same energy for an up and a down
transition [30].
• Redundancy: Redundancy in the search algorithm that is used in typical SAR
ADCs can relax the settling constraints to a tolerable error corresponding to
the step size. Inaccurate decisions in early conversion steps are tolerated and
corrected afterward [31].
• DAC trimming: Some matching techniques (such as dummy capacitor place-
ment) are used to improve matching [32]. Some level of reference trimming
also can be used to trim the voltage reference that is applied to capacitor
network.

Among these methods of calibrations that have been explained in this chapter,
split ADC calibration is known as a promising method of calibration for improving
the ADC nonlinearities which is explained in more detail in 2.5.3.

2.5.3 The Split ADC Structure

Fig.2.14 shows the split ADC concept [6,33]. The ADC is split into two channels.
The same input is applied to both channels and individual output codes xA and xB
are produced by each ADC. The ADC output code x is the average of the output
of the two channels.
The background calibration signal is derived from the difference Δx between two
output codes xA and xB . If both ADCs are precisely calibrated, the two outputs

21
agree and the difference Δx is zero; otherwise if Δx is a nonzero value, calibration
parameters in each ADC are adjusted until Δx and the ADC errors approaches to
zero.

2.6 Previous Works

2.6.1 Flash ADC Research
Comparator offset has been a significant problem for flash ADC design and so
far several methods has been proposed in literature to deal with it. Auto-zeroing,
averaging, redundancy, DAC-based calibration, digitally controlled trimming and
stochastic ADCs are the known techniques to mitigate the effects of comparator
offsets. Among all methods, digital calibration was a promising method which
results in less FOM (Figure-of-Merit). Table 2.2 outlines various calibration methods
and design of flash ADCs published in the IEEE International Solid-State Circuits
Conference (ISSCC), IEEE Journal of Solid-State Circuits (JSSC), IEEE Custom
Integrated Circuits Conference (CICC), IEEE Symposium on VLSI Circuits (VLSI)
and IEEE Asian Solid-State Circuits Conference (A-SSCC). In this table, calibration
techniques, the sampling rate, the power, the effective number-of-bits (ENOB), and
the resolution of different flash ADC structure in different process technology are

Figure 2.14: Split ADC Architecture [6]

22
 (a) Nominal Comparator Trip Voltages (b) Actual Comparator Trip Voltages

Figure 2.15: The basic principle of redundancy method [7]. Selected comparators
are highlighted.

compared.
Among the papers listed in Table 2.2 [19, 34, 35], use a redundancy calibration
method. Redundancy is a technique that deliberately uses excess of “cheap and
imprecise comparators [27], selects the best ones, and deactivates the others. In
case of flash ADC, the identical redundant comparators are spread over the reference
voltages and since the offset of comparators span over 1LSB, there will be a chance
of overlapping probability distribution functions (PDFs) of the comparator offsets
which is good for comparator reassignment. Instead of 2N − 1 comparators, a bank
of R × (2N − 1) comparators are used to quantize the input signal; meaning that
each code are associated with R comparators [7] and a calibration engine [7] will
select the best comparator for each code. The basic principle of redundancy method
for flash ADC is depicted in Fig 2.15a and 2.15b. In this case, redundancy factor,
R is equal to 3. Nominal trip voltages of the group of R comparators for each code
is shown in Fig 2.15a. These are the ideal trip points. In reality, the actual trip
points are comparators are different from the ones in this figure and they are shown
in Fig 2.15b. The trip voltage of the most suitable comparators for each code is
highlighted in this figure. For example, comparator 5b is reassigned to designate the
code 6. The comparators which are not assigned to any code are disabled to save on
power consumption. A problem with this method is the large area cost of disabled
comparators. Another difficulty with selection requirement in redundancy method
is the “edge effects” [7] which can reduce yield. One can add extra comparators to
recover the selection of suitable comparators at lowest and highest codes.
Large capacitive loading is a big challenge in designing a fast sample and hold
for a high speed flash [36]. In [36] a two stage track and hold (T/H) is used,
while the second stage works as a buffer between the first stage and the capacitive
loading of comparators. With clock duty cycle control SNDR improves. However,
the extra T/H stage implies extra power consumption and extra area. In [29, 40]
a large number of comparators are used in parallel, while removing the reference
ladder from the ADC structure and providing the trip points with random offsets.
A statistical selection technique is used as a redundancy method to deal variation in
comparator offset. This scheme limits the ADC resolution and also consumes a large

23
 Figure 2.16: Survey of Flash ADCs.

area and any changes in trip points due to temperature drift require recalibration
for proper ADC operation [18].
In [25, 39, 42, 46] resistive averaging is used to lower the impact of offset. Speed
and linearity is improved with interpolation in [41,43]. In [26] interpolation is used in
a folding flash structure and foreground offset calibration is expanded to use digitally
controlled DACs for folding-interpolating stages. In [44], analog input is sampled
and rectified by a 1-bit folding stage and a 4-bit flash sub-converter converts the
folding signal. The nonlinearity of the folding stage is calibrated using additional
input pairs in comparators. The combination of a simple folding technique with
DAC-based comparator calibration seems to be very practical in reducing the flash
ADCs power. In [47]a dynamic technique is used that adds binary-scaled variable
capacitors at the drain node of input pair of dynamic comparators. DAC-based
calibration has been used in [48–50]. Fig 2.16 plots the reported efficiency FOM
as a function of speed in (GS/s). It is evident that recent designs have a wide
performance range (20 MS/s to tens of GS/s) and achieve good power-efficiency in
high speed conversion.

2.6.2 SAR ADC Research

In recent years, there has been a significant progress in designing energy efficient
SAR ADCs. Recent ADC surveys [51] show the conversion speed and power con-
sumption of SAR ADCs have dramatically improved. Process scaling is beneficial
for this type of ADC that uses MOS switches, digital logic and capacitance network.
Table 2.3 outlines various SAR ADC designs in recent years.
This survey show there has been significant improvement in capacitive DAC

24
 Figure 2.17: Survey of SAR ADCs.

switching energy. Monotonic switching [63], capacitance splitting [30] and arbitrary
weight capacitor array [67] has been the promising methods of energy saving in
SAR ADC design. Eliminating the MSB capacitance switching [63], using a separate
coarse-ADC to calculate the MSBs, dual supply ADC that uses lower supply voltage
for power hungry digital portion of ADC and taking the advantage of unary-wighted
DAC [59] are some of the energy efficient design schemes that has been proposed in
recent years. Fig 2.17 shows a plot of Walden efficiency FOM vs. conversion speed
for SAR ADCs in 28nm, 40nm, 65nm, 90nm, 130nm, 180nm process nodes from
2007 to 2014. As it comes from the graph, recent designs that has conversion speed
< 100M S/s benefits from process scaling and reports better efficiency FOM.

2.6.3 Split ADC Research

The “Split ADC” was originally developed by my advisor Professor John A.
McNeill with collaborators Coln and Larrivee from Analog Devices [73, 78, 79]; a
similar technique was developed independently by Moon and Li at Oregon State
[80]. An indication impact of this technique is the broad range of published work
using the Split ADC approach developed by other investigators. While the original
work [73, 78, 79] was for an algorithmic (cyclic) ADC architecture, work has also
been published applying the split ADC concept to architectures such as flash [18],
folding [77], interleaved [74, 81], and SAR [60, 75, 76, 82] ADCs. For work with
numerical results, Fig 2.18 shows the speed and resolution reported. Over a broad

25
 RESOLUTION (bits) SUCCESSIVE APPROX
6 [73] [74]
16 INTERLEAVED
14 FOLDING
[75] CYCLIC
12 FLASH
[60]

10

8 [76]

6 [18]
[77]
SPEED (MSps)-
1 10 100 1000
Figure 2.18: Survey of ADCs using “Split ADC” approach.

range of the speed-resolution-architecture ADC trade off space, there are examples

in the literature in which the “split ADC” approach enables fast digital background
self-calibration. This will enable drastically improved power efficiency by moving all
calibration and correction into the digital domain, allowing flash ADCs (first part
of this dissertation) to fully realize the promise of nanometer scaled CMOS while
avoiding the performance trade offs and disadvantages of the calibration techniques
described in 2.6.1.

2.7 Summary
ADC characterization and different ADC architectures were explained in this chap-
ter. An overview of ADC calibration for flash and SAR ADC were presented and
split ADC structure was explained. A brief literature review of flash, SAR and split
ADC were presented.

26
Reference Technology (nm) Sampling- Calibration Resolution ENOB Power FOM
Rates (bits) (mW) (pJ/-
conv)
[19] 180 2KS/s Redundancy 6 5.05 0.00166 0.125
to 17.5
MS/s
[34] 180 4GS/s Redundancy 4 3.48 608 27
and DAC-
controlled
trimming
[35] 90 2.5 GS/s Comparator 4 4 30.2 0.79
reassignment
[36] 65 7.5 GS/s clock duty- 4.5 3.8 52 0.497
cycle control
[37] 180 18MS/s Stochastic 6 4.9 0.631 N/A
ADC
[38] 90 3.5GS/s voltage 5 3.6 227 42
trimable
offset-
canceling
buffer
[39] 90 3.5GS/s Averaging 6 5.19 98 0.95
and Interpo-
lation
[40] 90 210MS/s Stochastic N/A 5.9 34.8 N/A
ADC
[25] 350 1.3GS/s resistive av- 6 5.3 500 N/A
eraging
[41] 45 1.2GS/s Interpolation 6 5.7 28.5 0.45
[42] 65 5GS/s resistive av- 6 5.1 320 N/A
eraging
[43] 180 24GS/s Interpolation 5 4.4 3300 11
[26] 180 1GS/s Folding 10 9.1 1260 N/A
[44] 90 1.75GS/s Folding and 5 4.7 2.2 0.05
DAC calibra-
tion
[45] 32 5GS/s Dynamic- 6 5.1 8.5 0.594
offset cali-
bration
[28] 40 3GS/s digital offset 6 5.1 11 0.040
trim
[46] 180 1.6GS/s resistive av- 6 5.7 328 N/A
eraging
[47] 180 1GS/s Threshold 4 3.6 10.6 0.8
Calibration
[48] 90 1.75GS/s DAC-based 5 4.7 2.2 0.05
Calibration
[49] 65 800MS/s DAC-based 6 5.63 12 0.40
Calibration
[50] 130 3.5GS/s DAC-based 6 5.11 170 3.79
Calibration

27 flash ADCs in previous works

Table 2.2: Comparison of different
Reference Technology Sampling Resolution ENOB Power (mW) FOM
Rates (bits) (fJ/-
conv)
[52] 180nm 200KS/s 8 7.31 0.00615 97
[53] 90nm 10MS/s 8 7.7 0.0263 12
[54] 65nm 4.9MS/s 10 8 0.0019 4.4
[55] 180nm 100KS/s 10 9.4 0.0038 56
[56] 130nm 50MS/s 10 8.48 0.92 52
[57] 90nm 50MS/s 6 5.02 0.24 150
[58] 130nm 11MS/s 12 10.46 3.57 400
[59] 130nm 100KS/s 10 9.2 0.001 17
[60] 130nm 22.5MS/s 12 11.8 2.8 50.8
[61] 65nm 50MS/s 10 9.3 0.82 30
[62] 65nm 100MS/s 10 9.51 1.13 15.5
[63] 130nm 50MS/s 10 9.18 0.826 29
[64] 65nm 400MS/s 8 7.39 4 42
[65] 40nm 1.1MS/s 8 7.5 0.0012 6.3
[66] 40nm 80MS/s 10 9.15 5.45 85
[67] 90nm 100KS/s 10 9.46 0.00017 3.2
[68] 28nm 750MS/s 8 7.2 4.5 41
[69] 40nm 24MS/s 8 7 0.0546 17
[70] 65nm 20KS/s 10 8.84 0.00026 22.4
[71] 180nm 450KS/s 10 9.82 0.013 35
[72] 28nm 100MS/s 15 11.5 4.2 43.2

Table 2.3: Comparison of different SAR-ADCs in previous works

28
Chapter 3

FLASH ADC Calibration

Fig 3.1 shows a block diagram of the flash ADC designed for this work. Each of
the “A” and “B” ADCs is composed of 127 comparators, for a redundancy factor
[7, 83] of R = 2 compared with the 26 − 1 comparators required for a 6b ADC
with no redundancy. To tolerate nonmonotonic comparator outputs caused by large
threshold variation, the raw digital output n is simply the number of comparators
with a logic “high” output. Each of the nA , nB is realized with a Wallace tree
decoder. To correct the DNL and INL errors due to threshold variation, the raw
code n is used as the index to a LUT which provides the corrected output code x.
In the ideal case, each entry xi in the lookup table corresponds to the best fit code
for the range of analog input voltages corresponding to each raw code ni . Note that
the digital precision of the xi can be greater than the number of bits in ni to avoid
quantization effects in correction and calibration.

3.1 Using Split-ADC for calibration

Fig 3.2 shows the split ADC concept [73, 78, 79] applied to the design of this
flash ADC. The ADC from Fig 3.1 is used for each of the “A” and “B” ADCs
in Fig 3.2, for an overall redundancy factor of R = 4. The overall ADC output
code xOU T is the average of the individual output codes xA and xB . To enable
background calibration as described in 3.2, a small pseudo random voltage shift
±ΔV is introduced in the analog buffer at each ADC input. The ±ΔV shift is
derived from the ADC reference voltage, and for an ideal converter would cause a
known shift in output code of ±ΔC. Since the ±ΔV is equal in magnitude but
opposite in sign for the two channels, the shift cancels in the averaging process and
the output code xOU T is unaffected.
As shown in Fig 3.2, the difference Δx between the xA and xB outputs provides
information for the background calibration process. If both ADC lookup tables
were calibrated correctly, the Δx would be equal to ±2ΔC LSB corresponding to
the (known) shift ΔV which was introduced in each analog input. Any difference

29
 Figure 3.1: Block diagram of split redundant flash ADC

in Δx from the expected ±2ΔC LSB value provides information needed to update
the xA and xB values in the LUTs corresponding to each of the nA and nB raw
codes. As the input exercises the ADC inputs over their signal range, information is
accumulated to calibrate the LUTs for all entries used. The advantage of using the
split ADC is in the differencing operation, which removes the unknown input from
the background calibration signal path [73, 78, 79]. The following section describes
the correction and calibration process in more detail. The system level calibration

30
 Figure 3.2: System block diagram

method that used in this work has been simulated in MATLAB by Anthony Crasso,
M.S. student in the NECAMSID lab. Further details can be found in [84].

3.2 Digital Error Correction

To model the errors that need to be corrected and calibrated in this system, consider
an example in which an input voltage is applied with a −ΔV shift in the A path
and a +ΔV shift in B. Raw codes niA and njB from the A and B ADCs are mapped
through the respective LUTs to produce corrected codes xiA and xjB :

LUT“A”
niA −−−−−→ xiA = x − Δ C + iA
LUT“B”
njB −−−−−→ xjB = x + Δ C + jB (3.1)

In (3.1), we model each of the xiA and xjB outputs as being composed of the
ideal output x corresponding to the original unshifted analog input, the ±ΔC code
shift, and errors εiA and εjB in the ith and jth locations of the A and B LUTs
respectively. For the ADC output xOU T , averaging the individual outputs in (3.1)
gives
xiA + xjB 1
xOU T = = x + (εiA + εjB ) (3.2)
2 2
so, as indicated earlier, the shift cancels and we are left with the ideal correct
output x and an error component due to the errors in the LUTs. The calibration
process to be described in the following section is an iterative procedure that drives
the LUT errors εiA and εjB to zero, thereby ensuring accuracy of the digital output
code xOU T .

31
3.3 Calibration
There are several possible methods for obtaining the LUT used for correction. One
possibility is to use a foreground approach of applying a known signal, using a ramp
or DAC, and determining a best fit LUT for the outputs observed. As quality
of the calibration signal is increased, the accuracy of the LUT can be made as
precise as necessary. Disadvantages of this approach include the need to generate
the calibration signal, as well as taking the ADC offline whenever calibration is
required.
A novel aspect of this work is the background approach in which the errors are
estimated iteratively. The background calibration accommodates any variations in
comparator thresholds that may occur over time or temperature. The algorithm
estimates the LUT errors based on the information provided by the difference of the
outputs. Taking the difference of the outputs in (3.1) gives

Δx = xjB + xiA = εjB − εiA + 2ΔC (3.3)

From (3.3) we see that the (unknown) input signal is canceled from the cali-
bration path, leaving only the known shift and the errors εiA and εjB we need to
determine. To the extent that Δx differs from the target value of ±2ΔC, we know
there is a nonzero error in either or both of εiA and εjB . The purpose of the pseudo
random analog shift is to provide additional information over multiple conversions
that allows unambiguous determination of errors in the LUT. Without the shift, in
the case of a DC input, there would be no way to assign the error from the ob-
served Δx to εiA or εjB . We can keep track of all errors in the A and B LUTs with
127-element vectors εiA and εjB B; with this notation we can write (3) as
ê
⎡
⎤
ε0A
⎢ . ⎥
⎢ .. ⎥
ASSIGN M EN T Ŵ


⎢ ⎥
⎢ εiA ⎥
“A”LU T “B”LU T

. 
⎢ ⎥
Δx = [0 ... 0 − 1 ... 0..0 ... 0 + 1 ... 0]⎢ − ⎥ + 2ΔC (3.4)
⎢ ⎥
⎢ε0B ⎥
⎢ . ⎥
⎣ .. ⎦
εjB
The assignment vector has a -1 entry corresponding to the ith location in the A
LUT, and a +1 entry for the jth location in the B LUT. Over many conversions,
we can accumulate a matrix of information relating the Δx values to codes in the

32
LUTs:
ê
⎡
⎤
Ŵ ε
dˆ
⎡
⎤ 0A
⎢
..0 ... + 1 ... 0 ⎢ .. ⎥

⎤ . . ŝ
⎡
⎤
⎡ 0 ... − 1 ... 0 ⎥
.. ⎢ ⎥⎢ ⎥ ..
. ⎢ .. ⎥⎢ εiA ⎥ .
⎢ ⎥ ⎢ 0 − 1 0 ... 0.0 ... 0 + 1 0 ⎥⎢ ⎥ ⎢ ⎥
⎣Δx⎦ = ⎢ . . ⎥⎢ − ⎥ + ⎣2ΔC ⎦ (3.5)
.. ⎢ .. .. ⎥⎢ ⎥ ..
. ⎣ ⎦⎢ε0B ⎥ .
.. ⎢ . ⎥
0 ... − 1 ... 0.0 ... + 1 ... 0 ⎣ .. ⎦
εjB
Rather than solve the matrix equation in (3.5) exactly, the iterative technique in [73]
is used.

3.4 LMS Procedure

The mathematical development proceeds as in [73]. Formally, beginning with d =
W e + s in (3.5), we subtract s from each side and premultiply by the transpose of
W to obtain
Ŵ T (dˆ − ŝ) = Ŵ T Ŵ ê (3.6)
Since W is a very sparse matrix filled with only ±1 for nonzero values, the
product of Ŵ T Ŵ results in a diagonally dominant square matrix. If the matrix
were purely diagonal, then its inverse would be easy to compute exactly as the
inverse of the diagonal elements. Since, as in [73], we only need an approximate
solution for the iterative least mean squares (LMS) procedure, we multiply by a
factor μ to obtain estimates of the LUT errors:

ê = μŴ T (dˆ − ŝ) (3.7)

The LMS factor μ is chosen to be a power of 2 so the itration in [73] can be easily
computed as a shift in the digital hardware. The choice of μ also affects the dynamics
of the iteration convergence; for stable convergence μ should be chosen smaller than
the inverse of the largest diagonal element of Ŵ T Ŵ . The Ŵ T (dˆ − ŝ) data can be
accumulated on a conversion-by-conversion basis and requires the same number of
memory locations as the vector.
A block diagram of the calibration algorithm is shown in Fig 3.3. The calibration
portion on the left side is performed after the system collects a set of data over a
large number (of order 1000s) of conversion cycles.

3.5 Behavioral Results

The full split ADC system was simulated behaviorally using MATLAB by An-
thony Crasso [84] for 45nm technology. The simulation has been repeated for 180nm

33
 PARAMETER VALUE
LMS Parameter μ 2−21
Analog shift value ΔV 3.5 LSBs
Intial Error Estimate ε 0
Threshold variation standard deviation σ 5 LSBs
Total Number of Comparators 254
Effective Number of Bits (ENOB) 6.1
INL(after calibration) 1.52 LSB pk-pk
DNL(after calibration) +.85/ − .90 LSB

Table 3.1: System Simulation Parameters

Figure 3.3: Calibration block diagram

technology for this work, with the system parameters shown in Table 3.1.
All results are reported at the 6b level. The comparator threshold variation
value σ was estimated from circuit-level simulation and process specifications. Fig
3.4 show ADC differential nonlinearity (DNL) and integral nonlinearity (INL) of the
system before and after calibration. DNL improves from +1.53/−1.00 to +.85/−.90
LSB; INL improves from 2.56 to 1.52 LSB pk-pk.
The adaptation transient of the ADC for different μ values is shown in Fig 3.6.
So that the detailed performance of the calibration algorithm can be seen, corrected
code outputs are reported in 12b precision rather than truncated to 6 bits.

34
 Figure 3.4: Calibrated and Uncalibrated DNL

Figure 3.5: Calibrated and Uncalibrated INL

For the μ = 2−21 case, convergence to ENOB > 6 is seen within 2E+9 conver-
sions. At 200MS/s, this corresponds to less than 2 seconds to converge to what
would be quantization-limited accuracy. As is typical of LMS systems, faster con-
vergence is seen for smaller μ, subject to stability and accuracy trade offs.

3.6 Summary
This chapter has presented all digital background calibration of a redundant flash
ADC suitable for for aggressively scaled CMOS technologies. Implementation us-
ing the split-ADC calibration technique minimizes analog complexity and enables
purely background calibration. All redundant comparators are used and correction
is realized using a lookup table which is continuously updated in the background.
Simulation results show the proposed algorithm has the ability to reach performance

35
 Figure 3.6: Calibration Convergence

comparable to previous work without requiring additional silicon area, a precise sig-
nal source, or offline calibration.

36
Chapter 4

FLASH ADC Chip

Implementation

The 7-bit Split Redundant Flash ADC was implemented in 180nm IBM cmrf7sf
bulk CMOS technology. In this chapter, the design of this 7-bit flash ADC is pre-
sented, which is targeted for applications such as wireless receivers and high density
disk drives. This redundant flash ADC uses a Split-ADC calibration structure and
lookup-table-based correction. ADC input capacitance is minimized through use of
small, power efficient comparators which (in simulation) only consumed 17.4 μW
power with 1.8V supply voltage at 200MHz clock; redundancy is used to tolerate
the resulting large offset voltages. Correction of errors and estimation of calibration
parameters are performed in the background in the digital domain as it reduces
the test/trim time. This 5.8 ENOB flash ADC was designed for a sampling rate of
200MS/s.

4.1 System Overview

The block diagram of the proposed flash ADC is shown in Fig.4.1 again to illus-
trate the general building blocks that are used in to design the flash ADC in this
work. As it is mentioned before each of the “A” and “B” ADCs is composed of 127
comparators, for a redundancy factor [7,83] of R = 2 compared with the 26 − 1 com-
parators required for a 6b ADC with no redundancy. With the split ADC structure
the overall redundancy factor is R = 4. To assist background calibration as de-
scribed in 3.2, a small pseudo random voltage shift ±ΔV is presented at each ADC
input. The ±ΔV shift uses a source follower structure biased by current sources,
and for an ideal converter would cause a known shift in output code of ±ΔC. Each
of the digital outputs nA , nB is developed with a Wallace tree decoder. This chapter
explains the circuit level design of these building blocks.

37
 Figure 4.1: Block diagram of split redundant flash ADC

4.2 Analog Blocks

Analog blocks of the proposed flash ADC are 254 dynamic comparators and an
analog shift which are designed to be low power. Reference voltages for comparators
are provided through a resistive ladder.

4.2.1 Dynamic Comparator Design

Comparators are the core of all ADCs [85]. Therefore the properties of compara-
tors like speed, offset and power consumption directly affect the ADC’s performance,
accuracy and total power consumption. In this work, to minimize power consump-
tion, a dynamic comparator is chosen, with schematic as shown in Fig 4.2. Offset
is not a critical parameter in our design, since the digital background calibration

38
 Figure 4.2: Block diagram of dynamic comparator

that is explained in 3 will improve the ADC accuracy; thus there is no need for
a preamplification stage in front of the regenerative latch comparator and all the
transistors are minimum sized to reduce input capacitance and minimize power con-
sumption. The flow of current only happens during regeneration and reset which
helps with minimizing the power consumption. However, the absence of preamplifier
increases the sensitivity to dynamic latch noise behavior. In order to limit the error
probability of ADC a minimum step size up to 6 times the RMS noise is suggested
in literature [86]. In this dynamic comparator, a PMOS input differential pair is
used, to cover the the analog input common mode range that is close to ground.
The comparator uses the Lewis-Gray architecture [87]: when ‘Latch’ is high the
comparator is reset; when ‘Latch’ is low regeneration around the MN1-MN4 loop is
enabled. The conductivity imbalance from the MP1-MP4 input pair [63] forces the
comparator output to go low or high. Cadence virtuoso simulation waveform of this
dynamic comparator is shown in Fig 4.3.

Comparator Offset
The input offset voltage of the comparators accumulates into the ADC input
voltage and thus directly influences the flash ADC linearity. If the comparator offset,
Vof f set , is the only source of ADC nonlinearity, it will be measured as INL while

39
 Figure 4.3: Dynamic comparator simulation results

DNL can be defined as the difference between the adjacent offset errors. Fig 4.4
illustrates the indication of comparator offset in flash ADC design [8]. The dynamic
comparator that is used in this work consists of a differential pair at the input. The
mismatch between the differential pair transistors biased in saturation is assumed
to be normally distributed and defined as [8, 14]:
AV T
σ(ΔVT ) = √ (4.1)
WL
Δβ Aβ
=√ (4.2)
β WL
where VT is the threshold voltage, β is the current factor, W and L are the
width and length of the transistor respectively. Distance on chip between devices
in a differential pair has been ignored in Eq 4.1and Eq 4.2 [8]. The input offset for
differential pair can be calculated as [8]:

A2V T .A2β .ΔVgs2
σ(Vgs ) = (4.3)
4.W L
where ΔVgs is the overdrive voltage of the differential pair transistors. We can
extend the use of Eq 4.3 to estimate the input offset of the comparator. Based on
Eq 4.3 the input offset of the comparator is inversely proportional to transistor area.
Therefore in order to increase the resolution only one bit, the transistor area W L
has to increase 4 times if sizing is the only parameter to control the offset in the
design. It has been shown in literature in order to have high yield in flash ADC
design, the standard deviation of comparator offset should satisfy the Eq 4.4 [8]:

σof f set ≤ λ × LSB (4.4)

40
 Figure 4.4: Indication of comparator offset in flash ADC design [8]

where λ is a constant depending on the resolution and the desired yield percentage
and LSB is the least significant bit of the ADC [8]. Fig 4.5 shows the MonteCarlo
simulation of yield of ADC as a function of σof f set of comparator. As given by
this figure, in order to have a flash ADC with 99% yield σof f set should be less
than 0.2LSB [8] that requires a large area. As it is mentioned earlier, with digital
background calibration in this work and using redundant comparators any amount
of comparator offset is tolerable.

Dynamic Comparator Metastablity

Metastability is a problem that arises in latching comparators when the input
voltage is very close to the comparator threshold voltage, making the comparator
transition to a valid output state take more time than is available in the sampling
interval [88]. In an ideal condition the comparator outputs generate a thermometer
code. If the reference voltage is above the comparator input the digital output would
be 0, otherwise the digital output would be 1. Metastability can produce glitches
in digital output word and influences the ADC performance due to timing error
and possibly makes “bubble” error in thermometer code. [2, 9]. Fig 4.6 illustrates
effect of comparator metastability in flash ADCs. Metastability error is a function
of comparator regenerative time constant and clock frequency, which means this
type of error can increase in orders of magnitude with increasing of clock frequency
and scaling down the supply voltages [9]. It has been shown in literature that
metastability error rates of below 10−10 errors/cycle is required in flash ADC design
for telecommunication applications [9]. For a differential latch comparator, the

41
 Figure 4.5: MonteCarlo simulation of yield of ADC vs. σof f set of comparator [8]

regenerative time constatnt τ is:

C
τ= (4.5)
gm
where C is the total capacitance at a regenerative node, and gm is the transcon-
ductance of a regenerative device in the latch biased when it is switching [9]. The
two cross-coupled transconductors with load capacitances in a regenerative latch is
shown in Fig 4.7. The probability of having metastability error for an n-bit flash
ADC can be calculated as [2, 9]:

2(2n − 1)Vo tL
PM = eτ (4.6)
Vin .Ao
where Vo is the output voltage swing needed in thermometer code circuitry for
having a valid logic level, Vin is the analog input rang, τ is the regenerative time
constant, Ao is the gain of latch during the transparent state and tL is the resolution
time of the latch comparator [9]. Comparator resolution time is approximated to f1s ,
where fs is the sampling frequency. From Eq 4.6we can conclude that metastability
error increases exponentially with increasing sampling frequency. For input voltages
Vin greater than 0.5LSB, comparator should provide the ADC with a certain digital

42
 Figure 4.6: Flash ADC with unstable thermometer code as digital output [9]

Figure 4.7: Regenerative latch structure [2]

output. Thus for Vin = 2Vn+1

FS
the metastability error PM should be less than a desired
PM,max . From Eq 4.6we have [2]:
 Vo .2n+1  1
fs × n < (4.7)
PM,max .VF S .Ao 2τ
In order to reduce the possibility of metastability error, in designing a good
comparator, regenerative time constant should be minimized by maximizing the gm
and minimizing the total capacitance at the regenerative point. Using the minimum
size device will help with minimizing the total capacitance at the cost of increasing

43
the device mismatch.

Comparator Kickback Noise

Latch-based comparators have the disadvantage of creating kickback noise at the
input [5, 89]. The clock signal which is shown as latch signal in Fig. 4.2 can be
capacitively coupled into the input pair of class AB latched comparator and thus
the common-mode kickback noise is very high. This is due to large voltage transition
at regenerative node. During the reset phase the drain nodes of the MP1,MP4 are
reset to ground and during the regeneration phase, if the Vo ut is switched from low
to high, this large variation of regenerative node voltage induces the common-mode
kickback noise. In order to reduce the kickback noise in dynamic comparator in
this work, the neutralization technique in [90] is used. Transistors MP5 and MP6
in Fig. 4.2 isolates the input pair devices from the regenerative nodes and reduce
the kickback noise.

4.2.2 Reference Ladder

Reference voltages for the differential dynamic comparator are provided through
a resistive ladder since resistive ladders are an easy way of creating threshold levels.
In this design resistive ladder is made of 50Ω resistors (total resistor of 6.35kΩ for
each ADC). Due to the problem of ladder feed through, the value of the resistors
are chosen to be small although small resistance means higher power consumption
of ladder. For better current handling, better linearity and higher unit square sheet
resistance [91] silicided OP P+ poly resistors (opppcresx) are used for the ladder
implementation. One advantage of having silicide on polysilicon is minimization of
parasitic resistances [91].
Input feedthrough in the reference ladder is due to capacitive coupling from the
input signal that is applied to the input of differential pair into the reference ladder’s
threshold levels.The worst case feedthrough is from the input pair to the midpoint of
the ladder [92]. The total resistance of the ladder in order to avoid the degradation
of the performance of flash ADC due to the feedthrough can be calculated as [92]:

Vref × (2N − 1) π
= fin Rtotal Ctotal (4.8)
Vin 4

where Ctotal is the total capacitance from the input signal to the resistive ladder
and fi n is the input frequency [92]. Since the Ctotal is almost a fixed amount of the
capacitance in dynamic comparator’s design, using the small size of resistor can help
with reducing the feedthrough. One can also add decoupling capacitor to reduce the
feedthrough. It is important to know that the gate-source capacitance changes with
input signal amplitude which causes unwanted harmonic distortion [92]. However,
the differential architecture of the design can minimize this non-ideality.

44
 Figure 4.8: Analog Shift Circuit

4.2.3 Analog Shift Design

To assist background calibration as described in 3.2, a small pseudo random
voltage shift ±ΔV is presented at each ADC input. The ±ΔV shift uses a source
follower structure biased by current sources, and for an ideal converter would cause
a known shift in output code of ±ΔC. The analog shift is implemented as shown in
Fig 4.8. The ΔIS current which is added to one of the branches of the source follower
provides the appropriate voltage shift. The shift need not be instantaneous as long
as it is symmetric; samples from the transition region when ΔV has not reached its
full value are discarded from the calibration data. The size of the ΔV shift is subject
to an optimization trade off: too large a shift consumes excessive signal range, while
too small a shift does not provide sufficient information for calibration [18].
Since the input pair of differential latched comparator are PMOS devices, the
PMOS type source follower is used for analog shift circuit. Source follower senses
the input signal Vin at the gate and provides the load (comparator input pair) with

45
 Figure 4.9: Source Follower Circuit

the output at the source. As input voltage increases, the Vout follows the Vin with
a level shift which is equal to the gate-source voltage Vgs of the gain stage [93]. For
simplicity in explaining the input-output characteristic of a source follower, a single
ended structure with small signal model is shown in Fig. 4.9.
By using the small signal model in Fig. 4.9 the gain of this source follower can
be calculated as:

ro1  ro2  RL
Av = (4.9)
ro1  ro2  RL + g1m
As shown in Eq 4.9, the gain of source follower is not exactly 1 as it desired. The
source follower has a moderate output impedance ro and suffers from nonlinearity
and voltage headroom limitation [93]. The nonlinearity in source follower comes from
nonlinear dependence of threshold voltage to source potential voltage [93] which is
known as body effect. The advantage of using PMOS source follower is eliminating
the body effect (of MP1) as the bulk is tied to source since NMOS devices share
the same substrate. The lower mobility of PMOS devices leads to a higher output
impedance. In order to improve the output impedance of source follower for better
efficiency cascode transistors are used for the bias circuitry. Fig. 4.10 and 4.11
shows the source follower that is used as an analog shift in this design. Simulation
result shows the source follower does not limit the bandwidth of the input signal for
this flash ADC. Fig 4.12 shows the simulation result for analog shift design. The
3dB frequency is 713.9MHz which is adequate for a 200MS/s flash ADC. Fig 4.13
shows the DC simulation results for 6LSB shift.

46
 Figure 4.10: Source Follower with cascode bias Circuit

4.3 Digital Blocks

Fig 4.14shows the block diagram of digital circuitry. Each flash ADC (A and B) has
127 comparators. The thermometer code generated by comparators are latched in
127 D-flip flops and then through a one’s counter the number of high outputs (1.8V)
are counted and finally a 7-bit D- flip flop stores the digital outputs of each ADC.

47
 Figure 4.11: Analog shift schematic view

A tapered buffer is used to connect the digital output of each ADC to the pads on
the chip.

4.3.1 Decoder Design

The digital circuitry of flash ADC can have a significant influence on the ADC
performance. Comparator outputs generate a thermometer code. If the reference
voltage is above the comparator input the digital output would be 0, otherwise the
digital output would be 1. A thermometer to binary decoder reduces the number
of thermometer outputs to n-bit binary output. The errors in thermometer code
due to comparator offset, metastability or clock skew are known as “bubble” errors.
Bubble erros appears as 0s in the lower string of 1s or 1s in a upper string of 0s. In
this work, a ones-counter is used to decode the thermometer code. One’s counter
has the advantage of providing bubble error correction/supression [94]. Another
advantage of using ones-counter is that, based on the speed of the ADC, a suitable
ones-counter topology can be used while the power consumption is reduced [94].
Wallace tree topology has been a promising design for high speed applications [94].
The Fig 4.15 shows the block diagram of the Wallace tree decoder that is used in
this work. In order to have a symmetric layout, 63 output codes are decoded to 6
bits and the output of the 127th comparator is added to this 7-bit output word using
a full adder. To improve the speed of the design in decoding the 63 thermometer
output, carry look ahead topology was used. The design of Wallace decoder was
implemented with verilog HDL code. The functionality of the design was tested
with MODELSIM SE and then the code was synthesized with synopsis using the
IBM cmrf7f digital library. The whole layout was done in Encounter which is a

48
 Figure 4.12: Analog shift: AC simulation result

toolbox from Cadence. The Wallace tree decoder and full adder are fast enough
to prepare the digital output in 13ns. In other words ADC output is ready after a
digital pipeline delay of 2.5 clock frequency. The verilog code related to this design
is available in Appendix.

4.3.2 Output Buffer Design

Tapered buffers are used to connect ADC digital outputs to the pads without
any limitation for capacitive load up to 10.2pF . Simulation results show the output
buffers do not limit digital output speed. Fig 4.16 shows the block digram of tapered
buffer that is used in this work.

4.3.3 Summary
This chapter presented the details on designing a 7-bit flash ADC in circuit level.
Analog and digital blocks of this flash ADC were discussed. Dynamic comparator
design, metastability and kickback noise in comparators was explained. The PMOS

49
Figure 4.13: Analog shift simulation result: DC response

Figure 4.14: Digital block diagram of flash ADC

50
 Figure 4.15: Wallace tree decoder for a 7-bit flash ADC

Figure 4.16: Block diagram of output buffers

type source follower as an analog shift structure was discussed. The Wallace tree
decoder that is suitable for this flash ADC was explained.

51
Chapter 5

FLASH ADC Testing and Analysis

5.1 ADC Test Procedure

The split redundant flash ADC was fabricated in IBM cmrf7sf 180nm bulk CMOS
technology through MOSIS. The bare dies are wire bonded through MOSIS into a
lead-attach 68 pins ceramic QFN package. The die photo of the flash ADC test chip
is shown in Fig 5.1.
Test chip was tested on a printed circuit board (PCB) which was designed for
this ADC. The detailed PCB design is explained in section 5.1.1. The top level
layout of this ADC is shown in Fig 5.2. Each ADC occupies active area of 315 μm
×304 μm which excludes the digital buffers.

5.1.1 PCB Design

A 4-layer printed circuit board as an interface between the dies and test equip-
ment has been designed. Two inner layers are split VDD planes and ground planes.
Linear regulators with low dropout voltage from Linear Technology [95] are used
to create clean power supply and reference voltages. Each ADC has separate ana-
log supplies (AVDDA,AGNDA,AVDDB,AGNDB) and voltage references. Digital
output buffers also have their own supply rails (BufVDD,BufGND). Global VDD
and GND are used for digital design on chip. Fig 5.3shows the block diagram of
the voltage regulator. A 3-pin jumper is placed on the board that allows selection
between the regulated voltage and direct voltage from power supply. A decoupling
capacitor is also placed on the middle pin of the jumper which goes into the related
pin on chip.
The reference voltages for the resistive ladder of each flash ADC are directly gen-
erated by a LDO LT3080 and a potentiometer (POT) is used to generated different
ranges of voltages to the different ranges of input. A buffer from Analog Devices
(AD8652) is used after the resistive divider following a low pass filter to suppress
the noise of the reference voltages. Fig 5.4 shows the block diagram of the related
circuit.

52
 Figure 5.1: Flash ADC die photo

In order to provide a differential input for flash ADC a low distortion single-
ended-to-differential converter with adjustable output common-mode voltage from
Analog Devices (AD8138) is used. Fig 5.5 shows the bloack diagram of the related
circuit. The AD8138 as an ADC driver has a -3dB bandwidth of 320 MHz and low
harmonic distortion [96] which is suitable for this 200MS/s flash ADC. Single ended
input is available through an SMA.
Bias current are provided with each ADC through resistive dividers with a po-
tentiometer (POT). Latch signal for the dynamic comparators and clock signal for
digital block are generated by a high performance triple inverter [97] from ON Semi-

53
 Figure 5.2: Flash ADCs Layout

conductor (NL37WZ04) which is operating from a 1.65 V to 5.5 V supply and has a
propagation delay of 2ns. The differential input for pseudo random analog voltage
shift are also provided with a low Distortion Differential ADC Driver (AD8138).
In order to avoid signal reflection, PCB traces should be terminated properly.
Especially when driving an ADC, the clock distribution circuitry should be placed
as close as possible to the ADC clock input. This can help with preventing the
degradation in required slew rate and other losses such as undershoot and overshoot
[98]. PCB trace dimension (length, width, and depth) affects the characteristic
impedence (Z0) of the trace; therefore the output impedance of high speed signals
must be matched to the characteristic impedance of the traces [98]. 50Ω resistors
are placed on board for impedance matching of high speed signals such as ADC
digital outputs and the clock signals.
Although each flash ADC has separate analog ground(AGND) and digital ground

54
 Figure 5.3: Linear regulators with low dropout voltage

(gnd!), for better noise performance, these ground pins are connected on the PCB
board. Fig 5.6illustrates the concept of grounding for an ADC [99].
In order to decouple high frequency currents created by fast digital logic signals,
a ground plane can be serve as a low impedance return path which can also help
to minimize the EMI (Electromagnetic Interference) emissions [99]. The layout of
PCB board was produced using Cadence PCB Editor 16.6. The layout and PCB
board photo are shown in Fig 5.7 and 5.8.

5.2 Flash ADC Evaluation

While the flash ADC operates at 200MS/s, a slow ramp with 300mV amplitude is
used to test the static performance and then a 50MHz full-scale sinewave is applied
to measure the dynamic performance. Unfortunately the fabricated test chip failed
to work properly and the reason for this failure will be discussed in 5.2.2. Post
layout simlations with Casence Spectre shows the flash ADC digitizes the input

55
 Figure 5.4: Generating reference voltages

signal properly, as described in the following section.

5.2.1 Simulation Results

Cadence Virtuoso AMS Designer, as a mixed-signal simulation solution inte-
grated with the Cadence INCISIVE for digital design verification [100] is used for
this flash ADC design and verification. Fig 5.9 shows the simulation results for one
redundant flash ADC (out of two split flash ADCs) while the flash ADC works at
100MS/s for 10 consecutive conversions. A slow ramp is applied as an input. Due
to space limitation assigned to cadence simulations and the fact that the simula-
tions are time consuming (although APS feature for cadence simulation is used),
the number of simulated conversions was not enough to verify the algorithm that
introduced in chapter 3. Since the test chip failed to operate properly, the algorithm

56
 Figure 5.5: Generating differential input for each flash ADC

in chapter 3 was only tested with random input generated by MATLAB.

57
Figure 5.6: Connecting the Analog (AGND) and Digital Ground (DGND) Pins of
ADC to System Analog Ground

Figure 5.7: PCB layout for flash ADC evaluation

5.2.2 Measurement Results

This section presents failure analysis of swiftly identifying various failure con-
ditions that occur in evaluating the test chip fabricated in IBM7RF 180nm Bulk
58
 Figure 5.8: PCB board for flash ADC evaluation

Figure 5.9: Simulation results for redundant flash ADC evaluation

CMOS with 6 layers of Metal ( ie. M1, M2, M3, M4, MT, AM with DV (wirebound
glass cut). This test chip has 56 bond pads inside a LCC68 Ceramic package (from

59
MOSIS) and lid attached with 2 corner dot of epoxy. The test chip consists of two
ADCs as well as ten delay stages which are used for a DLL design that is not part
of this work. The focus will be on causes and mechanisms that led to the failures
of the ADCs. Isolation of test chip failure location began by investigating the elec-
trical characteristics using an evaluation board which was designed specifically for
this test chip. Then other investigations such as package inspections and bond wire
and ESD inspections were performed. Finally test chip analysis from MOSIS was
requested and careful layout check was done. Fig 5.10 summarizes the chip failure
determination procedures.

• Evaluation of Electrical Characteristics: An oscilloscope is used for DC and AC

characteristics evaluation. A voltage regulator (LT3080 from Linear Technol-
ogy) is used to feed the ADC with clean supply voltages. When the DC input
of 300mV is applied to the ADCs, the MUX and MUX’ the two outputs of the
DLL delay stages have a negative voltage of -400mV. NVDD (-5V) is only used
as a supply for AD8138 which is a single ended-to- Differential converter. The
assumption was failure due to ESD problem. To evaluate AC characteristic, a
low frequency signal generated by function generator was applied to AD8138.
ADC Input was a (10 kHz-100 kHz) sine wave with 300mVp-p amplitude and
common mode of 0.35V. It was observed the input of ADC was reflected to the
output of the ADC and by changing the frequency of the input, the frequency
of the signal at the output was changed. The power supplies reached the cur-
rent limit for the analog and digital supply during the DC and AC evaluation
(400mA for digital supply and 327mA for Analog supply). In case the problem
was caused by evaluation board, the second version of evaluation board with
different routing was made. Different test chips were tested on the populated
and non-populated evaluation boards in order to compare the current value
of each case. In all different test cases the power supply reached the current
limit. AVDDB which was the analog supply for the ADCB pulled a lot of
current. Bonding diagram and chip layout was checked carefully. The chip
footprint and the chip bond pads were compared. There was not any problem
with these tests. High voltage and low voltage across the ESD of each section
is connected to the related VDD and ground in that region. By disconnecting
the bond wire of AVDDB, it was expected to see the large amount of current
will disappear. But the power supply reached the current limit again. Then
the inputs to the ADC were grounded and tested the ESD performance by
sweeping the voltage from the low to high across the ESD diodes until the
power supply reached the current limit. The test had four different cases. The
test was performed on the cases with and without AVDDB connected to the
voltage. Fig 5.11 shows when the voltage reaches 0.6V, when the diodes inside
the ESD are ON, there is a big jump in the current!However cadence simula-
tions for ESD test did not show any unexpected behavior in ESD performance.
The next step was inspecting inside the package.

60
 Figure 5.10: Procedure of Chip Failure Determination

• External Visual Inspection of the chip: In this step, floating bond pads or
ESD defect were investigated. The test chip was observed with an optical
microscope and SEM. External visual inspection of the chip shows the ESD
and bond pads do not have any cracking or defect problem. There are no
floating pads over interconnects. There is no bond pad-to-bond pad failure
mechanism. The die photo for ESD defect investigation are shown in Fig 5.12
and 5.13.

• Fabrication Analysis: Prior to submission of flash ADC for fabrication, the

design had a DRC and LVS clean report. Several ESD tests done in cadence
and post layout simulation using Assura-QRC extracted layout did not show
any problem in the performance of the ADCs. A request for test chip analy-
sis was submitted to MOSIS. They provided their DRC report which showed
some antenna violations and ESD warnings. Investigation on possible floating
gates and the wells was perfomed. More DRC rules and ERC simulation was
used for well checking. Working with IBM technology ERC-checks raises the
flag to show contacts or diodes that create either a short or a forward biased

61
 Figure 5.11: ESD test for flash ADC evaluation

condition that happens between power and ground nets. NW bias checking is
also performed with ERC checking. In this technology substrate-derivation is
associated with the “N O − SU BC − IN − GRLOGIC” switch. ERC checking
is performed through LVS run. By adding this command: “ercCheckFloating-
Well( directOnly )”. ERC-checks shows the substrate of nfets is floating. Final
ERC and DRC simulation for the main subcircuit in the design which is the
comparator circuit shows floating WELL is happening for the PMOS input
pairs inside the comparators. The PMOS-body of input pairs must connect to
a voltage (BIAS1) different than supply VDD in order to use the body biasing
technique to improve the comparator speed. In IBM cmrf technology there is
no physical layer for PMOS body (inherited device) and subc represent the
substrate for NMOS devices. The layout mistake on using the subc to connect
the body of PMOS devices to BIAS1 created the floating substrate and was

62
 Figure 5.12: Test chip under optical microscope

the main reason of chip failure. Fig 5.14 ilustrates this connection mistake.

5.3 Performance Analysis

The 7-bit flash ADC was simulated in Cadence. Simulation results show the split
Flash ADC consumes 4.45mW power for analog block and 1mW for digital block
and has a FOM of 164 fJ/conversion step in simulation. Fig 5.15shows the histogram
based differential nonlinearity (DNL) plot of one redundant flash ADC according
to the simulation results. DNL results show the redundant flash ADC is monotonic
and has no missing codes. The peak DNL is 0.32/-0.39.

63
 Figure 5.13: Closer view of ESD and bond pads

5.3.1 Summary
This chapter presented the detail on test and measurement of the fabricated 7-bit
flash ADC. Design of a 4-layer evaluation board for this flash ADC was explained.
Source of errors for chip failure were explored and cadence simulation result was
provided. layout error to be corrected for future implementation was presented.

64
Figure 5.14: Layout mistake on PMOS substrate contact

Figure 5.15: DNL result for redundant flash ADC

65
Chapter 6

SAR ADC Chip Implementation

6.1 SAR ADC Proposed Algorithm

This chapter presents a new switching algorithm which is proposed to reduce
the power consumption of a successive approximation ADC (SAR ADC). Successive
approximation ADCs are widely used as medium-to-high resolution and medium
speed data converters. For high resolution SAR ADCs, fully differential techniques
provide the best common mode noise rejection and lowest distortion [101]. For
medium resolution ADCs in power-critical applications such as battery management,
the lower power consumption of simpler single-ended architectures are attractive.
This chapter describes the design of a single-ended 7-bit SAR ADC that drives
design tradeoffs toward minimum power consumption. Power reduction is achieved
using a new method of switching the SA-ADC capacitive DAC, as well as improved
efficiency in capacitor area.

6.2 SAR ADC Implementation

The conventional SAR ADC as it is explained in 2.4.3, consists of control logic,
comparator, and capacitive DAC (CDAC). For medium resolution SAR ADCs in
aggressively scaled CMOS technology, the contribution of control logic and CDAC
switching must be considered to minimize overall ADC power consumption [13].
Several methods have been proposed to reduce CDAC power consumption. In
[101], a switching method uses two CDAC arrays and a reference voltage of half
amplitude VREF /2. One capacitor array is used to sample the input and the switch-
ing is performed on the other array. This method imposes an area penalty for the
second CDAC array, and is sensitive to the VREF /2 biasing voltage. In [30], a capac-
itor splitting technique reduces the switching energy by 37%. In [102], a multi-step
charging method in the charge redistribution DAC using a split capacitor array
structure is proposed. This method introduces additional design complexity as well
as making ADC linearity dependent on proper control of CDAC switching.

66
 In [63], a switching method is described which is very power efficient. Eldo
simulation results in the 0.35μm technology targeted for this work demonstrate
power savings commensurate with those described in [63]. The work described in
this chapter explores the opportunity for further improvement in power and area
savings by eliminating the differential approach of [63] in favor of a single-ended
architecture.
For the 7-bit resolution required in this work, a single ended SA-ADC with
fewer numbers of devices than a differential topology is implemented as shown in
Fig. 6.1. The building blocks of the proposed ADC are a comparator, control logic
with decoder, CDAC, and switching network. As in [63], a binary weighted capacitor
DAC provides adequate linearity.
The CDAC capacitor network serves both sample-and-hold and DAC functions.
As shown in switching waveforms of Fig. 6.2, the signal and DAC voltage ranges
are bounded by Vin−min and Vin−max .
The distinguishing feature of this architecture is the use of switches S1-S4 at
the comparator inputs to allow a different target voltage for the DAC successive
approximation process. The target is chosen depending on the value of the input
and the MSB decision. Figure 6.2 shows the waveforms at the comparator inputs in
the two cases. The ADC splits the searching algorithm into two regions as follows.
At the beginning of the conversion switch S1 and S3 are closed and the ADC
input voltage Vinput is compared directly with Vin−half , the midpoint of the signal
range. After the MSB decision, switch S3 is opened and S4 is closed at the com-
parator - input for the remaining decisions. At the comparator + input one of two
outcomes results depending on the MSB decision:

• MSB=1 (Figure 6.2a): If the output of the comparator shows Vinput > Vin−half ,
the MSB is set high. Switch S1 remains closed and the successive approxima-
tion process converges toward Vin−half .

• MSB=0 (Figure 6.2b): If the output of the comparator shows Vinput < Vin−half ,
the MSB is set low. Switch S1 is opened, switch S2 is closed, and the successive
approximation process converges toward Vin−min .

The advantage of this technique is that the largest capacitance (and its associated
switching) is removed from the DAC network, which reduces the area, power and
capacitor switching.
While the function of the remaining cycles follows the conventional SA-ADC ap-
proach, the implementation of the design features techniques which provide further
power savings. This ADC was designed for an application in which the signal range
was limited to the range 300mV < Vinput < 900mV . Since this technology provides
a 3.3V supply and the maximum voltage in DAC is 2V no bootstrapped switches
are needed to turn on the NMOS switches.
A 3-to-8 decoder provides the switching for the remaining approximation cycles
of the ADC. Only one capacitor switch is needed for each bit cycle which minimizes

67
 Figure 6.1: Proposed SA-ADC architecture

charge transfer and power consumption. Since the first MSB is determined without
any capacitor switching, this can save a significant amount of power consumption.

6.3 ADC Building Blocks

6.3.1 Dynamic Comparator
To minimize power consumption, a dynamic comparator is chosen, with schematic
as shown in Fig.6.3. A PMOS input differential pair is used, since the analog input
common mode range in this specific application was close to ground. The compara-
tor uses the Lewis-Gray [87] architecture: when ‘Latch’ is high the comparator is
reset; when ‘Latch’ is low regeneration around the MN1-MN2 loop is enabled. The
conductivity imbalance from the MP1-MP2 input pair [63] forces the comparator
output to go low or high.
Additional offset cancellation techniques are applied to address mismatch in
M N 1 − M N 4. To minimize the variation of effective voltage of the input pairs
MP1-MP2, transistor Mc biased in saturation is added in the source path of switch
M P 3 [63]. M P 9 and M P 10 are added to improve the device matching. Cascode
transistors M N 5 and M N 6 are added to increase the gain of the differential struc-
ture and thus decrease the input-referred comparator offset. Note that separate
bias is used for NMOS cascode devices to minimize the influence on capacitance of
regeneration nodes. M P 4 and M P 5 are added to improve the rise time.
Figure 6.4 shows results of a Monte-Carlo simulation of comparator offset for
the comparator of Fig. 6.3. The standard deviation of σ = 2.26mV gives an overall

68
Figure 6.2: Waveforms of proposed switching procedure: (a) MSB=1 (b) MSB=0

ADC offset less than 1LSB, which is adequate for the targeted application.

6.3.2 DAC Capacitor Network

For the CDAC unit capacitor, a MOS capacitor in enhancement is used as it con-
sumes less area than an equivalent value MIM capacitor and the error of charge
injection from gate-source parasitic capacitance of NMOS switches in DAC logic is
minimized. To achieve more linearity given the voltage swings in this specific appli-
cation, P-type enhancement-mode MOS is chosen. The size of the unit capacitance
is 66fF, with total layout area 6.1μm × 6.1μm which satifies kT C
limitations. As
mentioned in Section 6.2, only one capacitor array is needed for the single ended
SA-ADC approach, resulting in significant area saving. The 7-bit SA-ADC uses 63

69
 Figure 6.3: Dynamic Comparator

Figure 6.4: Monte-Carlo simulation of comparator offset. σ = 2.26mV

unit capacitors, giving a total capacitance ≈ 4pF. Monte-Carlo simulation of the ca-
pacitor network shows adequate matching for the linearity required of a 7-bit ADC.
The charge and discharge path for the capacitors is through NMOS transistors.
The gates of these NMOS transistors are controlled by the output of the switching
logic network, as described in section 6.3.3 below. Careful layout techinques were
observed to avoid parasitic influences on DAC performance [63].

70
 Figure 6.5: Control logic switches and timing

6.3.3 Switching Logic Network

Figure 6.5 shows the structure of the control logic circuitry and the timing diagram
of the decoder signals and switches. To minimize the power consumption the clock
signal for registers are all produced by a decoder. 7 registers are used to hold the bit
values. A 3-to-8 decoder generates 8 signals Y[1],. . . ,Y[8]. Appropriate combinations
of these signals generate the control signals for the DAC and S1 and S2 switches.
Switch S1, S2 and S4 and the Sample and Hold signals are generated from Y[1] and
Y[8]. A one-shot reset is also generated at the beginning of the conversion from Y[1]
which is used to reset the registers when the conversion starts.

71
6.3.4 Sample and Hold
The input sampling signal is generated through the 3-to-8 decoder. To give enough
time to ADC to sample the input, the sample control is the OR of first and last
decoded signal (Y[1]+Y[8]). Sampling switches are CMOS transmission gates. The
sampled input is held on capacitive DAC network. No additional sample and hold
circuitry is needed.

6.3.5 Refference Volatges

Reference voltages for SAR ADC are generated by an on-chip band gap. A resistive
divider provides the 300mV and the 600mV reference voltages for the comparator
and the CDAC. Regerence voltages are followed by an analog buffer which features
4-bit trim with 4mV LSB for high and low trim after fabrication. This trim can affect
the refference voltage up to -20mV/+20mV. Fig 6.6 shows the top level schematic
of the SAR ADC. Datails on analog buffer with tuning feature is shown in Fig
6.7. R1-R8 have different values of . The comparator low voltage refference and the
reference voltage for the DAC are both 300mV. In order to separate the noise path of
these two refference voltages two separate analog buffers are used. The test chip can
use an on-chip clock of 2MHz and an external clock which can be selected through
a multiplexer as it is shown in Fig 6.6. Each clock path has its own buffer. Low
voltage buffers of reference voltages also has separate supply rail (Bufrail) which is
provided with the test chip externally.

6.3.6 Summary
This chapter presented the details on designing a 7-bit low power SAR ADC in
circuit level. Analog and digital blocks of this SAR ADC were discussed. Dynamic
comparator design, DAC capacitor network and switching logic network were ex-
plained.

72
Figure 6.6: Top level schematic of SAR ADC design

73
 74

Figure 6.7: Analog buffer with tuning

Chapter 7

SAR ADC Testing and Analysis

A 7-bit 100kS/s SAR ADC has been designed using the proposed algorithm in 6.1,
and simulated in 0.35μm CMOS-DMOS technology with Pyxis Mentor Graphic. Fig
7.1 shows the layout for this SAR ADC for analog blocks, including buffers, switches,
DAC and comparator. Clock and logic block are not included in this figure. The
analog part of the SAR ADC occupies 150μm× 105μm. The test chip has been
fabricated as an internship project at ON Semicondctor. The bare dies are wire
bonded in house at ON Semiconductor East Greenwich, RI into SOIC 28w package.
The I/O pads for ADC digital output were small (76μm × 76μ m with minimum
space 90 μm center-to-center of the pad. Therefore some of the digital outputs
(SAH for monitoring, Out0(LSB), out2, out3, out5, out6 (MSB)) are measured by
probe needles. 6 probe needles used simultaneously to measure these outputs. The
output of the probe needles met the 50Ω matching resistors and the digital outputs
were measured on the other side of the resitors using a rainbow digital cable and
a header. Logic Analyzer inside a Lecroy Osciloscope was used for observing the
analog and digital signals at the same time. Fig 7.2 shows the bonding diagram for
this test chip.
An onchip 2-V supply has been used for the CDAC and switching logic net-
work (DRAIL) while a separate on-chip 2V supply has been provided with the
dynamic comparator (ARAIL). The 2V supply for both analog and digital blocks
comes from a power block on-chip. The ADC input range in this case was 600mV
(An input from 300mV to 900mV) but this is not a limitation; the architecture can
be modified for other supply and input range combinations while preserving most
of the power saving advantages.
Table 7.1 shows the ADC parameters and simulation results for this SAR ADC
design.

75
 PARAMETER VALUE UNITS
Resolution 7 bits
Sampling Rate 100 KS/s
Input Range 600 mV pk-pk
Supply Voltage
DAC, Decoder, Logic 2.0 V
Comparator 2.0 V
Supply Current
(excludes reference buffers)
2.0V Supply 1.66 μA
2.0V Supply 0.69 μA
Power Consumption 4.7 μW
Sampling Capacitance 4.0 pF

Table 7.1: System Simulation Results

Figure 7.1: Analog portion of SAR ADC layout, including buffers, switches, DAC
and comparator

7.1 PCB Design

Two layers printed circuit board with a ground plane on top, as an interface
between the dies and test equipment has been designed. Linear regulator with low
dropout voltage from linear technology [95] is used to create clean power supply
for on-chip buffers (BufRAIL). A 3-pin jumper is placed on the board that allows

76
 Figure 7.2: SAR ADC bonding diagram

selection between the regulated voltage and direct voltage from power supply. A
decoupling capacitor is also placed on the middle pin of the jumper which goes
into the related pin on chip. ADC input and external clock are provided through
SMA connectors which have 50Ω matching resistors. Fig 7.3 shows the SAR ADC
evaluation board and the Cadence schematic for this PCB design respectively.

77
 Figure 7.3: Measure DNL and INL for Die1

7.2 Static Performance

In order to measure the static performance of SAR ADC, a slow ramp (2048
μs ramp) was applied to SAR ADC and the linearity is tested 1000 times with 2
hits per code histogram. For this 7-bit 100kS/s SAR ADC, each conversion takes 8
clock cycles which is equal to 8μs. For 128 possible codes at least a 1024 μs ramp is
needed. Two separate parts were tested with similar inputs. The results are shown
in Fig 7.4 and 7.5. The peak DNL and INL are 0.88/-0.99 LSB and 2/-1.5 LSB for
ADC1 and 0.9/-0.99 LSB and 1.6/-2 LSB for ADC2 respectively.
Static performance analysis of this SAR ADC shows the middle code 64 is the
missing code. The refference voltages (300mV,600 mV) to ADC was measured
through probing the test points on the chip and the tuning resistors in GM − C
buffers that is explianed in 6.3.5 were used to trim the reference voltages through
a laser microscope. The average measured reference voltages after the tuning were
299V and 600.2V respictively. A clibration is needed to improve the linearity of
this ADC. However since this SAR ADC is used in a feedback loop of a switching
mode regulator, only one missing code will not cause any problem for this specific
application.

78
 Figure 7.4: Measured DNL and INL with ramp input for Die1

Figure 7.5: Measured DNL and INL with ramp input for Die2

7.3 Dynamic Performance

Fig 7.6 show the measured FFT spectrum with input frequency of close to 40kHz at
a 2.0-V supply and a 100kS/sampling rate. The measured effective number of bits is
6.49 at low frequencies. The measured peak SNR due to quantization noise (SNQR)
is 40.87dB. Since needle probes are source of collecting the noise, peak SNDR of
27.9dB was measured. A proper wire bonding of all digital outputs can improve the
SNDR.
Total power consumption for this SAR ADC excluding the reference buffers is 4.7
μW, which is a 73% power reduction compared to an SAR ADC with conventional
switching. Table 7.2summerizes the performance analysis for the SAR test chip.
Walden FOM for this SAR ADC is 11.9 fJ/conversion-step.

7.4 summary
In this chapter the evaluation of SAR ADC and measurement results were pre-
sented. Measurement result shows the SAR ADC1 has a peak DNL of 0.88 /-0.99
and peak INL of 0.6/-1LSB. The SAR ADC2 has a peak DNL of 0.9 /-0.99 and peak

79
 Figure 7.6: Measured 4096-point FFT spectrum at 100 kS/s.

Specification [63] [103] [104] This Work

Technology(mum) 0.13 0.13 0.18 0.35BCD
Supply Voltage(V) 1.2 1.2 1.0 2.0
Resolution(bit) 10 10 12 7
Sampling Rate (fs) kS/s 50000 1000 200(100) 100
Input frequency fin (KHz) 500 101 100(50) 1
ENOB (bits @ fin) 9.18 8.39 7.96(10.55) 6.49
FOM (fJ/conversion-step) 29 437 381(166) 11.9
Power Consumption (μW) 826 150 19(25) 5.61

Table 7.2: SAR ADC performance analysis

INL of 1.6/-2 LSB. The measured effective number of bits of 6.49 at low frequen-
cies and the peak SNR due to quantization noise (SNQR) of 40.87dB was reported.
The proposed algorithm has 73% power reduction compared to an SAR ADC with
conventional switching. Although this SAR ADC suffers from a missing code in the
middle, it will not make any issue for the application that this ADC is used.

80
Chapter 8

Conculsions

All digital background calibration of a 7-bit redundant flash ADC suitable for
aggressively scaled CMOS technologies was presented and an ultra-low power single
ended SAR ADC with a new conversion method was proposed in this disserta-
tion.Chapter 2 provided a detailed background on flash ADC, SAR ADC and Split
ADC architectures and previous calibration techniques.
Chapter 3 presented the details on digital background calibration of flash
ADC and demonstrated the algorithm in behavioral simulation based on extracted
IC layout in 180nm CMOS. The details on circuit level flash ADC deisgn were
described in chapter 4 and simulation resluts, test and evaluation of flash ADC were
demonstrated in chapter5.
The new DAC switching algorithm for SAR ADC was explained in chapter 6.
The new architecture allows the ADC to perform the MSB decision without using
the DAC resulting in significant power and area savings. The work presented in
chapter 6 was implemented in an IC fabricated in 350nm CMOS DMOS technology
sponsored by ON Semiconductor. Measurement results from tesing the SAR test
chip were provided in chapter 7.

8.1 Future Work

All digital background calibration of split redundant flash ADC can be extended
to use for an time interleaved flash ADC for a better speed and resolution. The
algorithm can be applied to smaller technologies to achieve better performance.
The new DAC swithcing algorithm that is proposed for SAR ADC design can
be more effective if the comparator offset is calibrated with auto zeroing techniques
and a common centroid technique is used for capacitive DAC layout.

81
Appendix A

Glossary

A.1 Acronym

FS Full Scale
HDL Hardware Description Language
IC Integrated Circuit
LMS Least Mean Squares
LSB Least Significant Bit
LUT Lookup Table
MOSFET Metal Oxide Semiconductor Field Effect Transistor
MSB Most Significant Bit
NMOS N-Channel Metal Oxide Semiconductor
PMOS P-Channel Metal Oxide Semiconductor
PRN Pseudo Random Number
RMS Root Mean Square
SAR Successive Approximation Register
SNDR Signal to Noise and Distortion Ratio

82
 A.2 Flash ADC decoder design,verilog code
1 module CLA 4bit (
2 output [ 3 : 0 ] S ,
3 output Cout , / /PG,GG,
4 i n p u t [ 3 : 0 ] A, B,
5 i n p u t Cin
6 );
7 w i r e [ 3 : 0 ] G, P , C ;
8 a s s i g n G = A & B ; // Generate
9 a s s i g n P = A ˆ B ; // Propagate
10 a s s i g n C [ 0 ] = Cin ;
11 a s s i g n C [ 1 ] = G[ 0 ] | (P [ 0 ] & C [ 0 ] ) ;
12 a s s i g n C [ 2 ] = G[ 1 ] | (P [ 1 ] & G[ 0 ] ) | (P [ 1 ] & P [ 0 ] & C [ 0 ] ) ;
13 a s s i g n C [ 3 ] = G[ 2 ] | (P [ 2 ] & G[ 1 ] ) | (P [ 2 ] & P [ 1 ] & G[ 0 ] ) |
(P [ 2 ] & P [ 1 ] & P [ 0 ] & C [ 0 ] ) ;
14 a s s i g n Cout = G[ 3 ] | (P [ 3 ] & G[ 2 ] ) | (P [ 3 ] & P [ 2 ] & G[ 1 ] ) | (P [ 3 ]
& P [ 2 ] & P [ 1 ] & G[ 0 ] ) | ( P [ 3 ] & P [ 2 ] & P [ 1 ] & P [ 0 ] & C [ 0 ] ) ;
15 a s s i g n S = P ˆ C;
16 // a s s i g n PG = P [ 3 ] & P [ 2 ] & P [ 1 ] & P [ 0 ] ;
17 // a s s i g n GG = G[ 3 ] | (P [ 3 ] & G[ 2 ] ) | (P [ 3 ] & P [ 2 ] & G[ 1 ] ) | (P [ 3 ]
& P [ 2 ] & P [ 1 ] & G[ 0 ] ) ;
18 endmodule

1 module CLA 5bit (

2 output [ 4 : 0 ] S ,
3 output Cout ,
4 i n p u t [ 4 : 0 ] A, B,
5 i n p u t Cin
6 );
7 w i r e [ 4 : 0 ] G, P , C ;
8 a s s i g n G = A & B ; // Generate
9 a s s i g n P = A ˆ B ; // Propagate
10 a s s i g n C [ 0 ] = Cin ;
11 a s s i g n C [ 1 ] = G[ 0 ] | (P [ 0 ] & C [ 0 ] ) ;
12 a s s i g n C [ 2 ] = G[ 1 ] | (P [ 1 ] & G[ 0 ] ) | (P [ 1 ] & P [ 0 ] & C [ 0 ] ) ;
13 a s s i g n C [ 3 ] = G[ 2 ] | (P [ 2 ] & G[ 1 ] ) | (P [ 2 ] & P [ 1 ] & G[ 0 ] ) | (P [ 2 ]
& P[ 1 ] & P[ 0 ] & C[ 0 ] ) ;
14 a s s i g n C [ 4 ] = G[ 3 ] | (P [ 3 ] & G[ 2 ] ) | (P [ 3 ] & P [ 2 ] & G[ 1 ] ) | (P [ 3 ]
& P [ 2 ] & P [ 1 ] & G[ 0 ] ) | (P [ 3 ] & P [ 2 ] & P [ 1 ] & P [ 0 ] & C [ 0 ] ) ;
15 a s s i g n Cout = G[ 4 ] | (P [ 4 ] & G[ 3 ] ) | (P [ 4 ] & P [ 3 ] & G[ 2 ] ) | (P [ 4 ]
& P [ 3 ] & P [ 2 ] & G[ 1 ] ) | ( P [ 4 ] & P [ 3 ] & P [ 2 ] & P [ 1 ] & G[ 0 ] ) | (P [ 4 ] &
P [ 3 ] & P [ 2 ] & P[ 1 ] & P [ 0 ] & C [ 0 ] ) ;
16 a s s i g n S = P ˆ C;
17 // a s s i g n PG = P [ 4 ] & P [ 3 ] & P [ 2 ] & P [ 1 ] & P [ 0 ] ;
18 // a s s i g n GG = G[ 4 ] | (P [ 4 ] & G[ 3 ] ) | (P [ 4 ] & P [ 3 ] & G[ 2 ] ) | (P [ 4 ] &
P [ 3 ] & P [ 2 ] & G[ 1 ] ) | ( P [ 4 ] & P [ 3 ] & P [ 2 ] & P [ 1 ] & G[ 0 ] ) ;
19 endmodule

83
 1
2 ‘ t i m e s c a l e 1 ns /1 ps
3 module D f l i p f l o p ( d , c l k , r e s e t , q ) ;
4 input d , reset , clk ;
5 output q ;
6 reg q ;
7
8 always @( negedge c l k ) b e g i n
9 i f ( reset )
10 q<=0;
11 else
12 q<=d ;
13 end
14 endmodule

1 ‘ t i m e s c a l e 1 ns /1 ps
2 module D f l i p f l o p 6 ( d , c l k , r e s e t , q ) ;
3 input [ 5 : 0 ] d ;
4 input clk , r e s e t ;
5 output [ 5 : 0 ] q ;
6
7 // parameter d e l a y 1 = 0 . 1 ;
8

9 /////////1////////////////////
10
11 D flipflop DUT2( d [ 5 ] , clk , reset ,q[5]) ;
12 D flipflop DUT3( d [ 4 ] , clk , reset ,q[4]) ;
13 D flipflop DUT4( d [ 3 ] , clk , reset ,q[3]) ;
14 D flipflop DUT5( d [ 2 ] , clk , reset ,q[2]) ;
15 D flipflop DUT6( d [ 1 ] , clk , reset ,q[1]) ;
16 D flipflop DUT7( d [ 0 ] , clk , reset ,q[0]) ;
17
18
19 endmodule

84
 1 ‘ t i m e s c a l e 1 ns /100 ps
2 module D f l i p f l o p 6 3 ( d , c l k , r e s e t , q ) ;
3 input [ 6 2 : 0 ] d ;
4 input reset , clk ;
5 output [ 6 2 : 0 ] q ;
6 parameter d e l a y 1 =1;
7
8
9

10 D flipflop DUT62( d [ 6 2 ] , clk , reset ,q[62]) ;

11 D flipflop DUT61( d [ 6 1 ] , clk , reset ,q[61]) ;
12 D flipflop DUT60( d [ 6 0 ] , clk , reset ,q[60]) ;
13 D flipflop DUT59( d [ 5 9 ] , clk , reset ,q[59]) ;
14 D flipflop DUT58( d [ 5 8 ] , clk , reset ,q[58]) ;
15 D flipflop DUT57( d [ 5 7 ] , clk , reset ,q[57]) ;
16
17
18 //////////////8///////////////////
19 D f l i p f l o p DUT56( d [ 5 6 ] , c l k , r e s e t , q [ 5 6 ] ) ;
20 D f l i p f l o p DUT55( d [ 5 5 ] , c l k , r e s e t , q [ 5 5 ] ) ;
21 D f l i p f l o p DUT54( d [ 5 4 ] , c l k , r e s e t , q [ 5 4 ] ) ;
22 D f l i p f l o p DUT53( d [ 5 3 ] , c l k , r e s e t , q [ 5 3 ] ) ;
23 D f l i p f l o p DUT52( d [ 5 2 ] , c l k , r e s e t , q [ 5 2 ] ) ;
24 D f l i p f l o p DUT51( d [ 5 1 ] , c l k , r e s e t , q [ 5 1 ] ) ;
25 D f l i p f l o p DUT50( d [ 5 0 ] , c l k , r e s e t , q [ 5 0 ] ) ;
26 D f l i p f l o p DUT49( d [ 4 9 ] , c l k , r e s e t , q [ 4 9 ] ) ;
27 D f l i p f l o p DUT48( d [ 4 8 ] , c l k , r e s e t , q [ 4 8 ] ) ;
28 D f l i p f l o p DUT47( d [ 4 7 ] , c l k , r e s e t , q [ 4 7 ] ) ;
29
30
31 ///////////////9///////////////////
32 D f l i p f l o p DUT46( d [ 4 6 ] , c l k , r e s e t , q [ 4 6 ] ) ;
33 D f l i p f l o p DUT45( d [ 4 5 ] , c l k , r e s e t , q [ 4 5 ] ) ;
34 D f l i p f l o p DUT44( d [ 4 4 ] , c l k , r e s e t , q [ 4 4 ] ) ;
35 D f l i p f l o p DUT43( d [ 4 3 ] , c l k , r e s e t , q [ 4 3 ] ) ;
36 D f l i p f l o p DUT42( d [ 4 2 ] , c l k , r e s e t , q [ 4 2 ] ) ;
37 D f l i p f l o p DUT41( d [ 4 1 ] , c l k , r e s e t , q [ 4 1 ] ) ;
38 D f l i p f l o p DUT40( d [ 4 0 ] , c l k , r e s e t , q [ 4 0 ] ) ;
39 D f l i p f l o p DUT39( d [ 3 9 ] , c l k , r e s e t , q [ 3 9 ] ) ;
40 D f l i p f l o p DUT38( d [ 3 8 ] , c l k , r e s e t , q [ 3 8 ] ) ;
41 D f l i p f l o p DUT37( d [ 3 7 ] , c l k , r e s e t , q [ 3 7 ] ) ;
42
43
44 ////////////////10//////////////////
45 D f l i p f l o p DUT36( d [ 3 6 ] , c l k , r e s e t , q [ 3 6 ] ) ;
46 D f l i p f l o p DUT35( d [ 3 5 ] , c l k , r e s e t , q [ 3 5 ] ) ;
47 D f l i p f l o p DUT34( d [ 3 4 ] , c l k , r e s e t , q [ 3 4 ] ) ;
48 D f l i p f l o p DUT33( d [ 3 3 ] , c l k , r e s e t , q [ 3 3 ] ) ;
49 D f l i p f l o p DUT32( d [ 3 2 ] , c l k , r e s e t , q [ 3 2 ] ) ;
50 D f l i p f l o p DUT31( d [ 3 1 ] , c l k , r e s e t , q [ 3 1 ] ) ;
51 D f l i p f l o p DUT30( d [ 3 0 ] , c l k , r e s e t , q [ 3 0 ] ) ;

85
52 D f l i p f l o p DUT29( d [ 2 9 ] , c l k , r e s e t , q [ 2 9 ] ) ;
53 D f l i p f l o p DUT28( d [ 2 8 ] , c l k , r e s e t , q [ 2 8 ] ) ;
54 D f l i p f l o p DUT27( d [ 2 7 ] , c l k , r e s e t , q [ 2 7 ] ) ;
55
56
57 ///////////////11///////////////////
58 D f l i p f l o p DUT26( d [ 2 6 ] , c l k , r e s e t , q [ 2 6 ] ) ;
59 D f l i p f l o p DUT25( d [ 2 5 ] , c l k , r e s e t , q [ 2 5 ] ) ;
60 D f l i p f l o p DUT24( d [ 2 4 ] , c l k , r e s e t , q [ 2 4 ] ) ;
61 D f l i p f l o p DUT23( d [ 2 3 ] , c l k , r e s e t , q [ 2 3 ] ) ;
62 D f l i p f l o p DUT22( d [ 2 2 ] , c l k , r e s e t , q [ 2 2 ] ) ;
63 D f l i p f l o p DUT21( d [ 2 1 ] , c l k , r e s e t , q [ 2 1 ] ) ;
64 D f l i p f l o p DUT20( d [ 2 0 ] , c l k , r e s e t , q [ 2 0 ] ) ;
65 D f l i p f l o p DUT19( d [ 1 9 ] , c l k , r e s e t , q [ 1 9 ] ) ;
66 D f l i p f l o p DUT18( d [ 1 8 ] , c l k , r e s e t , q [ 1 8 ] ) ;
67 D f l i p f l o p DUT17( d [ 1 7 ] , c l k , r e s e t , q [ 1 7 ] ) ;
68
69

70 //////////////12////////////////////
71 D f l i p f l o p DUT16( d [ 1 6 ] , c l k , r e s e t , q [ 1 6 ] ) ;
72 D f l i p f l o p DUT15( d [ 1 5 ] , c l k , r e s e t , q [ 1 5 ] ) ;
73 D f l i p f l o p DUT14( d [ 1 4 ] , c l k , r e s e t , q [ 1 4 ] ) ;
74 D f l i p f l o p DUT13( d [ 1 3 ] , c l k , r e s e t , q [ 1 3 ] ) ;
75 D f l i p f l o p DUT12( d [ 1 2 ] , c l k , r e s e t , q [ 1 2 ] ) ;
76 D f l i p f l o p DUT11( d [ 1 1 ] , c l k , r e s e t , q [ 1 1 ] ) ;
77 D f l i p f l o p DUT10( d [ 1 0 ] , c l k , r e s e t , q [ 1 0 ] ) ;
78 D f l i p f l o p DUT9( d [ 9 ] , c l k , r e s e t , q [ 9 ] ) ;
79 D f l i p f l o p DUT8( d [ 8 ] , c l k , r e s e t , q [ 8 ] ) ;
80 D f l i p f l o p DUT7( d [ 7 ] , c l k , r e s e t , q [ 7 ] ) ;
81

82
83 //////////////13////////////////////
84
85 D flipflop DUT6( d [ 6 ] , clk , reset ,q[6]) ;
86 D flipflop DUT5( d [ 5 ] , clk , reset ,q[5]) ;
87 D flipflop DUT4( d [ 4 ] , clk , reset ,q[4]) ;
88 D flipflop DUT3( d [ 3 ] , clk , reset ,q[3]) ;
89 D flipflop DUT2( d [ 2 ] , clk , reset ,q[2]) ;
90 D flipflop DUT1( d [ 1 ] , clk , reset ,q[1]) ;
91 D flipflop DUT0( d [ 0 ] , clk , reset ,q[0]) ;
92
93

94
95 //////////////////////////////////
96
97 endmodule

86
 1 ‘ t i m e s c a l e 1 ns /1 ps
2 module DFF encoder63 ( data , c l k , r e s e t , f i n a l o u t ) ;
3 i n p u t [ 6 2 : 0 ] data ;
4 input clk , r e s e t ;
5 output [ 5 : 0 ] f i n a l o u t ;
6 w i r e [ 6 2 : 0 ] qout ;
7 w i r e [ 5 : 0 ] wout ;
8
9

10
11 D f l i p f l o p 6 3 DUT1( data , c l k , r e s e t , qout ) ;
12
13 w a l l a c e b l o c k 3 B DUT2( qout , wout ) ;
14

15 D f l i p f l o p 6 DUT3( wout , c l k , r e s e t , f i n a l o u t ) ;
16
17
18 endmodule

1 ‘ t i m e s c a l e 1 ns /1 ps
2 module f u l l a d d e r ( a , b , c , sum , c a r r y ) ;
3 input a , b , c ;
4 output sum , c a r r y ;
5 // w i r e sum , c a r r y ;
6
7 a s s i g n sum=a ˆbˆ c ; // sum b i t
8 a s s i g n c a r r y =(( a&b ) | ( b&c ) | ( a&c ) ) ; // c a r r y b i t
9
10 endmodule

87
 1 ‘ t i m e s c a l e 1 ns /1 ps
2 module w a l l a c e b l o c k ( d , out ) ;
3 input [ 1 4 : 0 ] d ;
4 output [ 3 : 0 ] out ;
5 wire [ 1 : 0 ] w;
6 wire [ 7 : 0 ] z ;
7 wire [ 7 : 0 ] s ;
8 f u l l a d d e r add1 ( z [ 0 ] , z [ 4 ] , d [ 1 4 ] , out [ 0 ] , w [ 0 ] ) ;
9 f u l l a d d e r add2 ( z [ 2 ] , z [ 6 ] , w [ 0 ] , out [ 1 ] , w [ 1 ] ) ;
10 f u l l a d d e r add3 ( z [ 3 ] , z [ 7 ] , w [ 1 ] , out [ 2 ] , out [ 3 ] ) ;
11 //////////////////////////////////////////
12 //2 nd b l o c k //
13 //////////////////////////////////////////
14 f u l l a d d e r add4 ( s [ 0 ] , s [ 2 ] , d [ 1 3 ] , z [ 0 ] , z [ 1 ] ) ;
15 f u l l a d d e r add5 ( s [ 1 ] , s [ 3 ] , z [ 1 ] , z [ 2 ] , z [ 3 ] ) ;
16 f u l l a d d e r add6 ( s [ 4 ] , s [ 6 ] , d [ 6 ] , z [ 4 ] , z [ 5 ] ) ;
17 f u l l a d d e r add7 ( s [ 5 ] , s [ 7 ] , z [ 5 ] , z [ 6 ] , z [ 7 ] ) ;
18 //////////////////////////////////////////
19 //3 rd b l o c k //
20 //////////////////////////////////////////
21 f u l l a d d e r add8 ( d [ 1 1 ] , d [ 1 0 ] , d [ 1 2 ] , s [ 0 ] , s [ 1 ] ) ;
22 f u l l a d d e r add9 ( d [ 8 ] , d [ 7 ] , d [ 9 ] , s [ 2 ] , s [ 3 ] ) ;
23 f u l l a d d e r add10 ( d [ 3 ] , d [ 4 ] , d [ 5 ] , s [ 4 ] , s [ 5 ] ) ;
24 f u l l a d d e r add11 ( d [ 1 ] , d [ 0 ] , d [ 2 ] , s [ 6 ] , s [ 7 ] ) ;
25 endmodule

1 ‘ t i m e s c a l e 1 ns /1 ps
2 module w a l l a c e b l o c k 2 B ( d , out ) ;
3 input [ 3 0 : 0 ] d ;
4 output [ 4 : 0 ] out ;
5 wire [ 3 : 0 ] t ;
6 wire [ 3 : 0 ] y ;
7 w a l l a c e b l o c k b1 ( d [ 1 4 : 0 ] , t [ 3 : 0 ] ) ;
8 w a l l a c e b l o c k b2 ( d [ 2 9 : 1 5 ] , y [ 3 : 0 ] ) ;
9 CLA 4bit u1 ( out [ 3 : 0 ] , out [ 4 ] , t , y , d [ 3 0 ] ) ;
10 endmodule

1 ‘ t i m e s c a l e 1 ns /1 ps
2 module w a l l a c e b l o c k 3 B ( d , out ) ;
3 input [ 6 2 : 0 ] d ;
4 output [ 5 : 0 ] out ;
5 wire [ 4 : 0 ] t ;
6 wire [ 4 : 0 ] y ;
7 w a l l a c e b l o c k 2 B b1 ( d [ 3 0 : 0 ] , t [ 4 : 0 ] ) ;
8 w a l l a c e b l o c k 2 B b2 ( d [ 6 1 : 3 1 ] , y [ 4 : 0 ] ) ;
9 // C a r r y l o o k A h e a d a d d e r 5 b i t u1 ( out [ 4 : 0 ] , out [ 5 ] , t , y , d [ 6 2 ] ) ;
10 CLA 5bit u1 ( out [ 4 : 0 ] , out [ 5 ] , t , y , d [ 6 2 ] ) ;
11 endmodule

88
 A.3 Sampling jitter at different SNR and input
frequency
1 clc ;
2 clear all ;
3 SNR=[−66 −78 −90 −102];
4 dt =[1 e6 : 5 e5 : 1 e8 ] ;
5 c l o s e ALL
6 a x i s ( [ 1 e6 1 e8 1 e −14 1 e −10])
7 h o l d on
8 f o r j =1: s i z e (SNR, 2 ) ;
9 f o r i =1: s i z e ( dt , 2 )
10 f ( j , i ) =10ˆ(−SNR( j ) / 2 0 ) / ( 2 ∗ p i ∗ dt ( 1 , i ) ) ;
11 end
12 % p l o t ( dt , f ( j , : ) )
13 end

89
 A.4 Flash ADC, DNL/INL plot, MATLAB code
1 clear ; clc ;
2 A=l o a d ( ’ F l a s h 1 0 m a t . csv ’ ) ;
3 B=s i z e (A) ;
4 A round =[A( : , 1 ) f i x (A( : , 2 ) ) f i x (A( : , 3 ) ) f i x (A( : , 4 ) ) f i x (A( : , 5 ) ) . . .
5 f i x (A( : , 6 ) ) f i x (A( : , 7 ) ) f i x (A( : , 8 ) ) f i x (A( : , 9 ) ) f i x (A( : , 1 0 ) ) . . .
6 f i x (A( : , 1 1 ) ) f i x (A( : , 1 2 ) ) ] ;
7 A round ( : , 1 3 )=A round ( : , 4 ) +2∗A round ( : , 5 ) +4∗A round ( : , 6 ) . . .
8 +8∗A round ( : , 7 ) +16∗A round ( : , 8 ) +32∗A round ( : , 9 ) +64∗A round ( : , 1 0 ) ;
9 %p l o t ( A round ( 1 : 1 5 0 0 , 1 ) , A round ( 1 : 1 5 0 0 , 1 1 ) )
10 j =0;
11 k=0;
12 n=2;
13 m=3;
14 f o r i =1:( s i z e ( A round , 1 ) −1)
15 i f and ( A round ( i , 1 1 ) >0, A round ( i +1 ,11)==0)
16 j=j +1;
17 i f j==n
18 k=k+1;
19 C( k , : ) =[ i +1 A round ( i +1 ,13) ] ;
20 e l s e i f j ==(n+m)
21 k=k+1;
22 C( k , : ) =[ i +1 A round ( i +1 ,13) ] ;
23 m=m+3;
24 end
25 end
26 end
27 %
28 c min=min (C ( : , 2 ) ) ;
29 c max=max(C ( : , 2 ) ) ;
30 j =1;
31 f o r i=c min : c max
32 i f f i n d (C ( : , 2 )==i )
33 d=s i z e ( f i n d (C ( : , 2 )==i ) , 1 ) ;
34 x1 ( j , : ) =[ i d ] ;
35 j=j +1;
36 end
37 end
38 t o t a l a v e=sum ( x1 ( : , 2 ) ) / s i z e ( x1 , 1 ) ;
39 x3 =[ x1 ( : , 1 ) x1 ( : , 2 ) / t o t a l a v e ] ;
40 d n l=x3 ( : , 2 ) −1;
41 i n l=cumsum ( d n l ) ;
42 c r e a t e f i g u r e ( x1 ( : , 1 ) , dnl , i n l )

90
 A.5 SAR ADC, DNL/INL plot, MATLAB code
1 clear ; clc ;
2 A=l o a d ( ’ c l k −1MHz−ramp−511 d i e 2 . csv ’ ) ;
3 B=s i z e (A, 2 ) ;
4 A( : , B+1)=A( : , B−7)+A( : , B−6)∗2+A( : , B−5)∗4+A( : , B−4) ∗ 8 . . .
5 +A( : , B−3)∗16+A( : , B−2)∗32+A( : , B−1) ∗ 6 4 ;
6 c min=min (A( : , 1 0 ) ) ;
7 c max=max(A( : , 1 0 ) ) ;
8 j =1;
9 f o r i=c min : c max
10 i f f i n d (A( : , B+1)==i )
11 d=s i z e ( f i n d (A( : , B+1)==i ) , 1 ) ;
12 x1 ( j , : ) =[ i d ] ;
13 j=j +1;
14 end
15 end
16 o u t l i e r =[0 63 123 1 2 7 ] ;
17 x2=x1 ;
18 k=0;
19 f o r i =1: s i z e ( o u t l i e r , 2 )
20 x2 ( ( f i n d ( x1 ( : , 1 )==o u t l i e r ( 1 , i ) ) )−k , : ) = [ ] ;
21 k=k+1;
22 end
23 t o t a l a v e=sum ( x2 ( : , 2 ) ) / s i z e ( x2 , 1 ) ;
24 x3 =[ x2 ( : , 1 ) x2 ( : , 2 ) / t o t a l a v e ] ;
25 d n l=x3 ( : , 2 ) −1;
26 i n l=cumsum ( d n l ) ;
27 c r e a t e f i g u r e ( x2 ( : , 1 ) , dnl , i n l )

91
 A.6 SAR ADC, fft plot, SNR calculation MAT-
LAB code
1 % ========================================================= %
2 % C a l c u l a t e s SNR u s i n g N−p o i n t FFT %
3 % ========================================================= %
4 clear ; clc ;
5 A=l o a d ( ’ c l k 1 m e g s i n e 1 0 2 4 . csv ’ ) ;
6 B=s i z e (A, 2 ) ;
7 A( : , B+1)=A( : , B−7)+A( : , B−6)∗2+A( : , B−5)∗4+A( : , B−4)∗8+A( : , B−3) ∗ 1 6 . . .
8 +A( : , B−2)∗32+A( : , B−1) ∗ 6 4 ;
9 A( : , 1 1 ) =(A( : , 1 0 ) / 1 2 8 ) ∗ . 6 − . 3 ;
10 c min=min (A( : , 1 1 ) ) ;
11 c max=max(A( : , 1 1 ) ) ;
12 nump=s i z e (A( : , 1 1 ) , 1 ) −111; % number o f FFT p o i n t s
13 %N =s i z e (A( : , 1 1 ) , 1 ) −111; % number o f FFT p o i n t s
14 N=2ˆ8;
15 f s = 10 e4 ; % sampling frequency
16 Ts = 1/ f s ;
17 t = 0 : Ts : ( N−1)∗Ts ; % s a m p l i n g time a r r a y
18 vout =[A( : , 1 ) A( : , 1 1 ) ] ;
19 vout ( 1 : 1 1 1 , : ) = [ ] ;
20 % −−−−−− S N R c a l c u l a t i o n −−−−−− %
21 vof = abs ( ( f f t ( vout ,N) ) ) /N;
22 vof = v o f /max( v o f ) ; % n o r m a l i z e t h e spectrum t o f u l l −s c a l e
23 v o f d b = db ( v o f ) ;
24 vofh = v o f ( 1 :N/ 2 ) ;
25 [ vs , i s ]= max( v o f h ( 1 :N/ 2 ) ) ;
26 Ps = vs ˆ 2 ; % fundamental s i g n a l power
27 Phar = norm ( v o f h ( 2 : i s −1) ) ˆ2 + norm ( v o f h ( i s +1:N/ 2 ) ) ˆ 2 ; % t o t a l
harmonic power
28 P n o i s e = norm ( v o f h ( f i n d ( db ( v o f h ) <−55) ) ) ˆ 2 ; % −60 i s s e t based on t h e
noise floor .
29 SQNR = 10∗ l o g 1 0 ( Ps/ P n o i s e )
30 SNDR = 10∗ l o g 1 0 ( Ps/ Phar )
31 NPWR = 10∗ l o g 1 0 ( Phar ) ;
32 freq = 0 : f s /N : ( f s /2 − f s /N) ;
33 f i g u r e ( 2 ) , H = p l o t ( f r e q ∗1 e −3, v o f d b ( 1 :N/ 2 ) , ’ k − ’) ;
34 g r i d on ;

92
Bibliography

[1] W. Kester, “The data conversion handbook,” 2005.

[2] F. Maloberti, “Data converters,” 2007.

[3] M. Boris. A/d converter figures of merit and performance trends.

[Online]. Available: https://courses.edx.org/c4x/IEEEx/ISSCCx/asset/
ISSCCx-2015-Murmann.pdf

[4] I. Ahmed, Pipelined ADC Design and Enhancement Techniques. Springer,

2010.

[5] D. Johns and K. Martin, Analog Integrated Circuit Design. John Wiley &
Sons, 1997.

[6] J. McNeill, M. Coln, and B. Larivee, “A split-adc architecture for deterministic

digital background calibration of a 16b 1 MS/s adc,” IEEE Journal of Solid-
State Circuits, vol. 1, pp. 2437–2445, Feb 2005.

[7] M. Flynn, C. Donovan, and L. Sattler, “Digital calibration incorporating re-

dundancy of fash adcs,” IEEE Transactions on Circuits and Systems II: Ana-
log and Digital Signal Processing, vol. 50, no. 5, pp. 205–213, 2003.

[8] K. Uyttenhove and M. Steyaert, “Speed-power-accuracy tradeoff in high-speed

cmos adcs,” Circuits and Systems II: Analog and Digital Signal Processing,
IEEE Transactions on, vol. 49, no. 4, pp. 280–287, Apr 2002.

[9] L. Portmann and T. H. Meng, “Power-efficient metastability error reduction

in cmos flash a/d converters,” Solid-State Circuits, IEEE Journal of, vol. 31,
no. 8, pp. 1132–1140, Aug 1996.

[10] R. H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Jour-

nal on Selected Areas in Communications, vol. 17, no. 4, pp. 539–550, 1999.

[11] P. Sunghyun and M. P. Flynn, “Design techniques for high performance cmos
flash analog-to-digital converters,” in Proceedings of the 2005 European Con-
ference on Circuit Theory and Design, vol. 1, 2005, Conference Proceedings,
pp. I/131–I/134 vol. 1.

93
[12] P. C. S. Scholtens, D. Smola, and M. Vertregt, “Systematic power reduction
and performance analysis of mismatch limited adc designs,” in Proceedings
of the 2005 International Symposium on Low Power Electronics and Design
(ISLPED), 2005, Conference Proceedings, pp. 78–83.
[13] M. Scott, B. Boser, and K. Pister, “An ultralow-energy adc for smart dust,”
IEEE Journal ofSolid-State Circuits,, vol. 38, no. 7, pp. 1123–1129, July 2003.
[14] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching
properties of mos transistors,” IEEE Journal of Solid-State Circuits,, vol. 24,
no. 5, pp. 1433–1439, 1989.
[15] A. S. Nastase. (2010, March) An adc and dac least significant
bit (lsb). [Online]. Available: http://masteringelectronicsdesign.com/
an-adc-and-dac-least-significant-bit-lsb/
[16] C. Man. Mt-229 mini tutorial,quantization noise: An expanded derivation of
the equation, snr = 6.02 n + 1.76 db, analog devices. [Online]. Available:
http://www.analog.com/static/imported-files/tutorials/MT-229.pdf
[17] J.-L. Huang, X.-L. Huang, Y.-F. Chou, and D.-M. Kwai, “A sar adc missing-
decision level detection and removal technique,” in VLSI Test Symposium
(VTS), 2012 IEEE 30th, April 2012, pp. 31–36.
[18] R. Majidi, A. Crasso, and J. A. McNeill, “Digital background calibration of
redundant split-flash adc in 45nm cmos,” in IEEE International Symposium
on Circuits and Systems (ISCAS), 2012, Conference Proceedings, pp. 1271–
1274.
[19] D. Daly and A. Chandrakasan, “A 6-bit, 0.2 v to 0.9 v highly digital flash adc
with comparator redundancy,” IEEE Journal of Solid-State Circuits, vol. 44,
no. 11, pp. 3030–3038, Nov 2009.
[20] G. Keskin, J. Proesel, J. O. Plouchart, and L. Pileggi, “Exploiting combi-
natorial redundancy for offset calibration in flash adcs,” IEEE Journal of
Solid-State Circuits, vol. 46, no. 8, pp. 1904–1918.
[21] W. Hu, Y.-T. Liu, T. Nguyen, D. Lie, and B. Ginsburg, “An 8-bit single-ended
ultra-low-power sar adc with a novel dac switching method and a counter-
based digital control circuitry,” IEEE Transactions on Circuits and Systems
I: Regular Papers, vol. 60, no. 7, pp. 1726–1739, July 2013.
[22] J. Hurwitz, “Layout - the other half of nanometer analog design,” 2011.
[23] R. Majidi, Low Power High Performance Successive Approximation Analog
to Digital Converter. University of Rochester. Department of Electrical and
Computer Engineering, Master Thesis, 2010.

94
[24] C. Enz and G. Temes, “Circuit techniques for reducing the effects of op-amp
imperfections: autozeroing, correlated double sampling, and chopper stabi-
lization,” Proceedings of the IEEE, vol. 84, no. 11, pp. 1584–1614, Nov 1996.
[25] M. Choi and A. Abidi, “A 6 b 1.3 gsample/s a/d converter in 0.35 /spl mu/m
cmos,” in IEEE International Solid-State Circuits Conference, 2001. Digest
of Technical Papers. ISSCC, Feb 2001, pp. 126–127.
[26] R. Taft, P. Francese, M. Tursi, O. Hidri, A. MacKenzie, T. Hohn, P. Schmitz,
H. Werker, and A. Glenny, “A 1.8 v 1.0 gs/s 10b self-calibrating unified-
folding-interpolating adc with 9.1 enob at nyquist frequency,” IEEE Journal
of Solid-State Circuits,, vol. 44, no. 12, pp. 3294–3304, Dec 2009.
[27] M. Frey and H.-A. Loeliger, “On the static resolution of digitally corrected
analog-to-digital and digital-to-analog converters with low-precision compo-
nents,” Circuits and Systems I: Regular Papers, IEEE Transactions on,
vol. 54, no. 1, pp. 229–237, Jan 2007.
[28] Y.-S. Shu, “A 6b 3gs/s 11mw fully dynamic flash adc in 40nm cmos with
reduced number of comparators,” in Symposium on VLSI Circuits (VLSIC),
June 2012, pp. 26–27.
[29] S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, and U.-K. Moon,
“Stochastic flash analog-to-digital conversion,” IEEE Transactions on Cir-
cuits and Systems I: Regular Papers,, vol. 57, no. 11, pp. 2825–2833, 2010.
[30] B. Ginsburg and A. Chandrakasan, “An energy-efficient charge recycling ap-
proach for a sar converter with capacitive dac,” in Circuits and Systems, 2005.
ISCAS 2005. IEEE International Symposium on, May 2005, pp. 184–187 Vol.
1.
[31] S. Haenzsche, S. Hoppner, and R. Schuffny, “A 10 bit 16 ms/s redundant sar
adc with flexible window function for a digitally controlled dc-dc converter in
28 nm cmos,” in NORCHIP, 2014, Oct 2014, pp. 1–4.
[32] Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yosh-
ioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda,
“Split capacitor dac mismatch calibration in successive approximation adc,”
in IEEECustom Integrated Circuits Conference,CICC, Sept 2009, pp. 279–282.
[33] J. A. McNeill, M. C. W. Coln, and B. J. Larivee, “’split adc’ calibration
for alldigital correction of time-interleaved adc errors,” IEEE Transactions on
Circuits and Systems II: EXPRESS BRIEFS, vol. 56, no. 5, pp. 344–348, 2009.
[34] S. Park, Y. Palaskas, and M. Flynn, “A 4-gs/s 4-bit flash adc in 0.18 μ m
cmos,” IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1865–1872,
Sept 2007.

95
[35] S. Timmy and A. Alvandpour, “A 6-bit 2.5-gs/s ash adc using comparator
redundancy for low power in 90 nm cmos,” Analog Integrated Circuits and
Signal Processing 2010, vol. 64.

[36] H. Chung, A. Rylyakov, Z. T. Deniz, J. Bulzacchelli, G.-Y. Wei, and D. Fried-

man, “A 7.5-gs/s 3.8-enob 52-mw flash adc with clock duty cycle control in
65nm cmos,” in IEEE Symposium on VLSI Circuits, 2009, June 2009, pp.
268–269.

[37] S. Weaver, B. Hershberg, D. Knierim, and U.-K. Moon, “A 6b stochastic flash

analog-to-digital converter without calibration or reference ladder,” in Solid-
State Circuits Conference, 2008. A-SSCC ’08. IEEE Asian, Nov 2008, pp.
373–376.

[38] S. Park, Y. Palaskas, A. Ravi, R. Bishop, and M. Flynn, “A 3.5 gs/s 5-b flash
adc in 90 nm cmos,” pp. 489–492, Sept 2006.

[39] K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, “A 6-bit 3.5-gs/s

0.9-v 98-mw flash adc in 90nm cmos,” in IEEE Symposium on VLSI Circuits,
June 2007, pp. 64–65.

[40] S. Weaver, B. Hershberg, and U.-K. Moon, “Digitally synthesized stochastic

flash adc using only standard digital cells,” IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 61, no. 1, pp. 84–91, 2014.

[41] P. Veldhorst, G. Goksun, A.-J. Annema, B. Nauta, B. Buter, and M. Vertregt,

“A 0.45pj/conv-step 1.2gs/s 6b full-nyquist non-calibrated flash adc in 45nm
cmos and its scaling behavior,” in ESSCIRC, 2009. ESSCIRC ’09. Proceedings
of, Sept 2009, pp. 464–467.

[42] M. Choi, J. Lee, J. Lee, and H. Son, “A 6-bit 5-gsample/s nyquist a/d con-
verter in 65nm cmos,” in VLSI Circuits, 2008 IEEE Symposium on, June
2008, pp. 16–17.

[43] J. Lee, J. Weiner, P. Roux, A. Leven, and Y.-K. Chen, “A 24gs/s 5-b adc with
closed-loop tha in 0.18m sige bicmos.” in IEEE Custom Integrated Circuits
Conference CICC, 2008, pp. 313–316.

[44] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas,

“A 2.2 mw 1.75 gs/s 5 bit folding flash adc in 90 nm digital cmos,” Solid-State
Circuits, IEEE Journal of, vol. 44, no. 3, pp. 874–882, March 2009.

[45] V.-C. Chen and L. Pileggi, “An 8.5mw 5gs/s 6b flash adc with dynamic offset
calibration in 32nm cmos soi,” in Symposium on VLSI Circuits (VLSIC), June
2013, pp. C264–C265.

96
[46] P. C. Scholtens and M. Vertregt, “A 6-b 1.6-gsample/s flash adc in 0.18-μm
cmos using averaging termination,” IEEE Journal of Solid-State Circuits,,
vol. 37, no. 12, pp. 1599–1609, 2002.

[47] P. Nuzzo, G. Van der Plas, F. De Bernardinis, L. Van der Perre, B. Gy-
selinckx, and P. Terreni, “A 10.6mw/0.8pj power-scalable 1gs/s 4b adc in
0.18/spl mu/m cmos with 5.8ghz erbw,” in Design Automation Conference,
2006 43rd ACM/IEEE, 2006, pp. 873–878.

[48] B. Verbruggen, P. Wambacq, M. Kuijk, and G. Van der Plas, “A 7.6 mw 1.75
gs/s 5 bit flash a/d converter in 90 nm digital cmos,” in IEEE Symposium on
VLSI Circuits, June 2008, pp. 14–15.

[49] C.-Y. Chen, M. Le, and K. Y. Kim, “A low power 6-bit flash adc with reference
voltage and common-mode calibration,” IEEE Journal of Solid-State Circuits,,
vol. 44, no. 4, pp. 1041–1046, April 2009.

[50] Y.-Z. Lin, C.-W. Lin, and S.-J. Chang, “A 2-gs/s 6-bit flash adc with offset
calibration,” in IEEE Asian Solid-State Circuits Conference,A-SSCC, Nov
2008, pp. 385–388.

[51] M. Boris. Adc performance survey 1997-2014,. [Online]. Available: http:

//web.stanford.edu/∼murmann/adcsurvey.html

[52] H.-C. Hong and G.-M. Lee, “A 65-fj/conversion-step 0.9-v 200-ks/s rail-to-rail
8-bit successive approximation adc,” IEEE Journal of Solid-State Circuits,,
vol. 42, no. 10, pp. 2161–2168, Oct 2007.

[53] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, “A

12fj/conversion-step 8bit 10ms/s asynchronous sar adc for low energy radios,”
in ESSCIRC, 2010 Proceedings of the, Sept 2010, pp. 214–217.

[54] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and

B. Nauta, “A 1.9 μw 4.4fj/conversion-step 10b 1ms/s charge-redistribution
adc,” in IEEE International Solid-State Circuits Conference, 2008. ISSCC
2008. Digest of Technical Papers, Feb 2008, pp. 244–610.

[55] A. Agnes, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-enob 1v 3.8 μw

100ks/s sar adc with time-domain comparator,” in IEEE International Solid-
State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers, Feb
2008, pp. 246–610.

[56] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mw 10-bit 50-
ms/s sar adc in 0.13 μm cmos process,” in VLSI Circuits, 2009 Symposium
on, June 2009, pp. 236–237.

97
[57] P. Nuzzo, C. Nani, C. Armiento, A. Sangiovanni-Vincentelli, J. Craninckx,
and G. Van der Plas, “A 6-bit 50-ms/s threshold configuring sar adc in 90-nm
digital cmos,” Circuits and Systems I: Regular Papers, IEEE Transactions on,
vol. 59, no. 1, pp. 80–92, Jan 2012.

[58] J. J. Kang and M. Flynn, “A 12b 11ms/s successive approximation adc with
two comparators in 0.13 μm cmos,” in Symposium on VLSI Circuits, 2009,
June 2009, pp. 240–241.

[59] R. Lotfi, R. Majidi, M. Maymandi-nejad, and W. Serdijn, “An ultra-low-

power 10-bit 100-ks/s successive-approximation analog-to-digital converter,”
in IEEE International Symposium on Circuits and Systems, 2009. ISCAS,
May 2009, pp. 1117–1120.

[60] W. Liu, P. Huang, and Y. Chiu, “A 12b 22.5/45ms/s 3.0mw 0.059mm2 cmos
sar adc achieving over 90db sfdr,” in IEEE International Solid-State Circuits
Conference Digest of Technical Papers (ISSCC), Feb 2010, pp. 380–381.

[61] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10b 50ms/s

820 μw sar adc with on-chip digital calibration,” in IEEE International Solid-
State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2010, pp.
384–385.

[62] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, C.-H. Huang,
L. Bu, and C.-C. Tsai, “A 10b 100ms/s 1.13mw sar adc with binary-scaled
error compensation,” in IEEE International Solid-State Circuits Conference
Digest of Technical Papers (ISSCC), Feb 2010, pp. 386–387.

[63] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-ms/s sar adc
with a monotonic capacitor switching procedure,” IEEE Journal of Solid-State
Circuits,, vol. 45, no. 4, pp. 731–740, April 2010.

[64] H. Wei, C.-H. Chan, U.-F. Chio, S.-W. Sin, U. Seng-Pan, R. Martins, and
F. Maloberti, “A 0.024mm2 8b 400ms/s sar adc with 2b/cycle and resistive
dac in 65nm cmos,” in Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2011 IEEE International, Feb 2011, pp. 188–190.

[65] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5v 1.1ms/sec

6.3fj/conversion-step sar-adc with tri-level comparator in 40nm cmos,” in
VLSI Circuits (VLSIC), 2011 Symposium on, June 2011, pp. 262–263.

[66] B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq, and J. Craninckx,

“A 70db dr 10b 0-to-80ms/s current-integrating sar adc with adaptive dy-
namic range,” in Solid-State Circuits Conference Digest of Technical Papers
(ISSCC), 2012 IEEE International, Feb 2012, pp. 470–472.

98
[67] H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2fj/c.-s. 0.35v 10b 100ks/s sar
adc in 90nm cmos,” in VLSI Circuits (VLSIC), 2012 Symposium on, June
2012, pp. 92–93.

[68] Y.-C. Lien, “A 4.5-mw 8-b 750-ms/s 2-b/step asynchronous subranged sar adc
in 28-nm cmos technology,” in VLSI Circuits (VLSIC), 2012 Symposium on,
June 2012, pp. 88–89.

[69] K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A

0.0058mm2 7.0 enob 24ms/s 17fj/conv. threshold configuring sar adc with
source voltage shifting and interpolation technique,” in VLSI Circuits (VL-
SIC), 2013 Symposium on, June 2013, pp. C266–C267.

[70] M. Yip and A. Chandrakasan, “A resolution-reconfigurable 5-to-10b 0.4-to-1v

power scalable sar adc,” in Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), 2011 IEEE International, Feb 2011, pp. 190–192.

[71] F. Yaul and A. Chandrakasan, “A 10b 0.6nw sar adc with data-dependent
energy savings using lsb-first successive approximation,” in IEEE Internationa
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2014,
pp. 198–199.

[72] M. Inerfield, A. Kamath, F. Su, J. Hu, Y. Xinyu, V. Fong, O. Alnaggar,

F. Lin, and T. Kwan, “An 11.5-enob 100-ms/s 8mw dual-reference sar adc in
28nm cmos,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium
on, June 2014, pp. 1–2.

[73] J. McNeill, M. Coln, and B. Larivee, “”split adc” architecture for deterministic
digital background calibration of a 16-bit 1 ms/s adc,” IEEE Journal of Solid-
State Circuits,, vol. 40, no. 12, pp. 2437–2445, Dec 2005.

[74] J. McNeill, C. David, M. Coln, and R. Croughwell, “’split adc’ calibration

for all-digital correction of time interleaved adc errors,,” IEEE Transactions
on Circuits and Systems II: Express Briefs,, vol. 56, no. 5, pp. 344–348, May
2009.

[75] J. McNeill, C. David, M. Coln, and K. Y. Chan, “Split adc background self-
calibration of a 16-b successive approximation adc in 180nm cmos,” in In-
strumentation and Measurement Technology Conference (I2MTC), 2013 IEEE
International, May 2013, pp. 310–313.

[76] N. Petrellis, M. Birbas, J. Kikidis, and A. Birbas, “Calibration method for a

cmos 0.06mm2 150ms/s 8-bit adc,” in Digital System Design, Architectures,
Methods and Tools, 2009. DSD ’09. 12th Euromicro Conference on, Aug 2009,
pp. 191–195.

99
[77] Y. Nakajima, A. Sakaguchi, T. Ohkido, N. Kato, T. Matsumoto, and
M. Yotsuyanagi, “A background self-calibrated 6b 2.7 gs/s adc with cascade-
calibrated folding-interpolating architecture,” Solid-State Circuits, IEEE
Journal of, vol. 45, no. 4, pp. 707–718, April 2010.

[78] J. McNeill, M. Coln, and B. Larivee, “A split-adc architecture for deterministic

digital background calibration of a 16b 1 ms/s adc,,” in IEEE International
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC, Feb
2005, pp. 276–598 Vol. 1.

[79] J. McNeill, S. Goluguri, and A. Nair, “”split-adc” digital background cor-

rection of open-loop residue amplifier nonlinearity errors in a 14b pipeline
adc,,” in IEEE International Symposium on Circuits and Systems, 2007. IS-
CAS 2007., May 2007, pp. 1237–1240.

[80] J. Li and U.-K. Moon, “Background calibration techniques for multistage

pipelined adcs with digital redundancy,,” IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing,, vol. 50, no. 9, pp. 531–538,
Sept 2003.

[81] T. Strohmer and J. Xu, “Fast algorithms for blind calibration in time-
interleaved analog-to-digital converters,” in IEEE International Conference
on Acoustics, Speech and Signal Processing, 2007. ICASSP 2007, vol. 3, April
2007, pp. III–1225–III–1228.

[82] J. McNeill, K. Y. Chan, M. Coln, C. David, and C. Brenneman, “All-digital

background calibration of a successive approximation adc using the ’split adc’
architecture,” IEEE Transactions on Circuits and Systems I: Regular Papers,,
vol. 58, no. 10, pp. 2355–2365, Oct 2011.

[83] C. Donovan and M. Flynn, “A ”digital” 6-bit adc in 0.25- mu;m cmos,” Solid-
State Circuits, IEEE Journal of, vol. 37, no. 3, pp. 432–437, Mar 2002.

[84] A. Crasso, ”Background Calibration of a 6-Bit 1Gsps Split-Flash ADC”.

Worcester Polytechnic Institute, Master Thesis, January 2013.

[85] L. Sumanen, M. Waltari, V. Hakkarainen, and K. Halonen, “Cmos dynamic

comparators for pipeline a/d converters,” in Circuits and Systems, 2002. IS-
CAS 2002. IEEE International Symposium on, vol. 5, 2002, pp. V–157–V–160
vol.5.

[86] P. Nuzzo, F. De Bernardinis, P. Terreni, and G. Van der Plas, “Noise analysis
of regenerative comparators for reconfigurable adc architectures,” Circuits and
Systems I: Regular Papers, IEEE Transactions on, vol. 55, no. 6, pp. 1441–
1454, July 2008.

100
 [87] L. Sumanen, M. Waltari, V. Hakkarainen, and K. Halonen, “Cmos dynamic
comparators for pipeline a/d converters,” in Circuits and Systems, 2002. IS-
CAS 2002. IEEE International Symposium on, vol. 5, 2002, pp. V–157–V–160
vol.5.
[88] W. Evan, E. Naviasky, H. Tang, B. Allison, and J. Matsuzaki.
Comparator metastability analysis. [Online]. Available: www.designers-guide.
org/analysis/metastability.pdf
[89] Y. Huang, H. Schleifer, and D. Killat, “Design and analysis of novel dynamic
latched comparator with reduced kickback noise for high-speed adcs,” in Cir-
cuit Theory and Design (ECCTD), 2013 European Conference on, Sept 2013,
pp. 1–4.
[90] K.-C. Kuo and C.-W. Wu, “Capacitive dynamic comparator with low kickback
noise for pipeline adc,” in Electron Devices and Solid-State Circuits (EDSSC),
2013 IEEE International Conference of, June 2013, pp. 1–2.
[91] Y. Ho, Y. Hsu, C. Lan, Y. Tsai, C. Chen, S. Horng, Y. Fang, T. Hu, C. Liu,
J. Huang, and W. Yeh, “Mis-matching characteristics study of p+-poly-silicon
resistor in newly cmos process technology,” in Electron Devices and Solid-State
Circuits, 2007. EDSSC 2007. IEEE Conference on, Dec 2007, pp. 1133–1137.
[92] K. Uyttenhove and M. Steyaert, “A 1.8-v 6-bit 1.3-ghz flash adc in 0.25- mu;m
cmos,” Solid-State Circuits, IEEE Journal of, vol. 38, no. 7, pp. 1115–1122,
July 2003.
[93] B. Razavi, “Design of analog cmos integrated circuits,” 2001.
[94] E. Sail and M. Vesterbacka, “A multiplexer based decoder for flash analog-
to-digital converters,” in TENCON 2004. 2004 IEEE Region 10 Conference,
vol. D, Nov 2004, pp. 250–253 Vol. 4.
[95] Linear regulators. [Online]. Available: http://www.linear.com/product/
LT3080
[96] Low distortion differential adc driver. [Online]. Available: http://www.
analog.com/media/en/technical-documentation/data-sheets/AD8138.pdf
[97] Triple inverter. [Online]. Available: http://www.onsemi.com/pub link/
Collateral/NL37WZ04-D.PDF
[98] J. Patoux.
[99] H. Zumbahlen, Linear Circuit Design Handbook. Elsevier, 2008.
[100] Flexible mixed-signal simulation for socs. [Online]. Available: http:
//www.cadence.com/products/cic/ams designer/pages/default.aspx

101
[101] W. Hu, D. Lie, and Y.-T. Liu, “An 8-bit single-ended ultra-low-power sar adc
with a novel dac switching method,” in Circuits and Systems (ISCAS), 2012
IEEE International Symposium on, May 2012, pp. 2349–2352.

[102] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and

B. Nauta, “A 10-bit charge-redistribution adc consuming 1.9 μ w at 1 ms/s,”
Solid-State Circuits, IEEE Journal of, vol. 45, no. 5, pp. 1007–1015, May 2010.

[103] Z. Zeng, C.-S. Dong, and X. Tan, “A 10-bit 1ms/s low power sar adc for rssi
application,” in Solid-State and Integrated Circuit Technology (ICSICT), 2010
10th IEEE International Conference on, Nov 2010, pp. 569–571.

[104] N. Verma and A. Chandrakasan, “An ultra low energy 12-bit rate-resolution
scalable sar adc for wireless sensor nodes,” Solid-State Circuits, IEEE Journal
of, vol. 42, no. 6, pp. 1196–1205, June 2007.

102