International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)

Performance Analysis of Low Power 6T SRAM Cell

in 180nm and 90nm
C Ashok Kumar1, Dr B K Madhavi2, Dr K Lalkishore3
1
Department of ECE, CMR Engineering College Hyderabad, Telangana State, India.
cheelikumar@gmail.com
2
Department of ECE, Sridevi Women Engineering College Hyderabad, Telangana State, India.
bkmadhavi2009@gmail.com
3
Department of ECE, JNTU Anantapur, Andhra Pradesh, India.

Abstract--The memories are more and more used as an

embedded element rather as a separate block. Being used
as a macro, its user has nothing to change or optimize. So,
the design of memory needs to address all the issues
specially to optimize the rigorous area and power
requirements. This paper discusses the issues in design of
SRAM memory cell for low power applications. 6T
architecture SRAM cell is taken as a reference model
which is designed using 180nm technology. The power,
area and speed is estimated. The cell is designed using
90nm technology and is used in 8K memory. The
performances of the memory in 180nm and 90 nm Fig. 1.1 – Functional SRAM Chip Model
technology is compared and analyzed for area, power and
speed. The design is simulated using cadence virtuoso for
schematic entry and layout. For comparison microwind is A. Operation of SRAM Cell
used for analysis and performance comparison. The
results clearly indicate that as we migrate from 180nm to
90nm technology power reduces and speed increases on a
single SRAM bitcell. The results have been verified using
BSIM3 model files, simulated at 27 degree centigrade
setting appropriate voltages.

Index Terms- Bitcell, low power, 8Kb memory, performance

analysis, SRAM.
I. INTRODUCTION
The address receives by address latch block. The
higher order bits of the address are connected to the row
decoder, that selects a row in the memory cell array. The
lower order address bits go to the column decoder, which
selects the required columns.
The contents of the selected cells in the memory cell
array are amplified by the sense amplifiers for a read
operation, loaded in the data register & presented on the data-
out line(s). The data on the data-in line(s) are loaded into the
data register during write operation & written in to the
memory cell array by the write driver.Normally the data-in &
data-out lines are grouped to form bidirectional data lines,
there by reducing the number of pins on the chip. The chip-
select line enables the data register,along with read/write line,
the write driver.
Fig. 1.2 – 6T SRAM Cell [2]
SRAM memory cells area unit supported the latch
structure with 2 consecutive connected inverters & 2 pass
transistors. Knowledge are often written by driving WL high
& driving the lines BL & ~BL with knowledge with
complementary values. as a result of the bit lines area unit
driven with additional force than the force with that the cell
retains its information (the transistors driving the lines BL
& ~BL area unit additional powerful, i.e. these area unit
larger than the NMOS of inverters), the cell are forced to the
state conferred on the lines BL & ~BL. within the scan
operation, a the row is chosen by activating the corresponding
WL. The contents of the cell on a row, accessed by the
activated WL, area unit passed to the corresponding sense
amplifiers via the BL & ~BL lines. the information
register is loaded by choosing the outputs of the required sense
amplifiers in check of the column decoder.

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 International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)
B. Design of SRAM Cell
The SRAM cell is designed symmetrically, but the transistors
need to be sized cautiously for proper read and write
operations. The required performance of good read and write
stability is to be achieved with minimized area. The read
operation is ensured with proper ratio between pull-down (PD)
and pass gate (PG) transistors. Also, write stability is
confirmed by proper ratio between pass gate and pull-up (PU)
transistors [2, 4].
C. Schematic of SRAM Cell and its Simulation
The sizes of the SRAM transistors are selected for proper sizes
(as described in [2]) for 0.18μ technology and the results are
simulated using Spectre. It was found that the size could be
tuned to be reduced to still achieve the figure of merit for read
and write operations. The sizes finalized are PU=0.66μ/0,18μ,
PD=1.20μ/0.18μ and PG=0.60μ/0.18μ. The schematic is
made using Virtuoso Schematic Editor (VSE) is shown in Fig.
1.3. The simulation results for write‘1’ operation is shown in
Fig. 1.4a.
Fig. 1.3 – SRAM Cell Schematic [3]
Fig. 1.4 – SRAM Cell Simulation and Layout
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D. Layout Design for SRAM Cell and its Verification
The layout of SRAM cell is made in symmetrically to
match the design for both the halves of the memcell, using
Virtuoso Layout Editor (VLE) and Virtuoso XL (VXL). The
node which can be easily shared with the adjacent cell i.e.
wordline horizontally and Gnd/Bitline vertically; are taken at
edges. The wordline and Gnd is in Metal3 horizontally, and
Bitlines, Vdd and Gnd are in Metal2 vertically. The substrate
connections are not provided in the basic cell to keep the area
utilization the maximum. A dense memcell with X=6.94μ and
Y=2.03μ as shown in Fig.1.4b is made. Placing strap
separately, the cell is validated for DRC violations and is also
verified for LVS using Assura. The layout is found to be DRC
and LVS clean.
E.Parasitic values for SRAM Cell
RC Extraction is done on the LVS clean database of the
SRAM using Assura. This step provides the av_extracted
view for the cell. In the view the parasitic resistances and
capacitances are added to the schematic. The combinational
view comprises of metallization with related parasitic values
and the devices represented with the related symbols. The
netlist is exported from this view to get the capacitances on
wordline and bitline.
 Capacitance on Wordline in reference to Gnd :
275.9e-18 F.
 Capacitance on Bitline in reference to Gnd : =
483e-18 F.
To get more accurate values of the capacitances on
wordline and bitline, especially to reduce the effects of fringe
capacitances, the capacitance is extracted from the SRAM
array and divided for each cell, also providing proper isolation
at the edges to reduce fringe capacitances.
II. 4x4 SRAM ARRAY
The SRAM cells are placed together in 4 rows and 4
columns to get a 4x4 array. For all cells in each row, the
wordline is same and similarly bitline is common for a
complete column. In layout the adjacent placements of SRAM
cells are flipped horizontally and vertically so that the
common nodes are shared easily and targeted area density is
achieved. The schematic and layouts are shown in Fig.1.5 &
1.6. The layout array does not have any bulk connection in it.
 International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)

connection with the core, it also provides the required strap

connections to the SRAM core. Its details are shown in Fig
1.7.

Fig.1.5 – 4x4 Array of SRAM Cells : Schematic and

Fig.1.7 – Schematic, Simulation Results and Layout for
Simulation Results
Precharge Logic

B.Sense Amplifier

During read operation, after the precharge, either of

bitline or ~bitline drops and the voltage difference between the
two is sensed by the sense amplifier. Depending on the drop
on the rail, the stored data is being read. The layout is made in
a way that the bit and ~bit nets remain matched w.r.t.
environments. The layout is also provided with a Guard Ring
to shield the sensitive logic from external noises. Details of
sense amplifier are shown in Fig.1.8.

Fig.1.6 – Layout for 4x4 Array of SRAM Cells

III. Periphery Logic Design

Although SRAM cell array is the main storage area
for storing the data, but it requires extra circuit logic to be
operated. This is called Periphery Logic. The various
periphery circuits are referred from [5], and the relative sizing
is done using logical efforts. These individual blocks are
described ahead with related layouts and simulation results.

A.Precharge Circuit
For both read and write operations the bitline and Fig.1.8 – Schematic, Simulation Results and Layout for
~bitline are required to be precharged to Vdd. This circuit Sense Amplifier
provides a switching for precharge. The precharge circuit
continues to match the bit and ~bit signals. Being in adjacent

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 International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)

C.Write Logic write operation the data from the write logic is transferred to
After the precharge, the data is to be forced at bitline be written to the memory. The details of the IO control logic is
and ~data on ~bitline for the write operation.The data from the used as shown in Fig.1.11.
port was read by write circuit and on receiving the write
enable signal, write operation was performed. Write logic’s
details are provided in Fig.1.9.

Fig.1.11 – Schematic and Layout for IO Control Logic

IV. COMPLETE SRAM CHIP INTEGRATION

Fig.1.9 – Schematic, Simulation Results and Layout for
Write Logic
D.Row Decoder
For the memory operation, the row decoder decodes
the high order address lines to select which wordline is to be
activated. A simple NOR-based decoder used as shown in Fig.
1.10.
When all the individual blocks are ready and validated,
these all need to be integrated to one complete chip. Care is to
be taken that signals match properly at each interface. The
power connections from all the individual blocks need to be
connected so that there is only one net for power and ground.
Only the required pins are promoted at the top level of the
chip.
A.Schematic for SRAM Chip & its Simulation
The schematic of the complete SRAM chip is shown
in the Fig.1.12a. The blocks are being taken into some mid-
level hierarchy especially for the core to reduce the
complexities in viewing a cumbersome net connects in a
schematic arena. The simulation result for the complete
memory write ‘1’ operation is also shown in Fig.1.12b.

Fig.1.10 – Schematic, Simulation Results and Layout for

Row Decoder

E.IO Control Logic

For the memory operation, particular column of
operation is also to be selected. A simple NOR-based decoder
together with controlled NMOS switches is used to make it Fig.1.12 – Schematic and Simulation Results for the
function like a multiplexer. While read operation the data from SRAM Chip
memory is transferred to the sense amplifier while during

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 International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)
B.Layout for SRAM Chip & its Validation
The Fig.1.12 shows the validated layout for the
complete SRAM chip. All the individual blocks being made in
consent with the abutment of the related cells, the technique
helped in reduced efforts in validation of the complete circuit.
As shown in Fig.1.13, the memory is limited up to Metal3. All
the signal and power pins are provided in Metal2 only. It has
X=40.5μm and Y=22.4μm which gives an area of 907.2μm2.
Fig.1.13.Validated Layout for the SRAM Chip
V. 90nm SRAM DESIGN
The layout and schematic design for 90nm SRAM is
shown in Fig.1.14..From the full chip layout view of a 8Mb
memory,it was observed that the total memory is seperated
into two 4Mb memory cuts created using stacked SRAM bit
cells of a single column, and several such columns are formed
(64 columns for 4Mb memory cut) to compose a 4Mb
memory cut and combining two such cuts, a 8Mb memory is
built. The decoder section consists of decoding logics excuted
in a tree structure and control block supplied with precoded
signal to sustain circuit-partitioning technique.
Fig.1.14.Full Chip Layout level view of 8Mb SRAM
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A. Characterization of 90nm SRAM bitcell
The characterization of cells determines variety of
cell attributes like propagation delays, output transition times,
run power, shift power, input pin capacitance's in dynamic
and standby modes.
The SRAM bit cell is characterised for largely
power, transition and delay times beside determination of
static noise margin of SRAM bit cell. The SNM is decided
from simulation by applying the voltage on one in every of
the inner nodes of the cell from ground to the power supply
and recording the response of the opposite node . The setup of
the simulation ought to be made with the worst-case contact
resistances, together with the cell’s ground path. repetition the
measuring with the opposite facet to come up with 2 electrical
converter transfer curves, which may be overlaid along on a
similar graph with one curve on the coordinate axis and
therefore the different on the coordinate axis. This diagram is
named as “Butterfly” curve for the memory cell as shown
within the below Fig.1.15
Fig.1.15.Butterfly Structure for SRAM
Fig.1.16.Operation of SRAM Circuit.
From the Figure one.16, it had been ascertained that the
dynamic operation of SRAM circuit depends upon the inputs
that require to be keep. Here AN input pulse is given as AN
input and therefore the output transitions, delay and dynamic
power are measured victimization Hspice simulations.
Fig.1.17.Bitline Voltage Swings
 International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)

For the dynamic operational mode, the information

content keep within the 6T SRAM is retrieved throughout the Table 1. Dynamic Characteristics of SRAM Bitcell
scan operation. If it’s a zero keep within the bitcell, then the
potential swing are reducing to 916mV as shown in Fig.1.17. Symbol Parameter Conditions Value
If a ‘0’ is keep within the SRAM bitcell, the precharged tphl Propagation delay 1.2 V 5.6596E-11
potential ‘Vdd’ flows to the bitcell, this reduces the bitline from high to low seconds
voltages by few 100mV. tplh Propagation delay 1.2 V 7.8503E-11
from low to high seconds
tf Fall time 1.2 V 1.6596E-11
seconds
tr Rise time 1.2 V 1.3453E-11
seconds
Ppeak Peak Power 1.2 V 3.3704E-
04watts
VI. PERFORMANCE COMPARISION OF 6T SRAM
In this section, 6T SRAM cell designed using both
180nm and 90nm cell is compared for its performances. The
results of comparison is discussed and analyzed. Fig 1.21
shows the simulation results of 1-bit SRAM cell. The data line
Fig.1.18 Leakage current in Standby mode feeds the inputs high and low in alternate cycle, the sel line
enables the memory cell and the mem line shows the results
The escape current is decided in standby mode, by stored and retrieved from the cell. Table 3 shows the
pruning ground path from the circuit, and 2 inputs a logic ‘1’ comparison of various parameters of the SRAM cell.
and ‘0’ area unit provided as input and currents at intermediate
nodes area unit measured and average of those values is taken
to search out the worth of escape current.

Fig.1.20.SRAM bit cell for 180 and 90nm

Fig.1.19.Dynamic Power Characteristics

The dynamic power characteristics for SRAM bit cell
(both Average power and Peak power) are observed by Hspice
simulations.
From the analysis, the peak-to-peak power of single bit
SRAM cell is decided that shows at most change and
parameters like, tphl, tplh, tr and tf are determined beneath
dynamic mode. when the SRAM bitcell characterization, the
standby power, is found to be 7.76 µW/bitcell and dynamic
power dissipated throughout change activity is found as
3.3704E-04W/bitcell. The results when performing arts the
characterization of one bit SRAM cell are mentioned within
the table one , that exhibit the dynamic characteristics.

Fig.1.21.Simulation results for 180nm and 90nm

technology SRAM bitcell

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 International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB16)

Table 3 comparison of 180nm and 90nm SRAM bit cell

Dynamic power Management
S. Parameters 180nm 90nm Remarks Use memory banking (Using multi-core architectures)
no Split large memory into little memories
01 Area 3.120ux3.120u 2.85ux2.85u Obviously Use twin rail i.e. separate peripery and array power supply
the cell area Standby Power Management
reduces Power gating –External and Integrated
with change Periphery shut down with data retention
in Complete shut down
technology Fine-grained power gating
Source biasing
02 tr 13ps 5ps Due to
Utilizing higher threshold voltage devices helps leakage
minimum
03 tf 23ps 8ps current reduction. Improved periphery circuits and reduced
amount of
operating voltage results in AC & DC Current reduction [6].
parasitics
VII. CONCLUSIONS
the rise
The operation of SRAM is studied in detail from the
timeand fall
cell level to the complete block including all the periphery
time are
circuits. This has provided a thorough understanding of its
low
operation. The design of schematics, its simulation and layout
04 Power 0.462uW 0.301uW Dynamic
design provided a great exposure to the tool in addition to the
power is
learning of the under lying fundamentals.
reduced
Efforts have been made in optimizing the layout for
with scaling
best area and power utilization. In most cases layouts are been
in
made with re-usability, so that the same layout repeats for
technology
each related schematic instance. The lots of area available has
due to low
been efficiently used for strengthening the bulk supply.
power
Considerations are taken to have a good power mesh all over
concepts
the memory. All the devices getting a connection from an
05 Idmax 0.256mA 0.168mA Due to
external pin are placed near the pin itself. Thus, SRAM chip
reduction in
layout is optimized w.r.t. various industry techniques.
geometries,
I is directly
VIII. REFERENCES
proportional
to width,
[1] Betty Prince, Semiconductor Memories: A Handbook of
hence
Design, Manufacture and Application, 2nd edition, John Wiley
current is
& Sons, Inc.
reduced
[2] David A Hodges, Resve Saleh, Horace G. Jackson,
06 VDD(Core) 2.0V 1.0V Constant Analysis and Design of Digital Integrated Circuits, 3rd
field scaling edition, McGraw Hill Inc.
is used to [3] Sung-Mo Kang, Yusuf Leblebici, CMOS Digital
reduce Integrated Circuits – Analysis and Design, 3rd ed., Tata
power McGraw Hill
07 VDD(I/O) 3.3V 2.5V Driving [4] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic,
current is Digital Integrated Circuits, 2nd ed, Pearson Education, Inc. [5]
high to have http://www.cedcc.psu.edu/khanjan/vlsispec.htm (last accessed
high fanout on 17-01-2008)
08 Temp 27○ C 27○ C Typical [6] Anuj, Investigation and Analysis of the Deep Sub-Micron
temperature Static Ram Architectures – IETE Project, February 2006.
[7] Vipin Tiwari, Memory Design Challenges in Nanometer
A.Recommendations for low power operation Era, Virage Logic Corporation, 2007.
The SRAM memories have experience changes with
respect to increased transistor density, decrease in geometric
cell size and high frequency. An extreme amount of power [6]
will be consumed by such circuits. The following techniques
can be implemented for low power operation of SRAM
memories [7]:

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