IIT BH DNC Lab EE Manual Expt 7

Control Unit
EE311
By
Dr. Sk Subidh Ali
Computer Datapath
MAR
Internal bus
IR R1 PC
ACC
R2
ALU
Instruction
Decoder
DR
Timing &
Control
Timing Signal
MOV R1, R2
Phases of instruction execution
OER2
• Instruction fetch
LDR1 • Instruction decode

• Instruction execute
Possible instructions
ADD R1 ACC ACC + R1
CMP ACC ACC
MVI SUB, MUL, DIV
ADI AND R1 ACC ACC ∧ R1
JMP NAND and all logical operation
MOV R1, R2 MOV R2, R1
MOV ACC, R MOV R, ACC
MOV ACC, M MOV M, ACC
Instruction Format
OpCode Operand
15 0
m-bit
There are two instruction groups

• Register reference
• Memory reference
Instruction Format
OpCode Operand
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
There are two instruction group

No operand address required
12 bits of operand can be used

to refer different register instructions
Instruction Format
OpCode Operand
1 1 1 0 0 0 0 0 0 0 0 0 0 0 1
I0 ADD R1 ACC ACC + R1


Instruction Format
OpCode Operand
1 1 1 0 0 0 0 0 0 0 0 0 0 1 0

There are two instruction group I1 CMP ACC ACC

Instruction Format
OpCode Operand
1 1 1 0 0 0 0 0 0 0 0 0 1 0 0

• Register reference I2 AND R1 ACC ACC ∧ R1

Instruction Format
OpCode Operand
0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0

• Register reference I2 AND R1 ACC ACC ∧ R1
• Memory reference I3 MOV R1,R2 R1 R2
I4 MOV R2,R1 R2 R1
No operand address required I5 MOV ACC,R1 ACC R1
I6 MOV R1, ACC R1 ACC
12 bits of operand can be used I7 MOV ACC,R2 ACC R2
to refer different register instructions I8 MOV R2, ACC R2 ACC
Instruction Format
OpCode Operand
0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1

0001 MOV ACC, [M] 001 0x234

0010 MOV [M], ACC 010 0x434
0011 JMP 011 0x123
12 bits of operand can be memory address

Instruction Format
OpCode Operand
0 0 1 0 1 1 0 0 1 0 0 0 1 0 1
There are two instruction group I15 can be used for immediate addressing
1001 MVI ACC, 0x02 1001 0x02

1010 ADI ACC, 0x23 1010 0x23
1011 0x03
1011 ANI ACC, 0x03
8 bits of operand can be taken for immediate value

Instruction Phases
T0: MAR<= PC
Instrn
T1: IR<= [MAR], PC<=PC+1
fetch
T2: DECD(IR), MAR<=IR11to0
T3: Depends on the instruction
Instruction Phases
ADD R1 : ACC<=ACC+R1
T0: MAR<= PC
MAR
Internal bus
T3: DR<= R1 IR R1 PC
ACC
R2
T4: ACC<= ALUADD(ACC, DR), T0 Instruction
Decoder
DR
Timing &
Control
Instruction Phases
MOV R1,R2 : R1<=R2
T0: MAR<= PC
MAR
Internal bus
T2: DECD(IR)
T3: R2<= R1 , T0 IR R1 PC
ACC
R2
Instruction
Decoder
DR
Timing &
Control
Instruction Phases
MOV ACC, [M] : ACC<=[M]
T0: MAR<= PC
MAR
Internal bus
T3: ACC<= M[MAR], T0 IR R1 PC
ACC
R2
Instruction
Decoder
DR
Timing &
Control
We need timing sequence and control signal

Control Hardware
IR
Decoder (4:16)
D15 D 1 D0
Timing
and
Control
Circuit
T15 T1 T0
Decoder (4:16)
Counter RST
INCR
4-bit CLK
Sequencer
Control Signals
ADD R1 : ACC<=ACC+R1
PC: OE = T 0+
T0: MAR<= PC
MAR: LD = T 0+ T 2+
T1: IR<= [MAR], PC<=PC+1 IR: LD = T 1+
T2: DECD(IR), MAR<=IR11to0 PC: INR = T 1+
T3: DR<= R1 IR: OE = T 2+
T4: ACC<= ALUADD(ACC, DR), T0

Control Hardware
0 1 1 1 1
IR
Decoder (4:16)
D15 D7 D 1 D0 I0
Timing IF (D7=1 &&I0=1&&T3)

and
Control
Circuit IR=ADD R1
T15 T1 T0
Decoder (4:16)
Counter RST
INCR
4-bit CLK
Sequencer
Control Signals
ADD R1 : ACC<=ACC+R1 MOV R1,R2 : R1<=R2
PC: OE = T0+
T0: MAR<= PC
MAR: LD = T0+ T2
T1: IR<= [MAR], PC<=PC+1 IR: LD = T1+
T2: DECD(IR), MAR<=IR11to0 PC: INR = T1+
T3: DR<= R1 IR: OE = T2+
R1: OE = T3D7I0+
T4: ACC<= ALUADD(ACC, DR), T0 LD = T3D7I3+
DR: LD = T3D7I0+
ACC: LD = T4D7I0+
ALU: ADD = T4D7I0+
SEQCNTR: INR = T0+T1+T2 +T3D7I0
CLR = T4D7I0 +
R2: OE = T3D7I3+
Control Signals
ADD R1 : ACC<=ACC+R1 MOV R1,R2 : R1<=R2 MOV ACC, [M] : ACC<=[M]
PC: OE = T0+
T0: MAR<= PC
MAR: LD = T0+ T2
T3: DR<= R1 IR: OE = T2+
R1: OE = T3D7I0+
DR: LD = T3D7I0+
ACC: LD = T4D7I0+
ALU: ADD = T4D7I0+
CLR = T4D7I0 +T3D7I3
R2: OE = T3D7I3+
Control Hardware
0 0 0 1 1 0001 MOV ACC, [M]
IR
Decoder (4:16)
D15 D7 D 1 D0 I11 I0
Timing IF (D1=1 &&T3)

and
Control
Circuit IR=MOV ACC, [M]
T15 T1 T0
Decoder (4:16)
Counter RST
INCR
4-bit CLK
Sequencer
Control Signals
PC: OE = T0+
T0: MAR<= PC
MAR: LD = T0+ T2
T3: DR<= R1 IR: OE = T2+
R1: OE = T3D7I0+
DR: LD = T3D7I0+
ACC: LD = T4D7I0+
ALU: ADD = T4D7I0+
R2: OE = T3D7I3+
Control Signals
PC: OE = T0+
T0: MAR<= PC
MAR: LD = T0+ T2
T3: DR<= R1 IR: OE = T2+
R1: OE = T3D7I0+
DR: LD = T3D7I0+
ACC: LD = T4D7I0+ T3D1 +
ALU: ADD = T4D7I0+
R2: OE = T3D7I3+
M: MR = T3D1+
Control Signals
PC: OE = T0+
T0: MAR<= PC
MAR: LD = T0+ T2
T3: DR<= R1 IR: OE = T2+
R1: OE = T3D7I0+
DR: LD = T3D7I0+
ALU: ADD = T4D7I0+
CLR = T4D7I0 +T3D7I3+
T3D1+
R2: OE = T3D7I3+
M: MR = T3D1+
Control Signals
PC: OE = T0+
T0: MAR<= PC
MAR: LD = T0+ T2
T3: DR<= R1 IR: OE = T2+
R1: OE = T3D7I0+
DR: LD = T3D7I0+
ALU: ADD = T4D7I0+
CLR = T4D7I0 +T3D7I3+
T3D1+
R2: OE = T3D7I3+ Mem. read during
M: MR = T3D1+T1 instrn fetch
Mirprogrammed Control Unit
CS2600 (3003)
By
Dr. Sk Subidh Ali
15-Feb-2017
Micro-programmed Control Unit
Instruction fetch
T0: MAR<= PC MAR: LD => C0
T1: IR<= [MAR], PC<=PC+1 PC: OE => C1
IR: LD => C2
M: RD => C3
PC: INR => C4
IR: OE => C5
Instruction fetch
IR: LD => C2
M: RD => C3
PC: INR => C4
IR: OE => C5
C5 C4 C3 C2 C1 C0
T0: 0 0 0 0 1 1
T1: 0 1 1 1 0 0
T2: 1 0 0 0 0 1
How to sequence??
T0=>T1=>T2
Instruction fetch
IR: LD => C2
M: RD => C3
PC: INR => C4
IR: OE => C5
C5 C4 C3 C2 C1 C0 BA M
T0: 0 0 0 0 1 1 0 0 0 1 1
T1: 0 1 1 1 0 0 0 0 1 0 1
T2: 1 0 0 0 0 1 x x x x 0
BA: Branch address

M: mode of address
Instruction fetch
IR: LD => C2
M: RD => C3
PC: INR => C4
External Addrs
IR: OE => C5
MUX
M=0 M=1
CMAR C5 C4 C3 C2 C1 C0 BA M
T0: 0 0 0 0 1 1 0 0 0 1 1
T1: 0 1 1 1 0 0 0 0 1 0 1
Control
Memory
T2: 1 0 0 0 0 1 x x x x 0
(ROM)
What about complete

M BA instruction????
0/1
CF CMAR: Control memory address register
CF: control field/control signals
BA: Branch address
Instruction fetch
IR: LD => C2
M: RD => C3
PC: INR => C4
IR: OE => C5
ADD R1 ACC<=ACC+R1
IR: LD => C2
M: RD => C3
T3: DR<= R1
PC: INR => C4
T4: ACC<= ALUADD(ACC, DR), T0 IR: OE => C5
R1: OE => C6
DR: LD => C7
ACC: LD => C8
ALU: ADD=> C9
ALU: OE => C10
C10 C9 C8 C7 C6C5 C4 C3 C2 C1 C0 BA M
T0: 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1
T1: 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1
T2: 0 0 0 0 0 1 0 0 0 0 1 L 0
ADD R1 ACC<=ACC+R1
IR: LD => C2
M: RD => C3
T3: DR<= R1
PC: INR => C4
T4: ACC<= ALUADD(ACC, DR), T0 IR: OE => C5
R1: OE => C6
DR: LD => C7
ACC: LD => C8
ALU: ADD=> C9
ALU: OE => C10
C10 C9 C8 C7 C6C5 C4 C3 C2 C1 C0 BA M
T0: 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1
T1: 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1
T2: 0 0 0 0 0 1 0 0 0 0 1 L 0
T3: 0 0 0 1 1 0 0 0 0 0 0 L+1 1
T4: 1 1 1 0 0 1 0 0 0 0 1 L+2 0

IIT BH DNC Lab EE Manual Expt 7

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Control Unit

LDR1 • Instruction decode

There are two instruction groups

I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

There are two instruction group

No operand address required

12 bits of operand can be used

I0 ADD R1 ACC ACC + R1

No operand address required

12 bits of operand can be used

I0 ADD R1 ACC ACC + R1

No operand address required

12 bits of operand can be used

I0 ADD R1 ACC ACC + R1

No operand address required

12 bits of operand can be used

I0 ADD R1 ACC ACC + R1

There are two instruction group

0001 MOV ACC, [M] 001 0x234

12 bits of operand can be memory address

1001 MVI ACC, 0x02 1001 0x02

8 bits of operand can be taken for immediate value

We need timing sequence and control signal

T4: ACC<= ALUADD(ACC, DR), T0

Timing IF (D7=1 &&I0=1&&T3)

0 0 0 1 1 0001 MOV ACC, [M]

Timing IF (D1=1 &&T3)

BA: Branch address

What about complete

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