Introduction To Digital Systems Solutions PDF

SOLUTIONS TO EXERCISES
for
INTRODUCTION TO DIGITAL SYSTEMS
Milos D. Ercegovac, Tomas Lang and Jaime H. Moreno
Wiley & Sons, New York, 1999
prepared by
Alexandre F. Tenca, Tomas Lang, Milos D. Ercegovac, and J.H. Moreno

with the help of
L. Alkalai, E. Gouriou, Y. He, M. Huguet, H. Liu, R. McIlhenny, M. Moraes de Azevedo,
A. Nananarelli, V. Oklobdzija, A. Panangadan, M.D.F. Schlag, T. Torii, M. Tremblay,
P. Vranes, and A. Wong.
Los Angeles, California

1999
.
Solutions Manual - Introduction to Digital Design - September 29, 2000 1
Chapter 2
Exercise 2.1
( x22 f0; 1; :::; 9g

Input: Output: z 2 f0; 2; 4; 6; 8; 25; 36; 49; 64; 81g
z = x2x ifotherwise
x>4
x 0 1 2 3 4 5 6 7 8 9
z = f (x) 0 2 4 6 8 25 36 49 64 81
2 Solutions Manual - Introduction to Digital Design - September 29, 2000
Exercise 2.2
Inputs: x = (x15; x14; :::; x1; x0) and y = (y1 ; y0), with xi ; yi 2 f0; 1; 2g.
Output: z = (z13; z12; :::; z0), with zi 2 f0; 1; 2g.
Function:
(
z = ((0x;150;; :::; xi+2; xi 1; :::; x0) if (xi+1 ; xi ) = y and (xj +1 ; xj ) 6= y for j > i
0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0; 0) otherwise
A tabular description would have as many rows as the number of combinations of x and y , which
is 318.
Exercise 2.3
Input: x = (xn 1 ; : : :; x0); xi 2 f0; 1g
Output: an integer 1 z n 1.
Function:
z = ji j j if (xi = xj = 1)
Exercise 2.4
Input: X is a 4 4 matrix of elements xij 2 fa; b; c; dg:
2 3
x x x x
66 11 12 13 14 77
66 x x x x 77
6 21 22 23 24 77
X = 66 77
66 x31 x32 x33 x34 77
64 5
x41 x42 x43 x44
Output: z 2 f0; 1g.
Function: The output is equal to 1 if one of x22; x23; x32; or x33 is b and it is surrounded by eight
a's. The conditional expression is
8
>
< 1 if xi;j = b and (xk;m = a for k 2 fi 1; i; i + 1g and m 2 fj 1; j; j + 1g)
z=> with i; j 2 f2; 3g and (k; m) 6= (i; j )
: 0 otherwise
A tabular representation would not be practical because there are 4 4 = 16 variables, each of
which can have 4 values, resulting in a table of 416 rows.
Exercise 2.5
Inputs: Integer 0 x < 216, binary control variable d 2 f0; 1g
16
( Integer 0 16z < 2 .
Output:
z = ((xx + 1)
1) mod 2 if d = 1
mod 216 if d = 0
Tabular representation: Requires 216 rows for d = 1 and 216 rows for d = 0.
Total rows = 2 216 = 217. A tabular representation is out of question.
Exercise 2.6
a b f1(a; b) f2(b; f1(a; b))

0 0 2 0
0 1 0 0
0 2 2 2
1 0 0 2
1 1 1 2
1 2 1 0
2 0 2 0
2 1 1 2
2 2 0 0
Exercise 2.7
Range from 10 to 25 ) 16 values.
Minimum number of binary variables: dlog2 16e = 4 variables.
Input: integer 10 x 25 Output: integer 0 z 15
z = (x 10)
In the next table the output z is represented by a vector z = (z3 ; z2; z1; z0), with zi 2 f0; 1g.
x 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
z 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Exercise 2.8
(a) Month: dlog2 12e = 4 bits
Month Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011
(b) Day: dlog2 31e = 5 bits
Year (assuming 0-2500): dlog2 2501e = 12 bits
Month: 4 bits
A total of 21 bits would be needed.
(c) Each decimal digit needs 4 bits. Two digits are necessary to represent the day, and 4 digits to
represent the year. The number of bits to represent these elds would be 6 4 = 24 bits. Adding
the bits used in the month eld we get 28 bits total.
(d) If only one component is used, we need to specify a code for each particular day. This code
may be calculated as:
(year 1) 12 31 + (month 1) 31 + day 1
where month, year and day are the usual numbers associated to each eld (Jan = 1, Feb = 2,...).
Maximum date is 12/31/2500, which corresponds to the value:
2499 372 + 11 31 + 30 = 929999
So dlog2 929999e = 20 bits are needed to represent all possible codes. The disadvantage of this
method is that many calculations must be done to convert the code to the usual representation of
the date, and vice-versa.
Exercise 2.9
decimal digit 2-4-2-1

0 0000
1 0001
2 0010
1000
3 0011
1001
4 0100
1010
5 0101
1011
6 0110
1100
7 0111
1101
8 1110
9 1111
Since there are six values that have two possible encodings, there are 26 dierent codes.
Exercise 2.10
Consider that the vector of weights is w = (w0; w1; w2; w3). A number x is represented as a vector
x = (x0; x1; x2; x3) and its value in decimal is calculated as:
3
X
x= xi wi ; xi 2 f0; 1g and wi > 0
i=0
Without loss of generality we consider that the weights are sorted in ascending order, such that
w0 w1 w2 w3. The conditions that the weights have to satisfy in order to enable the
representation of x 2 f0; 1; 2; :::; 9g, assuming wi > 0, are:
P
1. 3i 0 wi 9. This condition is important to enable the generation of 9, and thus assure
containment;
2. w0 = 1, to generate x = 1;
3. wi 9, for all i;
4. Continuity condition: for 0 < i 3, wi is chosen such that wi is the sum of a subset (including
the empty set) of weights wj plus one, j < i.
With this condition:
w1 2 fw0; w0 + 1g = f1; 2g
thus, if we choose w1 = 1, the set of values for w2 is
w2 2 fw0; w0 + 1; w1 + 1; w0 + w1 + 1g = f1; 2; 3g
and for the choice w1 = 2 we should have w2 in the set fw0; w0 + 1; w1 + 1; w0 + w1 + 1g =
f1; 2; 3; 4g, but since we are assuming w0 w1 w2 w3, we get:
w2 2 f2; 3; 4g
Notice that when w2 5 the value x = 4 cannot be represented since w0 + w1 = 3, and the
other weights are greater than 4. The same reasoning is applied to the fourth weight.
Exercise 2.11
(a)
34 567 = (0011 0100 0101 0110 0111)BCD
= (0110 0111 1000 1001 1010 )Excess 3
(b) BCD does not have the complementary property, so an actual subtraction is needed:
99 999 34 567 = 65 432 = (0110 0101 0100 0011 0010)BCD
2421 code has the complementary property, such that the subtraction is done by complementing
each bit:
34 567 = (0011 0100 1011 1100 1101)2421-code
99 999 34 567 = (1100 1011 0100 0011 0010)2421-code
Exercise 2.12
a) All possiblep5-bit vectors x = (x4x3 x2 x1x0 ) and the valid 2-out-of-5 combinations (marked with
a tick mark ( )) are shown in Table 2.1.
b)
Input= x = (x4x3 x2 x1x0 )
Output= z 2 f0; 1g
Function:
8
>
< 1 if (xi = xj = 1 and xk = 0) for
z = > i 6= j 6= k and i; j; k 2 f0; 1; 2; 3; 4g
: 0 otherwise
valid
2-out-of-5
x = (x4x3 x2x1x0 ) combinations
00000
00001
00010 p
00011
00100 p
00101 p
00110
00111
01000 p
01001 p
01010
01011 p
01100
01101
01110
01111
10000 p
10001 p
10010
10011 p
10100
10101
10110
10111 p
11000
11001
11010
11011
11100
11101
11110
11111
Table 2.1: Valid 2-out-of-5 combinations { Exercise 2.12(a)

Exercise 2.13
(a) (1001010100011110)2 = (1001 0101 0001 1110 )2 = (951E )16
(b) (3456)8 = (011 100 101 110)2 = (011100101110)2
(c) To convert from radix-2 to radix-2k we consider groups of k bits. The digits in radix-2k are
obtained converting each group (binary representation of the digit) into a single value in the new
radix.
To convert from radix-2k to radix-2, the digits in radix-2k are converted to binary. The nal vector,
that corresponds to the concatenation of all digit representations in binary, is the radix-2 represen-
tation of the number.
Exercise 2.14
We could directly build the tables of the functions and show that the identity holds by comparing
the tables. However, this would be time consuming since the table would have 32 rows. Therefore,
we look at dierent assignments as follows:
i) if a = 0 and b = 0 then both sides of the identity have value 0, since M (x; y; z) = 0 when
two of its arguments are 0.
ii) if a = 1 and b = 1 then both sides have value 1, since M (x; y; z) = 1 when two arguments
are 1.
iii) the two cases a 6= b are equivalent due to the symmetry of the majority function and the
fact that these variables appear together in all functions in the expression. Consequently, we
check only the case a = 0 and b = 1. For this assignment,
M [0; 1; M (c; d; e)] = M (c; d; e)

and
M [M (0; 1; c); d; M (0; 1; e)] = M [c; d; e]
The identity is true for all assignments of a and b and is therefore true.
Exercise 2.15
(a) Prove that fXOR (fAND (x1; x0); fAND(x1 ; x0)) = fEQUIVALENCE (x1; x0)
x1 x0 f
AND ( x1 ; x0 ) f
XOR ( AND (
f ) AND (
x1 ; x0 ; f x1 ; x0 )) f
EQUIVALENCE ( x1 ; x0 )
0 0 0 0 1
0 1 0 0 0
1 0 0 0 0
1 1 1 0 1
The conclusion is:

fXOR (fAND(x1 ; x0); fAND(x1; x0)) 6= fEQUIVALENCE (x1 ; x0)
(b) Prove that fNAND (fNAND (x1; x0); fNAND(x1 ; x0)) = fAND (x1; x0)
x1 x0 f
NAND ( x1 ; x0 ) f
NAND ( NAND (
f ) NAND (
x1 ; x0 ; f x1 ; x0 )) f
AND (
x1 ; x0 )
0 0 1 0 0
0 1 1 0 0
1 0 1 0 0
1 1 0 1 1
The conclusion is:

fNAND (fNAND(x1 ; x0); fNAND (x1; x0)) = fAND(x1 ; x0)
Exercise 2.16
Each variable can have 2 values (0 or 1).
Total number of n-variable inputs: |2 2 {z
::: 2} = 2n
n
For each input, the output function can have 2 values.
::: 2} = 22
Total number of functions: |2 2 {z n
2n
Exercise 2.17
a) Let f be a symmetric switching function of three variables, x; y; and z . Since the function is
symmetric, f (0; 0; 1) = f (0; 1; 0) = f (1; 0; 0) and f (0; 1; 1) = f (1; 0; 1) = f (1; 1; 0) so that we have
the following table:
x y z f
0 0 0 a
0 0 1 b
0 1 0 b
0 1 1 c
1 0 0 b
1 0 1 c
1 1 0 c
1 1 1 d
where a; b; c; and d are binary variables. From this description any particular example can be
generated by assigning values to a; b; c, and d.
b) Since a; b; c; and d can each take two values (0 or 1), the number of symmetric functions of three
variables is 24 = 16.
c) A symmetric switching function has the same value for all argument values that have the same
number of 1's, since all these values can be obtained by permuting the arguments. Consequently,
the values of the function of n arguments are decomposed into n + 1 classes dened by the number
of 1's in the argument vector (four classes in part a). Therefore the set A completely denes the
function.
d) The function has value 1 whenever 0; 2 or 3 arguments have value 1. The table is
w x y z f
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
e) In part (c) we saw that the argument values of symmetric switching function of n variables are
divided into n +1 classes. For each of these classes the function can have value 1 or 0. Consequently,
the number of symmetric switching functions of n variables is 2n+1 .
f) No, the composition of symmetric switching functions is not necessarily a symmetric function.
Consider as counterexample
f (x; y; z) = fAND (fOR(x; y ); z)
and interchange the variables x and z .

g) The table is
a b c f1 f2 f
0 0 0 1 1 0
0 0 1 1 0 0
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 1 0 1
1 0 1 0 0 1
1 1 0 0 0 1
1 1 1 0 1 0
h) Let U be the set f0; 1; : : :; ng where n is the number of variables of the symmetric function,
and let A be the set describing the function f . Since the complement of f is 0 when f is 1 and
viceversa, it is represented by the set Ac such that
Ac = U A
For example, considering a 4-variable symmetrical function with A = f0; 1g, we have Ac = f2; 3; 4g.
Exercise 2.18
(a) The threshold switching function of three variables with w1 = 1, w2 = 2, w3 = 1, and T = 2
is:
x x = fx3; x2; x1g z = f (x)
0 000 0
1 001 0
2 010 0
3 011 1
4 100 0
5 101 0
6 110 0
7 111 0
one-set = f3g
zero-set = f0,1,2,3,4,5,6,7g
(b) The system of inequalities for the function one set(3; 5; 7) is:
0 T (2.1)
w0 T (2.2)
w1 T (2.3)
w2 T (2.4)
w0 + w1 > T (2.5)
w0 + w2 > T (2.6)
w1 + w2 T (2.7)
w2 + w1 + w0 > T (2.8)
A solution for this system is:
w0 = 2 w1 = 1 w2 = 1 T = 2
(c) We have the following eight equations:
0 > T (2.9) w2 T (2.13)
w0 T (2.10) w2 + w0 > T (2.14)
w1 T (2.11) w2 + w1 > T (2.15)
w1 + w0 > T (2.12) w2 + w1 + w0 T (2.16)
From these equations, we get:

w0 + w1 2T [ (10)+(11) ]
T < w0 + w1 2T [ (12) and (10)+(11) ]
Therefore:
T < 2T but (1) gives T <0
These conditions are incompatible, we can't nd such a threshold function.

(d) The majority function is expressed as a threshold function with the weights w0 = w1 = w2 =
w3 = 1, and T = 2. Since x0 + x1 + x2 + x3 > 2 , three or four bits have the value 1
Exercise 2.19 The input of the system is x = (x3; x2; x1; x0), and the output is the bit-vector
z = (z1; z0). The output encoding and the respective function table are:
x3x2 x1 x0 z1 z0
0 0000 - -
1 0001 - -
2 0010 - -
3 0011 0 1
4 0100 - -
z z1 z0 5 0101 1 0
6 0110 0 1
1 01 7 0111 - -
2 10 8 1000 - -
3 11 9 1001 1 1
10 1010 1 0
11 1011 - -
12 1100 0 1
13 1101 - -
14 1110 - -
15 1111 - -
z1 : one-set(5,9,10), zero-set(3, 6, 12), dc-set(0,1,2,4,7,8,11,13,14,15)
z0 : one-set(3,6,9,12), zero-set(5, 10), dc-set(0,1,2,4,7,8,11,13,14,15)
Exercise 2.20 Using BCD code, the function specied in Exercise 2.1 is described as:
x z7 z6 z5 z4 z3 z2 z1 z0
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1 0
2 0 0 0 0 0 1 0 0
3 0 0 0 0 0 1 1 0
4 0 0 0 0 1 0 0 0
5 0 0 1 0 0 1 0 1
6 0 0 1 1 0 1 1 0
7 0 1 0 0 1 0 0 1
8 0 1 1 0 0 1 0 0
9 1 0 0 0 0 0 0 1
10 - - - - - - - -
11 - - - - - - - -
12 - - - - - - - -
13 - - - - - - - -
14 - - - - - - - -
15 - - - - - - - -
Using a two-dimensional table:
x1 x0
x3 x2 00 01 10 11
00 00000000 00000010 00000100 00000110
01 00001000 00100101 00110110 01001001
10 01100100 10000001 - -
11 - - - -
Using one-set and d.c.-set representation:
z7 = one set(9); dc set(10; 11; 12; 13; 14; 15)
z6 = one set(7; 8); dc set(10; 11; 12; 13; 14; 15)
z5 = one set(5; 6; 8); dc set(10; 11; 12; 13; 14; 15)
z4 = one set(6); dc set(10; 11; 12; 13; 14; 15)
z3 = one set(4; 7); dc set(10; 11; 12; 13; 14; 15)
z2 = one set(2; 3; 5; 6; 8); dc set(10; 11; 12; 13; 14; 15)
z1 = one set(1; 3; 6); dc set(10; 11; 12; 13; 14; 15)
z0 = one set(5; 7; 9); dc set(10; 11; 12; 13; 14; 15)
Exercise 2.21: Using EXCESS-3 code, the function specied in Exercise 2.1 is described as:
x z7 z6 z5 z4 z3 z2 z1 z0
0 - - - - - - - -
1 - - - - - - - -
2 - - - - - - - -
3 0 0 1 1 0 0 1 1
4 0 0 1 1 0 1 0 1
5 0 0 1 1 0 1 1 1
6 0 0 1 1 1 0 0 1
7 0 0 1 1 1 0 1 1
8 0 1 0 1 1 0 0 0
9 0 1 1 0 1 0 0 1
10 0 1 1 1 1 1 0 0
11 1 0 0 1 0 1 1 1
12 1 0 1 1 0 1 0 0
13 - - - - - - - -
14 - - - - - - - -
15 - - - - - - - -
x1 x0
x3 x200 01 10 11
00 - - - 00110011
01 00110101 00110111 00111001 00111011
10 01011000 01101001 01111100 10010111
11 10110100 - - -
Using one-set and dc-set representation:
z7 = one set(11; 12); dc set(10; 11; 12; 13; 14; 15)
z6 = one set(8; 9; 10); dc set(10; 11; 12; 13; 14; 15)
z5 = one set(3; 4; 5; 6; 7; 9; 10; 12); dc set(10; 11; 12; 13; 14; 15)
z4 = one set(3; 4; 5; 6; 7; 8; 10; 11; 12); dc set(10; 11; 12; 13; 14; 15)
z3 = one set(6; 7; 8; 9; 10); dc set(10; 11; 12; 13; 14; 15)
z2 = one set(4; 5; 10; 11; 12); dc set(10; 11; 12; 13; 14; 15)
z1 = one set(3; 5; 7; 11); dc set(10; 11; 12; 13; 14; 15)
z0 = one set(3; 4; 5; 6; 7; 9; 11); dc set(10; 11; 12; 13; 14; 15)
Exercise 2.22 Using 2-out-of-5 code, the function specied in Exercise 2.1 is described by the
following table. As the table has 32 entries, only the 10 entries that are useful are shown, the
others have don't care values:
x z9 z8 z7 z6 z5 z4 z3 z2 z1 z0
3 0 0 0 1 1 0 0 0 1 1
5 0 1 0 0 1 1 1 0 0 0
6 0 1 1 0 0 0 0 1 1 0
9 0 0 1 1 0 1 0 0 1 0
10 1 0 1 0 0 0 1 0 1 0
12 0 0 0 1 1 0 0 1 1 0
17 1 0 0 1 0 0 0 1 0 1
18 0 0 0 1 1 1 0 0 0 1
20 0 0 0 1 1 1 0 0 1 0
24 0 0 0 1 1 1 0 1 0 0
x1 x0
x4 x3 x2 00 01 10 11
000 - - - 0001100011
001 - 0100111000 0110000110 -
010 - 0011010010 1010001010 -
011 0001100110 - - -
100 - 1001000101 0001101001 -
101 0001110010 - - -
110 0001110100 - - -
111 - - - -
Using one-set and d.c.-set representation:
z9 = one set(10; 17);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z8 = one set(5; 6);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z7 = one set(6; 7; 8);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z6 = one set(3; 9; 12; 17; 18; 20; 24);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z5 = one set(3; 5; 12; 18; 20; 24);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z4 = one set(5; 9; 18; 20; 24);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z3 = one set(5; 10);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z2 = one set(6; 12; 17; 24);

dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z1 = one set(3; 6; 9; 10; 12; 20);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
z0 = one set(3; 17; 18);
dc set(0; 1; 2; 4; 7; 8; 11; 13; 14; 15; 16; 19; 21; 22; 23; 25; 26; 27; 28; 29; 30; 31)
Exercise 2.23
The number of values of n binary variables is 2n . For each of these, the function can take three
possible values (0; 1 or dc) resulting in 32 functions. Out of these 22 are completely specied
n n
functions.
Exercise 2.24
(a)
a0 b0 + ab + a0b = a0 (b + b0) + ab
= a0 1 + ab
= a0 + b
(b)
a0 + a(a0 b + b0c)0 = a0 + (a0b + b0c)0
= a0 + (a + b0)(b + c0 )
= a0 + ab + ac0 + bb0 + b0c0
= a0 + b + c0 + b0c0
= a0 + b + c0
(c)
(a0b0 + c)(a + b)(b0 + ac)0 = (a0 b0 + c)(a + b)b(a0 + c0 )
= (a0 b0 + c)b(a0 + c0)
= (ba0b0 + bc)(a0 + c0)
= bc(a0 + c0 )
= a0 bc
(d)
ab0 + b0c0 + a0c0 = ab0 + (a + a0 )b0c0 + a0c0
= ab0 + ab0c0 + a0 b0c0 + a0c0
= ab0 (1 + c0 ) + a0 (1 + b0)c0
= ab0 + a0 c0
(e)
wxy + w0 x(yz + yz0 ) + x0 (zw + zy 0) + z(x0w0 + y 0 x) = wxy + w0xy + z(x0(w + y0 ) + x0w0 + y 0x)
= (w + w0)xy + z (x0 (w + y 0 + w0) + y 0 x)
= xy + z (x0 + xy 0 )
= xy + z (x0 + y 0 )
= xy + z (xy )0
= xy + z
(f)
abc0 + bc0d + a0 bd = abc0 + (a + a0 )bc0d + a0bd
= abc0 + abc0d + a0bc0d + a0bd
= abc0(1 + d) + a0 bd(1 + c0)
= abc0 + a0bd
Exercise 2.25
xz 0 + x0 z =
= x(xy 0 + x0 y )0 + x0(xy 0 + x0y )
= x(xy 0)0(x0y )0 + x0 xy 0 + x0 x0y
= x(x0 + y )(x + y 0 ) + x0 y
= (xx0 + xy )(x + y 0 ) + x0 y
= (xyx + xyy 0) + x0 y
= xy + x0 y
= (x + x0)y
= 1y
Exercise 2.26
a + a0 b + a0 b0c + a0b0c0d + a0b0c0d0e =

= a + a0b + a0 b0c + a0 b0c0(d + d0e)
= a + a0b + a0 b0(c + c0(d + e))
= a + a0b + a0 b0(c + d + e)
= a + a0(b + b0(c + d + e))
= a + a0(b + c + d + e)
= a+b+c+d+e
Exercise 2.27 (a) With the assumption that c = a b we obtain

b c = b (a b)
= b (ab + a0 b0)
= b(ab + a0 b0) + b0(ab + a0 b0)0
= ab + a0 bb0 + b0(ab0)0(a0 b0)0
= ab + b0(a0 + b0)(a + b)
= ab + (a0b0 + b0)(a + b)
= ab + a0 ab0 + a0 bb0 + ab0 + b0b
= ab + ab0
= a(b + b0)
= a
Therefore, a = b c
(b)
a bc = a b(a b)
= a b(ab + a0 b0)
= a (ab + ba0b0)
= a ab
= aab + a0 (ab)0
= ab + a0 (a0 + b0)
= ab + a0 + a0 b0
= ab + a0
= a0 + b
Therefore, a bc 6= 1
Exercise 2.28 As a counterexample consider the case a = 0; b = 0; and c = 1. For this set of
values ab = ac = 0 and b 6= c.
abc a#(b&c) (a#b)&(a#c)

000 0#0 = 0 0&0 = 0
001 0#1 = 0 0&0 = 0
002 0#2 = 0 0&0 = 0
010 0#1 = 0 0&0 = 0
011 0#1 = 0 0&0 = 0
012 0#2 = 0 0&0 = 0
020 0#2 = 0 0&0 = 0
021 0#2 = 0 0&0 = 0
022 0#2 = 0 0&0 = 0
100 1#0 = 0 0&0 = 0
101 1#1 = 1 0&1 = 1
102 1#2 = 1 0&1 = 1
110 1#1 = 1 1&0 = 1
111 1#1 = 1 1&1 = 1
112 1#2 = 1 1&1 = 1
120 1#2 = 1 1&0 = 1
121 1#2 = 1 1&1 = 1
122 1#2 = 1 1&1 = 1
200 2#0 = 0 0&0 = 0
201 2#1 = 1 0&1 = 1
202 2#2 = 2 0&2 = 2
210 2#1 = 1 1&0 = 1
211 2#1 = 1 1&1 = 1
212 2#2 = 2 1&2 = 2
220 2#2 = 2 2&0 = 2
221 2#2 = 2 2&1 = 2
222 2#2 = 2 2&2 = 2
Table 2.2: Proof of distributivity for system in Exercise 2.29
Exercise 2.29 To be a boolean algebra the system must satisfy the postulates of commutativity,
distributivity, complement and additive (multiplicative) identity. Lets consider each one of these
cases:
(a) (#); (&) are commutative because the table is symmetric about the main diagonal, so
postulate 1 (P 1) is satised.
(b) For distributivity, we must show that a#(b&c) = (a#b)&(a#c). Let us prove that this
postulate is true for the system by perfect induction, as shown in Table 2.2.
(c) The additive identity element is 0 since a&0 = 0&a = a. The multiplicative identity
element is 2 since a#2 = 2#a = a.
(d) For 1 to have a complement 10 we need 1&10 = 2 and 1#10 = 0. Consequently, from the
table we see that 1 has no complement.
Exercise 2.30
Let us call the four elements 0; x; y , and 1 with 0 the additive identity, 1 the multiplicative identity
and let x be the complement of y . The corresponding operation tables are
+ 0 x y 1
0 0 x y 1
x x x 1 1
y y 1 y 1
1 1 1 1 1
* 0 x y 1
0 0 0 0 0
x 0 x 0 x
y 0 0 y y
1 0 x y 1
Exercise 2.31
To show that the NAND operator is not associative, that means, ((a:b)0:c)0 6= (a:(b:c)0)0 we just
need to nd a case when the expressions are dierent. Take a = 0, b = 0 and c = 1. For these
values we have:
((a:b)0:c)0 = ((0:0)0:1)0 = (1:1)0 = 0
(a:(b:c)0)0 = (0:(0:1)0)0 = 1
So, the NAND operator is not associative.
To show that the NOR operator is not associative, that means, ((a + b)0 + c)0 6= (a + (b + c)0)0 we
take a = 0, b = 0 and c = 1. For these values we have:
((a + b)0 + c)0 = ((0 + 0)0 + 1)0 = 0
(a + (b + c)0)0 = (0 + (0 + 1)0)0 = (0 + 0)0 = 1
So, the NOR operator is not associative.
Exercise 2.32
Part (a)
(i) show that XOR operator is commutative:
a b ab ba
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
(ii) show that XOR operator is associative: a (b c) = (a b) c
abc a b b c (a b) c a (b c)
000 0 0 0 0
001 0 1 1 1
010 1 1 1 1
011 1 0 0 0
100 1 0 1 1
101 1 1 0 0
110 0 1 0 0
111 0 0 1 1
(iii) show that XOR operator is distributive with respect to AND operator, that means:
a:(b c) = ab ac
abc a:b a:c (b c) a:(b c) ab ac
000 0 0 0 0 0
001 0 0 1 0 0
010 0 0 1 0 0
011 0 0 0 0 0
100 0 0 0 0 0
101 0 1 1 1 1
110 1 0 1 1 1
111 1 1 0 0 0
Part (b)
(a) prove that if x y = 0 then x = y .
x y = xy 0 + x0y = 0 ! (x = 1 and y = 1) or (x = 0 and y = 0)
This implies x = y .
(b) x0 y = (x y )0
x y x0 y (x y )0
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
(c) x y = x0 y 0
x y x y x0 y 0
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
(d) prove that if x y = z y then x = z .
xy = zy
(x y ) y = (z y ) y
x (y y ) = z (y y ) (Associativity)
x0= z0 (y y = 0)
x=z
Using the function table we come to the same conclusion. The lines where x y = z y are marked
with an *.
x y z xy z y
0 0 0 0 0 *
0 0 1 0 1
0 1 0 1 1 *
0 1 1 1 0
0 0 0 0 0 *
0 0 1 0 1
0 1 0 1 1 *
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1 *
1 1 0 0 1
1 1 1 0 0 *
1 0 0 1 0
1 0 1 1 1 *
1 1 0 0 1
1 1 1 0 0 *
(e) For an even number of x's the expression
x x x x ::: x
can be rewritten as
(x x) (x x) :::(x x)
since x x = 0 the expression becomes:
0 0 0::: 0
and since 0 0 = 0, the resulting value is 0.
For an odd number of x's the same grouping of x's can be done and the expression is transformed
into:
0 0 0:::0 x = 0 x = 00x + 0:x0 = x
Exercise 2.33
(a) Yes. (b) Yes. (c) No, Unmatched parenthesis.
Exercise 2.34
(a)
E (w; x; y; z) = w + x0 + (x + y )(w + z)0
E (0; 1; 1; 0) = 0 + 10 + (1 + 1)(0 + 0)0 = 0 + 0 + (1)(0)0 = 0 + 0 + 1 1
= 1
E (1; 1; 1; 0) = 1 + 10 + (1 + 1)(1 + 0)0 = 1 + 0 + (1)(1)0 = 1 + 1 0
= 1
(b)
E (x3; x2; x1; x0) = x2 x1 + x3
E (0; 1; 1; 0) = 1 1 + 0 = 1 + 0 = 1
E (1; 1; 1; 0) = 1 1 + 1 = 1 + 1 = 1
Exercise 2.35 Since the only term containing w is the same in both expressions (yw), to simplify
the tabular description (only 3 variables) we transform the proof as follows:
xyz + yw + x0z0 + xy0 = y 0z0 + yw + xz + x0yz0 if xyz + x0 z0 + xy 0 = y 0z 0 + xz + x0 yz0
Let us call E1 = xyz + x0 z 0 + xy and E2 = y 0z 0 + xz + x0 yz 0 . We show that E1 = E2 in the following
table.
x y z E1 E2
0 0 0 1 1
0 0 1 0 0
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 0 0
1 1 1 1 1
Note that if E1 is not equivalent to E2 it is still possible that the original expressions are equivalent.
An example of this type of situation is ab0 + b = a + b, in which ab0 and a are not equivalent.
Exercise 2.36
(a) E (x; y ) = xy + xy 0
xy E (x; y )
00 0
01 0
10 1
11 1
(b) E (x; y; z ) = xyz + x0 y + xyz 0
x y z E (x; y; z)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Exercise 2.37
Expr a Expr b Expr c Expr d Expr e
x y z xy
0 0
+ xz + xz 0
xy + x y
0 0
+ yz 0
xyz + x y z + x z
0 0 0 0
+ xyz 0
y z+xz
0 0 0
+ xyz x y
0 0
+ xz
0 0
+ xyz
0 0 0 1 1 1 1 1
0 0 1 1 1 1 1 1
0 1 0 1 1 1 1 1
0 1 1 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 0 0 1 0
1 1 0 0 1 1 0 0
1 1 1 1 1 1 1 1
Equivalent expressions: Expr a and Expr d, Expr b and Expr c.

Exercise 2.38
(a) E (a; b; c; d) = abc0d + ab0c + bc0d + ab0 c0 + acd + a0 bcd
E (a; b; c; d) = c0 d(ab + b) + ab0(c + c0) + (a + a0b)cd

= bc0d + ab0 + (a + b)cd
= bd(c + c0 ) + ab0 + acd
= bd + ab0 + a(b + b0)cd
= bd(1 + ac) + ab0 (1 + cd)
= ab0 + bd
(b) E (a; b; c; d) = acb + ac0d + bc0d + a0b0 c0 + ab0 c0d0 + bc0d
E (a; b; c; d) = bc0(d + d0 ) + b0c0(a0 + ad0 ) + acb + ac0d

= bc0 + b0c0 a0 + b0c0d0 + acb + ac0d
= c0(b + b0a0 + b0d0 + ad) + acb
= c0(b + a0 + d + d0 ) + acb
= c0 + acb
= ab + c0
Exercise 2.39
f = a0b0 c + a0bc0 + a0 bc + ab0c = m1 + m2 + m3 + m5 = P m(1; 2; 3; 5)
f = (a + b + c)(a0 + b + c)(a0 + b0 + c)(a0 + b0 + c0 ) = M0 + M4 + M6 + M7 = Q M (0; 4; 6; 7)
Exercise 2.40
(a)
a0b + ac + bc = a0 b(c + c0) + a(b + b0)c + (a + a0 )bc
= a0 bc + a0bc0 + abc + ab0 c + abc + a0bc
m3 + m2 + m7 + mY5 + m7 + m3
= X
= m(2; 3; 5; 7) = M (0; 1; 4; 6)
(b) g (a; b; c; d; e; f ) = (ab + c)(d0e + f ) = g1 (a; b; c)g2(d; e; f )
Since the g1 and g2 are disjoint, we may obtain their minterms separately and combine them later
to get the minterms for g (a; b; c; d; e; f ):
X Y
g1 (a; b; c) = ab + c = abc + abc0 + abc + a0 bc + ab0c + a0b0c = m(1; 3; 5; 6; 7) = M (0; 2; 4)
X Y
g2(d; e; f ) = d0e + f = d0ef + d0ef 0 + def + d0ef + de0f + d0e0f = m(1; 2; 3; 5; 7) = M (0; 4; 6)
If g1 has a minterm mi (a; b; c) and g2 has a minterm mj (d; e; f ), since the expression for g is
the AND of both expressions, g has the minterms m8i+j (a; b; c; d; e; f ) = mi (a; b; c):mj (d; e; f ).
Consequently, the minterms and maxterms of g are:
P
CSP: Q m( 9; 10; 11; 13; 15; 25; 26; 27; 29; 31; 41; 42; 43; 45; 47; 49; 50; 51; 53; 55; 57; 58; 59; 61; 63)
CPS: M ( 0; 1; 2; 3; 4; 5; 6; 7; 8; 12; 14; 16; 17; 18; 19; 20; 21; 22; 23; 24; 28; 30; 32; 33; 34; 35; 36; 37;
38; 39; 40; 44; 46; 48; 52; 54; 56; 60; 62)
(c)
a0 b(ab + c)(b + c0d) = (a0 bab + a0 bc)(b + c0 d) = a0bc(b + c0d)
= a0 bcb + a0 bcc0d = a0bc(d + d0 )
= a0 bcd + a0 bcd0
P
CSP: Q m(6; 7)
CPS: M (0; 1; 2; 3; 4; 5; 8; 9; 10; 11; 12; 13; 14; 15)
Exercise 2.41
CSP equivalent:
E (x; y; z) = x0 + x(x0 y + y0 z)0
= x0 (y + y 0 )(z + z 0) + x((x0y )0:(y 0z )0)
= x0 yz + x0yz 0 + x0 y 0 z + x0 y 0z 0 + x(x + y 0 ):(y + z 0 )
= x0 yz + x0yz 0 + x0 y 0 z + x0 y 0z 0 + x(xy + xz 0 + y 0 y + y 0 z 0 )
= x0 yz + x0yz 0 + x0 y 0 z + x0 y 0z 0 + xy + xz 0 + xy 0z 0
= x0 yz + x0yz 0 + x0 y 0 z + x0 y 0z 0 + xy (z + z 0 ) + xz 0 (y + y 0 ) + xy 0z 0
= x0 yz + x0yz 0 + x0 y 0 z + x0 y 0z 0 + xyz + xyz 0 + xyz 0 + xy 0z 0 + xy 0z 0
x0 yz + x0yz0 + x0 y0 z + x0y 0z 0 + xyz + xyz 0 + xy 0z0
= X
= m(0; 1; 2; 3; 4; 6; 7)
CPS equivalent:
E (x; y; z) = x0 + x(x0y + y0 z)0
= (x0 + x):(x0 + (x0 y + y 0 z )0)
= x0 + (x0y )0(y 0z )0
= (x0 + (x0 y )0)(x0 + (y 0 z )0)
= (x0 + x + y 0)(x0 + y + z 0 )
= 1Y:(x0 + y + z 0 )
= M (5)
Exercise 2.42
a) We rst convert to a sum of products
[((a + b + a0 c0)c + d)0 + ab]0 =

= (((a + b + a0 c0)c + d)0)0(ab)0
= ((a + b + a0 c0)c + d)(a0 + b0)
= (ac + bc + d)(a0 + b0)
= a0 bc + a0d + ab0c + b0d
To get the CSP we expand and eliminate repeated minterms
= a0bc(d + d0) + a0 d(b + b0)(c + c0) + ab0 c(d + d0) + b0d(a + a0)(c + c0)
= a0bcd + a0 bcd0 + a0bc0d + a0 b0cd + a0 b0c0d + ab0 cd + ab0 cd0 + ab0c0 d
In m-notation,
X
E (a; b; c; d) = m(1; 3; 5; 6; 7; 9; 10; 11)
b) We rst get a sum of products
[(w0 + (xy + xyz 0 + (x + z )0)0 )(z 0 + w0 )]0 =

= (w0 + (xy + xyz 0 + x0 z 0 )0)0 + (z 0 + w0)0
= (w(xy + xyz 0 + x0 z 0) + zw
= wxy + wxyz 0 + wx0 z 0 + wz
Now we expand and eliminate repeated minterms
= wxy (z + z 0 ) + wxyz 0 + wx0 z 0(y + y 0)wz (x + x0 )(y + y 0 )

= wxyz + wxyz 0 + wx0yz 0 + wx0 y 0z 0 + wxy 0z + wx0yz + wx0y 0z
In m-notation,
X
E (w; x; y; z) = m(8; 9; 10; 11; 13; 14; 15)
Exercise 2.43
(a) E (w; x; y; z ) = xyz + yw + x0z 0 + xy 0
E (w; x; y; z) = x(yz + y 0) + yw + x0 z0
= x(y 0 + z ) + yw + x0z 0
= (x(y 0 + z ) + yw + x0 )(x(y 0 + z ) + yw + z 0)
= (y 0 + z + yw + x0)(xy 0 + z 0 + xz + yw)
= (w + x0 + y 0 + z )(xy 0 + x + z 0 + yw)
= (w + x0 + y 0 + z )(x + z 0 + yw)
= (w + x0 + y 0 + z )(w + x + z 0 )(x + y + z 0 )
= (x + x0 + y 0 + z )(w + x + y + z 0 )(w + x + y 0 + z 0)(w0 + x + y + z 0)
(b) E (a; b; c; d) = (abc + ab0)0(a0 b + c0)
E (a; b; c; d) = (a0 + b0 + c0)(a0 + b)(a0 + c0 )(b + c0)

= (a0 + b0 + c0 )(a0 + b + c)(a0 + b + c0 )(a + b + c0)
Exercise 2.44
(a)
P m(0; 1; 3; 4; 11; 12; 14; 15) = Q M (2; 5; 6; 7; 8; 9; 10; 13)
Q P
(b) M (0; 1; 3; 5; 6; 9; 10; 13) = m(2; 4; 7; 8; 11; 12; 14; 15)
Exercise 2.45
Y
f (x; y; z) = M (0; 1; 4; 6; 7)
g (x; y; z) = (f (x; y; z))0
X Y
g (x; y; z) = m(0; 1; 4; 6; 7) = M (2; 3; 5)
Exercise 2.46
(a)
Input: A; B 2 f0; 1; 2; 3g and Cin 2 f0; 1g
Output: Z 2 f0; 1; 2; 3g and Cout 2 f0; 1g
Z = (A + B + Cin) mod 4
(
if (A + B + Cin ) 4
Cout = 01 otherwise
C
in A B C out Z i C in a1 a0 b1 b0 C out z1 z0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 1 0 0 0 0 1 0 0 1
0 0 2 0 2 2 0 0 0 1 0 0 1 0
0 0 3 0 3 3 0 0 0 1 1 0 1 1
0 1 0 0 1 4 0 0 1 0 0 0 0 1
0 1 1 0 2 5 0 0 1 0 1 0 1 0
0 1 2 0 3 6 0 0 1 1 0 0 1 1
0 1 3 1 0 7 0 0 1 1 1 1 0 0
0 2 0 0 2 8 0 1 0 0 0 0 1 0
0 2 1 0 3 9 0 1 0 0 1 0 1 1
0 2 2 1 0 10 0 1 0 1 0 1 0 0
0 2 3 1 1 11 0 1 0 1 1 1 0 1
0 3 0 0 3 12 0 1 1 0 0 0 1 1
0 3 1 1 0 13 0 1 1 0 1 1 0 0
0 3 2 1 1 14 0 1 1 1 0 1 0 1
(b) 0 3 3 1 2 (c) 15 0 1 1 1 1 1 1 0
1 0 0 0 1 16 1 0 0 0 0 0 0 1
1 0 1 0 2 17 1 0 0 0 1 0 1 0
1 0 2 0 3 18 1 0 0 1 0 0 1 1
1 0 3 1 0 19 1 0 0 1 1 1 0 0
1 1 0 0 2 20 1 0 1 0 0 0 1 0
1 1 1 0 3 21 1 0 1 0 1 0 1 1
1 1 2 1 0 22 1 0 1 1 0 1 0 0
1 1 3 1 1 23 1 0 1 1 1 1 0 1
1 2 0 0 3 24 1 1 0 0 0 0 1 1
1 2 1 1 0 25 1 1 0 0 1 1 0 0
1 2 2 1 1 26 1 1 0 1 0 1 0 1
1 2 3 1 2 27 1 1 0 1 1 1 1 0
1 3 0 1 0 28 1 1 1 0 0 1 0 0
1 3 1 1 1 29 1 1 1 0 1 1 0 1
1 3 2 1 2 30 1 1 1 1 0 1 1 0
1 3 3 1 3 31 1 1 1 1 1 1 1 1
one-set(Cout) = f7; 10; 11; 13; 14; 15; 19; 22; 23; 25; 26; 27; 28; 29; 30; 31g
one-set(z1) = f2; 3; 5; 6; 8; 9; 12; 15; 17; 18; 20; 21; 24; 27; 30; 31g
one-set(z0) = f1; 3; 4; 6; 9; 11; 12; 14; 16; 18; ; 21; 23; 24; 26; 29; 31g
z
x Ctl=Decrement Ctl=Increment
0 15 1
1 0 2
2 1 3
3 2 4
4 3 5
5 4 6
6 5 7
7 6 8
8 7 9
9 8 10
10 9 11
11 10 12
12 11 13
13 12 14
14 13 15
15 14 0
Table 2.3: Exercise 2.47(b)
Exercise 2.47
(a)
Inputs: Integer( x 2 f0; : : :; 15g, control variable Ctl 2 fIncrement,Decrementg
Output: z = ((xx + 1) 1) mod 16 if Ctl=Increment
mod 16 if Ctl=Decrement
(b) See Table 2.3 on page 52.
(c) We have to choose a code for x, Ctl and z . Coding x as x = (x3; x2; x1; x0) and z as
z = (z3; z2; z1; z0), using the conventional binary representation. Coding Ctl as c in binary with 0
meaning Decrement and 1 meaning Increment. Table 2.4 on page 53 shows the tabular representa-
tion of the switching functions.
The zero sets are:
zero-set(z3)=f1; 2; 3; 4; 5; 6; 7; 8; 16; 17; 18; 19; 20; 21; 22; 31g
zero-set(z2)=f1; 2; 3; 4; 9; 10; 11; 12; 16; 17; 18; 23; 24; 25; 26; 31g
zero-set(z1)=f1; 2; 5; 6; 9; 10; 13; 14; 16; 19; 20; 23; 24; 27; 28; 31g
zero-set(z0)=f1; 3; 5; 7; 9; 11; 13; 15; 17; 19; 21; 23; 25; 27; 19; 31g
cx3x2 x1x0
00 01 10 11
000 1111 0000 0001 0010
001 0011 0100 0101 0110
010 0111 1000 1001 1010
011 1011 1100 1101 1110
100 0001 0010 0011 0100
101 0101 0110 0111 1000
110 1001 1010 1011 1100
111 1101 1110 1111 0000
(z3; z2; z1; z0)
Table 2.4: Exercise 2.47(c)
Exercise 2.48
(a) A high-level description is
Input: x = (x3; x2; x1; x0), and xi 2 f0; 1g
Output: z 2 f0; 1; 2; 3; 4g
Function: 3
X
z = xi
i=0
(b) the table for arithmetic function and (c) the table for the switching functions considering binary
code for z are shown next:
x3x2 x1x0 z x3x2 x1x0 z2z1 z0
0000 0 0000 000
0001 1 0001 001
0010 1 0010 001
0011 2 0011 010
0100 1 0100 001
0101 2 0101 010
0110 2 0110 010
0111 3 0111 011
1000 1 1000 001
1001 2 1001 010
1010 2 1010 010
1011 3 1011 011
1100 2 1100 010
1101 3 1101 011
1110 3 1110 011
1111 4 1111 100
The one-sets that correspond to this table are:
one-set(z2 )=f15g
one-set(z1 )=f3; 5; 6; 7; 9; 10; 11; 12; 13; 14g

one-set(z0 )=f1; 2; 4; 7; 8; 11; 13; 14g
Exercise 2.49
(a)
Inputs: x; y where x; y 2 f0; 1; 2; 3g
Output: z 2 f0; 1; 2; 3; 4; 6; 9g
Function: z = x y
(b) The table for the arithmetic function is
x; y 0 1 2 3
0 0 0 0 0
1 0 1 2 3
2 0 2 4 6
3 0 3 6 9
(c) considering binary representation for inputs and outputs we obtain the following table:
x y z
i x1 x0 y1 y0 z3 z2 z1 z0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 0
2 0 0 1 0 0 0 0 0
3 0 0 1 1 0 0 0 0
4 0 1 0 0 0 0 0 0
5 0 1 0 1 0 0 0 1
6 0 1 1 0 0 0 1 0
7 0 1 1 1 0 0 1 1
8 1 0 0 0 0 0 0 0
9 1 0 0 1 0 0 1 0
10 1 0 1 0 0 1 0 0
11 1 0 1 1 0 1 1 0
12 1 1 0 0 0 0 0 0
13 1 1 0 1 0 0 1 1
14 1 1 1 0 0 1 1 0
15 1 1 1 1 1 0 0 1
one-set(z3 ) = f15g
one-set(z2 ) = f10; 11; 14g
one-set(z1 ) = f6; 7; 9; 11; 13; 14g
one-set(z0 ) = f5; 7; 13; 15g
Exercise 2.50 (a) A conditional expression is

(
L = ON if an odd number of switches are ON
OFF otherwise
The state of the light cannot be considered as an input because a feedback loop is formed and the
circuit generated with this loop will not be stable (it will oscillate for some combinations of the
switches).
(b) Calling w; x; y; z the four switches, the table for the switching functions is:
wxyz L
0000 0
0001 1
0010 1
0011 0
0100 1
0101 0
0110 0
0111 1
1000 1
1001 0
1010 0
1011 1
1100 0
1101 1
1110 1
1111 0
(c) The minimal sum of products expression for this function is
L = w0x0 y0 z + w0 x0yz0 + w0xy 0 z0 + w0xyz + wx0y 0 z0 + wx0yz + wxy 0z + wxyz0
Exercise 2.51
a)
Input: x | a decimal digit
Output: z | a decimal digit
Function: z = 9 x
b) The tables for the specied codes are shown in book. Inputs and outputs use the same code.
The exercise asks for only one case, but for the sake of completeness we show the solution for all
four cases.
b1) Tabular description of the function using Excess-6 code.
dec x = (x3; x2; x1; x0) z = (z3; z2; z1 ; z0)
0 0110 1111
1 0111 1110
2 1000 1101
3 1001 1100
4 1010 1011
5 1011 1010
6 1100 1001
7 1101 1000
8 1110 0111
9 1111 0110
z3 :one-set(6,7,8,9,10,11,12,13), dc-set(0,1,2,3,4,5)
z2 :one-set(6,7,8,9,14,15), dc-set(0,1,2,3,4,5)
z1 :one-set(6,7,10,11,14,15), dc-set(0,1,2,3,4,5)
z0 :one-set(6,8,10,12,14), dc-set(0,1,2,3,4,5)
c1) Switching expressions:
z3 = x3x02 + x3x2 x01 + x03 x2x1
z2 = x03 x2x1 + x3 x02x01 + x3x2 x1
z1 = x1
z0 = x00
b2) Tabular description of the function using 2-out-of-5 code.
dec x = (x4; x3; x2; x1; x0) z = (z4 ; z3; z2; z1; z0)
0 00011 00101
1 11000 01001
2 10100 10001
3 01100 00110
4 10010 01010
5 01010 10010
6 00110 01100
7 10001 10100
8 01001 11000
9 00101 00011
The dc-set is the same for all output functions and correspond to
dc-set(0,1,2,4,7,8,11,13,14,15,16,19,21,22,23,25,26,27,28,29,30,31)
z4 :one-set(20,10,17,9)
z3 :one-set(24,18,6,9)
z2 :one-set(3,12,6,17)
z1 :one-set(12,18,10,5)
z0 :one-set(3,24,20,5)
z4 = x4 x03 x2x01 x00 + x04 x3 x02x1 x00 + x4 x03 x02x01 x0 + x04 x3 x02 x01x0
b3) Tabular description of the function using 4,3,2,1 code. Since this code allows two representations
for some decimal values (such as 3 or 4) we adopted the representation with least number of 1 bits.
dec x = (x3; x2; x1; x0) z = (z3; z2; z1 ; z0)

0 0000 1110
1 0001 1101
2 0010 1100
3 0100 1010
4 1000 0110
5 0110 1000
6 1010 0100
7 1100 0010
8 1101 0001
9 1110 0000
z3 :one-set(0,1,2,3,6), dc-set(3,5,7,9,11,15)
z2 :one-set(0,1,2,8,10), dc-set(3,5,7,9,11,15)
z1 :one-set(0,4,8,12), dc-set(3,5,7,9,11,15)
z0 :one-set(1,13), dc-set(3,5,7,9,11,15)
z3 = x03x02 x01 + x03x02 x1x00 + x03x2 x01 x00 + x3 x02x01 x0

z2 = x03x02 x01 + x03 x02 x1x00 + x3x02 x01 x00 + x03 x2x1 x0
z1 = x03x02 x01x00 + x03 x2x01 x00 + x3 x02x01x0 + x3x2x01 x00
z0 = x03x02 x01x0 + x3 x2x01 x0
b4) Tabular description of the function using 8,-2,2,-1 code.

dec x = (x3; x2; x1; x0) z = (z3; z2; z1 ; z0)

0 0000 1011
1 0011 1000
2 0010 1001
3 1101 1110
4 1100 1111
5 1111 1100
6 1110 1101
7 1001 0010
8 1000 0011
9 1011 0000
z3 :one-set(0,2,3,12,13,14,15), dc-set(1,4,5,6,7,10)
z2 :one-set(12,13,14,15), dc-set(1,4,5,6,7,10)
z1 :one-set(0,8,9,12,13), dc-set(1,4,5,6,7,10)
z0 :one-set(0,2,8,12,14), dc-set(1,4,5,6,7,10)
z3 = x3x2 + x03x02 x1 + x03 x02x01 x00
z2 = x2
z1 = x01
z0 = x00
Exercise 2.52
(a)
Input:
x = (x3; x2; x1; x0) 2 f0; 1g4
Output:
z = (z 1; z0), where z 1 and z0 are in the range [0; 9], and z = 10z 1 + z0 .
Function:
z1 = BCD(z 1) = (z7; z6; z5; z4) and z0 = BCD(z 0 ) = (z3 ; z2; z1; z0), with zi 2 f0; 1g
P
As the value of x is x = 3i=0 xi 2i , we dene the digit values z 1 and z 0 as:
z 1 = x div 10
z 0 = x mod 10
(b)
Since 0 x 15 then z 1 2 f0; 1g, and therefore:
z7 = z6 = z5 = 0
one-set(z4 ) = f10; 11; 12; 13; 14; 15g
one-set(z3 ) = f8; 9g
one-set(z2 ) = f4; 5; 6; 7; 14; 15g
one-set(z1 ) = f2; 3; 6; 7; 12; 13g
Since z0 = z 0 mod 2 = (x mod 10) mod 2 = x0 then z0 = x0 .
Therefore :
z7 = 0
z6 = 0
z5 = 0
z4 = x3x02x1 x00 + x3x02 x1x0 + x3x2x01 x00 + x3 x2x01 x0 + x3x2 x1 x00 + x3x2x1 x0 = x3(x1 + x2)
z3 = x3x02x01 x00 + x3x02 x01x0 = x3x02x01
z2 = x03x2x01 x00 + x03x2 x01x0 + x03x2x1 x00 + x03x2x1 x0 + x3 x2 x1x00 + x3x2 x1x0 = x03 x2 + x3 x2x1
z1 = x03x02x1 x00 + x03x02 x1x0 + x03x2x1 x00 + x03x2x1 x0 + x3 x2 x01x00 + x3x2 x01x0 = x03 x1 + x3 x2x01
z0 = x0
Exercise 2.53
Let the inputs be a and b and the output w and z , all hexadecimal integers. A high-level description
is
(
w= a if a b
b otherwise
(
z= a if a < b
b otherwise
b) In the radix-2 representation all bit-vectors have four bits.
a = (a3; a2; a1; a0); b = (b3; b2; b1; b0)

z = (z3; z2; z1; z0) w = (w3; w2; w1; w0)
For the binary description we use the intermediate variables g; e; and s obtained from a comparison
of a and b, so that
zi = ai (g + e) + bis
wi = bi(g + e) + ais
Switching expressions for g; e, and s are
g = a3 b03 + e3 a2 b02 + e3e2 a1b01 + e3e2 e1 a0 b00

e = e3 e2e1 e0
s = g0e0
where ei = ai bi + a0i b0i
Exercise 2.54
a) A high level description of the priority encoder can be given as:
Input: x = (x7; x6; :::; x1; x0), with xi 2 f0; 1g.
Output: integer 0 z 7
Function:
z = k; where xk = 1 and (xj = 0 for every j < k)
b) In order to obtain switching expressions more easily, we divide the priority encoder into two
subsystems: a priority resolution system and an encoder. This is shown in Figure 2.16 in the
textbook.
The priority resolution subsystem has the same number of outputs as inputs, and gives a 1 on the
output that corresponds to the highest priority input that has value 1. So, the switching expressions
for the priority resolutor are
w0 = x0
w1 = x1 x00
w2 = x2 x01x00
w3 = x3 x02x01 x00
w4 = x4 x03x02 x01 x00
w5 = x5 x04x03 x02 x01 x00
w6 = x6 x05x04 x03 x02 x01x00
w7 = x7 x06x05 x04 x03 x02x01 x00
The second part is an encoder. If the output is represented in the binary code, we obtain the
following table:
w7 w6 w5 w4 w3 w2 w1 w0 z2 z2 z0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Now we can write the output switching expressions:
z0 = w1 + w3 + w5 + w7
z1 = w2 + w3 + w6 + w7
z2 = w4 + w5 + w6 + w7
c) For the output in Gray code we obtain the table:
w7 w6 w5 w4 w3 w2 w1 w0 z2 z1 z0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 1
0 0 0 0 1 0 0 0 0 1 0
0 0 0 1 0 0 0 0 1 1 0
0 0 1 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 1 0 1
1 0 0 0 0 0 0 0 1 0 0
The output expressions are
z0 = w1 + w2 + w5 + w6
z1 = w2 + w3 + w4 + w5
z2 = w4 + w5 + w6 + w7
Exercise 2.55
The combinational comparator module compares hexadecimal digits a and b. The output z has
three values called G; E , and S . A high-level specication is
8
>
< G if a > b
z = > E if a = b
: S if a < b
A tabular representation of this function is given next:
b
a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 E S S S S S S S S S S S S S S S
1 G E S S S S S S S S S S S S S S
2 G G E S S S S S S S S S S S S S
3 G G G E S S S S S S S S S S S S
4 G G G G E S S S S S S S S S S S
5 G G G G G E S S S S S S S S S S
6 G G G G G G E S S S S S S S S S
7 G G G G G G G E S S S S S S S S
8 G G G G G G G G E S S S S S S S
9 G G G G G G G G G E S S S S S S
10 G G G G G G G G G G E S S S S S
11 G G G G G G G G G G G E S S S S
12 G G G G G G G G G G G G E S S S
13 G G G G G G G G G G G G G E S S
14 G G G G G G G G G G G G G G E S
15 G G G G G G G G G G G G G G G E
For the binary description, digit a is represented by the vector a = (a3 ; a2; a1; a0) and digit b is
represented by b = (b3; b2; b1; b0). We encode the output variable z using 3 bits as follows:
z z2 z1 z0
G 1 0 0
E 0 1 0
S 0 0 1
We can derive switching expressions for the outputs considering the equality variable ei (bits ai
and bi are equal) and the conditional conditional expressions. The switching expressions are:
z2 = a3b03 + e3 a2 b02 + e3e2a1 b01 + e3e2e1 a0b00

z1 = e3 e2e1e0
z0 = b3a03 + e3 b2a02 + e3 e2b1a01 + e3 e2e1 b0a00
where e1 = a0i b0i + ai bi , equality function.
37
Chapter 3 (October 3, 2000)

38 Solutions Manual - Introduction to Digital Design - October 3, 2000
Exercise 3.1 (a) logic values

Voltage (V) Positive Logic Negative Logic
1.0 0 1
4.5 1 0
2.0 undened undened
-1.0 undened undened
(b) module has the following behavior (voltage levels):
Positive Logic Negative Logic
x1 x0 z x1 x0 z x1 x0 z
0.3 0.2 0.5 0 0 0 1 1 1

0.3 4.5 4.4 0 1 1 1 0 0
4.5 0.2 4.4 1 0 1 0 1 0
4.5 4.5 0.2 1 1 0 0 0 1
For positive logic, the module is a XOR gate. z = x0 x1 .

For negative logic, the module is a XNOR gate. z = (x0 x1 ) . 0
Solutions Manual - Introduction to Digital Design - October 3, 2000 39
Exercise 3.2 We can see from the gure that the switches S1 to S4 form a NAND gate and the
switches S5 to S8 implement a NOR gate. The organization of switches is such that we have the
NAND and the NOR gate implementations with the outputs connected together. This indicates
that the circuit was intended to implement the expressions ((ab)+(c + d) ) = (a + b )c d . However,
0 0 0 0 0 0
as indicated in the hint, for the case a = b = 1 and c = d = 0, there is a path from VDD to ground
passing through transistors S8, S7, S2, and S1. Consequently, this circuit does not operate correctly.
A correct circuit circuit for this function is shown in gure 3.1.
V
DD
a b
d
z
a c d
Figure 3.1: Network the implements the function z = (a + b )c d { Exercise 3.2

0 0 0 0
Exercise 3.3 The network on Figure 3.21 of the book corresponds to the expression: (abc + d) .
0
This function is implemented using AND and NOR circuits and also complex gates approach as
shown in Figure 3.2.
V
DD
d
a b c
a z
b d
(a) using AND and NOR circuits

V
DD
a b c d V
DD
(b) using complex gate approach
Figure 3.2: Function (abc + d) { Exercise 3.3

0
Exercise 3.4 The circuit that implements the function z = x0 x1 = (x0 + x1 ) is presented in
0 0 0
gure 3.3.
V
DD
x1
x0 z
x1
Figure 3.3: Exercise 3.4 - Circuit that implements z = (x0 + x1 )

0 0
Exercise 3.5 The circuit is similar to the one presented as an example for a transmission gate
(Figure 3.8 of the textbook).
When s = 1, the transmission gate in the bottom is ON and the transmission gate at the top
is OFF. When s = 0, the opposite happens. So, a switching expression for the circuit is:
z = b:s + a:s 0
Exercise 3.6
(a) the output load of gate 1 is 4, since this output is connected to 4 inputs of load 1.
(b) gate 6 has the output connected to two inputs (gates 7 and 8) with a total load of 4. The
remaining fanout of gate 6 is 4 loads (its original Fanout factor is 8).
Exercise 3.7 Based on the gure, and knowing that the propagation delay is measured based
on 50% of the voltage level transition (input to output), the propagation delay time is:
tpHL (NOR) = 4:5ns

tpLH (NOR) = 4:0ns
Exercise 3.8 Delay of the gate is tpHL = 0:43 + 0:15L (ns) and tpLH = 0:35 + 0:25L (ns). The
input and output waveforms for this gate are presented in Figure 3.4.
GATE TIMING
Input
0.58 0.60
output L=1
0.73 0.85
output L=2
Figure 3.4: Timing diagram, Exercise 3.8

Exercise 3.9 (a) For a load factor of L = 70 the propagation delays are:
tpHL = 0:43 + 0:15 70 = 10:93ns
tpLH = 0:35 + 0:25 70 = 17:85ns
(b) Using a buer with load factor of 2 and propagation time given by tpHL(buer) = tpLH (buer) =
0:6 + 0:02L(ns), the network consisting of a gate followed by the buer has a delay:
tpHL (gate&buer) = 0:43 + 0:15 2 + 0:6 + 0:02 70 = 2:73ns
tpLH (gate&buer) = 0:35 + 0:25 2 + 0:6 + 0:02 70 = 2:85ns
(c) using two buers we get:
tpHL (gate&2-buers) = 0:43 + 0:15 4 + 0:6 + 0:02 35 = 2:33ns
tpLH (gate&2-buers) = 0:35 + 0:25 4 + 0:6 + 0:02 35 = 2:65ns
(d) Optimum number of buers can be obtained by the generalization of the delay equation,
considering n as the number of buers:
tpHL (gate&n-buers) = 0:43 + 0:15 2n + 0:6 + 0:02 d70=ne = 1:03 + 0:3n + 0:02 d70=ne
tpLH (gate&n-buers) = 0:35 + 0:25 2n + 0:6 + 0:02 d70=ne = 0:95 + 0:5n + 0:02 d70=ne
The function has a minimum. We can see that for n = 3, the delays increase to tpHL = 2:41
and tpLH = 2:93, when compared to delays for n = 2. So, the best number of buers is 2, and the
load should be distributed in only 2 sets.
Exercise 3.10 From the gure we get the time tpLH = 3ns (12 ticks) and tpHL = 1:25ns (5
ticks).
Exercise 3.11 Noise margins are dened as:

V Hmin (OU T ) V Hmin(I N )
and
V Lmax(OU T ) V Lmax(I N )
Based on the values
e H (OU T ) f;
V
a VH (I N ) b;
g VL (OU T ) h;
c VL (I N ) d
we obtain the noise margins:

V Hmin(OU T ) V Hmin (I N ) = e a
and
V Lmax(OU T ) V Lmax(I N ) = h d
41
Chapter 4
Exercise 4.1
(a) gure 4.17(a) presents a valid gate network
(b) the network in gure 4.17(b) is not valid since:
the load factor (L) imposed to one of the 2-input AND gates exceeds the fan-out factor (F)
of this gate;
two outputs are connected together.
(c)gure 4.17(c) presents a valid network.
Exercise 4.2 There's no active loop in the network because variable b interrupts the loop in
two dierent points. When b = 0, the analysis of the network gives:
z1 = ad (4.1)
z0 = ad + c (4.2)
When b = 1, the output switching expressions are:
z1 = z0d (4.3)
z0 = e + c (4.4)
As we can see from the equations, there is no feedback of signals in the physical loop, and the
network is combinational.
Exercise 4.3
FROM TO
Gate Type Inputs Output X A1
A AND-2 A1 A3 Y A2
A2 W B1
B AND-2 B1 B3 Z B2
Gates: B2 Connections: A3 D1
C AND-2 C1 C3 A3 C1
C2 B3 D2
D OR-2 D1 D3 B3 E1
D2 C3 R
E NOT E1 E2 D3 C2
E2 T
Exercise 4.4 The network is shown in gure 4.1. It's a valid network.
R
A B
S
C E Z
T D
X
Y
Figure 4.1: Network for Exercise 4.4

Exercise 4.5
The network for this exercise is presented in Figure 4.2.
R A
B
S
Z
E C
T D

It is an invalid network since the outputs of gates D and E are connected to the same point.
As we don't know the function implemented by the net, any modication can be done to remove
this connection. One possible solution is given in the table that follows:
From To
R A1
S A2
A B1
B C1
E C2
T D1
A2 E1
D1 E2
D B2
C Z
Exercise 4.6
In gure 4.17, networks (a) and (c) are loop-free. Network (b) has a loop in one of the OR
gates.
In gure 4.20, network (a) has a loop and network (b) is loop-free.
Exercise 4.7 :
The operation specied by
g (x; y; z) = x0 yz + xy0 + y 0z
is universal because g (x; 1; 1) = x0 realizes the NOT operation, and g (x; 0; z ) = x + z realizes the
OR operation. Since the set fOR; NOT g is universal, the g operation is also universal.
Exercise 4.8 :
To show that the set fXNOR; ORg is universal it suces to show a realization of the NOT
operation. The XNOR operation is dened as
XNOR(x; y ) = xy + x0y 0
Assuming that the constant 0 is available, we have:
NOT (x) = XNOR(x; 0) = x:0 + x0 :1 = x0
Exercise 4.9
The function * is: x y = x0y . Observe that this function is not commutative (x y 6= y x).
For this reason, the order of inputs must be observed. The NOT gate is obtained as
x0 = x0 1 = x 1
The AND gate is mapped to the * function as:
x y = (x0)0 y = x0 y = (x 1) y
The networks to obtain the NOT and AND gates from the \*" gate are shown in Figure 4.3.
Since the * gate can implement the set fNOT,ANDg, and the set fNOT,ANDg is universal, the *
gate is also universal.
x x’ x
xy
* *
1 1 *
y
NOT gate AND gate
Figure 4.3: Implementing a NOT and AND gates using the * gate
Exercise 4.10
Using backward analysis, and the node names presented in gure 4.4.
x1
T2
z1
T1
x0 T3
z0
T4
Figure 4.4: NAND-NOR network for Exercise 4.9

z1 = (T2T3)0 z0 = (T3 + T4)0
= ((x1T1)0(T1x0 )0)0 = ((x0T1)0 + (T1 + x0 )0)0
= x1T1 + T1x0 = (x00 + T10 + T10 x00 )0
= T1(x1 + x0 ) = (x00 + T10 )0
= (x1x0 )0(x1 + x0 ) = x 0 T1
= (x01 + x00)(x1 + x0 ) = x0 (x1x0 )0
= x01x0 + x1x00 = x0 (x01 + x00)
= x1 x0 = x0 x01
Mixed logic notation could be used in this problem and the network could be transformed in
the one showed in gure 4.5. The equation obtained by backward analysis are now:
x1
T2
z1
T1
x0 T3
z0
T4
Figure 4.5: Mixed Logic Notation - Exercise 4.9

z 1 = T2 + T3 z 0 = T3 T4
= x1T1 + T1x0 = x0 T1(T1 + x0)
= T1(x1 + x0 ) = x 0 T1
= (x01 + x00)(x1 + x0 ) = x0 (x01 + x00)
= x01x0 + x1x00 = x0 x01
= x1 x0
The analysis turns out to be less complex.

Exercise 4.11
We obtain the following expressions:
z = ((x01 + x2x1 + x1x0 )(x2x1 + x2 x0 + x02 )(x2x0 + x1 x0 + x00 ))0
= ((x01 + x2 + x0 )(x02 + x1 + x0)(x00 + x1 + x2 ))0
= (x01 + x2 + x0 )0 + (x02 + x1 + x0 )0 + (x00 + x1 + x2 )0
= x1 x02 x00 + x2x01 x00 + x0 x01 x02
that is, the output is 1 whenever exactly two of the inputs are 0.
Exercise 4.12
We have:
z3 = x00
z2 = (x03 + x02)(x1 + x0 )(x01 + x00 )
z1 = (x3 + x0)(x02 + x1 )(x2 + x01 + x00)
z0 = x3 (x2 + x0 )(x2 + x1)
These switching functions are shown in the next table:

i x3 x2 x1 x0 z3 z2 z1 z0
0 0 0 0 0 1 0 0 0
1 0 0 0 1 0 1 1 0
2 0 0 1 0 1 1 0 0
3 0 0 1 1 0 0 0 0
4 0 1 0 0 1 0 0 0
5 0 1 0 1 0 1 0 0
6 0 1 1 0 1 1 0 0
7 0 1 1 1 0 0 1 0
8 1 0 0 0 1 0 1 0
9 1 0 0 1 0 1 1 0
10 1 0 1 0 1 1 1 0
11 1 0 1 1 0 0 0 1
12 1 1 0 0 1 0 0 1
13 1 1 0 1 0 0 0 1
14 1 1 1 0 1 0 1 1
15 1 1 1 1 0 0 1 1
Looking at the input values in the range 3 to 12 (that correspond to the decimal values 0 to 9
in excess-3 code), and reordering the output bits zi we obtain:
xEx 3 x3 x2 x1 x0 z0 z1 z2 z3 zBCD
0 0 0 1 1 0 0 0 0 0
1 0 1 0 0 0 0 0 1 1
2 0 1 0 1 0 0 1 0 2
3 0 1 1 0 0 0 1 1 3
4 0 1 1 1 0 1 0 0 4
5 1 0 0 0 0 1 0 1 5
6 1 0 0 1 0 1 1 0 6
7 1 0 1 0 0 1 1 1 7
8 1 0 1 1 1 0 0 0 8
9 1 1 0 0 1 0 0 1 9
The second table shows that the network implements an Excess-3 to BCD decoder.
Exercise 4.13
(a)The switching expressions are:
Eout = Ein I00 I10 I20 I30 I40 I50 I60 I70
G = Ein Eout0
z0 = Ein(I7 + I60 I5 + I60 I50 I40 I3 + I60 I40 I20 I1 )
z1 = Ein(I7 + I6 + I60 I50 I40 I3 + I50 I40 I2)
z2 = Ein (I7 + I6 + I60 I5 + I4 )
(b)Since a high-level description is not obvious from these expressions, we evaluate and present
the following table:
Ein I7 I6 I5 I4 I3 I2 I1 I0 Eout G z2 z1 z0
0 - - - - - - - - 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 0 1 0 1 0 0 0
1 0 0 0 0 0 0 1 - 0 1 0 0 1
1 0 0 0 0 0 1 - - 0 1 0 1 0
1 0 0 0 0 1 - - - 0 1 0 1 1
1 0 0 0 1 - - - - 0 1 1 0 0
1 0 0 1 - - - - - 0 1 1 0 1
1 0 1 - - - - - - 0 1 1 1 0
1 1 - - - - - - - 0 1 1 1 1
To get a high-level description we assume that the bit-vector z is the radix-2 representation of
the integer z . From the table we obtain:
(
z = j0 if Ij = 1 and Ik otherwise
= 0 for k > j and Ein = 1 (4.5)
(
Eout = 1 if Ein = 1 and Ij = 0 for all j (4.6)
0 otherwise
(
G= 1 if Ein = 1 and Ij = 1 for some j (4.7)
0 otherwise
In words, let us call Ein the module (network) enable. Then:
Eout is 1 when the module is enabled and all Ii inputs are 0.
G is 1 if the module is enabled and at least one of the Ii inputs is 1.
z corresponds to the highest index of the inputs Ii with value 1.
Such a network is called a priority encoder (studied in Chapter 9).
(c) The load factor of each input is calculated considering that each AND or NOT gate has an
input factor of 1.
Input Load Factor
Ein0 1
I70 2
I60 2
I50 2
I40 2
I30 2
I20 2
I10 2
I00 1
The maximum delay for the network is obtained considering number and type of gates of each
path from inputs to the outputs. The critical path in this case is the one that goes from input I60
to output z00 .
TpLH (I60 ; z00 ) = tpLH (NOT) + tpHL (NOT) + tpHL (AND-5) + tpHL(OR-4) + tpLH (NOT)
TpLH (I60 ; z00 ) = (0:02 + 0:038 2) + (0:05 + 0:017 3) + T1 + (0:45 + 0:025 1) + (0:02 + 0:038 L)
TpLH (I60 ; z00 ) = 0:692 + T1 + 0:038 L
TpHL(I60 ; z00 ) = tpHL (NOT) + tpLH (NOT) + tpLH (AND-5) + tpLH (OR-4) + tpHL (NOT)
TpHL(I60 ; z00 ) = (0:05 + 0:017 2) + (0:02 + 0:038 3) + T2 + (0:13 + 0:038 1) + (0:05 + 0:017 L)
TpHL(I60 ; z00 ) = 0:436 + T2 + 0:017 L
where T1 and T2 are the HL and LH propagation delays for an AND gate with 5 inputs and
load factor of 1, respectively. The values of T1 and T2 are obtained by decomposition of the AND-5
gate into the gates listed in Table 3.1 of the book. This decomposition is:
AND(x4; x3; x2; x1; x0) = AND(AND(x4; x3; x2); AND(x1; x0))
The resulting delays are:
T1 = tpHL(AND-3) + tpHL (AND-2) = 0:18 + 0:018 + 0:16 + 0:017L = 0:358 + 0:017L = 0:392
T2 = tpLH (AND-3) + tpLH (AND-2) = 0:2 + 0:038 + 0:15 + 0:037L = 0:388 + 0:037L = 0:462
The delays of the critical path become:

TpHL(I60 ; z00 ) = 0:436 + 0:462 + 0:017L = 0:90 + 0:017L
TpLH (I60 ; z00 ) = 0:692 + 0:392 + 0:038L = 1:08 + 0:038L
(d) Timing diagram, see gure 4.6:

AND-5
I6’ A B C z0 z0’
AND3 AND2 OR4
I6’
0.084 0.096
A
0.101
0.134
B
0.392
0.462
C
0.168 0.475
z
0.05+0.017L
0.02+0.038L
z0’
Figure 4.6: Timing diagram of Exercise 4.13
Exercise 4.14 (a) The switching expression for output z is

z = E (I0s02 s01s00 + I1s02s01 s0 + I2 s02s1 s00 + I3 s02 s1 s0 + I4s2 s01 s00 + I5 s2 s01 s0 + I6 s2 s1s00 + I7s2s1 s0 )
or
7
X
z=E Iimi (s2; s1 ; s0)
i=0
(b) A high-level description is
(
z = I0s ifotherwise
E=1
where s = 4s2 + 2s1 + s0 .

This function corresponds to an 8-input multiplexer (selector), that is discussed in Chapter 9
of the textbook.
(c) The load factor of each input is 1, since each input is connected to only one gate input in
the circuit.
The load applied to each gate is:
gate Load
NOT connected to E 0 8
NOT gates connected to si 5
NOT gates to restore si 4
AND gates 1
OR gate L1 + 1
NOT used to generate z 0 L2
where, L1 and L2 are the Load imposed to the outputs z and z 0 respectively.
The delay of this network cannot be calculated based on the table given because there are no
expressions for an AND gate with 5 inputs and an OR gate with 8 inputs. Calling these delays:
tpLH (AND-5) = T1
tpHL(AND-5) = T2
tpLH (OR-8) = T3
tpHL(OR-8) = T4
the critical path delay is:
tpLH (s2; z0) = tpLH (NOT) + tpHL (NOT) + tpHL (AND-5) + tpHL(OR-8) + tpLH (NOT)
= 0:02 + 0:038 5 + 0:05 + 0:017 4 + T2 + T4 + 0:02 + 0:038 L2
= 0:35 + T2 + T4 + 0:038 L2
0
tpHL(s2 ; z ) = tpHL (NOT) + tpLH (NOT) + tpLH (AND-5) + tpLH (OR-8) + tpHL(NOT)
= 0:05 + 0:017 5 + 0:02 + 0:038 4 + T1 + T3 + 0:05 + 0:017 L2
= 0:36 + T1 + T3 + 0:017 L2
The values of T1 ; T2; T3 and T4 are obtained by decomposition of the AND-5 and OR-8 gates
into the gates listed in Table 3.1 of the book. This decomposition is:
AND(x4; x3; x2; x1; x0) = AND(AND(x4; x3; x2); AND(x1; x0))
and
OR(x7; x6; : : :; x1; x0) = OR(OR(x7; x6; x5; x4); OR(x3; x2; x1; x0)
The resulting delays are:
T1 = tpLH (AND-3) + tpLH (AND-2) = 0:2 + 0:038 + 0:15 + 0:037 = 0:43
T2 = tpHL(AND-3) + tpHL (AND-2) = 0:18 + 0:018 + 0:16 + 0:017 = 0:38
T3 = tpLH (OR-4) + tpLH (OR-2) = 0:13 + 0:038 + 0:12 + 0:037(L1 + 1) = 0:33 + 0:037L1
T4 = tpHL(OR-4) + tpHL(OR-2) = 0:45 + 0:025 + 0:2 + 0:019(L1 + 1) = 0:69 + 0:019L1
(d) timing diagram presented in gure 4.7.
AND-5 OR-8
s2 A B C z z’
AND3 AND2 OR4 OR2
s2
0.14 0.21
A
0.12
0.17
B
0.38
0.43
C
0.33+0.037L1 0.69+0.019L1
z
0.05+0.017L2
0.02+0.038L2
z’
Figure 4.7: Timing diagram of Exercise 4.14
Exercise 4.15
We dene the modules as indicated in gure 4.8. For module M1 we obtain the switching
expression:
y = (abc + ab0c0 + a0bc0 + a0b0c)0
A high-level description is:
(
y = 10 otherwise
if there are 0 or 2 inputs with value 1 (4.8)
Module M1 implements a 3-input even-parity function which we denote EP (a; b; c).

Module M2 has three inputs e, f and g , and two outputs z1 and z0 . The switching expressions
are:
z1 = (efg + ef 0 g 0 + e0 fg 0 + e0 f 0g )0
z0 = (e0f 0g0 + e0 fg + ef 0 g + efg 0)0
The rst expression corresponds to the even-parity function EP (e; f; g ) and the second one to
the odd-parity function OP (e; f; g ).
By substitution we obtain:
z1 = EP (EP (I8; I7; I6); EP (I5; I4; I3); EP (I2; I1; I0)) = OP (I8; I7; :::; I0)
since an even number of groups (among 3 groups) with an even number of 1 inputs correspond to
an odd number of 1 inputs overall.
z0 = OP (EP (I8; I7; I6); EP (I5; I4; I3); EP (I2; I1; I0)) = EP (I8 ; I7; :::; I0)
since an odd number of groups (among 3 groups) with an even number of 1 inputs correspond to
an even number of 1 inputs overall.
That is, the network implements the even-parity and odd-parity functions of nine inputs.
I8 I7 I6 I5 I4 I3 I2 I1 I0
a b c a b c a b c
M1 M1 M1
y y y
e f g
M2
z1 z0
Figure 4.8: Modules used in Exercise 4.15
Delay of the network is obtained by the following expression for the path from input I2 to
output z1 :
TpLH (I2 z1) = tpLH (NOT ) + tpHL(OR-4) + tpHL(AND-3) + tpHL(NOT) +

tpLH (NOT) + tpHL (OR-4) + tpHL (AND-3) + tpHL(NOT) + tpLH (NOT)
= 0:02 + 0:038L + 0:45 + 0:025 1 + 0:18 + 0:018 1 + 0:05 + 0:017 4 +
0:02 + 0:038 5 + 0:45 + 0:025 1 + 0:18 + 0:018 1 + 0:05 + 0:017 2 +
0:02 + 0:038 3
= 1:91 + 0:038L
TpHL(I2 z1) = tpHL (NOT ) + tpLH (OR-4) + tpLH (AND-3) + tpLH (NOT) +
tpHL (NOT) + tpLH (OR-4) + tpLH (AND-3) + tpLH (NOT) + tpHL(NOT)
= 0:05 + 0:017L + 0:13 + 0:038 1 + 0:2 + 0:038 1 + 0:02 + 0:038 4 +
0:05 + 0:017 5 + 0:13 + 0:038 1 + 0:2 + 0:038 1 + 0:02 + 0:038 2 +
0:05 + 0:017 3
= 1:37 + 0:017L
Exercise 4.16 We partition the network as shown in Figure 4.9.
C A B A B A B A B
0 0 0 1 1 2 2 3 3
M0 M0 M0 M0
y z
x
x0 x1 x2 x3
M1 M2 M3 M4
c0
c1 c2 c3
M5 M5 M5 M5
S S S S C
0 1 2 3 4
Figure 4.9: Modules used in Exercise 4.16

Module M0 has two inputs a and b, and three outputs x, y and z . In particular, as marked in
the gure, the output x of each module M0 is used as an input to a module M5 . The expressions
for the outputs of module M0 which has inputs Ai and Bi are:
xi = (Ai + Bi )zi = (Ai + Bi )(A0i + Bi0 ) = Ai Bi
yi = (Ai + Bi )0 = A0i Bi0
zi = (Ai Bi)0 = A0i + Bi0
Module M1 implements the expression:
c1 = (c00z0 + y0 )0 = (c0 + z00 )y00 = c0y00 + z00 y00 = c0(A0 + B0 ) + A0 B0
because zi0 yi0 = Ai Bi (Ai + Bi ) = Ai Bi = zi0 .
The same way we obtain the expressions for M2 , M3 and M4 as:
c2 = (c00z0 z1 + y0z1 + y1)0
= ((c00z0 + y0 )z1 + y1 )0 = (c01 z1 + y1 )0 = c1y10 + z10 = c1 (A1 + B1 ) + A1 B1
c3 = (c00z0z1z2 + y0 z1 z2 + y1 z2 + y2 )0
= ((c0z0 z1 + y0 z1 + y1 )z2 + y2 )0 = (c02z2 + y2 )0 = c2 y20 + z20 = c2(A2 + B2 ) + A2 B2
c4 = (c00z0z1z2 z3 + y0 z1 z2 z3 + y1z2 z3 + y2 z3 + y3 )0
= ((c0z0 z1 z2 + y0 z1 z2 + y1 z2 + y2 )z3 + y3 )0 = (c03z3 + y3 )0 = c3 (A3 + B3 ) + A3 B3
From these previous expressions we obtain a general form:
ci+1 = (Ai + Bi )ci + AiBi
Module M5 implements the expression:
Si = ci xi = ci Ai Bi
To prove that the circuit implements a 4-bit adder we will show that it works for 2-bit addition,
and claim that the circuit works for 4 bits, based on the regularity of the circuit implementation.
Perfect induction over all the possible inputs is practically impossible, given the large number of
input combinations. From the previous equations, we are able to build the following switching
function table for the internal variables c2; c1; p1; and p0 :
c0B1 B0 A1A0
00 01 10 11
000 0000 0001 0010 0011
001 0001 0100 0011 1110
010 0010 0011 1000 1001
011 0011 1110 1001 1100
100 0000 0101 0010 1111
101 0101 0100 1111 1110
110 0010 1111 1000 1101
111 1111 1110 1101 1100
c2c1 p1p0
Since Ai = Bi = 0 for i > 1, that implies p2 = p3 = 0 and c3 = c4 = 0. With these conditions,
the above table, and knowing that Si = pi ci we have:
S3 = 0
S2 = c2
S1 = p1 c1
S0 = p0 c0
and the following table results to show the relation of inputs and outputs of the given circuit:
c0 B1 B0 A1A0
00 01 10 11
000 000 001 010 011
001 001 010 011 100
010 010 011 100 101
011 011 100 101 110
100 001 010 011 100
101 010 011 100 101
110 011 100 101 110
111 100 101 110 111
c2S1S0
Observe that the table describes the function of a 2-bit adder, with a carry-in bit c0. From this
result, taking into account the regularity of the design, we claim that the design implements a 4-bit
adder.
55
Chapter 5
Exercise 5.1
z z
0 1 0 1 - 0 1 1
x 0 1 0 0 x - 0 0 1
f1 y f0 y
Exercise 5.2
(a) the K-map for E (x; y; z ) =
P m(1; 5; 7) is:
z
0 1 0 0
x 0 1 1 0
y
(b)E (w; x; y; z ) = w x y + y z + xz
0 0 0 0
z
0 1 1 1
1 1 0 1
x
1 1 0 1
w
0 1 0 0
y
Exercise 5.3
Q P
(a) E (w; x; y; z ) = M (1; 3; 4; 7; 10; 13; 14; 15) = m(0; 2; 5; 6; 8; 9; 11; 12)
z
1 0 0 1
0 1 0 1
x
1 0 0 0
w
1 1 1 0
y
(b)E (w; x; y; z ) =
P m(0; 4; 5; 9; 11; 14; 15); dc(w; x; y; z ) = P m(2; 8)
z
1 0 0 -
1 1 0 0
x
0 0 1 1
w
- 1 1 0
y
P
(c) E (x; y; z ) = m(0; 1; 4; 6) = Q M (2; 3; 5; 7)
z
1 1 0 0
x 1 0 0 1
y
Exercise 5.4 f (w; x; y; z) = P m(0; 1; 2; 3; 5; 7; 8; 10; 11; 15)
(a) Kmap and prime implicants
z

1

1 1
1
0
1 1 0
x
0 0 1 0
w
1 0
1 1
y
prime implicants: w x ; w z; x y; yz; x z
0 0 0 0 0 0
(b) essential prime implicants: w z; yz; x z

0 0 0
(c)The minimal sum of products for this function is unique:

f (w; x; y; z) = w z + yz + x z
0 0 0
Exercise 5.5
(a) More implicants than minterms
z

0
1
1 0
x 0 0 0 0
y
implicants: x yz; x y z , and x z
0 0 0 0
minterms: x yz and x y z
0 0 0
(b) Equal number of implicants and minterms

z

1 0 0 0
x 0 0 0 0
y
implicant: x y z
0 0 0
minterm: x y z
0 0 0
Exercise 5.6
Q P
(a) E (w; x; y; z ) = M (1; 3; 4; 7; 10; 13; 14; 15) = m(0; 2; 5; 6; 8; 9; 11; 12)
z

1 0 0
1
0
1 0
1 x
1 0 0 0
w
1

1 1 0
y
minimal sum of products: wy z + wx z + w x z + w yz + w xy z

0 0 0 0 0 0 0 0 0 0
x

1
0 0 1

0
1 0 1
w
1
0
0 0
z
1 1 1
0
y
minimal product of sums: (w + x + z )(w + y + z )(x + y + z )(w + x + z )(w + x + y + z )

0 0 0 0 0 0 0 0 0 0
(b)E (w; x; y; z ) =
P m(0; 4; 5; 9; 11; 14; 15); dc(w; x; y; z ) = P m(2; 8)
z

-
1 0 0

1 1
0 0 x
0 0
1 1
w
-
1 1 0
y
minimal SP: w y z + w y x + wx z + wxy
0 0 0 0 0 0
z

1 0

0
-
1 1
0 0 x
0 0 1 1
w

- 1 1 0
y
minimal PS: (w+x+z')(w+y')(x+y'+z)(w'+x'+y)
P Q
(c) E (x; y; z ) = m(0; 1; 4; 6) = M (2; 3; 5; 7)
z

1 1 0 0
x 1 0 0
1
y
minimal sum of products: x y + xz 0 0 0
z

1 1
0 0

x 1
0 0 1
y
minimal product of sums: (x + y )(x + z ) 0 0 0
Exercise 5.7
f (w; x; y; z) = one set(1; 5; 7; 8; 9; 10; 14)
z

0 1
0 0

0
1 1
0 x
0 0 0 1
w

1 1
0 1
y
(a) prime implicates are:
(w + z ); (w + x + y ); (x + y + z ); (w + y + z ); (w + x + z ); (w + x + y ); (x + y + z )
0 0 0 0 0 0 0 0 0 0 0 0
(b) essential prime implicate is: (w + z )

(c) a minimal product of sums expression that implements f (w; x; y; z ) is:
E (w; x; y; z) = (w + z)(x + y + z )(w + x + z )(x + y + z)
0 0 0 0 0 0
the solution is not unique because there are other ways to cover the 0-cells (not covered by the
essential prime implicate) with the same number of terms.
Exercise 5.8
Input: (a; b; c; d), with a; b; c; d 2 f0; 1g
Output: y 2 f0; 1g
Function: (
y = 10 if (8a + 4botherwise
+ 2c + d) is prime
input value abcd y

0 0000 0
1 0001 0
2 0010 1
3 0011 1
4 0100 0
5 0101 1
6 0110 0
7 0111 1
8 1000 0
9 1001 0
10 1010 0
11 1011 1
12 1100 0
13 1101 1
14 1110 0
15 1111 0
d

0 0
1 1

0 1
1 0
b
0
1 0 0
a
0 0 1 0
c
From the Kmap we get the following prime implicants: a bd; b cd; a b c; a cd, and bc d
0 0 0 0 0 0
The essential prime implicants are: b cd; a b c, and bc d

0 0 0 0
A minimal sum of products for function y is:

y = b cd + a b c + bc d + a cd
0 0 0 0 0
and the gate network that implements this expression is shown in Figure 5.1.
d

0 0 1 1

0 1 1 0
b
0 1
0 0
a

0 0 1 0
c
b’
c
d
a’
b’
c y
b
c’
d
a’
c
d
Figure 5.1: AND-OR gate network for \prime detector" (Exercise 5.8)
From the Kmap we get the following prime implicates: (b + d); (a + d); (b + c); (c + d) and (a +
0 0 0
b + c ). Only the (c + d) prime implicate is not essential. So, the minimal product of sums in this
0 0
case is:
y = (b + d)(a + d)(b + c)(a + b + c )
0 0 0 0 0
and the gate network that implements this expression is shown in Figure 5.2. Notice that the cost
of the product of sums is lower.
b’
d
a’
d
y
b
c
a’
b’
c’
Figure 5.2: OR-AND gate network for \prime detector" (Exercise 5.8)
Exercise 5.9
To repeat the Exercise 5.8 using the Quine-McCluskey minimization method we make use of
two tables. The rst table is used to obtain the prime implicants and the second to select the
minimum cover.
The one set for this function is one set= f2; 3; 5; 7; 11; 13g
Minterms 3-literal Prods 2-literal Prods 1-literal Prods
0010 N 001-
0011 N -101
0101 N -011
0-11
0111 N 01-1
1011 N
1101 N
The second table consider the prime-implicants obtained in the previous table:
Prime Implicants 2 3 5 7 11 13 Essential
001- x x
-101 x x
-011 x x
0-11 x x
01-1 x x
Based on the table, the function is represented by 3 essential terms and the minterm 7 must be
covered with either 0 11 or 01 1. The minimal SP expressions are:
y = a b c + bc d + b cd + a cd
0 0 0 0 0
or
y = a b c + bc d + b cd + a bd
0 0 0 0 0
Exercise 5.10 A high-level description for this system is:
Input: a; b; c; d; e 2 f0; 1g
Output: f 2 f0; 1g
Function: (
(a + b + c + d + e) 3
f = 10 ifotherwise
Using Quine-McCluskey minimization method we obtain the following table:
Minterms 4-literal products 3-literal products
00111 N 0-111 N --111
01011 N -0111 N -1-11
10011 N 01-11 N 1--11
01101 N 10-11 N -11-1
10101 N 1-011 N 1-1-1
11001 N 011-1 N 11- -1
01110 N -1101 N -111-
10110 N 101-1 N 1-11-
11010 N 1-101 N 11-1-
11100 N 110-1 N 111--
11-01 N
01111 N 0111- N
10111 N -1110 N
11011 N 1011- N
11101 N 1-110 N
11110 N 1101- N
11-10 N
11111 N 1110- N
111-0 N
-1111 N
1-111 N
11-11 N
111-1 N
1111- N
To obtain a cover for the minterms we use a second table to identify the essential prime impli-
cants, as shown below:
7 11 13 14 15 19 21 22 23 25 26 27 28 29 30 31 Essential Prime
- -111 x x x x
-1-11 x x x x
1--11 x x x x
-11-1 x x x x
1-1-1 x x x x
11- -1 x x x x
-111- x x x x
1-11- x x x x
11-1- x x x x
111-- x x x x
All the terms obtained in the rst table are essential prime implicants. The minimal expression
is:
f = abc + abd + abe + acd + ace + ade + bcd + bce + bde + cde
and the corresponding two-level gate network is shown in Figure 5.3 on page 68. Note that the OR
gate has 10 inputs, which might make a two-level implementation impractical.
a
b
d
a
b
c
b
c
d
a
c
d
c
d
e f
b
c
e
b
d
e
a
b
e
a
d
e
a
c
e
Figure 5.3: Majority function - Exercise 5.10

Exercise 5.11 A high-level specication for the error detector is:
Input: x is a 2-out-of-5 code represented as x = (a; b; c; d; e), where a; b; c; d; e 2 f0; 1g.
Output: f 2 f0; 1g.
Function: (
f = 01 ifotherwise
the number of 1s in the input is 2
The synthesis of this function using Quine-McCluskey minimization method is shown in Table
5.1. The obtained 3-literal products generate a Prime-implicant chart similar to the one shown in
Exercise 5.10, where it was concluded that all products are essential. The minimal sum of products
is:
f = a b c d + abc + abd + acd + bcd + abe + ace + ade + bce + bde + cde
0 0 0 0
+a b c e + a b d e + a c d e + b c d e
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The gate network that implements the function f is shown in Figure 5.4. Note that the OR
gate has 15 inputs, which might make a two-level implementation impractical.
Minterms 4-literal prods 3-literal prods

00000 N 0000- --111
000-0 -1-11
00001 N 00-00 -11-1
00010 N 0-000 -111-
00100 N -0000 1--11
01000 N 1-1-1
10000 N 0-111 N 1-11-
-0111 N 11- -1
00111 N 01-11 N 11-1-
01011 N -1011 N 111--
01101 N 011-1 N
01110 N -1101 N
10011 N 0111- N
10101 N -1110 N
10110 N 1-011 N
11001 N 10-11 N
11010 N 1-101 N
11100 N 101-1 N
1-110 N
01111 N 1011- N
10111 N 11-01 N
11011 N 110-1 N
11101 N 11-10 N
11110 N 1101- N
111-0 N
11111 N 1110- N
1111- N
111-1 N
11-11 N
1-111 N
-1111 N
Table 5.1: Quine-McCluskey table for Exercise 5.11

a
b
c
a
b
d
a
c
d
b
c
d
a
b
e
a
c
e
a
d
e
b
c f
e
b
d
e
c
d
e a’
b’
c’
a’ e’
b’
d’
e’ a’
c’
d’
b’ e’
c’
d’
e’
a’
b’
c’
d’
Exercise 5.12 A high-level specication for this exercise is:

Input: a; b 2 f0; 1; 2; 3g and c 2 f0; 1g.
in
Output: z 2 f0; 1; 2; 3; 4; 5; 6; 7g
Function: z = a + b + cin
The input is represented by 2-bit vectors (a1; a0) and (b1; b0), and the output is represented
by a 3-bit vector z = (z2; z1; z0). Using Quine-McCluskey tabular method we obtain the following
tables, based on the switching function table presented in Exercise 2.46. The synthesis for z0 is
shown in Table 5.2, z1 is shown in Table 5.3, and z2 is shown in Table 5.4.

00001 N 000-1 N 0-0-1
00100 N 0-001 N 0-1-0
10000 N 001-0 N 1-0-0
0-100 N
00011 N 100-0 N 1-1-1
00110 N 1-000 N
01001 N
01100 N 0-011 N
10010 N 0-110 N
z0 11000 N 010-1 N
011-0 N
01011 N 1-010 N
01110 N 110-0 N
10101 N
11010 N 101-1 N
1-101 N
10111 N
11101 N 1-111 N
111-1 N
11111 N
1 3 4 6 9 11 12 14 16 18 21 23 24 26 29 31 Essential Prime
0-0-1 x x x x
0-1-0 x x x x
1-0-0 x x x x
1-1-1 x x x x
Table 5.2: Exercise 5.12 - synthesis of z0 output


00010 N 0001-
01000 N 00-10
00011 N -0010
00101 N 0100-
00110 N 01-00
01001 N -1000
01100 N
10001 N -0101
z1 10010 N 10-01
10100 N 1010-
11000 N
-1111
10101 N 11-11
1111-
01111 N
11011 N
11110 N
11111 N
2 3 5 6 8 9 12 15 17 18 20 21 24 27 30 31 Essential Prime
0001- x x
00-10 x x
-0010 x x
0100- x x
01-00 x x
-1000 x x
-0101 x x
10-01 x x
1010- x x
-1111 x x
11-11 x x
1111- x x

Minterms 4-literal prods 3-literal prods 2-literal prods

01010 N 0101- N 01-1- N -1-1-
01-10 N -101- N
00111 N -1010 N -1-10 N
01011 N
01101 N 0-111 N - -111
01110 N -0111 N -1-11 N
10011 N 01-11 N -11-1
10110 N -1011 N -111- N
11001 N 011-1 N 1- -11
11010 N -1101 N 1-11-
11100 N 0111- N 11- -1
-1110 N 11-1- N
01111 N 10-11 N 111--
z2 10111 N 1-011 N
11011 N 1011- N
11101 N 1-110 N
11110 N 110-1 N
11-01 N
11111 N 1101- N
11-10 N
1110- N
111-0 N
-1111 N
1-111 N
11-11 N
111-1 N
1111- N
7 10 11 13 14 15 19 22 23 25 26 27 28 29 30 31 Essential Prime
-1-1- x x x x x x x x
- -111 x x x x
-11-1 x x x x
1--11 x x x x
1-11- x x x x
11- -1 x x x x
111-- x x x x

The resulting expressions are:
z0 = x0y0c + x0 y0 c + x0y0 c + x0 y0 c
in
0 0
in
0 0
in
0 0
in
z1 = x1 x0y1 c + x1 y1 y0c + x1x0 y1 y0

0 0
in
0 0
in
0 0
+ x1 x0y1 c + x1 y1 y0 c + x1 x0 y1 y0
in in
+ x1 x0y1 c + x1 y1 y0 c + x1 x0 y1 y0
0 0 0
in
0 0 0
in
0 0 0
+ x1 y1 y0 c + x1 x0 y1 c + x1 x0 y1 y0
0 0 0
in
0 0 0
in
0 0 0
z2 = x1y1 + x1 x0y0 + x0 y1 y0 + y1 y0c + x0 y1 c + x1 x0 c + x1y0 c in in in in
The AND-OR networks are shown in Figure 5.5. They assume that the complement of inputs are
also available. Because of the large number of inputs to the OR gates, a two-level implementation
might not be practical.
x0
y0
cin
x0’
y0’
cin z0
x0 x1
y0’
cin’ y1
x0’ x1
y0 x0
cin’ y0 z2
x1’ total of 7 AND gates

x0 x1
y1’ y0
y0’ cin
z1
total of 12 AND gates

x1
x0’
y1’
y0’

Exercise 5.13
Input: x in the range [0; 15]
Output: y in the range [0; 7]
Function: y = x mod 7
The switching functions are shown in the table
x = (x3 x2x1 x0 ) y = (y2 y1 y0)
0000 000
0001 001
0010 010
0011 011
0100 100
0101 101
0110 110
0111 000
1000 001
1001 010
1010 011
1011 100
1100 101
1101 110
1110 000
1111 001
From K-maps (not shown) we obtain the following minimal switching expressions
y2 = (x3 + x2 )(x2 + x1 + x0)(x3 + x1 + x0 )(x2 + x1)
0 0 0 0 0
= x2 x1 + x3 x2x1 x0 + x3 x2 x0
0 0 0 0
y1 = (x3 + x1 )(x1 + x0 )(x3 + x2 + x0)(x3 + x2 + x1 )(x3 + x1 + x0)

0 0 0 0 0 0 0 0
= x3 x1x0 + x3x2 x1 + x3 x1 x0 + x2 x1x0

0 0 0 0 0 0 0
y0 = (x3 + x0 )(x3 + x2 + x0 )(x3 + x1 + x0 )(x2 + x1 + x0)(x3 + x2 + x1 )

0 0 0 0 0 0 0 0
= x3 x1x0 + x3x2 x0 + x3 x2 x1x0 + x3x1 x0 + x3 x2 x0

0 0 0 0 0 0 0 0
Using the lowest cost version of the network that produces each output, we obtain the gate
network shown in Figure 5.6.
x2
x1’
x3’ y2
x2 x3
x0’
x3 x0
x2’
x1 x3’
x0 x2
x0’
x3 x3’ y0
x1’ x1
x0 x0’
x3’ x2’
x2’ y1
x1’
x1 x0
x3’ x3
x1 x2’
x0’ x1’
x2’
x1
x0’
Figure 5.6: Exercise 5.13

Exercise 5.14
The multiplier is specied as follows:
Inputs: x; y where x; y 2 f0; 1; 2; 3g
Output: z 2 f0; 1; 2; 3; 4; 6; 9g
Function: z = x y
Coding the inputs and outputs in a binary code, produces the switching function of the following
table:
x y z
x1 x0 y1 y0 z3 z2 z1 z0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 0 1
From the table we get the following K-maps and expressions for the multiplier binary outputs:
y0 y0 y0
0 0 0 0 0 0 0 0 0 0 0 0

0 0 0
0 x0 0 0
1 1 x
0
0 1 1 0 x
0
0 0
x1 0 1
x1 0 1 0
1
x1 0 1 1
0
0 0
1 1

0
1 1 0 0 0 0 0
z2 y1 z1 y1 z0 y1
z 0 = x 0 y0
z1 = x1x0 y0 + x0y1y0 + x1x0y1 + x1y1 y0
0 0 0 0
z2 = x1x0y1 + x1y1 y0
0 0
Output z3 corresponds to only one minterm (no Kmap is needed in this case):
z3 = x1x0 y1y0
The NAND-NAND network is obtained directly from the sum of products. The correspoding
network is presented in Figure 5.7.
x0
z0
y0
x1
x0’
y0
x0
y1
y0’ z1
x1’
x0
y1
x1
y1’
y0
x1
x0’
y1 z2
x1
y1
y0’
x1
x0 z3
y1
y0
Figure 5.7: Network for a 2x2 bit multiplier. Exercise 5.14

Exercise 5.15
Input: binary code represented as b = (b3b2 b1b0), where b 2 f0; 1g i
Output: Gray code represented as g = (g3g2 g1g0), where g 2 f0; 1g i
Function: g is the Gray code that corresponds to b. The correspondence between binary and
Gray codes is shown in the following table:
Binary Gray
b3 b2b1 b0 g3g2 g1g0
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000
The correspoding Kmaps are as follows:
g3 g2
b0 b0

0 0 0 0
0 0 0 0
0 0 0 0
b2 1 1 1 1
b2
1 1 1 1 0 0 0 0
b3 b3
1 1 1 1 1 1 1 1
b1 b1
g1 g0
b0 b0

0 0 1 1
0 1 0 1

1 1 0 0 0 1 0 1
b2 b2
1 1
0 0 0 1 0 1
b3 b3
0 0 1 1
0 1
0 1
b1 b1
To obtain a NOR-NOR network we produce the minimal product of sums:

g3 = b3
g2 = (b2 + b3)(b2 + b3 )
0 0
g1 = (b1 + b2)(b1 + b2 )
0 0
g0 = (b0 + b1)(b0 + b1 )
0 0
The gate network is presented in Figure 5.8.
b0
b1
g0
b0’
b1’
b1
b2
g1
b1’
b2’
b2
b3
g2
b2’
b3’
b3 g3

Minterms 3-literal prods 2-literal prods 1-literal prods

1000 N 100- N 1-0- N 1-- -
10-0 N 10- - N
1001 N 1-00 N 1- -0 N
1010 N 1-0- N
1100 N 10-1 N
1-01 N 1- -1 N
g3 1011 N 101- N 11- - N
1101 N 1-10 N 1-1- N
1110 N 110- N
11-0 N
1111 N
1-11 N
11-1 N
111- N
Table 5.5: Exercise 5.16 - synthesis of g3 output

0100 N 010- N 01- -
1000 N 01-0 N 10- -
100- N
0101 N 10-0 N
g2 0110 N
1001 N 01-1 N
1010 N 011- N
10-1 N
0111 N 101- N
1011 N
Exercise 5.16
Using Quine-McCluskey minimization method to solve Exercise 5.15 we get Tables 5.5, 5.6, 5.7,
and 5.8. Minterms are obtained from the switching function presented in Exercise 5.15. From the
QM tables we obtain the expressions:
g3 = b3
g2 = b2b3 + b2b3
0 0
g1 = b1b2 + b1b2
0 0
g0 = b0b1 + b0b1
0 0

0010 N 001- N -01-
0100 N -010 N -10-
010- N
0011 N -100 N
g1 0101 N
1010 N -011 N
1100 N 101- N
-101 N
1011 N 110- N
1101 N

0001 N 0-01 N - -01
0010 N -001 N - -10
0-10 N
0101 N -010 N
g0 0110 N
1001 N -101 N
1010 N -110 N
1-01 N
1101 N 1-10 N
1110 N

Exercise 5.17
A high-level specication of the system is:
Input: x is an alphanumeric character coded in ASCII
Output: z 2 f0; 1g
Function: (
if x 2 fA; B; C; D; E g
z = 01 otherwise (5:1)
x6 x5 x4 x3 x2 x1 x0 z
A 1 0 0 0 1 0 0 1
B 1 0 0 0 1 0 1 0
C 1 0 0 0 1 0 1 1
D 1 0 0 0 1 1 0 0
E 1 0 0 0 1 1 0 1
otherwise 0
Since all combinations producing output 1 have x6 x5x4 x3 = 1000, we dene m = x6x5 x4 x3. 0 0 0
The K-map for this function is:

x0
0 m m m
x2 m m 0 0
x1
From the Kmap:
z = mx2x1 + mx2 x0 + mx2 x1
0 0 0
A two-level NAND network is obtained from this expression. It has 3 6-input NAND gates and
one 3-input NAND gate. The description of it is:
NAND(NAND(x6; x5; x4; x3; x2; x1); NAND(x6; x5; x4; x3; x2; x0); NAND(x6; x5; x4; x3; x2; x1))
0 0 0 0 0 0 0 0 0 0 0 0
For a NOR-NOR implementation we need to obtain an expression in PS form as follows:

z = m(x2 + x1)(x2 + x1 + x0) = x6x5 x4 x3 (x2 + x1 )(x2 + x1 + x0 )
0 0 0 0 0 0 0
that corresponds to the following description:

z = NOR(x6; x5; x4; x3; NOR(x2; x1); NOR(x2; x1; x0))
0 0 0
The gate networks are easily obtained from these expressions and descriptions.
Exercise 5.18 A high-level specication for the system is:

Input: x is a decimal digit, represented in BCD
Output: y is an unsigned integer represented in binary
Function: y = x2
The switching functions for this exercise are given as:
x (BCD) y = x2 (Binary)
0000 0000000
0001 0000001
0010 0000100
0011 0001001
0100 0010000
0101 0011001
0110 0100100
0111 0110001
1000 1000000
1001 1010001
Using K-maps we obtain:
y0 = x0
y1 = 0
y2 = x1 x0 0
y3 = x2 x1 x0 + x2 x1x0
0 0
y4 = x2 x1 + x2 x0
0
y5 = x2 x1
y6 = x3
The PLA implementation of this system is shown in gure 5.9.

x3 x2 x1 x0
OR Array
AND Array
y6 y5 y4 y3 y2 y1 y0
-- programmable connection
-- connection made
Figure 5.9: PLA implementation for Exercise 5.18
Exercise 5.19 The high-level specication for this system is:
Input: b is a decimal digit, represented in BCD
Output: e is a decimal digit, represented in Excess-3 code
Function: e = b
The conversion of a BCD code, represented as b = (b3; b2; b1; b0) to an Excess-3 code, represented
by e = (e3; e2 ; e1; e0), is dened by the following K-maps:
b0 b0
0 0 0 0
0 1
1 1
0 1 1 1 1 0 0 0

b2 b
-
-
--
- - - - 2
b3 b3
1 1 - -
0 1 - -
e3 : b1 e2 : b1
b0 b0

1 0 1 0 1 0 0 1
1 0 1 0 1 0 0 1
b b
- - - - 2 - - - - 2
b3 b3

1 0 -
- 1 0 - -
e1 : b1 e0 : b1
The minimal sum of products are:
e3 = b1b2 + b0b2 + b3
e2 = b1b2 + b0b2 + b2b1b0
0 0 0 0
e1 = b1b0 + b1b0
0 0
e0 = b0
0
The implementation of these expressions by a PLA is shown in gure 5.10.

b3 b2 b1 b0
OR Array
AND Array
e3 e2 e1 e0
-- connection made
Figure 5.10: PLA implementation of a BCD to Excess-3 converter
Exercise 5.20 A high-level specication for this system is:

Input: x is a decimal digit, represented in Excess-3 code
Output: y is a decimal digit, represented in 2-out-of-5 code
Function: y = x
The table that shows the correspondence between the excess-3 code (x) and the 2-out-of-5 code
(y ) is show in page 28 of the textbook (Table 2.3).
From the table we get the following K-maps:
x0 x0 x0

- - 1 -
-
- 1 - - - 0 -

0 0 0 0 x
2 0 0
1 0 x
0 1 0 1 x
2
- - - - - - - - -
2
x4
1 0
x4 x4
1

0 0 1 1 1 1 0 0 0
1 0 0
y0 : x1 y1 : x1 y2 : x1
x0 x0

- - 1 -
- - 0 -

0 0 0 1 x 1
1 1 0 x
2
- -
- - - -
2
x4 0 x4 0

0 1 1 0 0 0 0
1
y3 : x1 y4 : x1
Using the K-maps we obtain the following minimal expressions for output y = (y4 ; y3; y2; y1; y0 ):
y0 = x3x2 + x2x1
0
y1 = x2x1 + x3x1 x0
0 0 0
y2 = x1x0 + x3x2 + x2x1 x0

0 0
y3 = x2x0 + x2x1 x0
0 0
y4 = x2x0 + x3x1 + x3x1 x0

0 0 0
The implementation of these expressions using a PAL is shown in gure 5.11.

Input: x is a decimal digit represented in BCD
Output: y = (y (1)y (0)), where y (1) and y (0) are both BCD digits.
Function: y = 3x.
From this specication we dene y = (y7; y6 ; :::; y1; y0), y 2 f0; 1g. The table for the switching
i
functions is shown next:

x = (x3 x2x1 x0 ) y7 y6y5 y4 y3 y2 y1 y0
0000 0000 0000
0001 0000 0011
0010 0000 0110
0011 0000 1001
0100 0001 0010
0101 0001 0101
0110 0001 1000
0111 0010 0001
1000 0010 0100
1001 0010 0111
The implementation of this function using a PAL is shown in Figure 5.12. Output y7 and y6
were not mapped to the PAL since they are always zero. No minimization was performed in this
solution. An enable input was included to activate the circuit outputs.
I1
x0 0 4 8 12 16 20 24 28
O1
y0
I2
x1 8
IO2
y1
I3
x2
16
IO3
y2
I4
x3 24
IO4
y3
I5
Enable 32
IO5
y4
I6
40
IO6
I7
48
IO7
I8
56
O8
I9 I10
Figure 5.11: PAL implementation for Exercise 5.20

I1
x0 0 4 8 12 16 20 24 28
O1
y0
I2
x1 8
IO2
y1
I3
x2
16
IO3
y2
I4
x3 24
IO4
y3
I5
enable 32
IO5
y4
I6
40
IO6
y5
I7
48
IO7
I8
56
O8
I9 I10
Figure 5.12: PAL implementation for Exercise 5.21

85
Chapter 6
Exercise 6.1 From Exercise 5.11, we know that the single-error detector for a 2-out-of-5 code
(a; b; c; d; e) is implemented by the expression:
E (a; b; c; d; e) = abc + abd + acd + bcd + abe + ace + ade + bce + bde + cde + a b c e + a b d e +
0 0 0 0 0 0 0 0
acde +bcde
0 0 0 0 0 0 0 0
Using only gates from Table 4.1 of the textbook we can generate all product terms but the
OR operation of all 14 product terms must be implemented by a tree of gates. To minimize the
delay in the implementation, we should use NAND gates. The generation of the product terms is
done using 3 and 4-input NAND gates from Table 4.1. A 14-input NAND however is not available
and should be obtained combining smaller gates. The large NAND gate may be decomposed into
smaller ones as follows (for a 4-input NAND to 2-input NANDs):
(abcd) = (ab) + (cd)
0 0 0
The possibilities are:

Network Delay
tpLH tpHL
A - First Level: 1 NAND-6, 1 NAND-8, Second Level: 1 OR-2 0.40+0.037L 0.64+0.019L
B - First Level: 1 NAND-4, 2 NAND-5, Second Level: 1 OR-3 0.37+0.038L 0.70+0.022L
C - First Level: 2 NAND-3, 2 NAND-4, Second Level: 1 OR-4 0.27+0.038L 0.62+0.025L
Even though the LH transition delay of network C is less than the one for network A, the HL
transition delay of network C becomes worse when the output load is greater or equal to 3. For this
reason we consider network A as the implementation of the 14-input NAND, since it is going to be
less susceptible to output load values. The resulting circuit is presented in Figure 6.1, on page 86.
The delay of the network is obtained from the critical paths NAND-4 ! NAND-6 ! OR-2 or
NAND-3 ! NAND-8 ! OR-2:
TpLH (net) = max(tpHL (NAND-4) + tpLH (NAND-6) + tpLH (OR-2);

tpHL(NAND-3) + tpLH (NAND-8) + tpLH (OR-2))
= max(0:12 + 0:051 1 + 0:24 + 0:037 1 + 0:12 + 0:037 L;
0:09 + 0:039 + 0:24 + 0:038 + 0:12 + 0:039L)
= max(0:57 + 0:037L; 0:53 + 0:037L) = 0:57 + 0:037L
TpHL(net) = max(tpLH (NAND-4) + tpHL(NAND-6) + tpHL (OR-2);
tpLH (NAND-3) + tpHL (NAND-8) + tpHL(OR-2))
= max(0:10 + 0:037 1 + 0:36 + 0:019 1 + 0:20 + 0:019 L;
0:07 + 0:038 + 0:42 + 0:019 + 0:2 + 0:019L)
= max(0:72 + 0:019 L; 0:75 + 0:019L) = 0:75 + 0:019L
86 Solutions Manual - Introduction to Digital Design - November 2, 2000
a
b
c
a
b
d
a
c
d
b
c
d
a
b
e
a
c
e
a
d f(a,b,c,d,e)
e
b
c
e
b
d
e
c
d
e
a’
b’
c’
e’
a’
b’
d’
e’
a’
c’
d’
e’
b’
c’
d’
e’
Figure 6.1: Single-error detector for 2-out-of-5 code

Solutions Manual - Introduction to Digital Design - November 2, 2000 87
Exercise 6.2 Let us use the expressions obtained in Exercise 5.12 (only output variables' names
were changed):
s0 = x0 y0cin + x0y0 cin + x0 y0 cin + x0y0 cin

0 0 0 0 0 0
s1 = x1 x0y1 cin + x1 y1y0 cin + x0 x1y1 y0

0 0 0 0 0 0
+ x1 x0 y1 cin + x1 y1 y0 cin + x1 x0y1 y0

+ x1 x0 y1 cin + x1 y1 y0 cin + x1 x0y1 y0
0 0 0 0 0 0 0 0 0
+ x1 y1 y0 cin + x1x0 y1 cin + x1 x0y1 y0

0 0 0 0 0 0 0 0 0
cout = x1 y1 + x1x0 y0 + x0y1 y0 + y1 y0 cin + x0y1 cin + x1 x0cin + x1 y0 cin

The objective of the design is to reduce the number of gates sharing subnetworks among the
outputs, the manipulation of these expressions follows:
s0 = (x0y0 + x0y0 )cin + (x0y0 + x0 y0 )cin

0 0 0 0 0
= (x0 y0 ) cin + (x0 y0 )cin 0 0
= (x0 y0 ) cin
s1 = x1 (x0y1 cin + y1 y0cin + x0 y1y0 + x0y1 cin + y1 y0 cin + x0 y1 y0 )
0 0 0 0 0 0 0 0 0 0
+x1 (x0y1 cin + y1 y0 cin + x0y1 y0 + y1 y0 cin + x0y1 cin + x0 y1 y0 ) 0 0 0 0 0 0 0 0 0
= x1 (y1A + y1 B ) + x1 (y1A + y1 B )
0 0 0
= (x1y1 + x1y1 )A + (x1y1 + x1y1 )B = (x1 y1 ) A + (x1 y1 )B

0 0 0 0 0
where A = x0cin + y0 cin + x0y0 and B = x0cin + y0 cin + x0y0 . It can be shown that B = A , and
0 0 0 0 0 0 0
the expressions for s1 becomes:

s1 = x1 y1 A
For the cout output we obtain:
cout = x1 y1 + x1 A + y1A
= x1 (y1 + A) + y1 (x1 + A)
= x1 (y1 + y1 A) + y1 (x1 + x1 A) 0 0
= x1 y1 + x1 y1 A + x1y1 A 0 0
= x1 y1 + (x1 y1 + x1 y1 )A = x1 y1 + (x1 y1 )A 0 0
The expression for A can also be transformed to the following more convenient form:
A = x0 cin + y0 cin + x0 y0
= x0 (cin + y0 ) + y0 (cin + x0)
= x0 (ciny0 + y0 ) + y0 (cin x0 + x0 ) 0 0
= x0 cin y0 + x0 y0 + y0 cin x0 0 0
= (x0 y0 )cin + x0 y0
The gate network is shown in Figure 6.2 on page 88.
x0
y0 s0
cin
A
s1
x1
y1
cout
Figure 6.2: Network of Exercise 6.2

Input: x is a decimal digit represented in BCD.
Output: two BCD digits y and z .
Function: 10y + z = 3x.
From this specication we dene the following switching functions:
x3 x2x1 x0 y3 y2 y1y0 z3z2 z1 z0
0000 0000 0000
0001 0000 0011
0010 0000 0110
0011 0000 1001
0100 0001 0010
0101 0001 0101
0110 0001 1000
0111 0010 0001
1000 0010 0100
1001 0010 0111
The simplied switching expressions are obtained from K-maps (not shown):
y3 = y2 = 0
y1 = x3 + x2 x1 x0
y0 = x2 x1 + x2x0
0 0
z3 = x2 x1x0 + x2x1 x0
0 0
z2 = x3 + x2 x1x0 + x2x1x0
0 0 0
z1 = x2 x1x0 + x2x1 x0 + x2 x1x0

0 0 0 0 0 0
z0 = x0
The (NAND; NAND) network is shown in Figure 6.3.
0 y3
0 y2
x3’
y1
x2
x1
x0
x2
x1’ y0 x2
x1’
x2 x0’
x0’ x2’ z1
x1’
x2
x0
x1
x0’ z3 x2’
x2’ x1
x1 x0’
x0
x3’
x2
z0
x1’ x0
x0 z2
x2’
x1
x0’

Exercise 6.4 A high-level specication for the system is:
Input: A, B , both decimal digits in Excess-3 code.
Output: Y 2 fG; E; S g
Function:
8
>< G if A > B
Y = > E if A = B
: S otherwise
The inputs are represented as A = (a3 ; a2; a1; a0) and B = (b3; b2; b1; b0).
The output is encoded as:
8
>< (0; 0) if A (0; 1) if A = B
: (1; 0) if A > B
The network could be designed specically for the Excess-3 code, in which case it would make
use of the corresponding don't cares, or one can use a 4-bit binary comparator. The rst approach
might give a simpler network, but it is dicult to design because the simplications would require
K-maps of eight variables (or the use of some tabular minimization technique). Moreover, the
reduction would be only valid for a two-level network, which is quite complex anyhow (because of
the eight input variables). Consequently, we design a 4-bit binary comparator. It is an extension
to four bits of the 2-bit comparator described in the textbook. Therefore, we can write directly the
following switching expressions:
Equal = w3w2w1w0
Greater = a3 b3 + w3a2 b2 + w3 w2a1 b1 + w3w2w1a0 b0
0 0 0 0
where wi = ai bi + ai bi
0 0
Due to the code selected, the outputs are

y1 = Greater
and
y0 = Equal
The network is shown in Figure 6.4.
a3 w3
w2 y0
w3 w1
w0
a3
b3
b3’
w3
a2
a2 w2 b2’
W y1
b2 w3
w2
a1 a1
w1 b1’
b1 W
w3
w2
a0 w0 w1
b0 W a0
b0’

Exercise 6.5: The modication of the network of Example 4.6 is shown in Figure 6.5. Since
we are asked to use 4 complex gates 2-AND/NOR2, the best solution is to use them on the level
that has yi and wi as inputs. The fourth one should not be used to generate z2 since this output
is composed of 3 products and the complex gate is able to handle only 2. More logic is required
to generate the third product and combine it with the output of the complex gate (that would
take care of 2 products). For this reason, it is more interesting to use the fourth complex gate
to generate z1 and keep the same structure of gates that was used in Example 4.6 to generate z2.
Although the output of AN3 corresponds to z0 we didn't use its output as the network output to
avoid the in uence of the z0 output load on the delay of the other outputs.
y2 w2 y1 w1 y0 w0
x0
x1 O1
x2 2-AND/NOR2
N1
AN1 AN2 AN3
N2 N3 N4
ANx
A1 A2 A3 AN4 N6
N5
O2 z0
z1
z2
The network characteristics are:
Load factor: 1
Fanout factor: considering F = 12 we have F (z2) = F (z1) = F (z0) = 12
Network size: The NOT gates have size 1 and all others have size 2, thus the network has 23
equivalent gates. The size of the network on Example 4.6 was 38 equivalent gates.
Number of levels: 6
Network delays: consider the following table for gate delays:

gate Identier Output Load tpLH (ns) tpHL(ns)
OR3 O1 4 0.27 0.43
NOT N1/N4 3 0.13 0.10
2-AND/NOR2 AN2/AN3 3 0.40 0.18
2-AND/NOR2 AN4 1 0.25 0.13
2-AND/NOR2 AN1 2 0.32 0.16
NOT N2/N3 2 0.10 0.08
NOT N5 L1 0:02 + 0:038L1 0:05 + 0:017L1
AND3 A3 1 0.24 0.20
OR3 O2 L2 0:12 + 0:038L2 0:34 + 0:022L2
The rst critical path we may consider is O1 ! N 1 ! AN 1 ! N 2 ! A3 ! O2 that results
in the following delays:
TpLH (x1; z2) = tpHL (O1) + tpLH (N 1) + tpHL(AN 1) + tpLH (N 2) + tpLH (A3) + tpLH (O2)
= 0:428 + 0:134 + 0:156 + 0:096 + 0:24 + 0:12 + 0:038L2 = 1:17 + 0:038L2
TpHL(x1; z2) = tpLH (O1) + tpHL(N 1) + tpLH (AN 1) + tpHL(N 2) + tpHL(A3) + tpHL(O2)
= 0:272 + 0:101 + 0:32 + 0:084 + 0:2 + 0:34 + 0:022L2 = 1:32 + 0:022L2
Another path that may be considered is O1 ! N 1 ! AN 2 ! N 3 ! AN 4 ! N 5, that
results in the following delays:
TpLH (x1; z1) = tpHL(O1) + tpLH (N 1) + tpHL(AN 2) + tpLH (N 3) + tpHL(A4) + tpLH (N 5)
= 0:428 + 0:134 + 0:184 + 0:096 + 0:128 + 0:02 + 0:038L1 = 0:99 + 0:038L1
TpHL(x1; z1) = tpLH (O1) + tpHL(N 1) + tpLH (AN 2) + tpHL(N 3) + tpLH (A4) + tpHL (N 5)
= 0:272 + 0:101 + 0:395 + 0:084 + 0:245 + 0:05 + 0:017L1 = 1:15 + 0:017L1
We can see that the path from x1 to z2 is still the critical path in this circuit, however, the
delay was reduced when compared to Example 4.6.
Exercise 6.6: A high-level specication for the system is:
Input: x; y 2 f0; 1; 2; 3g
Output: z 2 fG; E; S g.
Function:
8
>< G if x > y
z = > E if x = y
: S if x < y
We encode the output as follows:
z z2 z1 z0
G 1 0 0
E 0 1 0
S 0 0 1
From this encoding we write:
z2 = G = x1y1 + SAME (x1; y1)x0 y0
0 0
z1 = E = SAME (x1; y1)SAME (x0; y0)

z0 = S = x1 y1 + SAME (x1; y1)x0y0
0 0
where SAME (x; y ) = xy + x y = (x y ). Since xy , x y and SAME (x; y ) are mutually exclusive,
0 0 0 0 0
the OR operation may be written as an Exclusive-OR operation, as follows:

z2 = G = x1 y1 (x1 y1 )x0 y0
0 0 0
z1 = E = (x1 y1 )(x0 y0 ) 0 0
z0 = S = x1y1 (x1 y1 )x0y0

0 0 0
The NOT gate is implemented using a XOR gate as: x = x 1. Thus, we can transform the
0
above expressions as follows:

z2 = G = x1 (y1 1) (x1 y1 1)x0(y0 1)
z1 = E = (x1 y1 1)(x0 y0 1)
z0 = S = (x1 1)y1 (x1 y1 1)(x0 1)y0
The gate network is shown in Figure 6.6
y1’ x1 z2=G
y1
1
y0 y0’ x0
1
x1 x1’
z0=S
1 y1
x0 x0’
1 y0
z1=E
x1
x0

Exercise 6.7 Using XOR gates it's possible to get the expressions for equality or dierence:
SAME = x y 0
DIFFERENT = x y
Using these expressions, we obtain the expression for each output, z2(GREATER), z1 (EQUAL)
and z0 (LESS) as:
z2 = DIFFERENT:x + SAME:c2
z1 = SAME:c1
z0 = DIFFERENT:y + SAME:c0
The gate network using XOR and NAND gates is shown in Figure 6.7, on page 97.
x’ SAME
z1
y
c1
c2
z2
x
x DIFFERENT
y
y z0
c0
Figure 6.7: Comparator using XOR and NAND gates

Exercise 6.8 The complementer is described by the expressions:
zi = xi c
The network that implements a 4-bit complementer using only XOR gates is presented in
Figure 6.8, on page 98.
z0
xo
x1 z1
x2 z2
z3
x3
Figure 6.8: Complementer using XOR gates

Exercise 6.9 The MUX function is dened as:
MUX(x; y; s) = xs + ys 0
and using this function we want to represent the following functions using muxes:
OR(a; b) = a + b = ab + b = MUX(a; 1; b )
0 0
NOR(a; b) = (a + b) = a b = 0:b + a b = MUX(0; a ; b)

0 0 0 0 0 0
NAND(a; b; c) = NAND(a; AND(b; c))

AND(b; c) = bc + 0:c = MUX(b; 0; c)
0
NAND(a; z ) = (az ) = a + z = a z + 1:z = MUX(a ; 1; z )

0 0 0 0 0 0
Thus NAND(a; b; c) = MUX(a ; 1; MUX(b; 0; c)) 0
XOR(a; b) = a b = a b + ab = MUX(a ; a; b)
0 0 0
XNOR(a; b) = a b = ab + a b = MUX(a; a ; b)
0 0 0 0
Exercise 6.10 From the network in Figure 6.13 we can obtain the following expressions for the
selection signal s (which controls the rightmost multiplexers), and the output signals z1 and z2 :
s = ab + a b = (a b)
0 0 0
z1 = cs + c s 0 0
= cs 0
= abc
z2 = bs + cs 0
= b(ab + a b ) + c(ab + a b)
0 0 0 0
= ab + ab c + a bc0 0
= a(b + b c) + b(a + a c)
0 0
= a(b + c) + b(a + c)
= ab + ac + bc
From the boolean expressions we can see that z1 = a b c corresponds to the high-level
description:
z1 = (a + b + c) mod 2
and z2 = 1 when 2 or more inputs have the value 1. These equations correspond to sum and
carry-out outputs of a one-bit adder, with inputs a; b, and c.
Exercise 6.11 Tree of multiplexers:
Part (a) E (a; b; c; d) = a b + a b c + bc d + abd + b cd
0 0 0 0 0 0 0
We use Shannon's decomposition to obtain the following four expressions:

E (a; b; 0; 0) = a b + a b + ab = a b + b = a + b
0 0 0 0 0 0
E (a; b; 0; 1) = ab+ab +b=a +b

0 0 0 0
E (a; b; 1; 0) = a b + ab = b
0
E (a; b; 1; 1) = a b + b = a + b = (ab)
0 0 0 0 0
From these expressions we obtain the tree of multiplexers as shown in Figure 6.9.
a’ E(a,b,1,1)
1 1 E(a,b,c,1)
MUX MUX 1 E(a,b,c,d)
E(a,b,0,1)
1 0 0 MUX
E(a,b,c,0)
0
b c
d
a’ 1 b 1
MUX
MUX
0 E(a,b,0,0)
1 0
b’
c
Figure 6.9: Multiplexer tree for E (a; b; c; d) = a b + a b c + bc d + abd + b cd 0 0 0 0 0 0 0
Part (b) E (a; b; c; d; e; f ) = a b c d e f

Using the same type of decomposition we get the functions shown in the next table:
(c; d; e; f ) E (a; b; c; d; e; f )
0000 ab
0001 (a b) 0
0010 (a b) 0
0011 ab
0100 (a b) 0
0101 ab
0110 ab
0111 (a b) 0
1000 (a b) 0
1001 ab
1010 ab
1011 (a b) 0
1100 ab
1101 (a b) 0
1110 (a b) 0
1111 ab
The straight implementation of the tree of multiplexers will look like the network shown in Figure
6.10(a). Simplifying the network by removing the repeated terms we obtain the network shown in
Figure 6.10(b), that looks more like a linear array than a tree, but has the same number of levels
and less muxes.
s 1
MUX a’ 1
s’ s=a’b+ab’
0 MUX
0
a
c
1 b a 1 s’
s’ MUX
MUX
0
a’ 0
s
c b
1
s’ 1 MUX
MUX 0
s 0
c d
s 1 1 1
MUX MUX MUX
s’ 0 0 0
1 E(a,b,c,d,e,f)
MUX
c d e 0
s’ 1 1 1
MUX MUX MUX
0 0 0
f
s
c d e
a’ 1
s=a’b+ab’
s 1
1
1 1 1
MUX MUX MUX MUX MUX
MUX
s’ 0 0 0 0 0
0 a
1 E(a,b,c,d,e,f)
MUX
c b c d e
d 0
s 1 a 1 1 1 1
MUX
s’
MUX MUX MUX MUX
s’ 0 f
a’ 0 0 0 0
c c
b d e
s’ 1
MUX (a) full multiplexer tree network (b) simplified network
s 0
Figure 6.10: Multiplexer network for Exercise 6.11 - part (b) - E (a; b; c; d; e; f ) = a b c d e f
A better multiplexer tree network is realized considering the implementation of the XOR and
XNOR functions by multiplexers (Exercise 6.9) and the associativity of the XOR function as follows:
a b c d e f = [(a b) (c d)] (e f )
The network for this case is presented in Figure 6.11. Observe that it has only 3 levels of multiplexers
in the critical path and 7 multiplexers. The previous implementation had 5 levels and used 9
multiplexers.
1
a’ 1 a xor b MUX
MUX 0
1 E(a,b,c,d,e,f)
a 0
MUX
0
b 1
a 1 (a xor b)’ MUX
MUX 0
a’ 0
e’ 1
b MUX e xor f
e 0
c’ 1 c xor d
MUX
c 0 f
Figure 6.11: Implementation using XOR property to solve Exercise 6.11(b) - E (a; b; c; d; e; f ) =
abcdef
Exercise 6.12 From Exercise 6.6, and considering that the input numbers are represented as
x = (x1; x0) and y = (y1; y0 ), we have the following expressions for the outputs x = y (E), x > y
(G) or x < y (S):
G(x1; x0; y1; y0) = x1y1 + x0 y1 y0 + x1 x0 y0
0 0 0 0
E (x1; x0; y1; y0 ) = (x1y1 + x1y1)(x0y0 + x0 y0 ) 0 0 0 0
S (x1; x0; y1; y0) = x1y1 + x0 y1 y0 + x1 x0 y0

0 0 0 0
By decomposition we obtain:
G(x1; x0; 0; 0) = x1 + x0 + x1 x0 = x0 + x1 = MUX(x0; 1; x1) 0
G(x1; x0; 0; 1) = x1
G(x1; x0; 1; 0) = x1x0 = MUX(x0; 0; x1)
G(x1; x0; 1; 1) = 0
E (x1; x0; 0; 0) = x1x0 = MUX(x0; 0; x1)
0 0 0 0
E (x1; x0; 0; 1) = x1x0 = MUX(x0; 0; x1)

0 0
E (x1; x0; 1; 0) = x1x0 = MUX(x0; 0; x1)

0 0
E (x1; x0; 1; 1) = x1x0 = MUX(x0; 0; x1)

S (x1; x0; 0; 0) = 0
S (x1; x0; 0; 1) = x1x0 = MUX(x0; 0; x1)
0 0 0 0
S (x1; x0; 1; 0) = x1 0
S (x1; x0; 1; 1) = x1 + x0 + x1 x0 = x0 + x1 = MUX(x0; 1; x1)

0 0 0 0 0 0 0
that corresponds to the network of multiplexers shown in Figure 6.12.

x0 1 0 1
MUX MUX
0
0 x1 0
1 G
MUX
x1 y1
0
x0 1 1
MUX MUX y0
1 0 0
x1’ y1
x0 1 1
MUX MUX
0 0 0
1 E
MUX
x1’ y1
0
x0’ 1 1
MUX MUX y0
0 0 0
x1 y1
x0’ 1 1
MUX MUX
0 0 0
1 S
MUX
x1’ y1
0
x0’ 1 x1’ 1
MUX MUX y0
1 0 0 0
x1 y1

99
Chapter 7
Exercise 7.1
Input:
x(t) 2 fa; b; cg
Output:
z(t) 2 fp; q g
Function:
(
z(t) = q if number of a's in x(0; t 1) is even and number of b's is odd.
p otherwise
State:
s(t) = (sa (t); sb (t))
sa (t) = (number of a's) mod 2
sb (t) = (number of b's) mod 2
Initial state:
sa(0) = 0
sb(0) = 0
Transition function:
(
sa (t + 1) = sa (t)0 if x(t) = a
sa (t) otherwise
(
sb (t + 1) = sb (t)0 if x(t) = b
sb (t) otherwise
Output function: (
z(t) = q if s(t)=(0,1)
p otherwise
The state transition and output table is shown below. The state diagram for the system is
presented in Figure 7.1 on page 100.
Input
PS x=a x=b x=c
(0,0) (1,0) (0,1) (0,0) p
(0,1) (1,1) (0,0) (0,1) q
(1,0) (0,0) (1,1) (1,0) p
(1,1) (0,1) (1,0) (1,1) p
NS Output (z )
c
c
b
(0,0)/p (0,1)/q
b
a
a a a
(1,0)/p (1,1)/p
b
c c
Figure 7.1: State Transition Diagram of Exercise 6.1

Exercise 7.2
Input: decimal digit x(t) 2 f0; 1; 2; 3; 4; 5; 6; 7; 8; 9g.
Output: z (t) 2 f0; 1; 2; 3; 4g.
Function:
t
X
z(t) = ( x(i)) mod 5
i=0
State: s(t) 2 f0; 1; 2; 3; 4g
Initial state: s(0) = 0
Function: The state-transition and output functions are described by the expressions:
s(t + 1) = (s(t) + x(t)) mod 5
z(t) = (s(t) + x(t)) mod 5
Exercise 7.3
State table:
x(t)
PS x=a x=b
S0 S0; 01 S1; 11
S1 S2; 11 S3; 00
S2 S3; 11 S3; 11
S3 S3; 00 S4; 01
S4 S4; 01 S0; 00
NS , z
Exercise 7.4 The state diagram for this exercise is shown in Figure 7.2 on page 103.
a/0 a/0
c/0
b/1
A B
c/1 b/1
b/1
c/1 c/1 C a/0
c/0 b/1
E
b/1 D
a/0
a/0

Exercise 7.5 The state diagram for this exercise is shown in Figure 7.3 on page 104
a a,c a
c
b,c
1/1 2/0 3/1
b
b
b c c
b
0/0 4/0
a a
Figure 7.3: State diagram of Exercise 7.5

Exercise 7.6 The state table for this exercise is:
PS Input
x=0 x=1
0 0 1 1
1 1 2 0
2 2 3 1
3 3 4 0
4 4 5 1
5 5 6 0
6 6 0 1
NS Output (z )
From where we obtain the following state transition and output functions:
s(t + 1) = (s(t) + x(t)) mod 7
z(t) = (s(t) + 1) mod 2
The system is a modulo-7 counter whose output is 1 whenever the number of 1's in the input
modulo 7 is even
Exercise 7.7
There are sixteen possible states. To obtain the state diagram, we rst obtain the state table,
by an evaluation of the expressions. To simplify the notation, we label the states with an integer
0 j 15 whose binary representation is the bit-vector (s3 ; s2; s1; s0 ). The state table is
Input
PS x=0 x=1
0 0 1 0
1 2 3 0
2 4 5 0
3 6 7 0
4 8 9 0
5 10 11 0
6 12 13 0
7 14 15 0
8 1 0 1
9 3 2 1
10 5 4 1
11 7 6 1
12 9 8 1
13 11 10 1
14 13 12 1
15 15 14 1
NS z
Observe that the state transition function is:

s(t)
s(t + 1) = (2s(t) + ( 8 + x(t)) mod 2) mod 16
The corresponding state diagram is shown in Figure 7.4.
0
0
0 1
1
15 0
1 1 2
14 0
0
1
1 0 1 3
1
1 0
13
0 0
1 0 1
4
1 0
12 1
0 0 5
1 0
1
11 1
6
0
1
10
0 7
9 8
Figure 7.4: State diagram for Exercise 7.7

Exercise 7.8
The indicated renaming results is in the following state table
Input
PS x=0 x=1
000 000 100 0
001 100 000 0
010 001 101 0
011 101 001 1
100 010 110 0
101 110 010 0
110 011 111 0
111 111 011 1
NS z
From the table we obtain the following expressions:
s2 (t + 1) = s0 (t) x(t)
si (t + 1) = si+1(t) for 0 i 1
z(t) = s1 (t) s0 (t)
Exercise 7.9 The sequential systems described by each table are:
(a) Mealy machine. The output function is a function of the Present State and of the Input.
(b) Moore machine. The output function does not depend on the input.
(c) Moore machine.
Exercise 7.10 The input has four values; we represent it by the bit-vector (x1 ; x0) with the
following code: a = 00; b = 01; c = 10; and d = 11.
There are six states; we represent each one by the bit vector (y2 ; y1; y0) and each state Si
correspond to a code shown in the next table (arbitrary):
State (y2; y1 ; y0)
S0 001
S1 010
S2 000
S3 011
S4 100
S5 101
The output z has ve integer values. We use binary code for these integers, (z2 ; z1; z0).
The corresponding state table is
PS x = 00 x = 01 x = 10 x = 11
000 001,011 010,001 000,000 000,000
001 011,100 010,001 001,000 001,000
010 010,000 010,000 010,000 101,000
011 011,000 011,000 101,000 011,000
100 100,000 100,000 100,000 010,000
101 000,010 001,001 100,001 101,000
NS (Y2Y1 Y0); Output(z)
To obtain switching expressions, Karnaugh maps can be used. Since there are ve variables, it
is convenient to use 4-variable maps and include the 5th variable in the cells.
x0 x0 x0
y2 y2 0 y2 y0 0 0 0

y
y 0
y20 y20 0
2y2 1
0 0
2 2 y y20 y20 0 0 y
1
1 1 y12 y0
y
20 0
0 0 0
1
0 1 0 0
y1 y1
1

1 y1

0 0
1 0
1 1 0
1 0 0
1 0
Y2 x1 Y1 x1 Y0 x1
x0 x0 x0
y0 0 y0 y0 0 0
y00 00
0 0
y2
0 0
2 2 y

2
0 0 y
0
2 0
0 0 y
0
0
1 0
2 y
0
y1 0 0 0 0 y1 0 0 0 0 y1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
z2 x1 z1 x1 z0 x1
The expressions are:
Y2 = x1x0 y1 y00 + x1x00 y10 y0 + x01 y10 y00 y2 + x00y10 y00 y2 + x1 y10 y0y2
Y1 = x01y1 + y1 y0 x0 + y1 y00 x00 + y0 x01 y20 + y10 y00 x0y20
Y0 = x01x00 y10 y20 + y00 y0y20 + x01x0y10 y0 y2 + y1 y0 + y0 x1x0 + y1 x1x0
z2 = x01x00 y10 y0 y20
z1 = x01x00 y20 y10 y00 + x01x00 y2 y10 y0
z0 = y10 y0 x1x0 y2 + y20 y10 y0 x01 + y10 y0x01x0
Exercise 7.11
The time behavior of the module-p counter is given by the arithmetic expressions
t
X
z(t) = ( s(0) + x(t)) mod p
i=0
s(0) = SIN
where SIN 2 f0; 1; : : :; p 1g and x(t) 2 f0; 1g
Exercise 7.12
The number of possible input sequences starting at time t1 = 5 and going up to t2 = 16 would
be:
216 5+1 = 212 possible input sequences
As it's possible to have the system in two dierent states at time t1 , S3 or S1 , for the same
input sequence it's possible to get two possible sequence pairs. So, the number of sequence pairs
needed to describe the system would be:
2 212 = 213
Calling the states by their number (e.g. S2 is called 2), three possible sequence pairs are:
t 5 6 7 8 9 10 11 12 13 14 15 16
x(t) 1 1 0 0 1 1 1 0 1 1 0 1
s(t) 3 3 3 1 2 2 2 2 0 1 3 1
z(t) c c c a b b b b a a c a
t 5 6 7 8 9 10 11 12 13 14 15 16
x(t) 1 1 0 1 1 0 1 1 0 0 1 0
s(t) 3 3 3 1 3 3 1 3 3 1 2 2
z(t) c c c a c c a c c a b b
t 5 6 7 8 9 10 11 12 13 14 15 16
x(t) 1 1 0 1 1 1 0 0 1 1 1 1
s(t) 1 3 3 1 3 3 3 1 2 2 2 2
z(t) a c c a c c c a b b b b
Exercise 7.13
The state diagram of Figure 7.11(a) of the textbook results in the following state table:
Input
PS 0 1
Sinit S0; 0 S1; 0
S0 S00; 0 S01; 0
S1 S10; 0 S11; 0
S00 S00; 0 S01; 0
S01 S10; 0 S11; 0
S10 S00; 0 S01; 1
S11 S10; 0 S11; 0
NS; Output
From the table we get
P1 = (Sinit; S0; S1; S00; S01; S11)(S10)
To obtain P2 , we determine the group of states P1 to which the successors of each state belong.
group 1 group 2
(Sinit ; S0; S1; S00; S01; S11) (S10)
0 112122 1
1 111111 1
Consequently,
P2 = (Sinit; S0; S00)(S1; S01; S11)(S10)
To obtain P3 , we determine the group of states of P2 to which the successors of each state
belong.
group 1 group 2 group 3
(Sinit ; S0; S00) (S1; S01; S11) (S10)
0 111 333 1
1 222 222 2
Thus, P3 = P2 = P = (Sinit ; S0; S00)(S1; S01; S11)(S10) = (Sinit ; A; B )
Using this partition we construct the state table (from the original table):
Input
PS 0 1
Sinit Sinit; 0 A; 0
A B; 0 A; 0
B Sinit; 0 A; 1
NS; Output
The corresponding state diagram is equivalent to the one presented in Figure 7.11(b) of the
textbook, thus both diagrams represent the same system.
Exercise 7.14
The loose description has eight states as follows:
s(t) = A if x(t 1) = a and # of a0 s is even
s(t) = B if x(t 1) = a and # of a0s is odd
s(t) = C if x(t 2; t 1) = ab and # of a0 s is even
s(t) = D if x(t 2; t 1) = ab and # of a0 s is odd
s(t) = E if x(t 3; t 1) = abc and # of a0 s is even
s(t) = F if x(t 3; t 1) = abc and # of a0 s is odd
s(t) = G if x(t 3; t 1) = other and # of a0 s is even
s(t) = H if x(t 3; t 1) = other and # of a0s is odd
Input
PS x=a x=b x=c
A B; 0 C; 0 G; 0
B A; 0 D; 0 H; 0
C B; 0 G; 0 E; 0
D A; 0 H; 0 F; 0
E B; 0 G; 0 G; 0
F A; 1 H; 0 H; 0
G B; 0 G; 0 G; 0
H A; 0 H; 0 H; 0
NS; Output
From the table we get
P1 = (A; B; C; D; E; G; H )(F )
To obtain P2 , we determine the class of P1 to which each successor of the states belong.
1 2
(A; B; C; D; E; G; H ) (F )
a 1111111 1
b 1111111 1
c 1112111 1
Consequently,
P2 = (A; B; C; E; G; H )(D)(F )
To obtain P3 , we repeat the process
1 2 3
(A; B; C; E; G; H ) (D) (F )
a 111111 1 1
b 121111 1 1
c 111111 3 1
Thus,
P3 = (A; C; E; G; H )(B)(D)(F )
And once more,
1 2 3
(A; C; E; G; H ) (B ) (D)
a 22221 1 1
b 11111 3 1
c 11111 1 4
So
P4 = (A; C; E; G)(H )(B)(D)(F )
Still not ready! Once more (hopefully the last)
1 2 3 4 5
(A; C; E; G) (B ) (D) (F ) (H )
a 2222 1 1 1 1
b 1111 3 5 5 5
c 1111 5 4 5 5
So, nally!
P = P5 = P4 = (A; C; E; G)(B)(D)(F )(H )
and the reduced table is
Input
PS x=a x=b x=c
A B; 0 A; 0 A; 0
B A; 0 D; 0 H; 0
D A; 0 H; 0 F; 0
F A; 1 A; 0 A; 0
H A; 0 H; 0 H; 0
NS; Output
Exercise 7.15
From the state table we get
P1 = (a; b; c; e)(d; h)(f )(g )
To obtain P2 , we determine the class of P1 to which the successors of the states belong.
1 2 3 4
(a; b; c; e) (d; h) (f ) (g )
0 3232 44 3 4
1 1111 11 1 2
Thus,
P2 = (a; c)(b; e)(d; h)(f )(g)
To obtain P3 , we determine the group of states of P2 to which the successors of the state belong.
1 2 3 4 5
(a; c) (b; e) (d; h) (f ) (g )
0 44 33 55 4 5
1 22 11 11 2 3
Therefore, P = P3 = P2 = (a; c)(b; e)(d; h)(f )(g ) and the reduced table is
Input
PS x = 0 x = 1
a f; 0 b; 0
b d; 0 a; 0
d g; 1 a; 0
f f; 1 b; 1
g g; 0 d; 1
NS; Output
Exercise 7.16
Based on the outputs for each state we get the rst partition P1 as:
P1 = (A; D; E )(B; F; G)(C; H )
Let's call (A,D,E) as group 1, (B,F,G) as group 2 and (C,H) as group 3.
We can construct a table representing the next group for each state transition:
A D E B F G C H
0 2 2 2 3 3 3 3 3
1 3 3 3 1 1 1 1 1
From the table we can see that the columns for each group of states are the same, and so, the
states in each group are also 2-equivalent. P2 = P1 . Renaming the states in group 1 as , the
states in group 2 as and in group 3 as , we can represent the reduced sequential system as:
PS Input
x=0 x=1
; 0 ; 0
; 1 ; 1
; 0 ; 1
Exercise 7.17
Based on the outputs for each state we get the rst partition
P1 = (A; C; G; H )(B; D; E )(F )
A C G H B D E F
a 2 2 2 2 1 1 1
b 1 1 1 1 3 3 3
c 2 2 2 2 2 2 2
d 2 3 3 3 2 2 2
Partition P2 is
group 1 group 2 group 3 group 4
A C G H B D E F
a 3 3 3 2 2 2
b 1 1 2 4 4 4
c 3 3 3 3 3 3
d 4 4 4 3 3 3
Partition P3 is
group 1 group 2 group 3 group 4 group 5
A C G H B D E F
a 4 4 2 2 2
b 1 1 5 5 5
c 4 4 4 4 4
d 5 5 4 4 4
STOP.
The equivalent states are: fAg, fB,D,Eg, fC,Gg, fFg, fHg
Minimal state transition table:
PS x = a x = b x = c x = d
A B=1 C=0 B=1 B=1
B C=0 F=1 B=1 B=0
C B=1 A=0 B=1 F=1
F C=1 F=1 B=0 H=0
H B=1 C=0 B=1 F=1
NS=output
Exercise 7.18Based on the outputs for each state we get the rst partition
P1 = (N; O; Q; R; X; Z )(P; U; V; Y )(S; T; W )
N O Q R X Z P U V Y S T W
a 3 3 3 3 3 3 2 2 2 2 1 1 1
b 1 2 2 2 1 1 1 1 1 1 2 2 2
Partition P2 is
group 1 group 2 group 3 group 4
N X Z O Q R P U V Y S T W
a 4 4 4 4 4 4 3 3 3 3 1 1 1
b 1 1 1 3 3 3 2 2 1 1 3 3 3
Partition P3 is
group 1 group 2 group 3 group 4 group 5
a 5 5 5 5 5 5 4 4 3 3 1 1 1
b 1 1 1 4 4 4 2 2 1 1 4 4 3
Partition P4 is
group 1 group 2 group 3 group 4 group 5 group 6
a 5 6 5 5 6 6 4 4 3 3 1 1
b 1 1 1 4 4 4 2 2 1 1 4 4
Partition P5 is
group 1 group 2 group 3 group 4 group 5 group 6 group 7 group 8
N Z X O Q R P U V Y S T W
a 7 7 8 8 6 6 5 5 1 1
b 1 1 6 6 4 4 1 1 6 6
STOP!
Equivalent states: fN,Zg, fOg, fP,Ug, fQ,Rg, fS,Tg, fV,Yg, fWg, fXg
Minimal state transition table:
PS input
x = a x = a0
N S=f N=e
O S=f V=e
P V=e Q=f
Q W=f V=e
S N=e V=e
V P=f N=f
W X=e P=e
X W=f N=e
NS=output
Exercise 7.19
Input: x(t) 2 fa; b; c; dg
Output: z (t) 2 f0; 1g
State: Since the pattern to be recognized has four symbols, using the vector-state approach, we
represent the state as the vector
s = (s2; s1; s0 )
and the states are s(t) 2 f0; 1; 2; :::; 7g.
Function: The corresponding state transition and output functions are:
si(t + 1) = si 1 (t) 1 i 2
s0 (t + 1) = x(t)
(
z(t) = 1 if (s(t); x(t)) = abca
0 otherwise
For the minimum-number-of-states approach, we dene a state with the following four values:
s(t) = A if x(t 1) = a
s(t) = B if x(t 2; t 1) = ab
s(t) = C if x(t 3; t 1) = abc
s(t) = D if none of the above (Initial)
The state description is given by the state diagram shown in Figure 7.5and the following table:
Input
PS a b c d
A A; 0 B; 0 D; 0 D; 0
B A; 0 D:0 C; 0 D; 0
C A; 1 D; 0 D; 0 D; 0
D A; 0 D; 0 D; 0 D; 0
NS; z
The output sequence corresponding to the given input sequence is
x(t) a a b c a b c a d a a a b c a
s(t) D A A B C A B C A D A A A B C A
z(t) 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1
b/0,c/0,d/0
a/0 a/0
D A
c/0,d/0
b/0, a/0 b/0

b/0,c/0,d/0 a/1 d/0
c/0
C B

Exercise 7.20 It is not possible to have a sequential system with m 1 states recognizing a
sequence of length m. As a proof, consider a pattern of length 2, let us say ab. The state diagram
for this sequential system is shown in Figure 7.6. We can easily see from the diagram that the states
are not equivalent, since their outputs are dierent. Thus, it is not possible to have a reduced state
machine with only ONE state to recognize the pattern with length 2.
a’/0 a/0
a/0
S0 S1
b/1,a’/0,b’/0

We now consider the generation of a m-state machine to recognize a sequence of length m.
Let the pattern to be recognized be p1 p2 : : :pm . The state description of the pattern recognizer is
obtained by having m states labeled S0 to Sm 1 as follows:
S0 is the initial state. Other states are s(t) = Si whenever the sequence x(t i; t 1) = p1p2 : : :pi ,
i > 0 (that is already i symbols of the pattern have been recognized).
The state-transition function is
8
> S
> i+1
> if s(t) = Si and x(t) = pi+1
< if s(t) = Si and pi j +2 pi j +3 : : :pi x(t) = p1 p2 pj ; j 2
s(t + 1) = > SSj if x(t) = p
>
> 1 1
: S
0 otherwise
and the output function

(
z= 1 if s(t) = Sm 1 and x(t) = pm
0 otherwise
Exercise 7.21
The state diagram that describes the system is presented in Figure 7.7 page 124, using the
minimum state approach. The vector state approach is not possible to be used since the system is
not a nite memory system.
b,c,d/1 a/1 a/1
Even a/1 b/1 c/1

a ab abc
c,d/1 b,d/1
b,c,d/1 a/0
a/1
b,c,d/0 a/0 a/0
a/0 b/0 c/0

Odd a ab abc
c,d/01 b,d/01
b,c,d/0
Figure 7.7: State Diagram for Exercise 7.21

Exercise 7.22
The input set is I = f0; 1; 2; 3; 4; 5; 6; 7; 8; 9g and the output set 0 = f0; 1; 2; 3; 4g. The state
is formed of two components: s1 to detect the pattern 358, and s2 to count mod 5 the number of
instances. For the pattern recognizer, we need three states as follows:
s1 (t) = A if x(t 1) = 3
s1 (t) = B if x(t 2; t 1) = 35
s1 (t) = C if none of above
s1 (0) = C
The state description of this component is
8
A
>
< if x(t) = 3
s1(t + 1) = > B if s1 (t) = A and x(t) = 5
: C otherwise
The second component is a modulo 5 counter. Consequently, the state has ve values which
we label with the integers 0; 1; 2; 3 and 4 to be able to write the state transition as the arithmetic
expression:
(
s2(t + 1) = (s2 (t) + 1) mod 5 if s1 (t) = B and x(t) = 8
s2 (t) otherwise
s2 (0) = 0
Finally, the output function is z (t) = s2 (t).
Exercise 7.23
Following the hint given in the exercise, the sequential system is decomposed into two. System
A recognizes the pattern 0110, and system B recognizes the pattern 1001, as shown in Figure 7.8.
The output z (t) is dened as a function of the system A states (SA (t)) and system B states (SB (t))
as follows:
SA (t) SB (t) z(t)
f0; 1; 2; 3g { 0
4 f0; 1; 2; 3g 1
4 4 2
System A System B
1 0 0 1
0 1 1 0
0 1 2 0 1 2
0 1 1 0
1 0
4 3 4 3
0 1

The timing behavior for the given input sequence, considering s(t) = (SA (t); SB (t)) is:
t 0 1 2 3 4 5 6 7
x(t) 0 0 1 0 1 1 1 0
s(t) (0,0) (1,0) (2,1) (1,2) (2,1) (3,1) (0,1) (1,2)
z(t) 0 0 0 0 0 0 0 0
t 8 9 10 11 12 13 14 15
x(t) 1 1 0 0 1 0 1 0
s(t) (2,1) (3,1) (4,2) (4,3) (4,4) (4,4) (4,4) (4,4)
z(t) 0 0 1 1 2 2 2 2
Exercise 7.24
Since two dierent patterns are generated, the system consists of two independent pattern
generators, let's call these systems A and B . The corresponding state diagram is given in Figure 7.9.
The states SA i belongs to system A and states SB i belongs to system B .
-/A
-/G -/O -/blank -/U -/C -/L

S0 S1 S2 S3 S4 S5 S6
A A A A A A A
-/N
1/R -/U
S 0 SB 1 S 2
B B
0/blank
Figure 7.9: State diagram of Exercise 7.24

Exercise 7.25
To make the design simple and tractable, we make the following assumptions:
Selection of stamps to buy is the rst step
If amount of accumulated coins is at least 15c greater than the face value of the selected
stamp, return all coins
Then the inputs and outputs are as follows (ref. Figure 7.10):
Inputs:
Reset : 2 fT; F g
CoinType : 2 fN; D; Qg
StampType : 2 fS 1(20c); S2(40c); S3(50c)g
ReturnCoinRequest : 2 fT; F g
Outputs:
RS 1 Release stamp 1 (20c)

RC Return Coin
RN Return Nickel
RD Return Dime
All outputs take values from the set fT, Fg. The state diagram is shown in Figure 7.11.
Reset RS1
RS2
Coin Type
RS3
Stamp Type Controller RC
RN
Return Coin Request
RD
Figure 7.10: Inputs & Outputs of Vending Machine Controller

D / RS1; Q / RS1,RN,RD Select Stamp 1
D/
Select N/ N/ N/
S1,5c S1,10c S1,15c
S3/ S1/ S1
Q / RS1, RN D/
Q / RS1, RD
Wait
N / RS1; D / RS1,RN; Q / RC
N / RS2; D / RS2, RN; Q / RC
D / RS2; Q / RS2, RN, RD

Q/RS2, RD
Q / RS2, RN
S2 Q/RS2 D/ D/
D/ D/
D/
N/ N/ N/ N/ N/ N/ N/
Select S2,5c S2,10c S2,15c S2,20c S2,25c S2,30c S2,35c
S2
D/
Q/
Q/
Select Stamp 2
Q/
N / RS3; D / RS3, RN; Q / RC

D / RS3; Q / RS3, RN, RD Select Stamp 3
Q / RS3, RD
Q / RS3, RN
Q / RS3
Select Q/
S3 D/ D/ D/ D/
N/ D/ D/ D/ D/
N/ N/ N/ N/ N/ N/ N/ N/
S3,5c S3,10c S3,15c S3,20c S3,25c S3,30c S3,35c S3,40c S3,45c
Q/ Q/
Q/ Q/
Note: We did not draw the transitions corresponding to inputs RESET and Return Coin Request.
Basically, for every state, its next state with the above inputs should be the same - go
back to State Wait. In the mean time, RC is true to return all coins deposited so far.
Figure 7.11: State Diagram of Exercise 7.25

119
Chapter 8
Exercise 8.1 : A minimum clock width of 5 ns and a latch delay of 2 ns are considered in this
problem.
(a) The minimum delay of the combinational network (tp ) considered in this problem is obtained
by the following equation
tp + 2ns 5ns ! tp 3ns
(b) If the delay of the combinational network can decrease by 30% and the latch delay can
decrease by 10%, the maximum clock pulse width (Tmax ) is calculated by the following equation:
0:7tp + 0:9 2ns = 0:7 3 + 1:8 = Tmax ! Tmax = 3:9ns
Exercise 8.2:
Using the notation given on Figure 8.15 of the textbook we obtain the following network pa-
rameters:
Combinational Networks' delays:
d1x = d1y = 4 tp (gate) = 2ns
d2 = 1 tp(gate) = 0:5ns
Network set-up time:
txsu (net) = tysu (net) = tsu (cell) + d1x = 1 + 2 = 3ns
Network hold time:
th (net) = th (cell) = 0:5ns
Network propagation delay:
tp (net) = tp (cell) + d2 = 3 + 0:5 = 3:5ns
Minimal period:
Tmin = max[(tin + txsu (net)); (tysu (net)+ tp (cell)); tp(net+ tout )] = max[2+3; 3+3; 3:5+2:5] = 6:0ns
Maximal frequency:
fmax = T 1 = 6:0 110 9 167MHz
min
Exercise 8.3
(a) There are no races because of the nonoverlapping nature of the two clocks. This assures
that in each clock cycle only one state change occurs.
(b) The number of states depends on the mode of operation of the network. We consider two
modes.
i) The clock period of the system corresponds to one of the phases (say phase 1). In this case,
the gated latch loaded during the phase two clock acts just as a temporary buer to prevent
races. The state register corresponds to the register loaded during phase 1. Consequently,
the number of states is 2n . The division of the combinational network into two can, in some
cases, make sense because of implementation restrictions. For example, if the combinational
network is implemented using pass transistors, there is a limitation on the number of them
that can be connected in series; in such a case the division in two networks might help.
ii) The clock period is the time between both clocks (phase 1 and phase 2). This results in a
system that has a smaller period than that in (i) (and, therefore, in a faster system). In this
case each register stores part of the state and the number of potential states is 22n , but these
states cannot be utilized in general. The state can be described by two components s1 (stored
in register 1) and s2 (stored in register 2). Each component changes in alternate clock cycles.
The output is a combination of two components z1 and z2 expressed as:
z1 (t) = G1(s1 (t); x1(t))
z2 (t) = G2(s2 (t); x2(t))
(c) Using the rst model, the implementation of the system of Exercise 8.4 (Figure 8.40 of
the textbook) is straightforward if we only replace the D-type cells for two gated latches in a
master/slave conguration, as shown on page 203 of the textbook. Doing this modication, the
new design will behave the same way as the one shown in Exercise 8.4, with a slower clock. One
way to improve this design would be to split the combinational network, reducing the propagation
delay between latches, as shown in Figure 8.1. Observe that one more latch is used in this case.
x1
x0’ Y1 y1
x0
Y0 y0
x0’
phase 2
phase 1 z
Figure 8.1: Redesign of system in Exercise 8.4 using latches - Exercise 8.3
Exercise 8.4
The transition and output functions are described by the following expressions:
Y1 = x00 x1 + x0 y1
Y0 = y0x00 + x0 y1
z = y0
PS Input (x1x0 )
y1 y0 00 01 10 11
00 00 00 10 00 0
01 01 00 11 00 1
10 00 11 10 11 0
11 01 11 11 11 1
NS(Y1 Y0 ) Output (z )
The corresponding state table is (for state assignments A = 00; B = 01; C = 10; D = 11 and
input coding a = 00; b = 01; c = 10; d = 11)
PS Inputs
x=a x=b x=c x=d
A A A C A 0
B B A D A 1
C A D C D 0
D B D D D 1
NS Output (z )
The diagram in Figure 8.2 shows the state transitions of this system. The following patterns
are recognized by the system (assuming that A is the initial state): cb; cbb; cbc; cd; cdc.
a,b,d c
A/0 a C/0
b,d b,d
c D/1
B/1 b,c,d
a
Figure 8.2: State digram for network on Exercise 8.4

Exercise 8.5
The state diagram of the pattern recognizer for the sequence 0101011 is shown in Figure 8.3
and has seven states. Each state was labeled with the sequence that it \recognizes". We encode
these states using three state variables (y2; y1 ; y0) so that the state assignment of state Si is the
radix-2 representation of i. The correspondence between the state assignment and sequence that
it detects is shown in the next table.
1/0 0/0
0/0
0/0 1/0 0/0

start 0 01 010
1/0
1/0
1/1
0/0 0101
1/0 0/0
1/0
010101 01010
0/0
Figure 8.3: State diagram for system in Exercise 8.5
State Sequence
S0 start
S1 0
S2 01
S3 010
S4 0101
S5 01010
S6 010101
The state and transition table is:
PS Input
y2y1 y0 x = 0 x = 1
S0 000 001,0 000,0
S1 001 001,0 010,0
S2 010 011,0 000,0
S3 011 001,0 100,0
S4 100 101,0 000,0
S5 101 001,0 110,0
S6 110 101,0 000,1
Y2 Y1Y0; z
The switching expressions for the next state and output are:
Y2 = y2 y00 x0 + y2 y0 x + y1 y0 x
Y1 = y10 y0 x + y20 y1y00 x0
Y0 = x0
z = y2y1 x
These expressions are implemented by AND-OR networks and the state is stored in a 3-bit
register. The corresponding sequential network is shown in Figure 8.4.
x’
y0’
y2
x
y2 Y2 x
y0 y2 z
x Y1
y1 y1
y0
Y0 y0
x’
x
y1’
y0 CK
x’
y2’
y1
y0’

Exercise 8.6 :
The pattern generator for the sequence abcaba is described by the following transition table:
PS NS/z
A B/a
B C/b
C D/c
D E/a
E F/b
F A/a
Let us dene the following encoding:
y2 y1 y0 State
000 A z1z0
001 B 00 a
010 C 01 b
011 D 10 c
100 E
101 F
From the state table and the previous encoding we get the following table and K-maps:
PS NS/z1 z0
000 001/00
001 010/01
010 011/10
011 100/00
100 101/01
101 000/00
101 - - -/- -
101 - - -/- -
y0 y0 y0

0
1 0 1

y2 -
0 0 1 0
1 0
- y2 y2
1 0 0 1

0 0 -
- 10 -
-
Y2 : y1 Y1 : y1 Y0 : y1
y0 y0

0
1 0 0
y2
0 0 0 1
0 0 -
- y2
1 0 -
-
z1 : y1 z0: y1
The expressions we get from the K-maps are:
Y2 = y1 y0 + y2 y00
Y1 = y20 y10 y0 + y1 y00
Y0 = y00
z1 = y1 y00
z0 = y20 y10 y0 + y2 y00
The network that implements a canonical version of this sequential network is presented in
Figure 8.5 on page 126.
Y2 y2
z1
Combinational Y1 cells y1 Comb.
Network Y0 y0 Network z0
y1
y2’
y0
y2
y1’
y2
y1
y0’ y0’
y0
y2’
y1’
y0
CK
y1 z1
y0’ z0
Figure 8.5: Pattern generator of Exercise 8.6

Exercise 8.7
The state diagram for this system is presented in Figure 8.6. State S1 represents a 1 followed
by a EVEN block of zeros, and state S5 indicates that the system received the required sequence.
The corresponding state table is:
0 1
1 1 1 0
S0/0 S1/0 S3/0 S4/0 S5/1
0
0,1 0 0
S1 - block of zeros of EVEN length
S2/0 S5 - block of zeros of ODD length
(after correct prefix)

Input
PS x = 0 x = 1
S0 S0 S1 0
S1 S2 S3 0
S2 S1 S1 0
S3 S2 S4 0
S4 S5 S4 0
S5 S4 S1 1
NS output(z )
We use the state code i (in binary) for the state Si . The PS is represented by the 3-bit vector
(y2 y1 y0 ) and the NS by the vector (Y2Y1 Y0 ). The output switching expression is:
z = y 2 y0
The K-maps for the next state bits are shown next.
y0 y0 y0
0

01 0 0 0 1 1 0 00 0 1
1 -- -- y2 0 0 - -
y2
1 0 -
-
y2
1 0 0 0 - -
1 1 0 1
0 1 - -
x x x
0 0 1 0 0 1 0 0
Y2 : y1 Y1 : y1 Y0 : y1
The switching expression for Y2 ,Y1, and Y0 are:
Y2 = y2 y00 + x0y2 + xy1 y0
Y1 = y20 y10 y0 + x0y20 y0
Y0 = xy20 y10 + xy10 y0 + y1 y00 + x0y2 y00
The corresponding sequential network is shown in Figure 8.7.
y2
y0’
Y2
x’ x x’
y2
x
y1
y0
y2’ y2
z
y1’ Y1
y0 y1
x’
y2’ y0 y0’
y0
x
y2’
y1’
x CK
y1’ y2 y2’
Y0
y0
y1 y1 y1’
y0’
x’
y2
y0’

Exercise 8.8
We need a 3-bit vector to represent the six states and a 2-bit vector to represent the output.
y2 y1 y0 State
000 A z1 z0
001 B 00 a
010 C 01 b
011 D 10 c
100 E
101 F
From the state table and the encoding we get the following K-maps.
y0 y0 y0
1 0 1
00 1
0 0 - - 1 0 0 1
1 0
-

-
y2 0 - y
00 -
1 0 - - y
x
2 2
0 1 - - 1 1 0 - -
x x
0 0 0
1 0 0 1 0 1
0 0
1
Y2 : y1 Y1 : y1 Y0 : y1
y0 y0

0
0 00 0
0 1
0
0
- -
0
1 -
-
y2 1 y2
x
0
1 - -
x
1
0 - -
0
1 10 1
0 0 1
z1 : y1 z0 : y1
The corresponding switching expressions are
Y0 = y00
Y1 = x0y20 y10 y0 + x0 y1y00 + xy2 y00 + xy1 y0
Y2 = x0y2y00 + x0 y1y0 + xy2y0 + xy20 y10 y00
z1 = y2 y0 + xy0
z0 = x0 y1 y0 + y2y00 + xy00
The sequential network is shown in Figure 8.8 on page 130.
x’
y2
y0’
x’
y1
y0 Y2
y2
x
y2 Y1 y2’
y0 y1
x Y0 y1’
y2’ y0’ y0
y1’ y0’
y0’
x’
y2’ CK
y1’
y0
x’
y1
y0’
x y2
y2
y0’ y0
z1
x x
y1 y0
y0
x’
y1
y0
y2 z0
y0’
x
y0’
Figure 8.8: Sequential network for Exercise 8.8

Exercise 8.9 :
Direct application of K-maps is not possible for this problem. To design this network it is
important to decompose it into smaller parts, as shown in Figure 8.9. The NOTBCD module
detects when the input code, or the stored minimum value is not a valid BCD code. The input
vector is represented by the vector x = (x3; x2; x1; x0), and the state vector is y = (y3 ; y2; y1; y0 ).
Input x (y ) is not a valid BCD code if x > 9 (y > 9). This condition is represented by the
expression x is not BCD = x3 x2 + x3x1 (y is not BCD = y3 y2 + y3 y1 ). The NOTBCD module is
implemented by an expression that combines both cases:
NOTBCD = x is not BCD + y is not BCD = x3x2 + x3x1 + y3 y2 + y3 y1
The MIN module is specied as:
Inputs: x; y 2 f0; 1; 2; ; 15g
Output: z 2 f0; 1; 2; ; 15g
Function:
(
z= x if x < y
y otherwise
NOTBCD
MIN Y Mem. y
OR
Cells
CLK

The MIN module may be implemented as an iterative array, comparing bits from most-signicant
to least-signicant. Each bit slice has two \data" inputs xi and yi and two \carry" inputs ei (equal)
and si (xj < yj for some j < i), and the outputs: mi , ei 1 , and si 1 . The folllowing expressions
are used for each output:
ei 1 = ei(xi yi)0
si 1 = si + (x0i yi)ei
mi = si 1xi + s0i 1 yi
e4 = 1
s4 = 0
The nal gate network for the system is shown in Figure 8.10.
x3
x2
x3
x1 NOTBCD
y3
y2
y3
y1
1 0 MIN slice
x3
x ei si
y y3
y3
m
s i-1
e i-1 y2
x2
y2 MIN slice y1
x1
y1 MIN slice y0
x0
y0 MIN slice
CLK
Figure 8.10: Minimum detector for Exercise 8.9

Exercise 8.10 :
To implement a sequential network that performs a Binary-to-Gray code conversion we use the
given equation:
gi = bi bi+1, i = 1; ::::; n 1
g n = bn
Thus, the conversion is done from left to right, storing a new binary-code bit in each clock cycle.
Initially the internal variable is 0 (bi+1 = 0).
The sequential network is shown in Figure 8.11.
BINARY-to-GRAY
b
bi i+1
D Q
g
CLK i
Figure 8.11: Binary-to-Gray converter

Exercise 8.11
To perform subtraction it is necessary to have a representation of negative integers, since the
result can be negative. Several of these representations are given in Chapter 10. Here we simplify
the problem by assuming that the result is positive.
Given two n-bit integers represented in the binary number system by x = (xn 1 ; : : :; x0) and
y = (yn 1; : : :; y0), and the result represented by (sn 1 ; : : :; s0), the function to be performed
serially in each bit position, for addition and subtraction, is described by the following tables:
Addition Subtraction
xi yi ci ci+1 si xi yi bi bi+1 si
0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1 1 1
0 1 0 0 1 0 1 0 1 1
0 1 1 1 0 0 1 1 1 0
1 0 0 0 1 1 0 0 0 1
1 0 1 1 0 1 0 1 0 0
1 1 0 1 0 1 1 0 0 0
1 1 1 1 1 1 1 1 1 1
where ci is the carry-in bit at position i, and bi is the borrow-in bit.
Let the variable k indicate the operation to be performed as follows:
(
k = 10 for x+y
for x y
Since we want to combine both operations in the same module, let us make c = b. A switching
expression for the result si is:
si = xi xi ci for i = 1; : : :; n 1
sn = cn
providing that an = bn = 0.
A switching expression for ci+1 is
ci+1 = ciyi + (k xi )0(ci + yi )
The initial condition c0 = 0 is set with INIT = 1.
The sequential network is given in Figure 8.12.
c
i+1
INIT
bi
ci
D Q
CK
k
ai si
Figure 8.12: Adder/subtractor, Exercise 8.11

Another implementation of this sequential adder/subtractor is possible using complementation
and addition. This approach will become clear after the discussion in Chapter 10.
Exercise 8.12
The state diagram for this sequential network is presented in Figure 8.13, for the case of receiving
least signicant bit and most signicant bit rst. In each transition we use a pair of bits representing
bits from input A (a(t)) and B (b(t)), respectively. The system output is the same as the state
coding used.
00,11,10
10
EQUAL GREATER
00,11 01 01
LEAST SIGNIFICANT BIT FIRST
10
SMALLER
00,11,01
10
EQUAL GREATER
00,11 01
MOST SIGNIFICANT BIT FIRST
SMALLER
Figure 8.13: Serial Binary Magnitude Comparator, Exercise 8.12

For both implementation we need three states, coded as:
State (y1 ; y0)
EQUAL (A = B ) 00
GREATER (A > B ) 01
SMALLER (A < B ) 10
(a) Least-signicant bit rst:
In this case the transition table is:
PS Inputs (a(t),b(t))
00 01 10 11
00 00 10 01 00
01 01 10 01 01
10 10 10 01 10
NS (Y1 ; Y0)
We can see from the table that:
Y1 = y1(a(t)0 b(t)) + a(t)0 b(t)
Y0 = y0(a(t)0 b(t)) + a(t)b(t)0
The network is presented in Figure 8.14.
Mem.
Cell
Y1 y1
y1
a(t)
b(t)
y0 Y0 y0
CK
Figure 8.14: Serial Binary Magnitude Comparator, Exercise 8.12 (a)

(b) Most-signicant bit rst: In this case the transition table is:
PS Inputs (a(t),b(t))
00 01 10 11
00 00 10 01 00
01 01 01 01 01
10 10 10 10 10
NS (Y1 ; Y0)
The new expressions are:
Y1 = y1 + y00 a(t)0b(t)
Y0 = y0 + y10 a(t)b(t)0
These expressions are easily implemented using gates.

Exercise 8.13
In order to simplify the design of this system, we decompose the state (S (t)) into two compo-
nents: the number of digits being inserted (S1(t)), and the correctness of the input (S2(t)). The
rst component is implemented by a modulo-4 counter with states S1 (t) 2 f0; 1; 2; 3g, and the
second component by a two-state machine with states S2 (t) 2 fY; N g. The output is generated as
a function os these states.
The initial state is S (t) = (0; Y ), and the combination (0; N ) never happens. The state transi-
tion table for the two-component system is:
Inputs
S1(t)S2(t) x = 0 x = 5 x = 6 others
0Y 1Y 1N 1N 1N
1Y 2N 2Y 2N 2N
1N 2N 2N 2N 2N
2Y 3N 3N 3Y 3N
2N 3N 3N 3N 3N
3- 0Y 0Y 0Y 0Y
S1(t + 1)S2(t + 1)
The state diagram for the lock is shown in Figure 8.15. We consider that the counter state
8/01
8’/10
0/00 5/00 6/00

0Y 1Y 2Y 3Y
0’/00 5’/00 6’/00
-/00 -/00
1N 2N 3N
-/10
Figure 8.15: State diagram for lock { Exercise 8.13

S1 (t) is represented by the vector (c1; c0), and S2(t) assumes the values 1 for Y and 0 for N . The
expression for the next state of the two-state component and the outputs are:
S2 (t + 1) = d0c01c00S2 (t) + d5c01c0S2(t) + d6 c1c00S2 (t) + c1c0
where di = 1 when x = i. Thus,
S2(t + 1) = S2(t)(x03x02 x01 x00c01 c00 + x03x2 x01x0c01c0 + x03x2x1x00c1c00) + c1c0
z2(t) = c1c0(S2(t)(x3x00)0 + S2(t)0) = c1c0(x03 + x0 + S2(t)0 )
z1(t) = c1c0S2(t)x3x00
The gate network that implements the locker is shown in Figure 8.16.
d0
c1’
c0’ s2(t)
x3 d5 s2(t+1)
c1’ D Q
x2 c0
x1
c1 CLK s2(t)’
x0 d6 Q’
c0’
c1 c1’ c1 z2
CLK 1
Modulo-4 c0
Counter 0 c0 c0’
CNT
x3 d8 z1
x0
Figure 8.16: Network for lock in Exercise 8.13

Exercise 8.14 We apply the same concepts presented for the D-latch network on page 200 of
the textbook and the master/slave conguration shown in Figure 8.11 of the textbook. The general
network conguration is shown in Figure 8.17. The slave cell is a D-type latch, as discussed in the
book. A combinational network must be designed to activate the set/reset inputs of an SR latch.
C represents the clock input.
SR cell
J S Q’
Comb. SR
Circ. Cell
A Q
K R
Figure 8.17: Gate implementation of a master-slave JK ip- op

The table for the combinational network is shown next:
C J K Q S R
0 - - - 0 0
1 0 0 0 0 -
1 0 0 1 - 0
1 0 1 0 0 -
1 0 1 1 0 1
1 1 0 0 1 0
1 1 0 1 - 0
1 1 1 0 1 0
1 1 1 1 0 1
It is easy to see that
S = Q0CJ
R = QCK
The combinational network is composed of two AND gates only.
The timing diagram for the network is shown in Figure 8.18. The timing diagram of the internal
signal A, the output of the master module, is also shown.
Figure 8.18: Timing diagram for Exercise 8.14

Exercise 8.15 We make use of the concepts presented for the D-latch network on page 200 of
the textbook and the master/slave conguration shown in Figure 8.11 of the textbook. The general
network conguration is shown in Figure 8.19. The slave cell is a D-type latch, as discussed in the
book. A combinational network must be designed to activate the set/reset inputs of an SR latch.
C represents the clock input.
The table for the combinational network is shown next:
C T Q S R
0 - - 0 0
1 0 0 0 -
1 0 1 - 0
1 1 0 1 0
1 1 1 0 1
It is easy to see that
S = Q0CT
R = QCT
The combinational network is composed of two 3-input AND gates.
SR cell
S Q’
T Comb. SR
Circ. Cell
A Q
R
Figure 8.19: Gate implementation of a master-slave T ip- op

Exercise 8.16 From the network we obtain the following table, based on the expressions below:
JA = KA = xQB
JB = KB = x
PS Input Input
QA QB x = 0 x = 1 x = 0 x = 1
00 0000 0011 00 01
01 0000 1111 01 10
10 0000 0011 10 11
11 0000 1111 11 00
JA KA JB KB NS
The outputs are expressed as:
z3 = QA QB
z2 = QA Q0B
z1 = Q0A QB
z0 = Q0A Q0B
Giving the following names to the states:
State Name Code
S0 00
S1 01
S2 10
S3 11
we get the transition table:
PS Input Output
QA QB x = 0 x = 1
S0 S0 S1 0
S1 S1 S2 1
S2 S2 S3 2
S3 S3 S0 3
NS
The state diagram for the given network is presented in Figure 8.20, and corresponds to a
modulo-4 counter with decoded output.
0 0
1
S0/0 S1/1
1
1
1
S3/3 S2/2
0 0
Exercise 8.17
The expression for the ip- op inputs are
JA = xQC JB = Q0A JC = xQB
KA = xQ0B KB = QA KC = x0 Q0B
From the characteristic expressions of the JK ip- op we get the following expressions for the
transition functions:
QA(t + 1) = QA (t)(x0 + QB (t)) + xQ0A(t)QC (t)
QB (t + 1) = QB (t)Q0A(t) + Q0B (t)Q0A(t)
QC (t + 1) = QC (t)(QB (t) + x) + Q0C (t)xQB (t)
z = Q0C (t)
The corresponding transition table is
PS Input Input Output
QA QB QC x=0 x=1 x=0 x=1 z
000 00,10,01 01,10,00 010 010 1
001 00,10,01 11,10,00 010 111 0
010 00,10,00 00,10,10 010 011 1
011 00,10,00 10,10,10 011 111 0
100 00,01,01 01,01,00 100 000 1
101 00,01,01 11,01,00 100 001 0
110 00,01,00 00,01,10 100 101 1
111 00,01,00 10,01,10 101 101 0
JA KA; JB KB ; JC KC NS
To get a high-level description we dene the following code:
QAQB QC state
000 S0
001 S1
010 S2
011 S3
100 S4
101 S5
110 S6
111 S7
The resulting state table is
PS Input Output
x=0 x=1 z
S0 S2 S2 1
S1 S2 S7 0
S2 S2 S3 1
S3 S3 S7 0
S4 S4 S0 1
S5 S4 S1 0
S6 S4 S5 1
S7 S5 S5 0
NS
The state diagram is shown in Figure 8.21.
A timing diagram can be obtained from the following input/output sequence pairs (the input
is arbitrary):
x(t) 0 1 0 1 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1
s(t) 0 2 3 3 7 5 4 4 0 2 3 7 5 4 0 2 2 2 3 7
z 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 1
S0/1
0,1
1
S7/0 S1/0
0,1 S6/1 S2/1 0

0
1
1 1
1
S3/0 0
S5/0
0
1
S0/1

Exercise 8.18
The expressions for the ip- op inputs are
TA = QA + Q0B
TB = QA + QB
The ip- ops change state in every clock pulse depending only on the previous state. The
transition table is
PS FF inputs NS
QA (t)QB (t) TA (t) TB (t) QA (t + 1)QB (t + 1)
00 1 0 10
01 0 1 00
10 1 1 01
11 1 1 00
QAQB
00 S0
01 S2
10 S1
11 S3
PS NS
S0 S1
S1 S2
S2 S0
S3 S0
The state diagram is presented in Figure 8.22. It is an autonomous modulo-3 counter.
S0 S1 S2 S3

Exercise 8.19
The expressions for the ip- op inputs and for the output are
JA = 1 KA = 1
JB = Q0C KB = 1
JC = QB KC = 1
z = Q0A Q0B Q0C
The sequential network does not have any input; therefore, the state register changes in each
clock pulse depending only on the previous state. The transition table is
PS FF inputs NS Output
QA (t)QB (t)QC (t) JA(t)KA (t) JB (t)KB (t) JC (t)KC (t) QA (t + 1)QB (t + 1)QC (t + 1) z(t)
000 11 11 01 110 1
001 11 01 01 100 0
010 11 11 11 101 0
011 11 01 11 100 0
100 11 11 01 010 0
101 11 01 01 000 0
110 11 11 11 001 0
111 11 01 11 000 0
QAQB QC state
000 A
001 B
010 C
011 D
100 E
101 F
110 G
111 H
The resulting transition table is
PS NS z
A G 1
B E 0
C F 0
D E 0
E C 0
F A 0
G B 0
H A 0
Let us try to reduce the number of states:
P = 1
1
( ) A (
2
B; C; D; E; F; G; H )
2 2 2 2 2 1 2 1
P2 = (A1 ) (
2
F; H ) (
3
B; C; D; E; G)
3 1 1 3 2 3 3 3
P3 = (A1) (F;2H ) (C3 ) (B; D;4 E; G)
4 1 1 2 4 4 3 4
P4 = (A1) (F;2H ) (C3 ) (E4 ) (B; D;5
G)
5 1 1 2 3 4 4 5
P5 = (A1 ) (F;2H ) (C3 ) (E4 ) (G5 ) (B;6D)
5 1 1 2 3 6 4 4
P6 = P5 = f(A); (E ); (C ); (F; H ); (G); (B; D)g

The reduced state table is
PS NS z
(A) = S0 S1 1
(E ) = S1 S2 0
(C ) = S2 S3 0
(F; H ) = S3 S0 0
(G) = S4 S5 0
(B; D) = S5 S1 0
S0/1 S1/0 S2/0
S5/0 S4/0 S3/0

The network in its equilibrium state produces a 1 every six clock pulses, that is, it implements
a modulo-6 frequency divider.
Exercise 8.20
The expressions for the ip- op inputs are:
TA = QA + QB
TB = Q0A + QB
The transition table is
PS FF inputs NS
QA (t)QB (t) TA (t)TB (t) QA (t + 1)QB (t + 1)
00 01 01
01 11 10
10 10 00
11 11 00
QAQB
00 S0
01 S1
10 S2
11 S3
PS NS
S0 S1
S1 S2
S2 S0
S3 S0
The state diagram is shown in Figure 8.24. The network implements an autonomous modulo-3
counter.
S0 S1 S2 S3

Exercise 8.21
The expressions for the ip- op inputs and for the output are
S2 = xQ01 + xQ02Q00
R2 = Q2Q1
J1 = Q0(x0 + Q2 )
K1 = Q0 + Q2
T0 = (x0 + Q2 + Q1)(Q02 + Q01 + Q0 )(x + Q02 + Q1 + Q00 )
z = (Q02 Q1 )(x0Q00 ) + Q01 (x0Q0 ) + (Q2 Q1)(xQ00) + Q1(xQ0)
The transition table is
PS Input Input
Q2 Q1 Q0 x=0 x=1 x=0 x=1
000 00 00 1 10 00 0 001,1 100,0
001 00 11 1 10 01 0 010,1 101,0
010 00 00 1 10 00 1 011,0 111,1
011 00 11 1 00 01 1 000,0 000,1
100 00 01 1 10 01 1 101,0 101,1
101 00 11 0 10 11 1 111,1 110,0
110 01 01 0 01 01 0 000,1 000,0
111 01 11 1 01 11 1 000,0 000,1
S2 R2 J1 K1 T0 NS,z
Q2Q1 Q0
000 A
001 B
010 C
011 D
100 E
101 F
110 G
111 H
PS Input
x=0 x=1
A B,1 E,0
B C,1 F,0
C D,0 H,1
D A,0 A,1
E F,0 F,1
F H,1 G,0
G A,1 A,0
H A,0 A,1
NS,z
Let us try to reduce the number of states.
P1 group 1 group 2
(A,B,F,G) (C,D,E,H)
0 1221 2111
1 2111 2111
P2 group 1 group 2 group 3 group 4 group 5
(A) (B,F) (G) (C) (D,E,H)
0 2 45 1 5 121
1 5 23 1 5 121
P3 group 1 group 2 group 3 group 4 group 5 group 6 group 7
(A) (B) (F) (G) (C) (E) (D,H)
0 2 5 7 1 7 3 11
1 6 3 4 1 7 3 11
P4 = P3 = f(A); (B); (F ); (G); (C ); (E); (D; H )g

The reduced state table is
PS Input
x=0 x=1
(A) S0 S1 ; 1 S4 ; 0
(B ) S1 S2 ; 1 S5 ; 0
(C ) S2 S3 ; 0 S3 ; 1
(D; H ) S3 S0 ; 0 S0 ; 1
(E ) S4 S5 ; 0 S5 ; 1
(F ) S5 S3 ; 1 S6 ; 0
(G) S6 S0 ; 1 S0 ; 0
NS,z
We now show that the network performs a serial conversion from BCD to Excess-3. Assume that
the initial state is S0 and that the BCD digit (x3; x2; x1; x0) is applied with the least signicant
bit (x0) rst. From the state diagram (following the corresponding paths) we get the following
table (since after a sequence of length four the state is again S0, we only consider sequences of that
length):
x3 x2 x1 x0 z3z2 z0
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1100
0/1 0/1
S0 S1 S2
1/0 0/0
1/0 1/1
0/0
1/1
S3
0/1
1/0
0/1
1/0 0/0
S6 S5 S4
1/1
This corresponds to the desired converter. A timing diagram is

x 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
State S0 S1 S2 S3 S0 S1 S2 S3 S0 S4 S5 S3 S0 S4 S5 S3
z 1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0
Exercise 8.22
Since the excitation function of a D ip- op is
D(t) = Q(t + 1)
the D input for each ip- op implementation corresponds to its characteristic function. That
is,
for a SR ip- op
D(t) = Q(t + 1) = S + R0Q(t)
for a T ip- op
D(t) = Q(t + 1) = T Q(t)
for a JK ip- op
D(t) = Q(t + 1) = Q(t)K 0 + Q(t)0J
The corresponding networks are shown in Figures 8.26.
S
Q
D Q
R CK Q’
Q’
(a)
T Q
D Q
CK
Q’
Q’
(b)
Q
D Q
K
CK Q’
Q’
(c)
Figure 8.26: Networks of Exercise 8.22

Exercise 8.23
To recognize a sequence with two consecutive 1's followed by one 0 we need to distinguish be-
tween the following cases:
S2 : x(t 2) = x(t 1) = 1
S1 : Not S2 and x(t 1) = 1
S0 : None of the above
PS Input
x=0 x=1
S0 S0 ; 0 S1 ; 0
S1 S0 ; 0 S2 ; 0
S2 S0 ; 1 S2 ; 0
NS,z
To implement these states we need at least two ip- ops. Let us dene the following state
assignment:
Q2 Q1
S0 00
S1 01
S2 10
PS Input
Q2Q1 x = 0 x = 1
00 00,0 01,0
01 00,0 10,0
10 00,1 10,0
NS,z
Since the excitation function of a JK ip- op is
PS NS
0 1
0 0- 1-
1 -1 -0
JK
the inputs J1 ; K1; J2 , and K2 to the JK ip- ops are
PS Input
Q2Q1 x = 0 x = 1
00 0-,0- 0-,1-
01 0-,-1 1-,-1
10 -1,0- -0,0-
J2 K2; J1 K1
Switching expressions for these ip- op inputs are
J2 = Q1 x J1 = Q02x
K2 = x0 K1 = 1
An expression for the output is
z = Q2 x0
Q1
Q2
J Q J Q z
CK 1 CK 2
1 K Q’ K Q’
CK
x x’

Exercise 8.24
Since the output at time t depends on the inputs at time t 3; t 2; t 1, it is necessary to
store these in the state register. That is, the register consists of three ip- ops such that
Q2 (t) = x(t 3)
Q1 (t) = x(t 2)
Q0 (t) = x(t 1)
Consequently, the state description is
Q2(t + 1) = Q1(t)
Q1(t + 1) = Q0(t)
Q0 (t) = x(t)
z = x(t 3) x(t 2) x(t 1) x(t) = Q2 Q1 Q0 x
If we use D ip- ops, we get
D2 = Q1
D1 = Q0
D0 = x
Q0 Q1
X D Q D Q D Q
FF0 FF1 FF2
Q’ Q’ Q’
CK

Exercise 8.25
We have to store the last input to be able to recognize the sequence 11; therefore, we need:
S0 : x(t 1) = 0
S1 : x(t 1) = 1
The state table is
PS Input
x=0 x=1
S0 S0 ; 0 S1 ; 0
S1 S0 ; 0 S1 ; 1
NS,z
Coding S0 as 0 and S1 as 1, the resulting state table is
PS Input
Q x=0 x=1
0 0,0 1,0
1 0,0 1,1
NS,z
We only need one JK ip- op. Since its excitation function is
PS NS
0 1
1 0- 1-
1 -1 -0
JK
the inputs are
J = x
K = x0
The output is described by
z = Qx
Z
X J Q
CK CK
K Q’

Exercise 8.26
The state corresponds to the count. That is,
s(t + 1) = (s(t) + 1) mod 3
Using a radix-2 representation for the count we get the following state table
PS Input
Q2Q1 x = 0 x = 1
00 00 01
01 01 10
10 10 00
NS
Since the excitation function of a SR ip- op is
PS NS
0 1
0 0- 10
1 01 -0
SR
we get the following switching expressions
S2 = xQ1 S1 = xQ02 Q01
R2 = xQ2 R1 = xQ1
The output is obtained directly from the state register. The sequential network is shown in
Figure 8.30.
Q2
S Q
CK CK
Q2’
R Q’
Q1
S Q
CK CK
Q1’
R Q’

Exercise 8.27
a) To design a cyclic counter with the output sequence 0; 1; 3; 7; 6; 4; 0; 1; : : : we need six states.
In this rst part, we select the coding so that the output corresponds to the state. The state table
is
PS Input
x=0 x=1
000 000 001
001 001 011
011 011 111
100 100 000
110 110 100
111 111 110
NS = z
PS NS
0 1
0 0- 1-
1 -1 -0
JK
we get the following ip- op inputs
PS Input
Q2Q1Q0 x=0 x=1
000 0- 0- 0- 0- 0- 1-
001 0- 0- -0 0- 1- -0
011 0- -0 -0 1- -0 -0
100 -0 0- 0- -1 0- 0-
110 -0 -0 0- -0 -1 0-
111 -0 -0 -0 -0 -0 -1
J2 K2 J1 K1 J0 K0
From K-maps we obtain
J2 = xQ1 K2 = xQ01
J1 = xQ0 K1 = xQ00
J0 = xQ02 K0 = xQ2
The sequential network is shown in Figure 8.31. Recall that the output z = (z2; z1; z0) corre-
sponds to the state vector (Q2 ; Q1; Q0).
b) In this second case, the state table is
z2
z1
J Q J Q J Q z0
CK 0 CK 1 CK 2
K Q’ K Q’ K Q’
CK
x
PS Input
x=0 x=1
S0 S0 S1 0
S1 S1 S2 1
S2 S2 S3 3
S3 S3 S4 7
S4 S4 S5 6
S5 S5 S0 4
NS Output
with the following encoding for the state:
Q2 Q1 Q0
S0
000
S1
001
S2
010
S3
011
S4
100
S5
101
Using the previously given excitation function for a JK ip- op, the ip- ops inputs are
PS Input Output
Q2Q1Q0 x=0 x=1 z(t)
000 0- 0- 0- 0- 0- 1- 000
001 0- 0- -0 0- 1- -1 001
010 0- -0 0- 0- -0 1- 011
011 0- -0 -0 1- -1 -1 111
100 -0 0- 0- -0 0- 1- 110
101 -0 0- -0 -1 0- -1 100
J2 K2 J1 K1 J0 K0
From K-maps we obtain
J2 = xQ1Q0 K2 = xQ0
J1 = xQ02Q0 K1 = xQ0
J0 = x K0 = x
For the output,
z2 = Q2 + Q1 Q0
z1 = Q1 + Q2 Q00
z0 = Q1 + Q02 Q0
J Q J Q J Q
CK 0 CK 1 CK 2
K Q’ K Q’ K Q’
CK
x
Q1 Q2 Q2’
Q0 z2 Q0’ Q0
z1 z0
Q2 Q1 Q1
Figure 8.32: Network for Exercise 8.27 (b)

A comparison of the networks of Figures 8.31 and 8.32 indicates that solution (a) results in a
simpler network.
Exercise 8.28
A modulo-7 up/down counter requires seven states. Since the counter is binary, the state
assignment is specied. The system has two inputs: x the variable to be counted, and c, to control
up (c = 1) or down (c = 0) counting. The state table is
PS Input
x = 0 x = 1(down) x = 1(up)
000 000 110 001
001 001 000 010
010 010 001 011
011 011 010 100
100 100 011 101
101 101 100 110
110 110 101 000
NS = z
(a) Based on the excitation function for a T ip- op we obtain the following table for ip- op
inputs:
PS Input
Q2Q1Q0 x = 0 x = 1(down) x = 1(up)
000 000 110 001
001 000 001 011
010 000 011 001
011 000 001 111
100 000 111 001
101 000 001 011
110 000 011 110
T2T1 T0
From K-maps we obtain:
T2 = x(cQ1Q0 + cQ2Q1 + c0Q01Q00)
T1 = x(cQ0 + Q2Q1 + c0 Q00) = x((c Q00 ) + Q2Q1)
T0 = x(c + Q2 + Q1 + Q0 )(c0 + Q02 + Q01 )
(b) using D-type ip- ops the next state is given as input, Q(t + 1) = D(t), so the rst table
shown in this exercise is used. This time, the next state bits for the case x = 0 have values dierent
than zero, and for this reason we need to consider the cases x = 0 and x = 1 separately. Let the
inputs of the D-type FFs be D2; D1, and D0. For the case x = 1, using K-maps, we obtain:
D2(x = 1) = Q2 Q0 + Q1Q0c + Q2Q01 c + Q2 Q1c0 + Q02 Q01Q00 c0
D1(x = 1) = Q01 Q00c0 + Q01Q0c + Q1Q0 c0 + Q02Q1Q00 c
D0(x = 1) = Q2 Q01Q00 + Q02Q00 c + Q1 Q00c0
For x = 0 the expressions for Di are:
D2(x = 0) = Q2
D1(x = 0) = Q1
D0(x = 0) = Q0
Combining both cases we obtain the expressions:
D2 = (Q2Q0 + Q1 Q0c + Q2Q01 c + Q2 Q1c0 + Q02 Q01 Q00c0 )x + Q2 x0
D1 = (Q01Q00 c0 + Q01 Q0 c + Q1 Q0c0 + Q02 Q1Q00 c)x + Q1 x0
D0 = (Q2Q01 Q00 + Q02Q00 c + Q1Q00c0)x + Q0 x0
(c) the implementation of this circuit using a combination of T and D-type ip- ops is a com-
bination of the cases presented in the previous two designs. Considering the two least signicant
state bits stored in T-type FFs and the most-signicant in a D-type FF, the switching expressions
are:
D2 = (Q2Q0 + Q1 Q0c + Q2Q01 c + Q2 Q1c0 + Q02 Q01 Q00c0 )x + Q2 x0
T1 = x((c Q00 ) + Q2 Q1)
T0 = x(c + Q2 + Q1 + Q0 )(c0 + Q02 + Q01 )
The network for this case is easily obtained from the other networks given for parts (a) and (b).
c
Q1
Q
x
c
Q2 T2 Q2
Q T Q
x
c’ CK
Q1’
Q0’
x
c
Q0’
x
c Q1 T1 Q1
T Q
Q2 Q2
Q1 x
CK
Q0
c
Q2 T0 Q0
T Q
Q1
Q0
CK
x
(a) T-type FF implementation
Q1’
Q0’
c’
Q1’
Q0
D1
c Q1
x D Q
Q1
Q0
Q2 c’ x’ CK
Q0 Q2’ Q1
Q1
Q1 Q0’
Q0 c
c
Q2
Q1’
c D2 Q2
x D Q
Q2
Q1
c’ x’ CK
Q2’ Q2
Q1’
Q0’ Q2
c’ Q1’
Q0’
Q2’
Q0’
D0
c Q0
x D Q
Q1
Q0’
c’ x’ CK
Q0
(b) D-type FF implementation
Figure 8.33: Networks for Exercise 8.28

Exercise 8.29
To recognize the sequence x(t 3; t) = 0101 or 0110 we need to distinguish among the following
cases:
S4 : x(t 3; t 1) = 011
S3 : x(t 3; t 1) = 010
S2 : x(t 2; t 1) = 01
S1 : Not S3 and x(t 1) = 0
S0 : None of the above
PS Input
x=0 x=1
S0 S1 ; 0 S0 ; 0
S1 S1 ; 0 S2 ; 0
S2 S3 ; 0 S4 ; 0
S3 S1 ; 0 S2 ; 1
S4 S1 ; 1 S0 ; 0
NS,z
Assigning to each state the binary value of its subindex the resulting state table is
PS Input
Q2 Q1Q0 x = 0 x = 1
000 001,0 000,0
001 001,0 010,0
010 011,0 100,0
011 001,0 010,0
100 001,1 000,0
NS,z
PS NS
0 1
0 0- 1-
1 -1 -0
JK
we determine the inputs J2 ; K2; J1; K1; J1, and K1 to be
PS Input
Q2Q1Q0 x=0 x=1
000 0- 0- 1- 0- 0- 0-
001 0- 0- -0 0- 1- -1
010 0- -0 1- 1- -1 0-
011 0- -1 -0 0- -0 -1
100 -1 0- 1- -1 0- 0-
J2K2 J1 K1 J0 K0
Using K-maps we get the following switching expressions:
J2 = xQ1 Q00
K2 = 1
J1 = xQ0
K1 = xQ00 + x0 Q0
J0 = x0
K0 = x
The output expression is:
z = x0Q2 + xQ1Q0
The sequential network is shown in Figure 8.34
x
Q2
Q1 J Q
Q0’ x’
CK 2
x x’ "1" Q2’ z
K Q’
x
Q0
x Q1
J Q
Q0
x CK 1
Q0’ Q1’
K Q’
x’
Q0
x’ Q0
J Q
CK
CK 0
x Q0’
K Q’

Exercise 8.30 The modulo-5 counter presented in Example 8.8 was implemented using T-type
ip- op. For this problem we need to synthesize dierent functions for D-type ip- ops. The
transition table, though, is exactly the same.
PS Input
Q2 Q1 Q0 x = 0 x = 1
000 000 001
001 001 010
010 010 011
011 011 100
100 100 000
NS
Since the D-type ip- ops has as inputs the bits of the next state (shown in the transition
table), the K-maps are:
Q0 Q0 Q0
0 0 0 0 0 0 1 1 0 1 1 0
1 - - - 0 - - - 0 - - -
Q Q Q
0 - - - 2 0 - - - 2 0 - - - 2
x x x
0 0 1 0 0 1 0 1 1 0 0 1
D2: Q1 D1 : Q1 D0: Q1
The inputs of the D-type ip- ops are:
D2 = xQ1 Q0 + x0 Q2
D1 = xQ01 Q0 + Q1 Q00 + x0 Q1
D0 = xQ02 Q00 + x0 Q0
The gate network for the sequential system is presented in Figure 8.35. Comparing Figure 8.35
with Figure 8.28 of the text we can easily see that this implementation uses more gates than the
one done with T-type ip- ops.
x
Q1
Q0
D2 Q2
D Q
x’
Q2
Q2’
CK Q’
x
Q1’
Q0
D1 Q1
Q1 D Q
Q0’
Q1’
x’ CK Q’
Q1
x
Q2’
Q0’
D0 Q0
D Q
x’
Q0
Q0’
CK Q’
Figure 8.35: Modulo-5 counter implemented using D-type ip- ops

Exercise 8.31 To implement Example 8.9 using JK ip- ops we use the following state tran-
sition table and output, that already includes the appropriate input functions for the ip- ops:
PS Input Input
Q1 Q0 01 10 11 01 10 11
00 01,0 10,1 10,0 0-1- 1-0- 1-0-
01 00,0 11,1 11,0 0{1 1{0 1{0
10 11,0 10,0 00,1 -01- -00- -10-
11 10,0 00,0 11,1 -0-1 -1-1 -0-0
NS, z J1 K1J0 K0
The Kmaps for the combinational circuit that activates the JK inputs of the ip- ops are:
x0 x0
-
-
-
01 1
0 1 1
-
-

- -
- - -
Q Q
- - - - 0 - 0
0 1
0
Q1 Q1
- -
- - - 0 1 0
J1 : x1 K1 : x1
x0 x0

- 1 0 0

- - - -
- - - -
Q
- - - - 0
Q
- 1 0 0
- - - - 0
Q1 Q1

- 10 0
-10
1
J0 : x1 K0 : x1
which result in the following expressions:
J1 = x1
k1 = x1 x0 Q00 + x00 Q0
J0 = x01
K0 = x01 + x00Q1
The gate network for this exercise is shown in Figure 8.36. This network has fewer gates than
that of Figure 8.29 of the text.
x0 x0’
x1 x1’ Q0
x1 x1
J Q
x1 x0
x0 CK 1 Q1 z
Q0’ Q0’
K Q’ x0’
x0’ Q1’
Q0 Q0
x1’ J Q
CK CK 0
x0’ Q0’
K Q’
Q1

Exercise 8.32Modulo-3 binary counter using \one ip- op per state" approach.
The counter has 3 states S 2 f0; 1; 2g, thus 3 ip- ops are required. The state codes are:
y2 y1 y0 State
001 0
010 1
100 2
The counter changes state when the input x = 1. The state diagram for the counter is shown in
Figure 8.37. The switching expressions for the network can be obtained by inspection of the state
diagram:
Y2 = S1 x + S2 x0 = y1 x + y2 x0
Y1 = y0 x + y1 x0
Y0 = y2 x + y0 x0
z1 = y2
z0 = y1
0 0 0
1 1
S0 S1 S2
1
Figure 8.37: State Diagram for a Modulo-3 Counter

The corresponding network is shown in Figure 8.38.
y2
x Y0 y0
D Q
y0
FF0
Y1 y1 z0
y1
D Q
FF1
Y2 y2 z1
D Q
y2
FF2
CK
Figure 8.38: Modulo-3 counter - Exercise 8.32

Exercise 8.33 Each state is represented by one ip- op. Consider that the input of these FFs
are represented as NA; NB; NC; ND; NE; and NF respectively. The switching expressions for
these variables are:
NA = Fx0 + Bx
NB = Ax0 + Cx
NC = Bx0 + Cx
ND = Cx0 + Ex
NE = Dx0 + Fx
NF = Ex0 + Ax
For the following output encoding

z1 z0
a 00
b 01
c 10
the switching expressions for the output are:
z0 = Dx0 + Ax + Cx + E
z1 = Bx + Dx + F
The network that corresponds to these expressions is shown in Figure 8.39.
B
x NA A D
F
D Q x’
FF0 A
z0
C C
NB B x
D Q E
A FF1
C
NC C B
D Q z1
B FF2 D
x
E
F
ND D
D Q
C FF2
F
NE E
D Q
D FF2
A
NF F
D Q
E FF2
CK

Exercise 8.34 The sequential network with a shifting state register is shown in Figure 8.40,
using a Mealy model. A Moore model implementation would require an extra ip- op.
x D Q D Q D Q D Q
FF0 FF0 FF0 FF0
CK
z

163
Chapter 9
Exercise 9.1 (a) Implement a 10 output (decimal) decoder for 2-out-of-5 code using NAND
gates. The 2-out-of-5 code represents decimal digits as shown in the following table:
i x4 x3x2 x1 x0
0 00011
1 11000
2 10100
3 01100
4 10010
5 01010
6 00110
7 10001
8 01001
9 00101
Each output zi of the decoder is activated when the input has the 2-out-of-5 code that represents
the value i in decimal and the enable input E = 1. The expressions for the outputs are:
z0 = x04 x03 x02x1 x0 E
z1 = x4 x3 x02x01x00 E
z2 = x4 x03 x2x01x00 E
z3 = x04x3 x2x01 x00 E
z4 = x4x03x02x1 x00E
z5 = x04 x3 x02x1 x00E
z6 = x04 x03 x2x1 x00E
z7 = x4 x03 x02x01 x0 E
z8 = x04 x3 x02x01 x0 E
z9 = x04 x03 x2x01x0 E
Part of the gate network for the circuit is shown in Figure 9.1.
x4 x4’ x4’
x3’
x2’ z0
x3 x3’ x1
x0
E
x2 x2’ x4
x3
x2’ z1
x1 x1’ x1’
x0’
E
x0 x0’
Figure 9.1: Network for Exercise 9.1 (a)

(b) Implement a 10 output (decimal) decoder using NAND gates for a 4-bit Gray code. The
code table is shown next.
i g3 g2g1 g0
0 0000
1 0001
2 0011
3 0010
4 0110
5 0111
6 0101
7 0100
8 1100
9 1101
The expressions for the ten outputs z0 to z9 are:
z0 = g20 g10 g00 E
z1 = g20 g10 g0E
z2 = g20 g1g0E
z3 = g20 g1 g00 E
z4 = g2g1 g00 E
z5 = g2g1g0E
z6 = g30 g2 g10 g0E
z7 = g30 g2 g10 g00 E
z8 = g3g00 E
z9 = g3g0 E
The implementation, shown in Figure 9.2, consists of six 4-input NAND gates, two 5-input NAND
gates, two 3-input NAND gates, and 14 NOT gates.
(c) Implement a 10 output (decimal) decoder using NAND gates for a 2-4-2-1 code. The code
table is shown next.
i c3 c2c1 c0
0 0000
1 0001
2 0010
3 0011
4 0100
5 1011
6 1100
7 1101
8 1110
9 1111
The switching expressions for the decoder outputs are:
z0 = c03c02 c01c00E
g2’
g1’ z0
g0’
g2’
g1’ z1
g0
g2’
g3’ g1 z2
g3 g0
g2’ g2’
g2 g1
g1’ g0’ z3
g1
g0’ g2
g0 g1 z4
g0’
g2
g1 z5
g0
g3’
g2
g1’ z6
g0
g3’
g2
g1’ z7
g0
g3 z8
g0’
g3
g0 z9
z1 = c03c02c01c0E
z2 = c03c02 c1c00E
z3 = c03c02 c1c0E
z4 = c03c2 c01c00E
z5 = c3c02 c1c0E
z6 = c3c2 c01c00E
z7 = c3c2 c01c0E
z8 = c3c2 c1c00E
z9 = c3c2 c1c0E
Part of the gate network that implements these expressions is shown in Figure 9.3.
c3 c3’ c3’
c2’ z0
c1’
c2 c2’ c0’
E
c3’
c1 c1’ c2’ z1
c1’
c0
c0 c0’ E
Figure 9.3: Gate network for Exercise 9.1 (c)

Exercise 9.2: Implement a BCD decoder using an Excess-3 decoder, a 2-input binary decoder
and a NOR gate.
The relation between BCD code and the Excess-3 code is:
x 0 1 2 3 4 5 6 7 8 9 10 11 12
z (Ex-3) - - - 0 1 2 3 4 5 6 7 8 9
y (BCD) 0 1 2 3 4 5 6 7 8 9 - - -
where x is the radix-2 representation of the input vector and z and y are the indices of the outputs
of the decoders with value 1.
From the table we see that for x between 3 and 9, the output of the Excess-3 decoder can be
relabeled to give some of the outputs of the BCD decoder. Since for x between 0 and 2, no output
of the Excess-3 decoder has value 1, it is necessary to decode these values separately. It's possible
to do this using a 2-input binary decoder that has as inputs the bits x1 and x0 (the least signicant
bits) and making the enable input active when x 3.
The corresponding network is shown in Figure 9.4, on page 167.
0
1 y4
2 y5
3 y6 BCD: (x3,x2,x1,x0)
x0 0
Excess-3 4 y7 decoded outputs: yi
x1 1
dec 5 y8
x2 2
6 y9
x3 3
7
8
E 9
E
0 y0
0
Binary 1 y1
dec y2
1 2
3 y3
Figure 9.4: BCD decoder - Exercise 9.2

Exercise 9.3 The 4-bit Odd/Even parity functions have value 1 when the number of 1s in the
input vector is odd/even. The implementation of these functions using a 4-input decoder and OR
gates is shown in Figure 9.5. The even parity is produced by output EP and the odd parity by
output OP .
I1
0 I0
1 I1 I2
2 I2 I4
3 I3 I8 OP
4 I4
x3 I7
3 5 I5
x2 6 I6 I11
2 Dec. 7 I7 I13
x1 1 8 I8
9 I9
I14
x0 0 I0
10 I10
11 I11 I3
12 I12 I5
13 I13 EP
14 I14 I6
15 I15 I9
E
I10
I12
1 I15
Figure 9.5: Parity functions - Exercise 9.3

Exercise 9.4: For a coincident decoder using n = 12 and k = 4, we use r = n=k = 3 4-input
decoders and 212 3-input AND gates.
The circuit is shown in Figure 9.6. In the gure only some of the AND gates are shown, with
the corresponding output numbers. In general, if we partition the input into groups of 4 bits, we
get:
u = 8x11 + 4x10 + 2x9 + x8
s = 8x7 + 4x6 + 2x5 + x4
t = 8x3 + 4x2 + 2x1 + x0
and the output zi = 1 if i = u28 + s24 + t.
x11 x10 x9 x8 x7 x6 x5 x4 x3 x2 x1 x0
3 2 1 0 3 2 1 0 3 2 1 0
E E Decoder E E Decoder E E Decoder
15 14 2 1 0 15 14 2 1 0 15 14 2 1 0
z4095 z4094 z31 z1 z0
Figure 9.6: Coincident decoder for Exercise 9.4

Part (a)
Exercise 9.5
number of levels in the tree of decoders = 20=4 = 5 levels.

the number of decoders in this tree = 1 + 16 + 162 + 163 + 164 = 69905 decoders.
Part (b) using coincident decoding we need ve 4-input decoders to receive the 20 inputs. We
would need 220 AND gates.
Exercise 9.6
Let us call x = (x9 ; x8; x7; x6; x5; x4; x3; x2; x1; x0) the input vector of the 10-input decoder. The
output vector will depend on the code to be generated.
(a) For the 2-out-of-5 code (consider the table presented in exercise 9.1) the expressions are:
z4 = (x1 + x2 + x4 + x7)E
z3 = (x1 + x3 + x5 + x8)E
z2 = (x2 + x3 + x6 + x9)E
z1 = (x0 + x4 + x5 + x6)E
z0 = (x0 + x7 + x8 + x9)E
(b) For the 4-bit Gray code the output vector is (z3 ; z2; z1; z0) (see table in Exercise 9.1.). The
expressions are:
z3 = (x8 + x9)E
z2 = (x4 + x5 + x6 + x7 + x8 + x9 )E
z1 = (x2 + x3 + x4 + x5 )E
z0 = (x1 + x2 + x5 + x6 + x9)E
(c) For Excess-3 code the output vector is (z3; z2; z1 ; z0). The Excess-3 code is shown in the
next table:
i z3z2 z1 z0
0 0011
1 0100
2 0101
3 0110
4 0111
5 1000
6 1001
7 1010
8 1011
9 1100
The expressions for the outputs are:
z3 = (x5 + x6 + x7 + x8 + x9)E
z2 = (x1 + x2 + x3 + x4 + x9)E
z1 = (x0 + x3 + x4 + x7 + x8)E
z0 = (x0 + x2 + x4 + x6 + x8)E
The networks of gates are easily obtained from these expressions.
Exercise 9.7
From the gure, we get the following expressions for the circuit outputs:
D = (I80 + I90 )0 = I8 I9
C = ((I80 + I90 )0:(I40 + I50 + I60 + I70 ))0
= (I8I9 :(I40 + I50 + I60 + I70 ))0
B = (I8I9:(I20 I4 I5 + I30 I4I5 + I60 + I70 ))0
= (I8I9 (I60 + I70 ) + I9I8 I7 I6 I5I4 (I30 + I20 ))0
A = ((I8I9 ):(I10 I2 I4 I6 + I30 I4I6 + I50 I6 + I70 ) + I90 )0
= (I90 + I9I8 I70 + I9 I8 I7I6 I50 + I9 I8 I7 I6I5 I4 I30 + I9 I8I7 I6 I5I4 I3 I2I10 )0
From these expression we get the following table:
I90 I80 I70 I60 I50 I40 I30 I20 I10 D' C' B' A' Output(decimal)
1 - - - - - - - - 1 0 0 1 9
0 1 - - - - - - - 1 0 0 0 8
0 0 1 - - - - - - 0 1 1 1 7
0 0 0 1 - - - - - 0 1 1 0 6
0 0 0 0 1 - - - - 0 1 0 1 5
0 0 0 0 0 1 - - - 0 1 0 0 4
0 0 0 0 0 0 1 - - 0 0 1 1 3
0 0 0 0 0 0 0 1 - 0 0 1 0 2
0 0 0 0 0 0 0 0 1 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Consequently, if Z = (D0; C 0; B 0; A0) represents a decimal digit z in BCD, we get
( 0 0
z = 0i otherwise
if (Ii = 1 for some i > 0) and (Ij = 0 for all j > i);
which corresponds to a priority encoder function.

Exercise 9.8 : (a) From Figure 9.34 of the textbook we get the following table:
BCD 7-segment display
b3b2 b1b0 abcdefg
0000 0000001
0001 1001111
0010 0010010
0011 0000110
0100 1001100
0101 0100100
0110 0100000
0111 0001111
1000 0000000
1001 0001100
The implementation of this code converter using a decoder and OR gates is shown in Figure 9.7.
The implementation using a decoder and an encoder is not ecient, and for this reason it is not
shown. Two 4-bit encoders or a large 7-bit encoder should be used, and since there is only a small
set of 7-segment codes, many of the encoder inputs would not be used, or would require OR gates
to combine two or more decoder outputs.
0 a
1
2 b
3
4 c
5
d
b0 0 6
b1 1 Binary 7
b2 2 decoder 8
e
b3 3 9
10
11
f
12
13
14 g
15
E
Figure 9.7: Network of Exercise 9.8 (a)

(b) Four-bit binary to 4-bit Gray code. The function table is:
binary Gray
b3b2b1 b0 g3g2g1 g0
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
1010 1111
1011 1110
1100 1010
1101 1011
1110 1001
1111 1000
Although the implementation by a gate network is quite simple, we show two dierent imple-
mentations in Figure 9.8. One uses a decoder and OR gates, and the other uses a decoder and
encoder.
0
g0 0 0
1
1 1
2
2 2
3
3 3
4
4 4
5 g1
5 5
b0 0 6
b0 0 6 6 0 g0
b1 1 Binary 7
b1 1 Binary 7 7 Binary 1 g1
b2 2 decoder 8
b2 2 decoder 8 8 encoder 2 g2
b3 3 9
g2 b3 3 9 9 3 g3
10
10 10
11
11 11
12
12 12
13
13 13
14 g3
14 14
15
15 15
E
E E
1
1 1
Figure 9.8: Binary to Gray-code converter - Exercise 9.8 (b)

(c) BCD to 2-out-of-5 code converter. The function table of the system follows:
BCD 2-out-of-5
b3b2 b1b0 c4c3 c2c1c0
0000 00011
0001 11000
0010 10100
0011 01100
0100 10010
0101 01010
0110 00110
0111 10001
1000 01001
1001 00101
Two implementations of this code converter, one using a decoder and OR gates, and another using
a decoder and encoder are shown in Figure 9.9.
0 c0 0 0
1 1 1
2 2 2
3 3 3
c1 4 4
4
5 5 5
b0 6 b0 0 6 6
0
b1 7 c2 b1 1 Binary 7 7
1 Binary
b2 8 b2 2 decoder 8 8
2 decoder
b3 9 b3 3 9 9
3
10 10 10
c3 11 11
11
12 12 12
13 13 13
c4 0 c0
14 14 14 Binary
1 c1
15 15 15 encoder
2 c2
E E 16
3 c3
17
1 4 c4
1 18
19
20
21
22
23
24
25
26
27
28
29
30
0
31 E
Figure 9.9: Network of Exercise 9.8 (c)

Exercise 9.9: The implementation is shown in Figure 9.10, on page 176. The outputs of the
decoder are labeled according to the Gray code and connected to the corresponding inputs of the
encoder.
0 0
g2 2 1 1 2 b2
2 2
Binary Binary
g1 1 decoder 3 3
Encoder 1 b1
4 4
g0 0 5 5 0 b0
6 6
E 7 7 E
1 1
Figure 9.10: Code converter Binary-Gray, Exercise 9.9

Exercise 9.10 A specication of the cyclic priority encoder is
z = i if xi = 1 and x(i+j)mod 8 = 0 for (j (c i) mod 8)
where c is the value of the control input.
In one implementation, a left 7-shifter is used to move the highest-priority input (xc ) to the
highest input of the priority encoder (w7). The amount of shift is therefore 7 c to the left (this
is obtained by complementing each bit of the binary representation of c).
This produces w(i+7 c)mod 8 = xi , so that if xi is the highest-priority input, the output of the
priority encoder would be (i + 7 c) mod 8. Consequently, to obtain the correct result, the output
of the encoder y has to be decremented by (7 c) mod 8. That is,
z = (y (7 c)) mod 8 = (y + c + 1) mod 8
The corresponding network is shown in Figure 9.11(a). To avoid the complementation of c, we
can use a right shift of c instead of the left shift. This would put xc in w0 instead of w7. Therefore,
the connections between the output of the shifter and the input of the priority encoder have to be
as shown in the Figure 9.11(b).
x1 -7
x2 -6
Left
x3 -5 1 x0 0
7-Shifter
x4 -4 x1 1
w0 E Right
x5 -3 0 0 1 x2 2
7-Shifter
1
x6 -2 1 1 x3 3
x7 -1 2 2 0 cin E
x4 4 0 0
x0 0 3 3 Priority 1
x5 5 1 1
x1 1 4 4 Encoder 2 z0
x6 6 2 2
x2
x3
2
3
5
6 w7
5
6
+ z1
z2
x7
x0
7
8
3
4
3
4 Encoder 2
0
Priority 1
x4 4 7 7 A x1 9 5 5
x5 5 x2 10 6 6
x6 6 x3 11 7 7 A
x7 7 x4 12
2 1 0 A
x5 13
x6 14
c0 2 1 0
c1 c2 c1 c0
c2
(b)
(a)
Figure 9.11: Cyclic priority encoder - Exercise 9.10

Exercise 9.11
Input: x 2 f0; 1; 2; 3; 4; 5; 6; 7g, represented in binary by the vector x = fx2 ; x1; x0g; xi 2 f0; 1g.
Output: y 2 f0; 1; 2; 3; 4; 5; 6; 7g, represented in binary by the vector y = fy2 ; y1; y0g; yi 2 f0; 1g
Function: y = (3x) mod 8
The function table for the system is:
x 0 1 2 3 4 5 6 7
y 0 3 6 1 4 7 2 5
The implementation of this system using a binary decoder and a binary encoder is shown in
Figure 9.12.
0 0
x2 2 1 1 2 y2
Binary 2 2 Binary
x1 1 decoder 3 3 Encoder 1 y1
4 4
x0 0 5 5 0 y0
6 6
E 7 7 E
1 1
Figure 9.12: Function y = 3x using decoder and encoder

Exercise 9.12 The 64-input encoder network in Figure 9.35 of the textbook consists of two
levels of modules. In the rst level there are eight encoders, each of them encoding part of the
input vector x. Since there is only one input with value 1, the outputs of all encoder modules are 0
except the one corresponding to this xi = 1. Also, only the corresponding A has value 1. Naming
wj the value of the 3-bit output of the encoder that has inputs xi, 8k i 8k + 7, the output is
described as:
(
wj = i mod 8 if xi = 1 for j = bi=8c
0 otherwise
and
(
Aj = 1 if xi = 1 for j = bi=8c
0 otherwise
In the second level, there are three OR gates with eight inputs each which produce (y2; y1 ; y0) and
an eight-input encoder to encode the A outputs of the rst level encoders and produce (y5; y4; y3 ).
The connection of the OR gates produces:
X
2
yj 2j = OR(w7; w6; :::; w0) = i mod 8
j =0
since all w's except one are 0.
Similarly, the output of the second-level encoder is
X
5
yj 2j = bi=8c
j =3
and, therefore,
X
5
y= yj 2j = bi=8c 23 + i mod 8 = i
j =0
and the network performs the encoding function.
Exercise 9.13 The 256-input multiplexer has eight select inputs. Since each 4-input multiplexer
has two select inputs, the tree has four levels. The number of multiplexer in each level is:
rst level: 256
4 64= 64
second level: 4 = 16 (9:1)
third level: 164 = 4
fourth level: 44 = 1
A total of 85 multiplexers distributed in four levels are required to implement a 256-input
multiplexer.
Exercise 9.14
The exercise asks for a multiplexer tree with r levels, and 2n inputs in the last level, with
n = rk. That means, each multiplexer has k selection lines and 2k inputs. Figure 9.13 shows a
block diagram of the rst and second level of the tree. We can see from the gure that from one level
to the next, the number of inputs is multiplied by p = 2k (the number of inputs of each individual
multiplexer module). For r levels, the total number of inputs in the last level is pr = 2rk = 2n .
2
p inputs
Mux Mux Mux Mux
p inputs
Level 1
Level 2
Figure 9.13: Two levels of multiplexer tree

The number of modules is:
X1
pj = p0 + p1 + p2 + : : : + pr 1 = pp 11
r r
j =0
Exercise 9.15
f (a; b; c; d) = oneset(1; 3; 4; 9; 14; 15)

abcd f (a; b; c; d)
0 0000 0
1 0001 1
2 0010 0
3 0011 1
4 0100 1
5 0101 0
6 0110 0
7 0111 0
8 1000 0
9 1001 1
10 1010 0
11 1011 0
12 1100 0
13 1101 0
14 1110 1
15 1111 1
(a) the implementation using 8-input multiplexer is presented in Figure 9.14. The expression
can be manipulated as follows:
f (a; b; c; d) = a0b0 c0d + a0 b0cd + a0bc0d0 + ab0c0 d + abcd0 + abcd
f (a; b; c; d) = m0(a; b; c)d + m1 (a; b; c)d + m2 (a; b; c)d0 + m4(a; b; c)d + m7 (a; b; c)(d0 + d)
d 0
d 1
d’ 2
0 3 f(a,b,c,d)
MUX
d 4
0 5
0 6
1 7
2 1 0
a b c
Figure 9.14: Implementation for Exercise 9.15 (a)

(b) the implementation using 4-input multiplexer is presented in Figure 9.15. The expression
for this implementation is:
f (a; b; c; d) = m0(a; b)(c0d + cd) + m1 (a; b)c0d0 + m2 (a; b)c0d + m3 (a; b)(cd + cd0)
f (a; b; c; d) = m0 (a; b)d + m1(a; b)(c + d)0 + m2 (a; b)(c + d0)0 + m3 (a; b)c
d 0
c
d 1 f(a,b,c,d)
MUX
d 2
c
3
1 0
a b

Exercise 9.16 The implementation of an 8-input multiplexer using a 3-input binary decoder
and NAND gates is shown in Figure 9.16. The selection lines s = (s2 ; s1; s0 ) are decoded and used
to make z = ij , such that j = s = s2 :22 + s1 :2 + s0 .
i0
i1
0
s2 2 1 i2
s1 Binary 2
1 decoder 3
4 i3
s0
0 5
z
6
E 7 i4
1 i5
i6
i7

Exercise 9.17
Part (a) The specication of an n bit simple shifter is given on page 265 of the textbook. A
description of an 8-bit shifter is easily obtained from there. The block diagram of the circuit is
x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x -1
s
shift/no shift
SHIFTER E
d left/right
y7 y6 y5 y4 y3 y2 y1 y0
Figure 9.17: Block diagram of 8-bits shifter

To generate each output, a 4-input multiplexer is used as shown in Figure 9.18. The selection
inputs are dened according to following table:
c1c0 Operation s d E
00 LEFT shift L 1
01 RIGHT shift R 1
10 NO SHIFT no shift - 1
11 DISABLED - - 0
Considering shift = L = 1 and no shift = R = 0 (same convention used in page 266 of the
textbook) we obtain the following Kmaps:
x
i-1 0
x yi
i 1
MUX
x
i+1
2
0
3
1 0
c1 c0
Figure 9.18: Circuit for each output of the 8-bit simple shifter
E E
1

1 1 1 1
1 0 0 1
s 10 0
1 s 10
1
c1 d c0 d
that correspond to the following expressions:
c1 = E 0 + s 0
c0 = sd + E 0
Part (b) An 8-bit bidirectional 3-shifter is specied as:

Inputs:
x = (x10; x9; x8; x7; : : :; x0; x 1; x 2; x 3 ), with xi 2 f0; 1g.
s 2 f0; 1; 2; 3g
d 2 fL; Rg
E 2 f0; 1g
Output: y = (y7 ; y6; : : :; y1; y0), with yj 2 f0; 1g.
Function:
8
>
< xi s if (d = L) and (E = 1)
yi = > xi+s if (d = R) and (E = 1) (9:2)
:0 otherwise
Let us assume that L = 1 and R = 0. Each output is generated by an 8-input multiplexer as
shown in Figure 9.19. The table for the control inputs c2c1 c0 is:
x
i-3 0
x
i-2 1
x
i-1 2 y
x i
i 3
x
i+1 4 MUX
x
i+2 5
x
i+3 6
0 7
2 1 0
c2 c1 c0
Figure 9.19: Circuit for each output of the 8-bit bidirectional shifter
Eds 000 001 002 003 010 011 012 013 100 101 102 103 110 111 112 113
c2c1 c0 111 111 111 111 111 111 111 111 011 100 101 110 011 010 001 000
The values on the table are mapped into the following Kmaps, considering that s is represented
in binary code:
s0 s0 s0

1
1

1 1 1 1
1 1

1 1 1 1

1 1 1 1
d 1 1 1 1
d
1 1 1 1
d
E
0 0 0 0
E 1 1

0 0
E
1 0 0 1
0 1 1 1
1 0
1 0 10 0
1
c2 s1 c1 s1 c0 s1
The switching expressions are:
c2 = E 0 + s1 d0 + s0 d0
c1 = E 0 + ds01 + Es1s0 + s01 s00
c0 = E 0 + s00
Exercise 9.18 The module is obtained by renaming inputs and outputs of the shift register.
For the right 3-shifter we have the specication:
Inputs:
x = (xn+2 ; xn+1 ; xn ; xn 1 ; : : :; x1; x0), with xi 2 f0; 1g
s 2 f0; 1; 2; 3g
E 2 f0; 1g
Output: y = (yn 1 ; yn 2 ; : : :; y1; y0), yi 2 f0; 1g
Function:
(
yj = x0 j+s ifotherwise
E=1 (9:3)
And we would like to have a left 3-shifter, which is specied as:
Inputs:
w = (wn 1 ; wn 2; : : :; w1; w0; w 1; w 2; w 3), with wi 2 f0; 1g
s 2 f0; 1; 2; 3g
E 2 f0; 1g
Output: z = (zn 1 ; zn 2 ; : : :; z1; z0), zi 2 f0; 1g
Function:
(
zi = w0 i s otherwise
if E = 1 (9:4)
The mapping of the inputs is
xi = wk
with k = n 1 i. Renaming the output also, we have
yj = z t
with t = n 1 j . Replacing these values on Equation 9.3 we obtain:
(
zt = x0 n 1 t+s = wn 1 (n 1 t+s) = wt s ifotherwise
E=1 (9:5)
that corresponds to a left 3-shifter. So, only renaming the inputs we are able to obtain a left shifter
from a right shitfter.
Exercise 9.19 A n-bit p-shifter has (n + 2p) input bits and n output bits. It can shift right or
left (direction input d) and the distance of shifting can vary from 0 to p.
The implementation of a 32-bit 3-shifter using four 8-bit 3-shifters is presented in Figure 9.20.
The circuit on the top is a 32-bit 3-shifter that shifts to the left only. The circuit on the bottom of
the gure is a bi-directional 32-bit 3-shifter. The input of the circuit was named i31 to i0, and the
output z31 to z0 .
i to i i to i i to i i to i
31 24 23 16 15 8 7 0
shift inputs
10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3
LEFT d d d d
distance s 8-bit 3-shifter s 8-bit 3-shifter s 8-bit 3-shifter s 8-bit 3-shifter
from 0 to 3 3 3 3 3
z to z z to z z to z z to z
31 24 23 16 15 8 7 0
LEFT 32-bit 3-shifter

i to i i to i i to i i to i
31 24 23 16 15 8 7 0
shift inputs shift inputs
10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3
LEFT/RIGHT d d d d
distance s 8-bit 3-shifter s 8-bit 3-shifter s 8-bit 3-shifter s 8-bit 3-shifter
from 0 to 3 3 3 3 3
z to z z to z z to z z to z
31 24 23 16 15 8 7 0
Bi-directional 32-bit 3-shifter
Exercise 9.20 Calling the output of stage 1 w1 and of stage 2 w2 then:

(
w1j = xj if s0 = 0
x(j+1)mod8 if s0 = 1
which indicates that this stage rotates 0 or 1 position left depending on the value of s0 .
Similarly,
(
w2j = w1j if s1 = 0
w1(j+2)mod8 if s1 = 1
Finally,
(
yj = w2j if s2 = 0
w2(j+4)mod8 if s2 = 1
and this corresponds to rotating 0 or 4 positions.
Consequently, the module rotates left s = 4s2 + 2s1 + s0 positions with 0 s 7. For example,
if the input vector is (x7 ; x6; :::; x0) = 11010110 the output vector, for a rotation of 2 to the left is:
01011011.
Exercise 9.21 Design of
Part (a) 12-bit right 3-shifter using 4-bit right shifter modules. The network is shown in Figure
9.21.
x14 x13 x12 x11 x10 x 9 x 8 x7 x6 x5 x4 x3 x2 x1 x0
6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0
dist right 3-shifter E dist right 3-shifter E dist right 3-shifter E
3 2 1 0 3 2 1 0 3 2 1 0
d
E
Figure 9.21: 12-bit right 3-shifter

Part (b) using k-bit right p-shifter modules we may implement a larger n-bit right p-shifter
using:
M = d nk e
modules of k-bit right p-shifter. The input vector of the n-bit shifter is:
x = (xn+p 1 ; xn+p 2 ; :::; xn 1; xn 2 ; :::; x1; x0)
Each k-bit shifter module i receives the vector:
x(i) = (xik+p 1 ; :::; xik+1; xik )
The enable and distance control lines of all shifters are connected together to from the control
lines of the larger shifter.
Exercise 9.22
Considering the network formed by the decoder and the multiplexer we have that
(
(w; d; e) = (f; g; h)
z = 10 ifotherwise (9:6)
where w is the output of the rst multiplexer. An expression for this output is:
w = a0b0c + bc0 + abc = ab + bc0 + a0b0 c
The gate network that implements the network in Figure 9.38 of the textbook is shown in Figure
9.22. The equality comparator that generates z is implemented using XOR and NOR gates (as
proposed in the hint). The gate network to generate w is implemented with AND and OR gates.
a
b
b w
c’
f
a’
b’ d z
c g
e
h

Exercise 9.23 The network in Figure 9.39 of the textbook has a serial line (w ) between the
MUX and DEMUX that is described as:
(
w = 0xi ifotherwise
i = 4a + 2b + c and E1 = 1 (9:7)
The outputs of the DEMUX are specied as:

(
yi = 0w otherwise
if i = 4a + 2b + c and E2 = 1 (9:8)
Combining both equations we obtain:

(
yi = 0xi otherwise
if i = 4a + 2b + c and E1 = E2 = 1 (9:9)
So, yi is the same as xi or is zero. This circuit is useful to allow the sharing of the single line
between Mux and Demux among all pairs of (input,output): (x0; y0), (x1 ; y1) ... and so on. It's
used in communication lines to divide the full capacity of the communication line among the many
transmitters and receivers. Each pair can communicate without interference of the other pairs.
Exercise 9.24
From the network we obtain:
Y0 = x0 y10 S10 + x0y1 S1 + xy10 S3 + xy1 (S2 + S0 )
= x0 y10 (y20 y0 )0 + x0 y1 y20 y0 + xy10 y2 y0 + xy1 (y2y00 + y20 y00 )
= x0 y10 y2 + x0 y10 y00 + x0 y1 y20 y0 + xy10 y2 y0 + xy1 y00
Y1 = x0 y10 (S3 + S0 ) + x0 y1(S2 + S0) + xy10 S0 + xy1 (S3 + S2 )
= x0 y10 (y2y0 + y20 y00 ) + x0 y1 (y2y00 + y20 y00 ) + xy10 y20 y00 + xy1 (y2y0 + y2 y00 )
= x0 y10 y2 y0 + x0 y10 y20 y00 + x0 y1 y00 + xy10 y20 y00 + xy1 y2
Y2 = x0 y10 (S0 + S1 ) + x0 y1 S1 + xy10 S0 + xy1 (S1 + S0)
= x0 y10 (y20 y00 + y20 y0 ) + x0 y1 y20 y0 + xy10 y20 y00 + xy1 (y20 y00 + y20 y0 )
= x0 y10 y20 + x0 y1 y20 y0 + xy10 y20 y00 + xy1 y20
z = (y2 y0)y10 x = (y20 y0 + y2 y00 )y10 x = x(y20 y10 y0 + y2 y10 y00 )
From these expressions we following state transition and output table:
State PS Input
Number y2 y1 y0 x = 0 x = 1
0 000 111,0 110,0
1 001 100,0 000,1
2 010 010,0 101,0
3 011 101,0 100,0
4 100 001,0 000,1
5 101 011,0 001,0
6 110 010,0 011,0
7 111 000,0 010,0
NS (Y2Y1 Y0 ),z
To reduce the number of states we use the minimization procedure presented in Section 7.6 of the
textbook. The rst partition is:
#1 #2
x 1 4 0 2 3 5 6 7
0 1 1 2 2 2 2 2 2
1 2 2 2 2 1 1 2 2
Second partition:
#1 #2 #3
x 1 4 0 2 6 7 3 5
0 1 1 2 2 2 2 3 3
1 2 2 2 3 3 2 1 1
Third partition:
#1 #2 #3 #4
x 1 4 0 7 2 6 3 5
0 1 1 2 2 3 3 4 4
1 2 2 3 3 4 4 1 1
No more new partitions! Stop. The reduced sequential system has only 4 states. We rename the
states as:
Sate number State name
1,4 A
0,7 B
2,6 C
3,5 D
and obtain the following state transition and output table:
PS Input
x=0 x=1
A A,0 B,1
B B,0 C,0
C C,0 D,0
D D,0 A,0
NS,z
A state diagram for the system is shown in Figure 9.23 and corresponds to a modulo-4 counter.
0/0 0/0
1/1
A B
1/0 1/0
1/0
D C
0/0 0/0
Figure 9.23: State digram for Exercise 9.24

A better canonical implementation of this sequential circuit is shown in Figure 9.24 and it uses
only two memory elements and some gates. The design steps are not shown.
Y0 y0
x x z
Y1 y1
Figure 9.24: Redesign of sequential system in Exercise 9.24
Exercise 9.25 From the circuit presented in the gure we can obtain the state diagram in
Figure 9.25. The binary decoder connected to the state register generates the signals Si , which is 1
when the sequential system is at state i. The system outputs correspond to the state signals, that
means, each output is active in one particular state. For this reason we used the output names as
state names to make the state diagram more meaningful. In each present state we identify which
input of the binary encoder is 1. This input determines the next state. For example, the origin
of arcs going into state S1 (check) are obtained by considering the input of the Binary Encoder
labeled 1, which is S0 for input GO, S2 (always, no condition), and S3 (always).
The state diagram shows the operation of a controller which starts to operate with a GO signal.
During operation it monitors two variables: dist and count and issues movement control signals
and counter control signals, until (dist 10) and (count = 3).
GO’
(dist 10) and

Initial CLEAR
COUNT
GO
check
6
(count = 3) turn
left
(dist 10) and

(count = 3)
dist > 10
stop move count
up

Exercise 9.26. The codewords of both systems are presented in the following table:
n Code A Code B
p = (3n) mod 16 q = (7n) mod 16
p2 p1p0 q2 q1 q0
0 0000 0000
1 0011 0111
2 0110 1110
3 1001 0101
4 1100 1100
5 1111 0011
6 0010 1010
7 0101 0001
8 1000 1000
9 1011 1111
10 1110 0110
11 0001 1101
12 0100 0100
13 0111 1011
14 1010 0010
15 1101 1001
(a) the design of an A-to-B converter using one 8-input multiplexer and one 2-input XOR gate
is shown in Figure 9.26. Observe that:
q0 = p0
q1 = p1
q2 = p2 p0
and q3 is easily implemented using an 8-input multiplexer from the following function table:
p3 p2p1 p0 q3
0000 0
0001 1
0010 1
0011 0
0100 0
0101 0
0110 1
0111 1
1000 1
1001 0
1010 0
1011 1
1100 1
1101 1
1110 0
1111 0
(b) the code converter designed using one 4-input decoder and one 16-input encoder is shown
in Figure 9.27.
p0
q0
p1 q1
p2
q2
0
1
0 2
1 3 MUX q3
4
5
1 6
0 7 2 1 0
p3 p2 p1
Figure 9.26: Code converter - Exercise 9.26 (a)
0 0
1 1
2 2
3 3
4 4
5 5
p0 0 6 6 0 q0
p1 1 Binary 7 7 Binary 1 q1
p2 2 decoder 8 8 encoder 2 q2
p3 3 9 9 3 q3
10 10
11 11
12 12
13 13
14 14
15 15
E E
1 1
Figure 9.27: Code converter - Exercise 9.26 (b)

189
Chapter 10
Exercise 10.1 Comparison of FA implementations
(a) using a two-level network (Fig. 10.3(a) of the textbook) the critical path for the circuit has
3 gates. The path connects the input xi (or yi or ci ) and output zi . The propagation delay of this
path is obtained as:
TpHL(xi ! zi ) = tpHL (NOT ) + tpLH (NAND 3) + tpHL (NAND 4)
TpHL(xi ! zi ) = 0:05 + 0:017 2 + 0:07 + 0:038 1 + 0:12 + 0:051L
TpHL(xi ! zi ) = 0:312 + 0:051L
TpLH (xi ! zi ) = tpLH (NOT ) + tpHL(NAND 3) + tpLH (NAND 4)
TpLH (xi ! zi ) = 0:02 + 0:038 2 + 0:09 + 0:039 1 + 0:10 + 0:037L
TpLH (xi ! zi ) = 0:325 + 0:037L
However, the delay of the path connecting the carry input to the carry output is also important
for carry ripple adders. This path has a worst case delay:
TpHL(ci ! ci+1 ) = tpLH (NAND 2) + tpHL (NAND 3)
TpHL(ci ! ci+1 ) = 0:05 + 0:038 + 0:09 + 0:039L
TpHL(ci ! ci+1 ) = 0:18 + 0:039L
TpLH (ci ! ci+1 ) = tpHL (NAND 2) + tpLH (NAND 3)
TpLH (ci ! ci+1 ) = 0:08 + 0:027 + 0:07 + 0:038L
TpLH (ci ! ci+1 ) = 0:18 + 0:038L
The number of equivalent gates is:
gate type number of gates equivalent gates
NOT 3 3 1 = 3
NAND-3 5 5 2=10
NAND-2 3 3 1=3
NAND-4 1 1 2 = 2
Total 18
(b) using HA (Fig. 10.3(b) of the textbook)
The critical path for this circuit has 3 gates: XOR-2, AND-2 and OR-2. The path connects the
input xi (or yi ) and output ci+1 . The propagation delay of this path is obtained as:
TpHL(xi ! ci+1 ) = tpHL (XOR 2) + tpHL(AND 2) + tpHL(OR 2)
TpHL(xi ! ci+1 ) = 0:3 + 0:021 3 + 0:16 + 0:017 + 0:2 + 0:019L
TpHL(xi ! ci+1 ) = 0:74 + 0:019L
TpLH (xi ! ci+1 ) = tpLH (XOR 2) + tpLH (AND 2) + tpLH (OR 2)
TpLH (xi ! ci+1 ) = 0:3 + 0:036 3 + 0:15 + 0:037 + 0:12 + 0:037L
TpLH (xi ! ci+1 ) = 0:72 + 0:037L
XOR-2 2 2 3 = 6
AND-2 2 2 2=4
OR-2 1 1 2=2
Total 12
(c) using XOR and NAND gates (Fig. 10.3(c) of the textbook)
As the NAND gates have smaller propagation delays than XOR gates, the critical path for
this circuit is through the 2 XOR gates. The path connects the input xi (or yi ) and output zi .
Observe that when the rst XOR gate is connected to the input with higher load factor of the
second XOR gate, the delay of the second XOR gate is reduced. So, two cases must be considered.
The propagation delay of this path is obtained as:
TpLH (xi ! zi ) = tpLH (XOR 2) + tpLH (XOR 2)

TpLH (xi ! zi ) = max(0:3 + 0:036 3 + 0:16 + 0:036L; 0:3 + 0:036 2:1 + 0:3 + 0:036L)
TpLH (xi ! zi ) = max(0:568 + 0:036L; 0:6756 + 0:036L)
TpLH (xi ! zi ) = 0:68 + 0:036L
TpHL(xi ! zi ) = tpLH (XOR 2) + tpHL(XOR 2)
TpHL(xi ! zi ) = max(0:3 + 0:036 3 + 0:15 + 0:020L; 0:3 + 0:036 2:1 + 0:3 + 0:021L)
TpHL(xi ! zi ) = max(0:558 + 0:02L; 0:6756 + 0:021L)
TpHL(xi ! zi ) = 0:68 + 0:021L
The carry output propagation delay is:
TpLH (ci ! ci+1 ) = tpHL (NAND 2) + tpLH (NAND 2)
TpLH (ci ! ci+1 ) = 0:08 + 0:027 + 0:05 + 0:038 L
TpLH (ci ! ci+1 ) = 0:16 + 0:038L
TpHL(ci ! ci+1 ) = tpLH (NAND 2) + tpHL (NAND 2)
TpHL(ci ! ci+1 ) = 0:05 + 0:038 + 0:08 + 0:027L
TpHL(ci ! ci+1 ) = 0:17 + 0:027L

XOR-2 2 2 3 = 6
AND-2 3 3 1=3
Total 9
This last implementation is the one with the least number of gates. It also has less propagation
delay for the carry than case (a).
Exercise 10.2 Analysis of a 4-bit binary Carry Ripple Adder using the HA implementation
with NANDs presented in Figure 10.3c of the textbook, each FA has 3 NAND-2 and 2 XOR-2
gates. Given the number of equivalent gates of the NAND-2 (1) and XOR-2 (3), the FA has a size
of 9 equivalent gates, and the 4-bit CRA has size 4 9 = 36 equivalent gates.
The input load factors for the FA are:
Input load factor
Input load
xi 2.1
yi 3
ci 3
where we assume that the XOR input with highest load (2) is used for yi and ci .
The worst case delay is given in the book (page 281) as:
tp = tXOR + 2(n 1)tNAND + max(2tNAND; tXOR)
Two NAND gates in series have a delay:
tpLH (NAND NAND) = 0:08 + 0:027 + 0:05 + 0:038L = 0:16 + 0:038L
tpHL(NAND NAND) = 0:05 + 0:038 + 0:08 + 0:027L = 0:17 + 0:027L
and since cin is connected to the XOR input with L = 2, the XOR delay is:
tpLH (XOR 2) = 0:16 + 0:036L
tpHL(XOR 2) = 0:15 + 0:020L
Since the XOR gate may complement or not its input; any type of input transition may cause
a desired output transition. The worst delay of the series of NAND gates is for LH transition. In
this case, the critical path for each type of transition is:
LH transition: XOR-2 ! 4 two NAND-2 ! XOR-2
HL transition: XOR-2 ! 5 two NAND-2
and the delays are:
TpLH (x0 ! z3) = 0:3 + 0:021 2:1 + 3 (0:168 + 0:027 3) + 0:16 + 0:036L
TpLH (x0 ! z3 ) = 1:25 + 0:036L
TpHL(x0 ! c4 ) = 0:3 + 0:021 2:1 + 3 (0:168 + 0:027 3) + 0:17 + 0:027L
TpHL(x0 ! c4 ) = 1:26 + 0:027L
Analysis of the 4-bit Carry Look-ahead Adder (Figure 10.5 from the textbook):
In order to have a fair comparison, we replace the AND-OR network inside the CLG by a
NAND-NAND network. No decomposition into smaller gates is necessary since NANDs with 5
inputs are available on Table 4.1 of the textbook.
The network size of the CLA when using NAND gates inside the CLG is:
Gate type Number Eq. gate Size
XOR2 8 3 24
AND2 4 2 8
NAND2 5 1 5
NAND3 4 2 8
NAND4 3 2 9
NAND5 2 4 8
OR4 1 3 3
AND4 1 3 3
Total 68
For the delay we examine two possibilities:
Option 1:
tpLH (x0 ! c4) = tpLH (XOR2) + tpHL(NAND5) + tpLH (NAND5)
tpLH (x0 ! c4) = 0:3 + 0:036 5:1 + 0:34 + 0:019 + 0:21 + 0:038L = 1:05 + 0:038L
tpHL(x0 ! c4) = tpHL (XOR2) + tpLH (NAND5) + tpHL(NAND5)
tpHL(x0 ! c4) = 0:3 + 0:021 5:1 + 0:21 + 0:038 + 0:34 + 0:019L = 1:00 + 0:019L
Option 2:
tpLH (x ! z ) = maxftpLH (XOR2) + tpHL(NAND4) + tpLH (NAND4); tpHL(XOR2) +
0 3
tpLH (NAND4) + tpHL(NAND4)g + 0:16 + 0:036L

tpLH (x ! z ) = maxf0:3 + 0:036 5:1 + 0:12 + 0:051 + 0:10 + 0:037 2;
0 3
0:3 + 0:021 5:1 + 0:10 + 0:037 + 0:12 + 0:051 2g + 0:16 + 0:036L

tpLH (x ! z ) = maxf0:66; 0:77g + 0:16 + 0:036L
0 3
tpLH (x ! z ) = 0:93 + 0:036L

0 3
tpHL(x ! z ) = maxf: : :g + 0:15 + 0:020L

0 3
tpHL(x ! z ) = 0:77 + 0:15 + 0:020L = 0:92 + 0:020L

0 3
From these equations we determine the network delay taking the largest values for LH and HL
transitions from both options:
tpLH (x0 ! c4) = 1:05 + 0:038L
tpHL(x0 ! c4) = 1:00 + 0:019L
From these gures we conclude that the CLA adder uses more gates than the ripple carry adder
but has a smaller propagation delay.
Exercise 10.3 The BCD to Excess-3 converter using 4-bit binary adder is shown in Figure 10.1.
BCD
code 0011
not used Binary 0

cout Adder cin
Excess-3
Code
Figure 10.1: BCD to Excess-3 converter - Exercise 10.3

Exercise 10.4BCD Addition
When we add two BCD digits (0..9), considering a carry-in bit, the range of values obtained is
from 0 to 19. The output consists of a carry out and a digit coded in BCD also.
s = ((a + b + CIN ) mod 10
(a + b + CIN ) 10
COUT = 01 ifif otherwise
where s; a and b are BCD digits.
When the integers a and b are applied to the inputs of the binary adder, the output is:
z = ((a + b + CIN ) mod 24
(a + b + CIN ) 24
C0 = 01 ifif otherwise
So, looking at the binary adder output and comparing to the expected output for the BCD
adder, we must consider three cases:
(i) C0 = 0 and z < 10: the output of the binary adder does not need correction
(ii) 10 z 15 and C0 = 0: in this case we convert the sum as follows:
s = z mod 10 = (z 10) = (z + 6) mod 16
As the operation is done with 4 bits, adding 6 is equivalent to subtracting 10.
COUT = 1
(iii) C0 = 1: in this case z = (A + B + Cin ) 16 and we want s = (A + B + Cin ) mod 10. For
this range of values we have (A + B + Cin ) mod 10 = (A + B + Cin ) 10, so we make:
s =z+6
COUT = 1
Therefore, to obtain the BCD adder, the following operations must be performed to the binary
adder output (z ):
(
s = (zz + 6) mod 16 ifif 10z 9 and C0 = 0
z 15 or C = 1
0
(
COUT = 0 if z 9 and C0 = 0
1 if z 10 or C0 = 1
The condition z 10 or C0 = 1 is described by the switching expression:
w = (z1 z3 + z2 z3 + C0 )
The circuit is shown in Figure 10.2.
a
_ _
b
Binary cin =0
Adder
0 0
Binary 0
Adder
Cout s
_
Figure 10.2: BCD adder (Exercise 10.4)

Exercise 10.5: Adder of decimal digits in Excess-3 code.
Let a and b be the decimal digits to be added. The addition is described by:
s = ((a + b + Cin) mod 10
if (a + b + Cin ) 10
Cout = 01 otherwise
The relation between the Excess-3 and the binary representation of a is:
ar (E3 ) = ar (bin ) + 3
where
X
3
ar (bin) = ai(bin )2i
i=0
X
3
ar (E3 ) = ai(E3 )2i
i=0
and similarly for b and s.
Consequently, the digit addition is described by the following expressions:
(a) If (ar (E3 ) + br (E3 ) + Cin ) < 16) (that means (a + b + Cin ) 9), then
sr (E3 ) = ar (E3 ) + br (E3 ) 3 + Cin
and
Cout = 0
(b) If (ar (E3 ) + br (E3 ) + Cin ) 16) then
sr (E3 ) = ar (E3 ) + br(E3 ) 3 + Cin 10
and
Cout = 1
Now consider the implementation. If we apply a and b in E3 code to a 4-bit binary adder we
get the sum z and the carry-out bit (Co ) as:
z = (ar (E3 ) + br (E3 ) + Cin) mod 16
and
Co = 1 if (ar (E3 ) + br (E3 ) + Cin) 16
Comparing the expressions for (sr ; Cout) and (z; Co) we get:
(
sr (E3 ) = zz + 33 ifif CCo = 0
o=1
Cout = Co
and since z 3 = (z + 13) mod 16, we obtain the network of Figure 10.3, on page 197.
_a b_
4 4
Cout Binary Adder Cin
4
_z Excess-3 adder
Binary Adder
4
_s
Figure 10.3: Excess-3 adder - Exercise 10.5

Exercise 10.6 The connection between the decoder and the encoder implies:
w = (a; b; c) = (x + 2) mod 8
Considering x and y the integers represented by (x2; x1; x0) and (y2 ; y1; y0), respectively, the
output of the adder is:
z = (w + y ) mod 8
and substituting w, we get:
z = (x + y + 2) mod 8
The switching functions can be obtained introducing the appropriate codes for variables x and
y , and specifying the functions by means of tables or expressions. This process is straighforward.
However, the obtained high-level description indicates that the system can be implemented with
two 3-bit adders to add up x, y , and 2 in modulo 8. The value An equivalent network with fewer
modules is shown in Figure 10.4.
x2 x1 x0 y2 y1 y0
Binary cin 0
ADDER
0 1 0
Binary cin 0
ADDER
z2 z1 z0

Exercise 10.7
Input: A; B 2 f0; 1; 2; 3g and Cin 2 f0; 1g
Output: Z 2 f0; 1; 2; 3g and Cout 2 f0; 1g
Function:
Z = ((A + B + Cin) mod 4
C = 1 if (A + B + Cin) 4
out 0 otherwise
A function table is shown in Table 10.1.
The Kmaps for the cases cin = 0 and cin = 1 are shown next:
cin = 0
b0 b0 b0

0 0
1 1 0
0 0
01 00
0
1 0
1 a

1 1 0
0
01 1 a 1 0 1 0 1 0 0 1 a

1 1
0 0 10 0
0 0 0
a1 0 1 a1 a1 1
0 0 1 1
0 1 1 0
Cout : b1 z1 : b1 z0 : b1
Inputs Outputs
i Cin a1 a0 b1 b0 C out z1 z0
0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 1
2 0 0 0 1 0 0 1 0
3 0 0 0 1 1 0 1 1
4 0 0 1 0 0 0 0 1
5 0 0 1 0 1 0 1 0
6 0 0 1 1 0 0 1 1
7 0 0 1 1 1 1 0 0
8 0 1 0 0 0 0 1 0
9 0 1 0 0 1 0 1 1
10 0 1 0 1 0 1 0 0
11 0 1 0 1 1 1 0 1
12 0 1 1 0 0 0 1 1
13 0 1 1 0 1 1 0 0
14 0 1 1 1 0 1 0 1
15 0 1 1 1 1 1 1 0
16 1 0 0 0 0 0 0 1
17 1 0 0 0 1 0 1 0
18 1 0 0 1 0 0 1 1
19 1 0 0 1 1 1 0 0
20 1 0 1 0 0 0 1 0
21 1 0 1 0 1 0 1 1
22 1 0 1 1 0 1 0 0
23 1 0 1 1 1 1 0 1
24 1 1 0 0 0 0 1 1
25 1 1 0 0 1 1 0 0
26 1 1 0 1 0 1 0 1
27 1 1 0 1 1 1 1 0
28 1 1 1 0 0 1 0 0
29 1 1 1 0 1 1 0 1
30 1 1 1 1 0 1 1 0
31 1 1 1 1 1 1 1 1
Table 10.1: Function table of a 2-bit adder

cin = 1
b0 b0 b0

0 1 0
1 10 0

0 0 1 0
1 1 0 0
1
1
0 0 1 1 a

a 0 1 1 0 a

01 00
11 10 0
1 1
0 0 0
a1 1
0
1
1
1 a1 a1 0

1
1

1 0 0 1
Cout : b1 z1 : b1 z0 : b1
The following logic expressions are obtained from the K-maps.
Cout = (a1 b1 + a1 a0 b0 + a0b1 b0)c0in + (a1 b1 + a0b1 + a1 b0 + b1b0 + a1a0 )cin
z1 = (b1b00a01 + a01a00 b1 + a1 a0b1 b0 + a01 a0 b01b0 + a1 a00b01 + a1 b01b00)c0in
+(a01 a00 b1b00 + a1 a00b01b00 + a1 b1b0 + a1 a0 b1 + a01 a0 b01 + a01b01 b0)cin
z0 = (a00 b0 + a0 b00)c0in + (a0b0 + a00 b00)cin
Using boolean algebra we reduce the expressions to:

Cout = a1 b1 + a0b1 b0 + a1 a0 b0
+ cin b1b0 + cin a0 b1 + cin a1 a0 + cin a1 b0
z1 = a01 a00 b1b00 + a01a0 b01b0 + a1 a0 b1b0 + a1a00 b01b00
+ cin a01 b01b0 + cin a01 a0b01 + cin a1 a0 b1 + cin a1b1 b0
+ c0in a01 a00b1 + c0in a01 b1b00 + c0in a1 b01b00 + c0in a1 a00 b01
z0 = cina00 b00 + cina0 b0 + c0ina0 b00 + c0ina00 b0
From the equations, we count 26 NAND gates, with a maximum fan-in of 12 inputs. We assume
that NOT gates are used to obtain the complement of the input variables, so 5 NOT gates are also
used in the network. The network has one level of NOT gates, and two levels of NAND gates.
Internally, all NAND gates in the intermediate level are connected to only one input of the next
level, all loads are 1. The loads of the input signals and their complements (generated by the NOT
gates) are:
Signal Load
a1 11
a01 6
b1 11
b01 6
a0 11
a00 6
b0 11
b00 6
c 11
c0 6
Exercise 10.8 Design of a 6-bit CLA adder using gates with a maximum of 4 inputs. The
section that generates propagate and generate signals doesn't need gates with more than 2 inputs.
The same for the last layer of XOR gates that generates the nal sum. The highest fan-in is required
by the gates inside the CLG module. The expressions for the CLG outputs are:
c6 = g5 + p5 g4 + p5p4 g3 + p5p4 p3 g2 + p5 p4 p3p2 g1 + p5p4 p3 p2p1 g0 + p5p4 p3p2 p1 p0c0
c5 = g4 + p4g3 + p4p3 g2 + p4p3 p2 g1 + p4p3p2p1 g0 + p4p3 p2 p1p0 c0
c4 = g3 + p3g2 + p3p2 g1 + p3p2 p1 g0 + p3p2p1p0 c0
c3 = g2 + p2 g1 + p2p1 g0 + p2p1 p0 c0
c2 = g1 + p1g0 + p1p0 c0
c1 = g0 + p0 c0
P = p5p4p3p2 p1p0
G = g5 + p5g4 + p5p4 g3 + p5p4 p3 g2 + p5 p4 p3p2 g1 + p5p4 p3 p2p1 g0
From these expressions we observe that AND and OR gates with 5, 6 and 7 inputs are required.
We decompose these gates into three gates. The implementation of the 6-bit CLA is shown in
Figure 10.5. From the Figure we count 66 gates distributed in 6 levels.
x5 x4 x3 x2 x1 x0
y5 y4 y3 y2 y1 y0
g5 p5 g4 p4 g3 p3 g2 p2 g1 p1 g0 p0
c0
p0
c0
p2 c2 p1 c1
p3 c3
P s3 s2 s1 s0
c6 p5 c5 p4 c4
G
s5 s4
Figure 10.5: 6-bit CLA using gates of at most 4 inputs - Exercise 10.8
Exercise 10.9 Design of 64-bit adders.
a) a Ripple Carry Adder (RCA) using 4-bit adder modules is shown in Figure 10.6. This
implementation of a 64-bit adder needs 16 adder modules (CLA-4). The delay is:
TCRA = CLA xy c4 + 14 CLA c0 c4 + maxfCLA c0 c4 ; CLA c0 s3 g
where CLA xy c4 is the delay to propagate the signal from input to the carry output of the 4-bit
CLA, and CLA c0 c4 and CLA c0 s3 are the delays from the input c0 to the carry out c4 and the
sum output bit s3 , respectively.
y_ _x y_ x_ y_ x_
15 15 1 1 0 0
4 4 4 4 4 4
cout cin
4-bit adder 4-bit adder 4-bit adder
15 1 0
4 4 4
_z15 _z _z 0
1
Figure 10.6: Carry Ripple Adder (CRA) - Exercise 10.9

Based on a NAND-NAND implementation of the 4-bit CLG that is part of the 4-bit CLA we
obtain:
CLA xy c4 =tLH (XOR 2) + tHL(NAND 5) + tLH (NAND 5)
=0:30 + 0:036 5:1 + 0:34 + 0:019 1 + 0:21 + 0:038L
=1:05 + 0:038L
CLA c0 s3 =tLH (XOR 2) + tHL(NAND 4) + tLH (NAND 4)
=0:3 + 0:036L + 0:21 + 0:038 1 + 0:34 + 0:019 2
=0:93 + 0:036L
CLA c0 c4 =tHL(NAND 5) + tLH (NAND 5)
=0:21 + 0:038 1 + 0:34 + 0:019L
=0:59 + 0:019L
Based on the fact that the input load of c0 is 4, we obtain the delay of the CRA as:
TCRA = 1:07 + 0:019 4 + 14(0:59 + 0:019 4) + 0:93 + 0:036L
= 11:4 + 0:036L
b) a Carry-lookahead Adder (CLA) using 4-bit carry-lookahead adder modules (CLA-4) and
4-bit carry-lookahead generator modules (CLG-4) is presented in Figure 10.7. Note that this design
is an extension of the design showed in Figure 10.8 of the textbook.
Observe from the Figure that 20 modules are necessary, 16 CLA modules and 4 CLG modules.
The delay of this adder can be calculated considering the following module delays:
CLA xy PG = CLA xy c4 = 1:07 + 0:019L
CLG = pg c4 CLA c0 c4 = 0:59 + 0:019L
CLG = c0 c3 tHL(NAND 4) + tLH (NAND 4)
= 0:21 + 0:038 1 + 0:34 + 0:019L
= 0:59 + 0:019L
CLA c0 s3 = tLH (XOR 2) + tHL (NAND 4) + tLH (NAND 4)
= 0:3 + 0:036L + 0:21 + 0:038 1 + 0:34 + 0:019 2
= 0:93 + 0:036L
The load of the p, g , and c0 inputs of the CLG is 4.
The total delay is:
TCLA = CLA xy PG + CLG pg c4 + 2 CLG c0 c4 + CLG c0 c3 + CLA c0 s3
= 1:07 + 0:019 4 + 0:59 + 0:019 4 + 2(0:59 + 0:019 4) + 0:59 + 0:019 4
+0:93 + 0:036L
= 4:74 + 0:036L
c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c8 c4
y15 x- 15 y14 x- 14 y13 x- 13 y12 x- 12 y11 x- 11 y10 x- 10 y 9 x- 9 y 8 x- 8 y 7 x- 7 y 6 x- 6 y 5 x- 5 y 4 x- 4 y 3 x- 3 y 2 x- 2 y 1 x- 1 y 0 x- 0 cin
- - - - - - - - - - - - - - - -
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
_z15 _z14 _z13 _z12 _z11 _z10 _z 9 _z 8 _z 7 _z 6 _z 5 _z 4 _z 3 _z 2 _z 1 _z 0
CLG-4 CLG-4 CLG-4 CLG-4
c64 c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c8 c4
Figure 10.7: 64-bit CLA with 1 level of CLGs - Exercise 10.9

Another approach is to use one more level of CLGs, this time to generate the carries of groups
of 16 bits. This scheme is presented in Figure 10.8. The propagation delay of this case is:
TCLAv2 = CLA
+ CLG pg pg + CLG pg c3 + CLG c0 c3 + CLA c0 s3
xy PG
where CLG pg pg = CLA c0 c4 = CLG pg c3 = CLG c0 c3 = 0:59 + 0:019L. Thus
TCLAv2 = 1:07 + 0:019 4 + 3(0:59 + 0:019 4) + 0:93 + 0:036L
TCLAv2 = 4:07 + 0:036L
which results in a faster implementation of the CLA, at the cost of one extra CLG-4 module.
c60 c56 c52 c48 c44 c40 c36 c32 c28 c24 c20 c16 c12 c8 c4
y15 x- 15 y14 x- 14 y13 x- 13 y12 x- 12 y11 x- 11 y10 x- 10 y 9 x- 9 y 8 x- 8 y 7 x- 7 y 6 x- 6 y 5 x- 5 y 4 x- 4 y 3 x- 3 y 2 x- 2 y 1 x- 1 y 0 x- 0 cin
- - - - - - - - - - - - - - - -
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
_z15 _z14 _z13 _z12 _z11 _z10 _z 9 _z 8 _z 7 _z 6 _z 5 _z 4 _z 3 _z 2 _z 1 _z 0
CLG-4 CLG-4 CLG-4 CLG-4
c48 c32 c16
2 2 2 2
c60 c56 c52 c44 c40 c36 c28 c24 c20 c12 c8 c4
CLG-4
c64 c48 c32 c16
Figure 10.8: 64-bit CLA with 2 levels of CLGs - Exercise 10.9

Exercise 10.10:
considering radix r = 2
case (a) | two's complement, n = 7 bits; C = 27
case (b) | one's complement, n = 8 bits; C = 28 1
case (c) | two's complement, n = 5 bits; C = 25
case (d) | two's complement, n = 8 bits; C = 28
Signed Integer - x Representation - xR Bit vector
(in decimal) (in decimal)
(a) -37 91 1011011
(b) -50 205 11001101
(c) -5 27 11011
(d) 9 9 00001001
We present now the calculations performed to obtain the numbers for the rst row (a). These
numbers can be obtained in two dierent ways: using expressions or manipulating the vector of
digits (or bits, if r = 2).
Using the expression for x < 0, we know that:
jxj = C xR = 2 7
xR = 37
So,
xR = 27 37 = 128 37 = 91
.
The vector of bits is easily obtained from this number in base 10.
Another way is to manipulated the vector of digits. As we know, for two's complement number
system, the representation of a number with a dierent sign is obtained complementing all digits
with respect to (r 1) (the greatest digit) and adding one. First we get the representation for jxj:
jxj = (37) = 0100101
10
note that the number was represented using n = 7 bits.

1011010
+ 1 (10:1)
1011011
Where 1011011 = (91)10 = xR .
Exercise 10.11:
Fixed-point number representation: (x6x5 x4:x3 x2x1 x0 )
(a) Sign-and-magnitude: the most signicant bit corresponds to the sign
xmax = 011:1111 ! 2 24 1 = 3:9375

6
xmin = 111:1111 ! (224 1) = 3:9375

6
(b) Two's Complement
xmax = 011:1111 ! 2 24 1 = 3:9375

6
xmin = 100:0000 ! 2 2+4 2 = 4:0

7 6
(c) One's Complement
xmax = 011:1111 ! 2 24 1 = 3:9375

6
xmin = 100:0000 ! (2 241) + 2 = 3:9375

7 6
Exercise 10.12: For addition we use the following table:
Kx Ky Kmx c0 x y z = x + y cout = c8 ovf zero sgn
0 0 1 0 01010011 00100111 01111010 0 0 0 0
0 0 1 0 01010011 01000001 10010100 0 1 0 1
0 0 1 0 10101010 10100000 01001010 1 1 0 0
0 0 1 0 10101010 11110001 10011011 1 0 0 1
0 0 1 0 10110110 00110011 11101001 0 0 0 1
0 0 1 0 10110110 01100111 00011101 1 0 0 0
For subtraction we use the table:
Kx Ky Kmx c0 x y z = x y cout = c8 ovf zero sgn
0 1 1 1 01010011 00100111 00101100 1 0 0 0
0 1 1 1 01010011 01000001 00010010 1 0 0 0
0 1 1 1 10101010 10100000 00001010 1 0 0 0
0 1 1 1 10101010 11110001 10111001 0 0 0 1
0 1 1 1 10110110 00110011 10000011 1 0 0 1
0 1 1 1 10110110 01100111 01001111 1 1 0 0
Exercise 10.13:
(a) to show that the addition in one's complement can be performed by two steps let us consider
two numbers x and y represented by xR = x mod C and yR = y mod C , where C = 2n 1. We
want to obtain sR = wR mod C , where wR = xR + yR is the result of the addition, represented by
the vector wR = fwn ; wn 1; : : :; w1; w0). The most signicant bit of wR is the carry out bit of the
n bit addition performed with xR and yR. Since xR ; yR < C , wR < 2C . We must consider the
following 3 cases:
1. If wR < C then wR mod C = wR and wn = 0
2. If wR = C then wR mod C = 0 and wn = 0
3. If 2C > wR > C then wR mod C = wR C = wR 2n + 1 and wn = 1
Consequently, if wn = 0, the result is equal to wR, and if wn = 1 the result is obtained discarding
wn (subtracting 2n ) and adding 1. Note that case (2) produces a result vector (1; 1; : : :; 1), which
is correct since this is another representation of 0 in the one's complement system.
(b) To verify that the operation of the adder with the carry output connected to the carry-in
is combinational we consider the following cases:
there is a combination 00 or 11 for one particular bit position. In that case the carry chain
is broken by this combination. No active loop.
there is no combination 00 or 11, that means, all bit positions have the combination 01. In
that case, there is an active loop. To have a stable result all carries have to be reset to zero
before the operation starts.
Figure 10.9 shows examples of both cases.
Some position with 00 or 11 All positions with 01 or 10

011011010 cout 1 = cin
100110101 011001010
+
ppppgpppp 100110101
1 111111110
spureous carry!
c 0
carry bit 011001010
100110101
0 111101111
carry chain carry chain
no active loop active loop
Figure 10.9: Example of carry chains for One's complement adder - Exercise 10.13 (part b)
Exercise 10.14: Implementation of addition in Sign-and-magnitude with 8 bits (including the
sign bit).
The algorithm for addition z = a + b in sign-and-magnitude representation is as follows:
Input: a represented by (as ; am ), b represented by (bs; bm).
Output: z represented by (zs ; zm ).
Algorithm:
IF as = bs THEN zm = am + bm
zm = am
ELSE
IF (am bm ) THEN zm = am bm ;zs = as ;
ELSE zm = bm am ; zs = bs;
(a) the design using a subtractor of magnitudes, one adder/subtractor, two-muxes and gates is
shown in Figure 10.10. The dierence in sign between the operands is detected by the XOR gate,
that controls the adder/subtractor. The magnitude subtractor is used to compare the operands,
performing the operation (a b). The comparison result is obtained from the borrow output.
When the borrow output is 1, a < b. Using the result of this comparison, the larger magnitude
operand is routed to the rst input of the adder/subtractor, and the smaller one to the second input
(subtraend). The output of the adder/subtractor corresponds to the magnitude part of the result.
The sign must be selected, and it must be the sign of the number with the largest absolute value.
This operation is accomplished by a multiplexer controlled by the borrow output of the magnitude
subtractor, as shown in the Figure.
x y
sign(x) 8 8
sign(y)
7 7 bout =1 if a<b
a b
0 1 1 0 bout bin
Mux Mux Mag. Subtractor
1-sub
Adder/subtractor sign(y) sign(x)
0-add
1 0
Mux
sign(x+y)
x+y
Figure 10.10: SM Adder - Exercise 10.14 (part a)

(b) the design with conversion of the SM number to two's complement, operation in two's
complement system, and conversion back to SM system is shown in Figure 10.11. The conversion
from SM to two's complement is done as follows, considering x = (xn ; xn 1 ; : : :; x1; x0) as the SM
representation of an operand (xn is the sign) and z its 2's complement representation:
(
z = (0 ; xn 1; : : :; x1; x0) if xn = 0
(1; x0 ; : : :; x0 ; x0 ) + 1 if x = 1
n 1 1 0 n
The conversion from two's complement to SM is done as follows:
(
x = (0 ; zn 1; : : :; z1; z0) if zn = 0
0 0 0
(1; (z ; : : :; z ; z ) + 1) if z = 1 n
n 1 1 0
The complementer and incrementer shown in the Figure are controlled by the sign bit of the numbers
being converted.
x y
sign(x) 8 sign(y) 8
0 7 0 7
Bit complementer Bit complementer

8 8
Incrementer Incrementer
Adder 0
sign 8
7
Bit complementer
Incrementer
7
8
x+y
Figure 10.11: SM Adder - Exercise 10.14 (part b)

A better implementation would just complement one of the operands when the signs are dier-
ent. This single complementation can be done by bit-invert and carry-in forced to 1 in the adder,
as shown in Figure 10.12.
x y
sign(x) 8 sign(y) 8
0 7 0 7
Bit complementer Bit complementer
8 8
dif
Adder dif
sign 8
Bit complementer
7
Incrementer
8
x+y
Figure 10.12: Another solution for SM Adder - Exercise 10.14 (part b)

Exercise 10.15: Consider the following table for the most signicant bits of the operands an 1
and bn 1 and the sum bit sn 1 , during the addition of n-bit two's complement operands a and b.:
an 1 bn 1 sn 1 cn cn 1 Ovf
0 0 0 0 0 No
0 0 1 1 0 Yes
0 1 0 1 1 No
0 1 1 0 0 No
1 0 0 1 1 No
1 0 1 0 0 No
1 1 0 0 1 Yes
1 1 1 1 1 No
From the table one can see that the over ow cases are related to the cases when cn cn 1 = 1.
For the one's complement system the test doesn't work properly in the case of adding ( 0) +
( 2n 1 + 1), which corresponds to the addition of the vectors (111 : : : 11) and (100 : : : 00). If the
addition is performed in two stages (no end-around-carry), the rst stage will generate cn = 1 and
cn 1 = 0, detecting an over ow condition that does not exist.
Exercise 10.16:
The range extension of x = (xn 1 ; : : :; x1; x0) is represented as z = (zm 1 ; : : :; z1; z0 ), with
n < m, such that:
(
zi = xxn 1 for for i = m 1; : : :; n
i = n 1; : : :; 1; 0
i
To show the correctness of this implementation let us dene:
z = zR mod Cz
x = xR mod Cx
There are two possible cases:
1. if x 0 the most signicant bit is zero, xn 1 = 0, and zR = xR , thus the algorithm is correct.
2. if x < 0 the following holds:
zR = Cz jxj
xR = Cx jxj
Consequently, zR = Cz Cx + xr .
From the denition of Cz and Cx we get:
Cz Cx = 2m 2n
and the value of the extended range zR should be:
zR = 2m 2n + xR
From this last equation we get the following vector:
(1; 1; : : :; 1; xn 1; : : :; x0)
with (m n) 1s to the left of vector x, which shows the correctness of the algorithm.
Exercise 10.17: A 4-bit ALU for ADD and NAND operations is shown in Figure 10.13. A
carry-ripple adder was implemented. By the use of a multiplexer, the output of the adder, or the
NAND gate is selected as circuit output.
xi yi
M
x3 y3 x2 y2 x1 y1 x0 y0
cin cin
cout
M M M M
f=ADD/NAND
1 0 ADD/NAND z3 z2 z1 z0
Mux
cout
zi
Figure 10.13: 4-bit ALU for ADD/NAND

Exercise 10.18: The analysis follows the inverse path of the description given on page 300 of
the text. First, from the network, we obtain the switching expressions. Then, using the encoding
given there, we obtain the high-level description. As an intermediate step we could produce the
following Table:
Position i
3 2 1 0 output relation
S - - - S x<y
G - - - G x>y
E S - - S x<y
E G - - G x>y
E E S - S x<y
E E G - G x>y
E E E S S x<y
E E E G G x>y
E E E E depends on cin x = y
The G, E, and S conditions are mutually exclusive.
Exercise 10.19: Figure 10.14 shows the iterative structure to be designed. Each cell has one
bit of each of the operands (ai and bi ), one carry-in (CIN ), and one carry-out (COUT ). These
carries have three values: Equal, Greater, and Smaller. The comparator output is obtained from
the carry-out of the last cell. The high-level description of the cell is:
8
>
< CIN if ai = bi
COUT = > GREATER if ((ai > bi) and CIN = EQUAL) or (CIN = GREATER)
: SMALLER if ((ai < bi ) and CIN = EQUAL) or (CIN = SMALLER)
with the initial condition CIN = EQUAL (applied to the leftmost cell).
a n-1 b n-1 a 1 b 1 a 0 b 0
0
carry-out
carry-out
carry-out
carry-in
carry-in
carry-in
Iterative Iterative Iterative COMPARATOR
Bit Bit Bit OUTPUT
0 Comparator Comparator Comparator
Figure 10.14: Iterative network to compare two numbers - Exercise 10.19

Considering the following encoding:
Condition Code
EQUAL 00
SMALLER 01
GREATER 10
the implementation of each module is done as a combinational circuit that has the following switch-
ing function table:
aibiCIN1CIN0 COUT1COUT0
0000 00
0001 01
0010 10
0011 {
0100 01
0101 01
0110 10
0111 {
1000 10
1001 01
1010 10
1011 {
1100 {
1101 {
1110 {
1111 {
Observe that the code 11 is a don't care condition.
Based on K-maps for each COUT1 and COUT0 we get the expressions:
COUT1 = CIN1 + aiCIN00
COUT0 = CIN0 + biCIN10
These expressions are easily implemented by gate networks.
Exercise 10.20: The network that sorts two non-negative numbers a and b is shown in Fig-
ure 10.15. The sorting order is such that z1 z0 .
a b
A B 0 1 0 1
s s
Comparator MUX MUX
A>B A=B A<B
SEL
z1 z0
Figure 10.15: Circuit to sort two non-negative numbers

The output of the circuit for dierent conditions of a and b is shown in the next table.
Input condition SEL OUTPUT (z1; z0)
ab 1 (b; a)
Exercise 10.21: A tree of 4-bit comparators implementing a 32-bit comparator is shown in
Figure 10.16, where A(i) = (a4i+3 ; a4i+2; a4i+1; a4i) and B (i) = (b4i+3; b4i+2; b4i+1; b4i). The equality
among inputs is implied when both G and S conditions are zeros.
(7) (7) (6) (6) (5) (5) (4) (4) (3) (3) (2) (2) (1) (1) (0) (0)
A B A B A B A B A B A B A B A B
A B A B A B A B A B A B A B A B
4-bit comparator 4-bit comparator 4-bit comparator 4-bit comparator 4-bit comparator 4-bit comparator 4-bit comparator 4-bit comparator
G E S G E S G E S G E S G E S G E S G E S G E S
G signals G signals
S signals S signals
A B A B
4-bit comparator 4-bit comparator
G E S G E S
0 0 0 0
cin inputs are zeroes
A B
for all modules
4-bit comparator
G E S
Figure 10.16: 32-bit comparator - Exercise 10.21

Exercise 10.22: The values of the outputs are shown in Figure 10.17.
0 0 0 0
0 1 1 0
1 2 2 1
0
DEMUX
0 3 3
MUX
g 1
1 4 4 0
1 5 5 0
0
0 6 6
0
1 7 7
2 1 0 2 1 0
0 1 0
d e f
0 (high) 1
carry_out ADDER carry-in
1
2
a 0
ENCODER
PRIORITY
2
3 b 1
1
4 c 0
0
5
6
1 1 1
7

Exercise 10.23: The values of the outputs of each module in the array multiplier is shown in
Figure 10.18.
Solutions Manual - Introduction to Digital Design - November 15, 2000
x_bit x_bit
x7 =1 x 6 =0 x5 =1 x 4 =1 x 3=0 x 2=0 x 1=1 x 0=1
sum_in y_bit y_bit =1
y0
1 1
c_out c_out 0 0 1
Half Half 1 1 0 0 1 1 1 1 0 0 1 1 1
Adder Adder c_in 0 0 y1 =0
OR
sum_out sum_out MH MF MH
0 0 MF 0 MF 0 MF MF 0
MF 0
0 0
Module MH
1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 1
x_bit 0 0 0 0 0 0 0 0 y 2 =0
sum_in y_bit (a)
MF MF 0 MF MF 0 MF 0
MF 0 MF MH
0 0 0 0
c_out 1 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0
Full 1
1 1 1 1 1 1 1 y 3 =1
Adder c_in
sum_out 0 MF 0 MF 1 MF 1 MF 0 MF 1 MF 1
MF 0 MH
Module MF
1 1 0 1 0 1 0 0 1 0 0 1 0 1
1 1
1 1 1 1 1 1 1 1 y 4 =1
1 MF 1 MF 1 MF 0 MF 0 MF 0
MF 0 MF 0 MH
1 0 0 0 1 0 1 0 0 0 1 1 1 1 1
1
1 1 1 1 1 1 1 1 y5 =1
1 MF 0 MF 0 MF 0 MF 0 MF 0 MF 1 MF 1 MH
0 0 1 1 1 1 1 0
p13 p 12 p 11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
(b)
223
Exercise 10.24 The implementation of the 84-bit multiplier is shown in Figure 10.19.
y7 y6 y5 y4 y3 y2 y1 y0
x0
y7 y6 y5 y4 y3 y2 y1 y0
x1
a3 a2 a1 a0 b3 b2 b1 b0 a3 a2 a1 a0 b3 b2 b1 b0
cout cin cout cin 0
4-bit Binary adder 4-bit Binary adder
s3 s2 s1 s0 s3 s2 s1 s0
y7 y6 y5 y4 y3 y2 y1 y0
x2
cout cout cin 0
4-bit Binary adder cin 4-bit Binary adder
s3 s2 s1 s0 s3 s2 s1 s0
y7 y6 y5 y4 y3 y2 y1 y0
x3
cout cin cout cin 0
4-bit Binary adder 4-bit Binary adder
s3 s2 s1 s0 s3 s2 s1 s0
z11 z10 z9 z8 z7 z6 z5 z4 z3 z2 z1 z0
Figure 10.19: 84-bit multiplier - Exercise 10.24

215
Chapter 11
Exercise 11.1 The register requires the load (LD), clear (CLR), and data inputs that are not
available in the SR ip op. We need to design a combinational network to generate the correct
SR inputs as shown in the next table:
x LD CLR S R
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 0 0
1 0 1 0 1
1 1 0 1 0
1 1 1 0 1
From the table we obtain:
S = x:LD:CLR0
CLR

0 1
1 1

x 0 1 1 0
R: LD
R = CLR + LD:x0
The circuit for the 4-bit register using SR ip ops is shown in Figure 11.1.
x3
M M q3
x x2
S Q q2
CK M
LD
R x1
CLR q1
M
x0
CK M q0
LD
CLR
Figure 11.1: 4-bit register using SR ip ops - Exercise 11.1

Exercise 11.2: The implementation of a serial-in/parallel-out right/left shift register using
parallel-in/parallel-out right shift register is shown in Figure 11.2.
Q3 Q2 Q1 Q0
Ir Q3 Q2 Q1 Q0
Ir
Shift Right Shift Parallel In/out RSR
Shift Left LOAD
CK
I3 I2 I1 I0
IL
Figure 11.2: serial-in/parallel-out right/left shift register

The SHIFT input is used to enable the shift-right function, while the serial data is entered
through the Ir input. The LOAD input is used to shift left, while the serial data and other next
state bits are entered through the parallel inputs of the shift register (Ii ).
Exercise 11.3
Bit-serial arithmetic for addition/subtraction of 16-bit operands in two's complement form. The
network for this exercise is shown in Figure 11.3. The two serial inputs a and b are added/subtracted
generating the result s, from least-signicant to most-signicant bit. When subtraction is requested,
a carry in of 1 in the rst clock cycle is applied to the Full-Adder, together with the complementation
of all bits of b. When the 16th bit of the number is being computed, the signal last bit is 1. Observe
that the serial hardware may compute a dierent number of bits only changing the counter design.
b
a 16
16 1 parallel input Load
shift reg. CK
Load parallel input 1
CK shift reg.
Shift
Shift
CK
Modulo-16 TC cin
CLR counter
cout FA
4
1
D Q
CK
shift reg.
subtract parallel output CK
zero 16
Shift
s
last_bit
Figure 11.3: Serial addition - Exercise 11.3

Exercise 11.4 The pattern recognizer for the sequences 0101 and 0110 is presented in Fig-
ure 11.4.
x input
3-bit Shift Register
CK
Figure 11.4: Pattern recognizer - Exercise 11.4

K0 K1 K2 K3 x y Si ci+1 shift reg. FF 2nd adder input Internal carry z

(K 1 + K 2)FF (serial adder)
1 0 0 0 1 0 1 0 0000 0 0 0 0
0 1 0 0 0 1 1 0 1000 0 0 0 0
0 0 1 0 0 1 1 0 1100 0 0 0 0
0 0 0 1 1 0 1 0 1110 0 0 0 0
1 0 0 0 0 1 1 0 1111 1 0 0 1
0 1 0 0 1 0 1 0 1111 1 1 1 0
0 0 1 0 1 0 1 0 1111 1 1 1 1
0 0 0 1 0 0 0 0 1111 1 0 1 0
1 0 0 0 0 0 0 0 0111 0 0 1 0
0 1 0 0 0 0 0 0 0011 0 0 1 0
0 0 1 0 0 0 0 0 0001 0 0 1 0
0 0 0 1 0 0 0 0 0000 0 0 0 1
1 0 0 0 0 0 0 0 0000 0 0 0 0
Table 11.1: Circuit behavior - Exercise 11.5

Exercise 11.5: (a) Consider the information provided in Table 11.1, which presents the network
operation for the inputs x = 01101001 and y = 00010110:
Observe that a new digit begins when K0 = 1. There is a delay of 4 cycles between the input
digits and the output digit. The result of the operation is 85 in decimal. It is correct since x = 69
and y = 16.
(b) The output of the rst serial adder is the radix-2 sum of the x and y bit strings. Consider
a group of four bits corresponding to one decimal digit of x and y . These bits are applied at the
input of the adder from least signicant to most signicant at clock cycles when K0, K1 , K2, and
K3 are active. Consequently, at the time K3 is active, the sum is (c4; s3; s2; s1; s0), as indicated
below:
x3 x2 x1 x0
+ y3 y2 y1 y0
c4 s3 s2 s1 s0
Bits (s2 ; s1; s0) are inside the shifter, s3 and c4 are outputs of the rst adder. Since the result
should be in BCD (radix-10) it is necessary to correct it whenever it is larger than 9. That is:
(
z = s mod 10 = ss 10 ifif ss 9 (11:1)
10
P
where s = 16c4 + 3i=0 si 2i . Consequently, it is necessary to detect whether the addition of 2
decimal digits is greater than 9 and then subtract 10 form the result.
Moreover, the carry to be used for the next digit is
(
10
Cout = 01 ifif ss (11:2)
9
which can be written as (
if (s 16) or (10 s < 16)
Cout = 01 otherwise (11:3)
As BCD digits come in groups of 4 bits, the detection of greater or equal to 10 condition as
presented in Equation 11.3 corresponds to the following expression:
G = c4 + s3 (s2 + s1 )
This detection is implemented in the combinational network connected to the outputs of the rst
adder and the shift register. The value of G is stored in the FF only when K3 = 1. In any other
cycle the value in the FF doesn't change (function performed by the FF and MUX circuit).
For the subtraction of 10 (when the addition of the two BCD digits are larger than 9), since
binary adders add modulo-16 instead, the following equation must be considered:
s 10 = (s + 6) mod 16
This addition of 6 is performed using the second binary adder. Since the binary representation
of 6 is 0110, it's necessary to add 1 in two consecutive cycles. The least signicant bit of the rst
addition reaches the second adder when K0 is active, if the addition of 6 is necessary, the input of
the second adder must have a 1 during the cycles when K1 or K2 are active.
Note that when the least signicant bits of another pair of BCD digits come into the rst adder,
the least signicant bit of the addition of the previous pair is at the input of the second serial adder.
The analysis nishes when we consider the carry bits of the BCD addition. When the sum
value of the digits of x and y is a value greater than 15, the carry bit is stored in the rst adder,
to be used with the next BCD digits. When the value is in the range 10 to 15, the correction step
(addition of 6) executed in the second adder generates a carry which is stored in the second adder
for the next sum value which is the contents of the shifter.
The timing diagram is shown in Figure 11.5.
CK
K0
K1
K2
K3
si
c i+1
shift reg 1000 1100 0110 1011 1101 1110 0111 1011 0101 0010 0001 0000 0000
FF in
FF out
Figure 11.5: Timing diagram for Exercise 11.5

Exercise 11.6: The state diagram for this sequential network is presented in Figure 11.6, for
the case of receiving least signicant bit and most signicant bit rst. In each transition we use a
pair of bits representing the inputs x and y , respectively. The system output corresponds to the
system's present state.
xi>yi
equal
xi>yi xi>yi
EQUAL GREATER EQUAL GREATER
equal
xi<yi xi<yi equal
xi<yi
xi>yi
SMALLER SMALLER
xi<yi
equal
LEAST SIGNIFICANT BIT FIRST MOST SIGNIFICANT BIT FIRST
Figure 11.6: State Diagrams for Serial Binary Magnitude Comparators - Exercise 11.6
(a) The system implementation for the comparison starting with the least signicant bit is
shown in Figure 11.7. A one-hot state encoding is used. The expressions for the next state in this
case are:
E (t + 1) = E (t):(x = y )
G(t + 1) = G(t):(x = y ) + (x > y )
S (t + 1) = S (t):(x = y ) + (x < y )
The initialize input clears the ip- ops and the counter such that initially E = 1, G = S = 0,
and the counter state is 0. The counter monitors the number of clock cycles while the signal compare
is active. After 32 clock cycles the Done signal becomes active for one clock cycle. Load signal
is used to store the parallel input values into the shift register. The system must be reset to start
another operation.
(b) The implementation of the serial comparator starting with the most-signicant bit is shown
in Figure 11.8. The expressions for the next state in this case are:
E (t + 1) = E (t):(x = y )
G(t + 1) = G(t) + E (t):(x > y )
S (t + 1) = S (t) + E (t):(x < y )
The counter has the same function as the one used in part (a).
G
D Q
x
x>y
initialize CLR I4 I3 I2 I1 I0
Load Compare CNT Done
x=y E Mod-32 Counter TC
Shift Register D Q CK
CK LD q4 q3 q2 q1 q0
Load x<y 0
Shift Register S
CK D Q
y initialize
CK
Figure 11.7: Serial Binary Magnitude Comparator - LS bit rst - Exercise 11.6
G
D Q
x
x>y
initialize CLR I4 I3 I2 I1 I0
Load
E Compare CNTMod-32 Counter TC Done
Shift Register x=y D Q
CK CK LD q4 q3 q2 q1 q0
Load x<y 0
Shift Register S
CK D Q
y initialize
CK
Figure 11.8: Serial Binary Magnitude Comparator - MS bit rst - Exercise 11.6
Exercise 11.7:
(a) The implementation of the serial change of sign module (complementer) for a 32-bit number
in two's complement system is shown in Figure 11.9. After the clear signal the counter is in state
0 and the NOR gate connected to its output forces a 1 input into the half-adder (HA). The other
input of the HA is connected to the complemented serial output of the shift register. The bits are
shifted out least-signicant bit rst and stored back into the same register. The carry bit of each
bit addition is delayed and inserted back into the HA, as done in serial addition.
clear CLR I4 I3 I2 I1 I0
complement CNT Mod-32 Counter TC Done
CK q4 q3 q2 q1 q0
LD
X
32
In out
Shift Register
CK
HA
CK FF
Figure 11.9: Serial change of sign (two's complement system) - Exercise 11.7
(b) When the adder receives two bits each clock cycle, it is necessary to use two shift registers.
One stores the bits of X in even positions, Xeven = (x30; x28; : : :; x2; x0). The other stores the bits
in odd positions, Xodd = (x31; x29; : : :; x3; x1). The output is stored back into the registers with
the same organization. Two HAs with extra logic are used to increment X 0. Since 2 bits per clock
cycle are processed, a modulo-16 counter is enough. This design is shown in Figure 11.10.
clear CLR I3 I2 I1 I0
complement CNT Mod-16 Counter TC Done
X even CK LD q3 q2 q1 q0
16
In out
Shift Register 0
X CK
32 X odd
16
In out
Shift Register
CK
HA HA
CK FF
Figure 11.10: Serial complementer (two's complement system) - Exercise 11.7

Exercise 11.8: The implementation of the variable-length shift register is presented in Fig-
ure 11.11. Since the length of the shift register varies from 1 to 8, we use a 3-bit control variable
represented as L = (L2; L1; L0). The value L = 0 corresponds to the shift of 8 bit positions. L is
used as selection control signal for the multiplexer. The multiplexer selects the proper output of
the shifter that corresponds to the system output for a given value of L. So, for example, if L = 3
then z is obtained from output 2 of the shift register, imposing a delay of 3 clock cycles from the
data input to the output z .
Data Serial IN SHIFT

Input REGISTER
CK 0 1 2 3 4 5 6 7
L2 2 0 1 2 3 4 5 6 7
L1 1 MUX E 1
L0 0
Figure 11.11: Variable-length serial-in/serial-out shift register - Exercise 11.8.

Exercise 11.9: The design is presented in Figure 11.12. A modulo-m divider is implemented
by a counter that loads the value 16 m every time TC is 1. In two's complement system, the
computation of 16 m results in m. The value of m is obtained from m by bit complementation
(Compl module) and addition of 1. Another option is to use 15 m as a loading value and load
the counter with this value when it reaches the state 14. Such operation corresponds to the one's
complement of m and it is obtained by simple bit complementation (no incrementer).
m m
Compl
I3 I2 I1 I0
Incrementer 1 CNT Modulo-16 LOAD
CK counter TC z
Q3 Q2 Q1 Q0
I3 I2 I1 I0
LOAD
1 CNT Modulo-16
CK counter TC z
Q3 Q2 Q1 Q0
state 14
(a) (b)
Figure 11.12: Programmable modulo-m divider - Exercise 11.9

Exercise 11.10: The solution for this exercise is shown in Figure 11.13. The network computes
the next state adding one to the present state value when the value is less than 9, or adding 7 to
the present state when it reaches 9 (forcing the counter to go back to state 0). Using high-level
specication we have:
(
s(t) = (ss((t)t)++17) mod 16 = 0 ifif ss((tt)) =
<9
9
CK Register
0 1
Binary ADDER 0
Figure 11.13: BCD counter - Exercise 11.10

Exercise 11.11: Using a modulo-16 binary counter with parallel inputs
(a) 4-to-11 counter.
CNT = x
LOAD = Q3Q1Q0 x = TC
I = 0100
0 1 0 0
x CNT Mod-16 Counter TC
CK LD q3 q2 q1 q0
TC
Figure 11.14: 4-to-11 counter - Exercise 11.11(a)

(b) modulo-13 counter.
CNT = x
LOAD = Q3 Q2x = TC
I = 0000
The network for this counter is shown in Figure 11.15.
0 0 0 0
CK LD q3 q2 q1 q0
TC
Figure 11.15: Modulo-13 counter - Exercise 11.11(b)

(c) The state diagram is shown in Figure 11.16, with notes associated to the transitions for
which the counter must be loaded. From the diagram we obtain the condition for loading on a
Kmap as follows:
Q0
0
01 0- 0-
0
Q2
- - 0 0
Q3
0

0
1 0
Q1
that results in the minimal expression:
LOAD = (Q3Q02Q1 Q0 + Q03Q2 Q0 )x
0 1 2 3 4 5
counter loads
the value
15 14 11 10 9 8
counter loads
the value
Figure 11.16: State diagram for Exercise 11.11(c)

We use the fact that LOAD overides CNT input to dene:
CNT = x
Considering the inputs Ii as d.c.s for the cases when LOAD = 0 and the appropriate next state
value for when LOAD = 1, and using Kmaps we obtain the expressions:
I3 = 1
I2 = I1 = Q1
I0 = 0
The network for this system is shown in Figure 11.17.
1 Q1 0
CK LD q3 q2 q1 q0
Q1 Q0
Q3
Q2’
Q1 Q2 Q2’
Q0 Q3 Q3’
Q3’ LOAD
Q2
Q0
Figure 11.17: Network for Exercise 11.11(c)

Exercise 11.12: Actually what was intended in this exercise was to design the counters of Ex.
11.11. However, since there is a typo, we give the solution as stated. The design of a BCD counter
for both cases are given next:
(a) using T type ip ops and NAND gates. The state transition table is:
PS Input Input
x=0 x=1 x=0 x=1
0000 0000 0001 0000 0001
0001 0001 0010 0000 0011
0010 0010 0011 0000 0001
0011 0011 0100 0000 0111
0100 0100 0101 0000 0001
0101 0101 0110 0000 0011
0110 0110 0111 0000 0001
0111 0111 1000 0000 1111
1000 1000 1001 0000 0001
1001 1001 0000 0000 1001
NS T3T2T1 T0
From the table we obtain T0 = x and draw the following Kmaps for the other variables when
x = 1:
Q0 Q0 Q
0
1 0
0

0 0 0 0 0 0 1 1 0
0

0 1 0
Q 0 0 1 0
Q
0
1 10
Q2
- -
- - 2 - - - - 2 - - - -
Q3 Q3 Q3
0
1 - - 0 0
- - 0 0 - -
T3 Q1 T2 Q1 T1 Q1
and the minimal expressions are:
T3 = Q3 Q0 x + Q2 Q1 Q0x
T2 = Q1 Q0 x
T1 = Q03 Q0 x
The network of this design is shown in Figure 11.18.
(b) same solution given to Exercise 11.10.
Q3
x
Q3 Q0 Q2
Q0
T Q Q1 T Q
Q2
Q1 3 x 2
Q3’
Q0 CK Q’ CK Q’
Q3’ Q1 Q0
x
Q0 T Q T Q
x 1 0
CK Q’ CK Q’
Figure 11.18: BCD counter using T ip ops - Exercise 11.12(a)

Exercise 11.13:
Assuming that the module-16 counter has only up-counting feature, the down-counting must
be implemented by loading the next state and a zero must be loaded when up-counting and the
counter state (count) is 10.
The LOAD signal is expressed as:
(
(countup and count = 10) or countdown
LOAD = 10 ifotherwise
The value to be loaded is:
8
>
> i 1 if countdown and count 6= 0
< (10)10 if countdown and count = 0
i=> 0 if countup and count = (10)10
>
: don't care otherwise
Representing the parallel input i by a vector I = (I3 ; I2; I1; I0) and the count state by a vector
Q = (Q3; Q2; Q1; Q0), the following expression is obtained:
LOAD = countup:Q3 :Q1 + countdown
Lets rst consider the values to be loaded when counting down.
Q = (Q3; Q2; Q1; Q0) I = (I3 ; I2; I1; I0)
0000 1010
0001 0000
0010 0001
0011 0010
0100 0011
0101 0100
0110 0101
0111 0110
1000 0111
1001 1000
1010 1001
1011 ----
1100 ----
1101 ----
1110 ----
1111 ----
1 0Q00 0 Q0
0 0 0 0
0 0 0 0 0 1 1 1
Q2 Q2
- - - - - - - -
Q3 Q3
0 1 - 1 1 0 - 0
I3: Q1 I2: Q1
I3 = (Q03Q02 Q01Q00 + Q0Q3 + Q1Q3 ):countdown

I2 = (Q2Q0 + Q2 Q1 + Q3 Q01Q00 ):countdown
Q0 Q0
1 0 1 0 1
0
0 0
1 0 1 0
- - - - 2
Q
1
0 0 1
Q2
Q3 Q3
-
- - -
1 0 - 0 1
0 -
1
I1: Q1 I0 : Q1
I1 = (Q01Q00 + Q1Q0):countdown
I0 = (Q2Q00 + Q3 Q00 + Q1Q00):countdown
Since when countup = 1 we must have countdown = 0, the value loaded when counting up (at
state count = 10) is I = 0, which is correct.
The network that implements the counter is shown in Figure 11.19. Black boxes were used to
represent the gate networks that implement I3 ; I2; I1; and I0.
countdown
Q
_
4 4 4 4
CC4 CC3 CC2 CC1
CLEAR I3 I2 I1 I0
clr
CNT Modulo-16 counter
CK L Q3 Q2 Q1 Q0
countdown Q
_
4
Q3
LOAD
Q1
countup where CCi means
combinational circuit
for function I
i
Figure 11.19: Modulo-11 up/down counter - Exercise 11.13

Exercise 11.14: The state and output are represented by the vector (Q4; Q3; Q2; Q1; Q0),
where Q4 is the output of the ip- op, and (Q3Q2 Q1Q0 ) is the output of the modulo-16 counter.
To achieve the desired counting sequence it is necessary to have:
(
(Q4 ; Q3; Q2; Q1; Q0) = (25)10
LD = 10 ifotherwise
Moreover, the additional ip- op is set to 1 when the modulo-16 counter goes from 15 to 0,
which corresponds to the clock cycle when TC = 1, and reset when the state 5 is loaded. The
network is shown in Figure 11.20.
0 1 0 1
clear CLR I3 I2 I1 I0 Q4
x J Q
CNT Mod-16 Counter TC
CK LD q3 q2 q1 q0 CK
Q4
K
Q3
Q0
Q3 Q2 Q1 Q0

Exercise 11.15:
There is a mistake on Figure 11.32 of the textbook. The two counters should be congured as
z z
S3 S2 S1 S0 CLR S3 S2 S1 S0 CLR
TC Module-16 CNT x TC Module-16 CNT x

Counter Counter
CLK CLK
I3 I2 I1 I0 LD I3 I2 I1 I0 LD
1 1 0 1 0 0
Figure 11.21: Frequency dividers for Exercise 11.15

The rst counter has a load condition given as
LD = S10
for which the value loaded is I = (S3; 1; 1; 0), and z = S3. Looking at all possible present states we
are able to obtain the following state-transition and output table:
PS NS output (z )
0000 0110 0
0110 0111 0
0111 1000 0
1000 1110 1
1110 1111 1
1111 0000 1
This counter implements a modulo-6 frequency divider, with 50%-duty-cycle frequency.
The second counter has LD = S20 , z = S3 , and I = (S3; 1; 0; 0). The state-transition and output
table for this case is:
PS NS z
0000 0100 0
0100 0101 0
0101 0110 0
0110 0111 0
0111 1000 0
1000 1100 1
1100 1101 1
1101 1110 1
1110 1111 1
1111 0000 1
This counter implements a modulo-10 frequency divider, with 50%-duty-cycle frequency.
The timing diagram for both cases is shown in Figure 11.22.
CLK
z
first
counter
z
second
counter
Figure 11.22: Timing digram for counters in Exercise 11.15

Exercise 11.16: The state diagram is presented in Figure 11.23. The condition for LOAD is:
LOAD = S0 x + S1x + S2x0 + S3 x0 + S4 x + S5 x + S6
where Si is a product term that is 1 when the state is i. The values to be loaded are presented in
the next table:
State State code (Q2; Q1; Q0) Inputs (I2; I1; I0)
S0 000 000
S1 001 000
S2 010 001
S3 011 001
S4 100 000
S5 101 000
S6 110 101 when x' and 011 when x
From the table we can use K-maps to get the following expressions. Care must be taken with
the input values for Ij when in S6 . In this particular case, LOAD is active independent of x, and
the input is a function of x:
I2 = Q2Q1 x0
I1 = Q2Q1 x
I0 = Q1
When the value of the LOAD input is not active, the counter goes to the next state ((s(t) +
1) mod 8). The circuit is presented in Figure 11.23.
1
1
1
0 0 1 1 0 0
S0/0 S1/0 S2/0 S3/0 S4/0 S5/1 S6/0
1 0 0
0 1
Q2 x
Q2 x’ Q1
Q1
clear 0 Q1
x 0
1
x
2
x’ 3 CLR I3 I2 I1 I0
x’ 4 CNT
MUX Modulo-16
x 5 CK CK Counter
x 6 LD
7 Q3 Q2 Q1 Q0
1
2 1 0
Q2 Q1 Q0
Q2 Q1 Q0

Exercise 11.17:
From the network in Figure 11.33 of the text we get the following expressions for timing behavior:
z(t + 1) = [z(t) + COUNT (t)] mod 256
COUNT (t + 1) = [COUNT (t) + 1] mod 256
with the initial condition COUNT (0) = c0 we get the solution for the second recurrence as:
COUNT (t) = (t + c0 ) mod 256
The rst recurrence equation is transformed to:
z(t + 1) = [z(t) + ((t + c0) mod 256)] mod 256 = [z(t) + t + c0] mod 256
To nd a solution for the rst recurrence, let us evaluate a few terms, considering the initial
condition z (0) = z0 :
z(1) = (z0 + 0 + c0 ) mod 256
z(2) = ((z0 + 0 + c0) + 1 + c0) mod 256 = (z0 + 1 + 2c0 ) mod 256
Then the general solution is:
t 1
X
z(t) = (z0 + i + tc0 ) mod 256 = (z0 + (t 1)t=2 + tc0 ) mod 256
i=0
For z0 = 0 and c0 = 0 we get:

z(10) = ( 92 10) mod 256 = 45
Exercise 11.18:
To simplify the notation, let us use the following variables:
A = (DIST 10)AND(COUNT = 3)
B = (DIST > 10)
C = (DIST 10)AND(COUNT 6= 3)
Three networks to implement the controller are shown in Figure 11.24. Each network uses a
dierent approach to control the CNT and LOAD inputs. The rst and second implementations
makes LOAD = CNT ', which forces the counter to be counting or loading in each clock cycle. In
the rst implementation, the CNT input is:
CNT = S0 :GO + S1:C + S2
The second implementation is based on the generation of the LOAD input as:
LOAD = S0 :GO0 + S1(A + B) + S3 + S4 + S5
The third implementation uses the fact that LOAD overides the CNT input, and the counter
is always counting, by default. The LOAD input has the same circuit as the one used for imple-
mentation 2.
GO’ 0 E 0 I2 0 I0
A+B 1
A I0 0 2 clear CLR I3 I2 I1 I0
Q0 Q1 1 3 CNT
Q2 Mod-16 Counter TC
1 4 MUX CK LD q3 q2 q1 q0
I2
Q1 1 5
1 6
Q2 Q1 Q0
1 7
2 1 0
Q2 Q1 Q0 (b) implementation 2
1 1
GO 0 E 0 I2 0 I0 GO’ 0 E 0 I2 0 I0
C 1 A+B 1
1 2 clear CLR I3 I2 I1 I0 0 2 clear CLR I3 I2 I1 I0
0 3 CNT Mod-16 Counter TC 1 3 1 CNT Mod-16 Counter TC
0 4 MUX CK LD q3 q2 q1 q0 1 4 MUX CK LD q3 q2 q1 q0
0 5 1 5
0 6 1 6
Q2 Q1 Q0 Q2 Q1 Q0
0 7 1 7
2 1 0 2 1 0
Q2 Q1 Q0 (a) implementation 1 Q2 Q1 Q0 (c) implementation 3
Figure 11.24: Networks to implement the controller in Exercise 11.18

The combinational network for each parallel input (Ij ) is the same for all 3 networks. These
gate networks are obtained from the following table and Kmaps.
PS Parallel input
Q2Q1Q0 I2 I1I0
000 000
001 10A
010 |
011 001
100 001
101 101
The table has a special parallel input value for state S1 , when condition A determines the value
of the least signicant bit (next state is 5 if condition A is true, 4 otherwise).
Q0 Q0 Q0
0 1 0 - 0 0 0 - 0 A 1 -
Q2 0 1 - - Q2 0 0 - - Q2 1 1 - -
I2: Q1 I1 : Q1 I0 : Q1
I2 = Q01 Q0
I1 = 0
I0 = Q1 + Q2 + Q0 A
The gate networks for Ij are shown in Figure 11.24 for implementation 1 only, but it is the
same for all other implementations.
Exercise 11.19:
We use up-counting for (s(t)+1) mod 10 function. Since the counter is module-16, it is necessary
to detect when the counter state is 9 and load a 0. Similarly, the count-down feature is used for
(s(t) 1) mod 8. For this case the value 7 has to be loaded whenever the counter state is 0, and
the value 0 is loaded whenever the count is 9 (since (9 1) mod 8 = 0). Consequently, if LOAD
overrides the count signals, we get:
(
(x = 1)
Count up = 10 ifotherwise (11:4)
(
Count down = 1 if (x = 2) (11:5)
0 otherwise
(
LOAD = 1 if ((x = 1 or x = 2) and s(t) = 9) or (x = 2 and s(t) = 0) (11:6)
0 otherwise
The value to be loaded is 8
>
<0 if s(t) = 9
i=> 7 if s(t) = 0 (11:7)
: don't care otherwise
For the binary implementation it is necessary to encode x into binary variables. We choose a binary
enconding such that x = 2x1 + x0 . This results in
Count up = x0
Count down = x1
LOAD = Q3Q0 (x1 + x0) + x1Q03 Q02 Q01Q00
I3 = 0
I2 = I1 = I0 = Q03
The corresponding network is presented in Figure 11.25.
Q3
clear 0
Q3
Q0
x1
CLR I3 I2 I1 I0
Q3 x1 DOWN
Q0 Modulo-16
CK CK
x0 Counter
Q3’ x0 UP LD Q3 Q2 Q1 Q0
Q2’
Q1’
Q0’
x1
Q3 Q2 Q1 Q0

Exercise 11.20:
The state diagram is shown in Figure 11.26. The state names represent even number of 1s (with
an \e" subscript) and odd number of 1s (with an \o" subscript). From the diagram we obtain the
following expressions for the counter control inputs:
CNT = Ae x0 + Be x + Co x + Dex + Ao x0 + Box + Ce x + Do x
LOAD = CNT 0
0/
0/0
0/ 0/
Ae Be Ce 1/ 1/ De
1/
1/ 1/
1/
0/ 0/ 1/
Ao Bo Co 1/ Do
0/1
0/ when the output is not shown
2 or 3 can be used as output
Figure 11.26: State diagram - Exercise 11.20

Consider the following state codes:
State code
Ae 0
Be 1
Ce 6
De 3
Ao 4
Bo 5
Co 2
Do 7
The expressions for the parallel inputs, outputs and CNT are obtained from Kmaps:
I2 = Q2 Q0 + Q02Q00 = (Q2 Q0)0
I1 = 0
I0 = Q1 + Q0
z0 = Q2
z1 = x + Q01 + Q00
CNT = xQ0 + xQ1 + x0 Q01 Q00
The network for this system is shown in Figure 11.27.
Q0
Q1
Q0
Q2
x 0 0
Q0
x CLR I3 I2 I1 I0
Q1 CNT Mod-16 Counter TC
CK LD q3 q2 q1 q0
x’
Q1’
Q0’ Q2 Q1 Q0

Exercise 11.21:
From the network we get:

J = Q00
K = Q1Q0
As only the leftmost FF is of JK type, we can write the following table:
Present State Leftmost FF Next State
Q3 Q2Q1Q0 JK Q3Q2Q1Q0
0000 10 1000
0001 00 0000
0010 10 1001
0011 01 0001
0100 10 1010
0101 00 0010
0110 10 1011
0111 01 0011
1000 10 1100
1001 00 1100
1010 10 1101
1011 01 0101
1100 10 1110
1101 00 1110
1110 10 1111
1111 01 0111
The state diagram that corresponds to this transition table is presented in Figure 11.28.
6 11 5 4
2 10
9 13
0 8 12 14 15
1 3 7
Figure 11.28: State diagram for the circuit in Exercise 11.21

Some of the states are transitory states. Others are part of a cycle that represents a counter
behavior. This type of counter is called twisted tail counter. Figure 11.15 of the textbook describes
this counter.
As we can see from the state diagram, it's a self starting counter, since there's always a path
from any state to the main counter cycle. The additional NAND gate (when compared to the
design shown in the textbook) is used for self-starting feature.
Exercise 11.22:
Shift input overides LOAD. The loaded value is always (0111)2. The SHIFT input is expressed
as:
SHIFT = (Q3Q1Q0)0 = Q03 + Q01 + Q00
Based on the network we obtain the following table for state transitions:
PS SHIFT NS
Q3Q2 Q1Q0
0000 1 1000
0001 1 0000
0010 1 1001
0011 1 0001
0100 1 1010
0101 1 0010
0110 1 1011
0111 1 0011
1000 1 1100
1001 1 0100
1010 1 1101
1011 0 0111
1100 1 1110
1101 1 0110
1110 1 1111
1111 0 0111
The state diagram for the system is presented in Figure 11.29. We can see from the Figure that
the main loop consists of the sequence: 0,8,12,14,15,7,3,1,0.... Any other state, dierent than those
in the main loop will be in a path that ends in state 7 (that is part of the main loop). Thus, the
counter is self starting. It is a twisted-tail counter.
5 2 9 4 10
11 6 13
0 8 12 14
1 3 7 15

Exercise 11.23: Using two modulo-16 binary counters we implement cascade and parallel
counters for the cases:
(a) a cascade implementation of a modulo-23 counter is shown in Figure 11.30. The state 22,
Q = 10110 is detected and the counter is loaded with the value 0.
0 0 0 0 0 0 0 0
clear CLR CLR

I3 I2 I1 I0 I3 I2 I1 I0
CNT Mod-16 Counter TC x CNT Mod-16 Counter TC
CK LD q3 q2 q1 q0 CK LD q3 q2 q1 q0
Q4
TC
Q2
Q1
Q4 Q3 Q2 Q1 Q0
Figure 11.30: Cascade implementation of modulo-23 counter - Exercise 11.23(a)

The parallel implementation of the same counter uses a modulo-8 and a modulo-3 counter that
together form a modulo-24 parallel counter. The counting sequence, considering T = (T1T0 ) as the
output of the modulo-3 counter and E = (E2E1E0 ) as the output of the modulo-8 counter is given
by the following table:
state T1 T0 E2E1E0
0 00 000
1 01 001
2 10 010
3 00 011
4 01 100
5 10 101
6 00 110
7 01 111
8 10 000
9 00 001
10 01 010
11 10 011
12 00 100
13 01 101
14 10 110
15 00 111
16 01 000
17 10 001
18 00 010
19 01 011
20 10 100
21 00 101
22 01 110
23 10 111
The state code is given by the two counters' output, (T; E ). For simplicity we represent the
state code using decimal numbers. To modify this modulo-24 counter to a modulo-23 counter, state
22 is detected, which is represented by the code (1; 6), and the state 0, coded as (0; 0) is loaded, as
0 0 0 0 modulo-8
counter
CK LD q3 q2 q1 q0
T1
T0
E2 TC
E1 E2 E1 E0
E0
0 0 0 0
modulo-3
counter
CLR I3 I2 I1 I0
CK LD q3 q2 q1 q0
T1 T0
Figure 11.31: Parallel implementation of modulo-23 counter - Exercise 11.23(a)
(b) an 11-to-29 counter. A total of 19 states are needed. The cascade implementation of this
counter is shown in Figure 11.32. Observe that state 29 (11101) is detected and generates a load
signal. The value loaded corresponds to state 11 (1011).
0 0 0 0 1 0 1 1
clear CLR I3 I2 I1 I0 CLR I3 I2 I1 I0

Q4
Q3 TC
Q2
Q0
Q4 Q3 Q2 Q1 Q0
detects
state 29
Figure 11.32: Cascade implementation of a 11-to-29 counter - Exercise 11.23(b)
The parallel implementation of this counter uses a modulo-30 parallel counter that is obtained
combining a modulo-5 and a modulo-6 counter. The state sequence, assuming that the state is
composed by (E; T ), where E = (E2E1E0 ) is the state of the modulo-5 counter and T = (T2T1T0)
is the state code of the modulo-6 counter, is presented (in decimal) in the following table:
state E T state E T
0 0 0 15 0 3
1 1 1 16 1 4
2 2 2 17 2 5
3 3 3 18 3 0
4 4 4 19 4 1
5 0 5 20 0 2
6 1 0 21 1 3
7 2 1 22 2 4
8 3 2 23 3 5
9 4 3 24 4 0
10 0 4 25 0 1
11 1 5 26 1 2
12 2 0 27 2 3
13 3 1 28 3 4
14 4 2 29 4 5
Thus, to obtain the 11-to-29 counter we need to detect state 29 (4; 5) and load state 11 (1; 5).
modulo-5
0 0 0 counter
CK LD q3 q2 q1 q0
E2 E1 E0
0 0 modulo-6
counter
CLR I3 I2 I1 I0
CK LD q3 q2 q1 q0
E2
T2 T1 T0
TC
Figure 11.33: Parallel implementation of a 11-to-29 counter - Exercise 11.23(b)

(c) a frequency divider by 27
For the cascade implementation, the state (11010) is detected and the value 0 is loaded as the
next state. The same load signal (TC) is the output of the frequency divider. The network is shown
in Figure 11.34.
The parallel implementation makes use of a modulo-4 and a modulo-7 counter to obtain a
modulo-28 counter. The state code is represented by two components (E; T ), where E = (E1E0)
is the state code for the modulo-4 counter and T = (T2T1T0 ) is the state code of the modulo-7
counter. When state 26 (2; 5) is reached, both counters are loaded with the initial state 0. The
0 0 0 0 0 0 0 0
clear
CLR I3 I2 I1 I0 CLR I3 I2 I1 I0
CK q3 q2 q1 q0 CK q3 q2 q1 q0
LD LD
Q4
Q3 TC z
Q1
Q4 Q3 Q2 Q1 Q0
detects
state 26
Figure 11.34: Cascade implementation of a frequency divider by 27 - Exercise 11.23(c)
network shown in Figure 11.35 shows the parallel implementation of this frequency divider. The
circuit output corresponds to the load signal (TC).
modulo-7
0 0 0 0 counter
CK LD q3 q2 q1 q0
T2 T1 T0
0 0 0 0
CLR I3 I2 I1 I0
CK LD q3 q2 q1 q0
E1
E0’ TC E1 E0
T2
T1’
T0 z
Figure 11.35: Parallel implementation of a frequency divider by 27 - Exercise 11.23(c)

Exercise 11.24: We notice that the counting sequence can be described by the following nested
loops:
for i=0 to 14 do
for j=i to 15 do
z=j
endfor
endfor
Consequently, to implement this counter we can use one mod-16 counter for each loop. The
output of the counter in the inner loop (counter 2) is z = j , and the output of the counter in
the outer loop (counter 1) is i. The implementation is shown in Figure 11.36. The counter on
top (counter 1) is a modulo-15 counter (counts from 0 to 14) and provides a loading value for
the bottom counter (counter 2). Every time counter 2 loads the value on its parallel inputs (Ii ),
counter 1 goes to its next state. Counter 1 counts the number of TCs from counter 2 (when counter
2 reaches 15). However, counter 1 must be initialized with value 1 when the clear signal is issued.
That happens because counter 2 will start counting from zero after the clear signal (no load is
needed), and after 15 cycles its TC output becomes a 1, and the value to be loaded must be 1. For
this reason the clear signal is connected to input I0 of counter 1 and it is combined with the \state
14" signal to generate the correct load input.
0 0 0 0
CLR I3 I2 I1 I0
CNT
Modulo-16 TC
CK CK Counter
LD Q3 Q2 Q1 Q0
state
clear 14
CLR I3 I2 I1 I0
1 CNT
Modulo-16 TC
CK CK Counter
LD Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0

Exercise 11.25:
The counter shown in Figure 11.37 of the text is a mod-24 parallel counter composed of a
modulo-3 counter and a modulo-8 counter (twisted-tail counter). It has the following sequence of
state values:
modulo-3 modulo-8
Q1Q0 q0 q1q2q3
00 0000
01 1000
10 1100
00 1110
01 1111
10 0111
00 0011
01 0001
10 0000
00 1000
01 1100
10 1110
00 1111
01 0111
10 0011
00 0001
01 0000
10 1000
00 1100
01 1110
10 1111
00 0111
01 0011
10 0001
Observe that the output z is 1 when Q1 Q0 q0 q1 q2 q3 = 100001, that corresponds to the expression
z = Q1Q00 q20 q3 , and is equivalent to a Terminal Count (TC) signal in a binary counter.
(a) a binary modulo-24 autonomous counter using T ip ops and gates is shown in Figure 11.37.
State 23 (10111) is detected by a network that implements the expression S23 = Q4 Q2 Q1Q0 . Since
the next state from (10111) must be (00000), we need T0 = T1 = T2 = T4 = 1 and T3 = 0. The
values of T0 = T1 = T2 = 0 are already generated when the present state is (10111). The values
T4 = 1 and T3 = 0 must be forced when S23 = 1. The implementation has fewer ip ops, more
gates and more connections than the implementation in Figure 11.37 of the text.
(b) a twisted-tail modulo-24 autonomous counter using D ip ops and gates is shown in
Figure 11.38. Twelve ip ops are needed, instead of the six ip- ops used in Figure 11.37 of the
text. However, no gates are required and besides the clock line, all interconnections can be made
very short. The TC condition is generated when the present state is (000000000001), and that is
the only state when we have a 0 preceding a 1 at the rightmost ip op.
1 T Q T Q T Q T Q T Q Q4
Q0 Q1 Q2 Q3
0 1 2 3 4
CK
Q4 S 23
Q2 z
Q1
Q0
Figure 11.37: Modulo-24 autonomous counter - Exercise 11.25(a)
z
D Q D Q D Q D Q D Q
1 2 3 4 12
Q Q Q Q Q
CK
Figure 11.38: Twisted-tail modulo-24 autonomous counter - Exercise 11.25(b)

Exercise 11.26:
(a) The network is shown in Figure 11.39. The right counter is a modulo-5 counter. Taking only
into account the state bits (Q2Q1 Q0), the left counter in the Figure corresponds to a \subcounter"
that is modulo 8. When the state of the modulo-5 counter is 100 and the state of the other counter
is 111, the output z becomes 1. For all other states, z = 0. As we have 40 dierent states, and
z = 1 only once, the circuit implements a modulo-40 frequency divider.
0 0 0 0 0 0 0 0
clear CLR I3 I2 I1 I0 clear CLR I3 I2 I1 I0

1 CNT Mod-16 Counter TC 1 CNT Mod-16 Counter TC
0
z
Figure 11.39: Modulo-40 frequency divider - Exercise 11.26(a)

(b) the counting sequence of a counter formed by a modulo-10 and a modulo-4 counter is:
(0,0), (1,1), (2,2), (3,3), (4,0), (5,1), (6,2), (7,3), (8,0), (9,1), (0,2), (1,3), (2,0), (3,1), (4,2),
(5,3), (6,0), (7,1), (8,2), (9,3), (0,0), : : :
Observe that although 4x10=40 this is a modulo-20 counter instead of a modulo-40 counter
because 4 and 10 are not relatively prime.
Exercise 11.27: The state diagram for the electronic lock is shown in Figure 11.40. Such a
state diagram is adequately implemented using a modulo-16 counter and a 16-input multiplexer.
In order to generate the required outputs, another counter is used to count the number of times the
buttons were pressed. This counter generates a signal END when the keys were pressed 12 times.
We assume that the outputs of the push buttons that generate the inputs are 1s for only one clock
A A A A A C C C B B B B
Init A1 A2 A3 A4 A5 C1 C2 C3 B1 B2 B3 B4
B,C B,C B,C A,B
B,C B,C A,B A,B A,C A,C A,C A,C
Error
A,B,C
Figure 11.40: State Diagram for the electronic lock - Exercise 11.27
period, each time the user press them. A network for this task is shown in Figure 11.41 together
with the network that implements the lock controller. When a correct sequence is inserted (state
is B4) the output z = 1 is generated, and the controller goes back to the initial state. When a
wrong sequence is inserted the RED output is activated by the condition B 40 END (END = 1
when 12 characters were inserted). The output GREEN is 1 when the controller is at state INIT .
The Y ELLOW is 1 while the sequence is being inserted, that means, the sequence started to be
inserted and the RED or z output were not generated yet. When z = 0 the top counter goes to
state 15 (ERROR), and the bottom one stays at state 12. Only a reset signal R will remove the
counters from these states, if the wrong sequence is inserted. When z = 1 both counters load the
value 0 and they are ready to start another operation.
A 0
A 1
A 2
A 3
A 4
C 5
C 6
C 7
B 8 MUX
B 9
B 10
B 11
0 12
0 13 R CLR I3 I2 I1 I0 push button
0 14 CNT Mod-16 Counter TC D Q
0 15 CK
3210 LD q3 q2 q1 q0
CK Q
B4
circuit used to obtain A, B, and C
0 0 0 0
A
R CLR I3 I2 I1 I0
B
C CNT Mod-16 Counter TC z
CK LD q3 q2 q1 q0
RED
z e
GREEN
YELLOW
Figure 11.41: Sequential Lock network - Exercise 11.27

Exercise 11.28: The design of this controller can be done using an approach similar to the
one presented in Figure 11.21 of the text. The network is shown in Figure 11.42.
clear CLR I2 I1 I0 clear CLR I4 I3 I2 I1 I0

NEQ CNT Mod-6 Counter TC CNT Mod-32 Counter TC n
CK LD q2 q1 q0 CK LD q4 q3 q2 q1 q0
5
2 1 0 0 a4 a3 a2 a1 a0 b
0 Decoder 5-bit Comparator
0 1 2 3 4 5 a<b
NEQ
S Q c0
CK
R
S Q c1
CK
R
c2
S Q
CK
R
c3
S Q
CK
R
Figure 11.42: Controller - Exercise 11.28

Exercise 11.29: The network to perform the comparison x(t 7; t 4) < x(t 3; t) is shown
in Figure 11.43.
serial x
Left-shift Register input
CK
A3 A2 A1 A0 B3 B2 B1 B0
4-bit comparator
A>B A=B A 10
B (DIST 10) and (COUNT = 3)
C (DIST 10) and (COUNT 6= 3)
Calling the inputs of the ip ops for each state as NS , we generate the following expressions:
i
NS0 = S0 :GO 0
NS1 = S0 :GO + S3
NS2 = S1 :C
NS3 = S2 + S4
NS4 = S1 :A
NS5 = S1 :B + S5
These expressions are implemented in a PSA as shown in Figure 12.1.
S0 S1 S2 S3 S4 S5 GO A B C
OR Array
NS0 NS1 NS2 NS3 NS4 NS5

AND Array
CK State Register
-- connection made
S0 S1 S2 S3 S4 S5
Figure 12.1: PSA implementation of a controller - Exercise 12.1

Exercise 12.2:
A modulo-11 counter is expressed by the following state transition and output function table:
PS Input
y3 y2 y1 y0 x = 0 x=1
0000 0000,0 0001,0
0001 0001,0 0010,0
0010 0010,0 0011,0
0011 0011,0 0100,0
0100 0100,0 0101,0
0101 0101,0 0110,0
0110 0110,0 0111,0
0111 0111,0 1000,0
1000 1000,0 1001,0
1001 1001,0 1010,0
1010 1010,0 0000,1
NS(Y3 Y2 Y1 Y0 ), output
From this table, using Kmaps we obtain the following minimal expressions for the next state
bits and the output (terminal count - TC):
Y3 = y3x + (y3y1 + y2 y1 y0 )x = y3 x + y3 y1 x + y2 y1 y0 x
0 0 0 0
Y2 = y2x + (y2 y1 + y2 y0 + y2 y1 y0 )x = y2 x + y2 y1 x + y2 y0 x + y2 y1 y0 x
0 0 0 0 0 0 0 0
Y1 = y1x + (y1 y0 + y3 y1 y0 )x = y1 x + y1 y0 x + y3 y1 y0 x
0 0 0 0 0 0
Y0 = y0x + (y1 y0 + y3 y0 )x = y0 x + y1 y0 x + y3 y0 x
0 0 0 0 0 0 0 0 0 0
TC = y3 y1 x
The implementation of these equations using a PSA is shown in Figure 12.2.
y3 y2 y1 y0 x
OR Array
10
11
12
13
14
AND Array
Y3 Y2 Y1 Y0 TC
-- programmable connection CK State Register
-- connection made
y3 y2 y1 y0
Figure 12.2: Modulo-11 counter - Exercise 12.2

Exercise 12.3:
The number of address lines should be 4, since a BCD digit is the single input. The maximum
value to be stored in the ROM is 92 = 81, which requires dlog281e = 7 bits to be represented in
binary. Thus, at least a 16 7 ROM is required to implement the function.
Exercise 12.4:
The system that converts from BCD to Excess-3 is shown in Figure 12.3. It implements the
following table:
BCD Excess 3
b3b2 b1b0 q3 q2 q1 q0
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1100
ROM
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
b0 0 6 1 0 0 1
b1 1 7 1 0 1 0
b2 2 decoder 8 1 0 1 1
b3 3 9 1 1 0 0
10 - - - -
11 - - - -
12 - - - -
13 - - - -
14 - - - -
15 - - - -
q2 q0
q3 q1
Figure 12.3: BCD to Excess-3 converter - Exercise 12.4

Exercise 12.5:
For this implementation we need a 212 6 ROM. Twelve address lines receive the input bits
from a, b, and c 2 f0; 1; :::; 15g. Six bits are required to represent 0 s 45. The block diagram
of the component is shown in Figure 12.4.
ROM
0 000000
1 000001
2 000010
a0 0 3 000011
a1 1
a2 2
a3
3
b0 4
decoder
b1 5
b2 6
b3 7
c0 8
c1 9
c2 10
c3 11
4095 1 0 1 1 0 1
s4 s2 s0
s5 s3 s1
Figure 12.4: ROM implementation - 3-input 4-bit adder - Exercise 12.5

Exercise 12.6:
The high-level specication of the single-digit decimal adder is:
Input: A,B 2 f0; 1; 2; :::; 9g and c 2 f0; 1g
in
Output: S 2 f0; 1; 2; :::; 9g and c 2 f0; 1g

out
Function:
(
S = A A+B +c if A + B + c < 10
in in
+ B + c 10 if A + B + c 10
in in
(
c = 0 if A + B + c < 10
in
out
1 if A + B + c 10
in
Calling a, b and s the integers obtained from the Excess-3 representation we get:
a = A+3
b = B +3
s = S+3
Substituting these expressions on the equations above, we obtain:

(
s = aa + + b + c 3 if a + b + c 6 < 10
in
b + c 13 if a + b + c 6 10
in
in in
(
c = 0 if a + b + c in 6 < 10
out
1 if a + b + c in 6 10
The ROM implementation of a single digit Excess-3 adder requires 9 addressing lines (512
words). Four bits are used by each Excess-3 digit a or b (represented by a and b), and one bit is
used for carry input (c ). Each word needs to have 5 bits: four bits for the output digit in Excess-3
in
(s) and one bit for carry output (c ). We dene the address vector as x = (a; b; c ), which is the
out in
binary representation of x = 32a + 2b + c and the contents of each word as w = (c ; s), which
in out
corresponds to w = 16c + s. The value in each word position x of the ROM is given as:
out
(
w = aa + + b + c 3 if a + b + c < 16
in
b + c + 3 if a + b + c 16
in
in in
A block diagram for the ROM showing some words' contents is presented in Figure 12.5. Address
102, for example, corresponds to the addition of A = 0 and B = 0 in Excess-3 (a = b = 3), and
c = 0.
in
ROM
0 -----
1 -----
2 -----
3 -----
c in 0
a0 1 102 00011
a1 2 103 00100
decoder
a2 3 104 00100
a3 4 105 00101
b0 5 106 00101
b1 6 107 00110
b2 7
b3 8
408 1 1 0 1 1
409 1 1 1 0 0
511 1 1 1 1 1
cout s 2 s 0
s3 s1
Figure 12.5: ROM implementation of an Excess-3 digit adder - Exercise 12.6

Exercise 12.7:
Part (a) - using one decoder and ROM modules of eight 4-bit words. Figure 12.6
a b
1 0
decoder
0 1 2 3
ROM E ROM E ROM E ROM E

0 0110 0 0001 0 1000 0 0001
21 1000 21 0010 21 0010 21 0010
c c c c
2 0000 2 0000 2 0000 2 1000
d 1 d 1 d 1 d 1
3 0100 3 0100 3 0001 3 0000
e 0 e 0 e 0 e 0
4 1000 4 0001 4 0010 4 0000
5 1000 5 0010 5 0010 5 0100
6 0001 6 1000 6 1000 6 1010
7 0000 7 0000 7 0100 7 0000
f0 f1 f2 f3
Figure 12.6: Implementation of switching function using one decoder and ROM- Ex. 12.7
COST = 4 (ROM ) + DEC = 4 (ROM ) + 4 (AND-2) + 2 (NOT)

#interconnections = 13
delay = (ROM ) + (AND-2) + (NOT)
where represents the component delay.
Part (b) - using ROM modules and a multiplexer. Figure 12.7.
COST = 4 (ROM ) + MUX = 4 (ROM ) + 16 (AND-3) + 4 (OR-4) + 2 (NOT)
#interconnections = 29
delay = (ROM ) + (MUX ) = (ROM ) + (AND-3) + (OR-4)
Thus, the rst design is better than the second one in all aspects.
1 1 1 1
ROM E ROM E ROM E ROM E

0 0110 0 0001 0 1000 0 0001
1 1000 1 0010 1 0010 1 0010
c 2 2 0000 c 2 2 0000 c 2 2 0000 c 2 2 1000
d 1 3 0100 d 1 3 0100 d 1 3 0001 d 1 3 0000
e 0 4 1000 e 0 4 0001 e 0 4 0010 e 0 4 0000
5 1000 5 0010 5 0010 5 0100
6 0001 6 1000 6 1000 6 1010
7 0000 7 0000 7 0100 7 0000
0123 0123 0123 0123

a 1
4x4-input MUX
b 0
f0 f1 f2 f3
Figure 12.7: Implementation of switching function using ROM and MUX - Ex. 12.7
Exercise 12.8:
Since the number of products used by each output is not known, we need to assume the worst
case situation, when most of them are used by a single output, and 1 (or none) is used by the other
outputs. The PLA provides only 128 product terms, thus, we need to use two PLAs to obtain 256
product terms, combining their outputs with OR gates. The number of inputs is also larger than
the number of inputs in each PLA device, thus, a binary decoder is used to select among 4 dierent
PLA banks, each bank consisting of a pair of PLAs with ORed outputs. The design is shown in
Figure 12.8.
(x11,x10,...,x1,x0)
PLA bank
0
x12 0
binary 1
En Input En Input x13 1
dec 2
3
PLA PLA E
outputs outputs 1 PLA Bank PLA Bank PLA Bank PLA Bank
0 1 2 3
z0 z1 z2 z3
Figure 12.8: Design using PLAs - Exercise 12.8

Exercise 12.9:
For the ROM implementation of the function we need 26 words of 2 bits. Thus, a complete
switching function table should be implemented, with 64 entries.
For the PLA implementation, it is important to notice that z1 = 1 when a = b, and z0 = 1
when a = (b 1) mod 8. The minterms used to generate z1 are shown in the following table:
a2a1a0 b2b1b0 product terms to generate z1
000 000 a2 a1a0 b2b1b0
0 0 0 0 0 0
001 001 a2 a1a0 b2b1b0

0 0 0 0
010 010 a2 a1a0 b2b1b0

0 0 0 0
011 011 a2 a1a0 b2b1b0

0 0
100 100 a2 a1a0 b2b1b0

0 0 0 0
101 101 a2 a1a0 b2b1b0

0 0
110 110 a2 a1a0 b2b1b0

0 0
111 111 a2 a1a0 b2b1b0

For PLAs what matters is the number of product terms. It is not possible to reduce the number
of product terms shown in the table since both a and b change one bit from one row to another.
Thus, two literals are dierent from one minterm to another, making impossible the combination
of two minterms. The number of product terms is already minimal.
Similarly, for z0 (the case a = (b 1) mod 8):
a2a1a0 b2b1b0 product terms to generate z0
000 111 a2 a1a0 b2b1b0
0 0 0
001 000 a2 a1a0 b2b1b0

0 0 0 0 0
010 001 a2 a1a0 b2b1b0

0 0 0 0
011 010 a2 a1a0 b2b1b0

0 0 0
100 011 a2 a1a0 b2b1b0

0 0 0
101 100 a2 a1a0 b2b1b0

0 0 0
110 101 a2 a1a0 b2b1b0

0 0
111 110 a2 a1a0 b2b1b0 0
where again the number of product terms is minimal.

Thus, the PLA would need to have 16 products, 6 inputs, and 2 outputs.
Exercise 12.10:
The design of the BCD counter can be done with the ROM module, 4-bit register and AND
gate, as shown in Figure 12.9. No need for the adder. The ROM module receives the Present State
of the counter (stored in the 4-bit register) as address bits. Each word contains the value of the
next state. Using the LOAD input of the register the circuit will load the next state only when
CNT = 1. The state is kept the same when CNT = 0. The terminal count output is generated by
the AND gate, as TC = Q3 Q0 .
ROM
0 00010
1 00100
2 00110
3 01000
4 01010
5 01100
6 01110
0 7 10000
decoder
1 8 10010
2 9 00001
3 10 -----
11 -----
12 -----
13 -----
14 -----
15 -----
TC
CNT
LD
CK Register
Q3 Q2 Q1 Q0
Figure 12.9: BCD counter - Exercise 12.10

Exercise 12.11:
Size of state register and ROM for:
(a) Moore sequential system with 512 states, 3 inputs and 2 outputs. For 512 states, a minimum
of 9 bits are required to represent each state. The ROM needs to have as many address lines
as the number of state bits plus the number of inputs, which corresponds to a total of 12 bits.
Since this is a Moore machine the total number of ROM bits is reduced by using separate
ROMs to generate the next state and to generate the outputs. The ROM for the next state
will have 212 9 bits. The ROM to generate the output will be a 29 2 bits ROM. Thus, the
implementation will require a 212 9 ROM, a 29 9 ROM, a and a 9-bit register. Of course,
the implementation can use only one ROM, resulting the same as for the Mealy case.
(b) For a Mealy model, the system will have only a single 212 11 ROM, and a 9-bit register.
This time the output values are stored with the next state bits.
(c) When the state transition depends only on one input, a multiplexer (in this case a network of
multiplexer would be required, since the number of inputs is quite large). The multiplier is
used to select the correct input among the possible system inputs, depending on the present
state of the system. The output of the multiplexer is used as an address line for the ROM
which will have a size of 210 9 bits, and generates the next state bits. Since this is a Moore
machine, another ROM is used to generate the outputs. Same way as done in part (a), a
29 2 ROM is required for the outputs. A 9-bit register is used to store the state values. A
block diagram of the system is shown in Figure 12.10.
system
inputs
address
active MUX
in each ROM
state
Present
address
State CLK
ROM
outputs
Figure 12.10: Block diagram for Exercise 12.11(c)
(d) For a Mealy system, with the same conditions of the one considered in part (c), a 210 11
ROM, a network of muxes to select the input (same as in part (c)), and a 9-bit register are
used. The ROM stores both the next state bits and the output values.
(e) Since the system in part (c) is implemented as a Moore machine, the output doesn't depend
on the input values, and for this reason, this question doesn't make sense. If we apply this
idea to the system in part (d), then the output should be generated by a separate ROM with
11 addressing lines and 2-bit words. The generation of the next state would be done by a
210 9 ROM. The network of muxes to select the inputs would be used, and a 9-bit register
would store the state bits.
Exercise 12.12:
From Figure 12.18 of the text we obtain the following state transition and output table:
PS Input z
y2 y1 y0 x = 0 x = 1
000 000 100 1
001 010 110 0
010 000 100 0
011 011 111 0
100 001 101 1
101 000 100 0
110 011 111 0
111 001 101 1
NS
Using the name S for state i we obtain the following high level description of the sequential
i
system:
Input: x 2 f0; 1g
Output: z 2 f0; 1g
States: S , with 0 i 7
i
State transition and output function table:

PS Input z
y2 y1 y0 x = 0 x = 1
S0 S1 S4 1
S1 S2 S6 0
S2 S0 S4 0
S3 S3 S7 0
S4 S1 S5 1
S5 S0 S4 0
S6 S3 S7 0
S7 S1 S5 1
NS
The state diagram for the system is shown in Figure 12.11.
0
0
0 0
S0/1 S1/0 S2/0 1 S3/0
1 1
1
0
0
0 0
1 1
S7/1 S6/0 S5/0 S4/1
1
1
Figure 12.11: State diagram for system in Exercise 12.12.

Exercise 12.13:
Observe that each state has transitions to another state based on only one input among 3
possible inputs 2 fa; b; cg. A multiplexer can be used to select the desired input, and the diagram
can be modied to have only one input, let's call it x. The new transition table would be:
PS Inputs
x=0 x=1
S0 S3/10 S1/01
S1 S1/00 S2/01
S2 S3/00 S4/01
S3 S1/00 S0/00
S4 S4/00 S3/11
NS,z1 z0
Assume that the state S is represented by the vector i = (y2 ; y1; y0). The network that imple-
i
ments the state diagram is given in Figure 12.12.
Next Present
1 1 ROM state Reg State
a 0 E E 0 01110 Y2 y2
c 1 1 00100
a 2 2 01100 Y1 y1
b x
3 MUX 3 3 00100
b 4 y2 2 4 10000 Y0 y0
5 y1 1 5 xxxxx
6 y0 0 6 xxxxx CK
7 2 1 0 7 xxxxx
8 00101
y2 y1 y0 9 01001
10 10001
(present state) 11 00000
12 01111
13 xxxxx
14 xxxxx
15 xxxxx
z0
z1
Y2Y1Y0
(next State)

Exercise 12.14:
Part (a): Based on the information that the ROM word contains:
the next state bits (3 bits are required for a sequence of 8 clock cycles),
the output bits for T1, T2, and T3, and
one bit L that controls the load of the register that stores the sequence number s.
we conclude that each ROM word requires 7 bits. Since 16 dierent sequences are generated by
the system, 16 8 = 128 words are required. Thus, a 128 7 ROM is used.
Part (b): The system diagram is shown in Figure 12.13. COMMENT: the s value is loaded at
the last clock cycle of the sequence, not the one before the last.
T1 ROM
s
8 words s=0
T2
System
CK T3
s=1
s=2
3 s=3
Q2Q1Q0
4
s 4 D Q most significant
s=4 Q2Q1Q0 T1T2T3 L
address bits 0 0 1 0 1 1 0
CK 0 1 0 1 1 0 0
ce s=5 0 1 1 1 1 1 0
1 0 0 1 0 0 0
1 0 1 1 0 1 0
L 1 1 0 0 0 0 0
1 1 1 0 0 1 0
0 0 0 0 0 0 1
s=15
3 3
Q2Q1Q0
L
T1T2T3
Figure 12.13: System implementation for Exercise 12.14

Part (c): The contents of the ROM for the case s = 5 is the following:
Address Next State T1T2T3 L
101000 001 011 0
101001 010 110 0
101010 011 111 0
101011 100 100 0
101100 101 101 0
101101 110 000 0
101110 111 001 0
101111 000 000 1
Exercise 12.15:
For this design we use a ROM that receives as input lines the values of the present state,
and 2 input bits. In fact, there are 3 conditions that are used as inputs, but making use the the
multiplexer we are able to select among two inputs: GO and DIST > 10. The third input is
inserted directly as an address signal to the ROM. The ROM contains the information on the next
state and the outputs (CLEAR,CHECK ,TURNLEFT 90,COUNTUP ,MOV E ,STOP ). Thus 9
bits are required per ROM word. The design is shown in Figure 12.14.
ROM
0 000100000
1 000100000
2 001100000
3 001100000
4 010010000
5 101010000
6 100010000
7 100010000
8 011001000
9 011001000
10 --------
GO 0 11 --------
DIST>10 1 12 001000100
0 2 COUNT=3 13 001000100
0 3 0 decoder 14 --------
0 4 MUX 1 15 --------
0 5 2 16 011000010
0 6 3 17 011000010
Reg.
0 7 4 18 --------
CK
19 --------
2 1 0 20 101000001
21 101000001
22 --------
23 --------
24 --------
25 --------
26 --------
27 --------
28 --------
29 --------
30 --------
31 --------
STOP
MOVE
COUNTUP
TURNLEFT90
CHECK
CLEAR
Figure 12.14: Circuit for Exercise 12.15

Exercise 12.16:
The ROM used to design this counter should have 28 words of 8 bits each. We consider the design
of an autonomous counter. The block diagram for the circuit is shown in Figure 12.15. The contents
address
ROM
TC
CLK
Figure 12.15: ROM implementation of Decimal Counter - Exercise 12.16

of the ROM would be too lengthy to describe using a table with all entries. It is easier to consider
the following tabular description that uses ranges of values. ROM addresses or word contents
are represented by a pair (x; y ), with x; y 2 f0; 1; 2; :::15g. As an example, the range specied as
(1; 10) (1; 15) represents the ordered sequence of values: (1; 10); (1; 11); (1; 12); (1; 13); (1; 14); and
(1; 15).
Address Contents
(0,0)-(0,9) (0,1)-(0,9),(1,0)
(0,10)-(0,15) d.c.
(1,0)-(1,9) (1,1)-(1,9),(2,0)
(1,10)-(1,15) d.c.
(2,0)-(2,9) (2,1)-(2,9),(3,0)
(2,10)-(2,15) d.c.
(3,0)-(3,9) (3,1)-(3,9),(4,0)
(3,10)-(3,15) d.c.
(4,0)-(4,9) (4,1)-(4,9),(5,0)
(4,10)-(4,15) d.c.
(5,0)-(5,9) (5,1)-(5,9),(6,0)
(5,10)-(5,15) d.c.
(6,0)-(6,9) (6,1)-(6,9),(7,0)
(6,10)-(6,15) d.c.
(7,0)-(7,9) (7,1)-(7,9),(8,0)
(7,10)-(7,15) d.c.
(8,0)-(8,9) (8,1)-(8,9),(9,0)
(8,10)-(8,15) d.c.
(9,0)-(9,9) (9,1)-(9,9),(0,0)
(9,10)-(15,15) d.c.
The ROM address receives the present state bits and the contents of a ROM word provides the
next state value. A content of D.C. means that ANY value can be used. A Terminal Count signal
is generated when the next state is (0; 0).
Exercise 12.17:
The ROM implementation of the system is shown in Figure 12.16. The complete contents of
the ROM that generates (z22; z21; z20) (using decimal notation) is given in the next table:
0 0 0 0
1 0 0 0
2 0 0 0
3 0 0 0 0 0 0
4 0 0 0 1 0 0
5 - - - 2 0 0
x 20 6 - - - 3 - - 0 0
0
x 21 7 - - - 4 0 0 x 00 0 1 0
1
x 22 8 0 0 0 5 0 1 y 00 1 2 0
2 x 10 0
y 20 9 0 0 1 6 1 0 3 1
3 x 11 1
y 21 10 0 1 0 7 - -
4 y 10 2
y 22 11 0 1 1 8 0 0
5 y 11 3
12 1 0 0 9 1 0 z 00
13 - - - 10 0 1
14 - - - 11 - -
15 - - - 12 - -
13 - -
14 - -
40 - - - 15 - -
z 11 z 10
63 - - -
z22 z 21z 20
Figure 12.16: ROM implementation of Exercise 12.17

y2 x2 z2 y2 x2 z2 y2 x2 z2 y2 x2 z2
0 0 0 2 0 0 4 0 0 6 0 dc
0 1 0 2 1 2 4 1 4 6 1 dc
0 2 0 2 2 4 4 2 3 6 2 dc
0 3 0 2 3 1 4 3 2 6 3 dc
0 4 0 2 4 3 4 4 1 6 4 dc
0 5 dc 2 5 dc 4 5 dc 6 5 dc
0 6 dc 2 6 dc 4 6 dc 6 6 dc
0 7 dc 2 7 dc 4 7 dc 6 7 dc
1 0 0 3 0 0 5 0 dc 7 0 dc
1 1 1 3 1 3 5 1 dc 7 1 dc
1 2 2 3 2 1 5 2 dc 7 2 dc
1 3 3 3 3 4 5 3 dc 7 3 dc
1 4 4 3 4 2 5 4 dc 7 4 dc
1 5 dc 3 5 dc 5 5 dc 7 5 dc
1 6 dc 3 6 dc 5 6 dc 7 6 dc
1 7 dc 3 7 dc 5 7 dc 7 7 dc
The PLA implementation of the system needs the representation of the output functions as a
sum of product terms. The switching expressions in sum-of-products form for the various outputs
are:
z22(y22; y21; y20; x22; x21; x20) = m2 (12; 18; 27; 33)
z21(y22; y21; y20; x22; x21; x20) = m2 (10; 11; 17; 20; 25; 28; 34; 35)
z20(y22; y21; y20; x22; x21; x20) = m2 (9; 11; 19; 20; 25; 26; 34; 36)
z11(y11; y10; x11; x10) = m1 (6; 9)
z10(y11; y10; x11; x10) = m1(5; 10)
z00(y00; x00) = x00y00 = m0(3)
Since the outputs z2 depend on the same set of inputs, they should be mapped to the same
i
PLA. If more inputs and products are available in the component, functions z1 and z00 could also
i
be implemented in the same PLA. A total of 21 products were listed in the expressions above,
however, it is possible to reduce this number of products to 20. Using ESPRESSO we were able to
reduce the number of products to generate z2 from 16 to 15 (the others cannot be reduced). One
possible solution is to combine m2 (9) and m2 (25) on the generation of z20 and obtain the single
product term y22 y20x22 x21x20. ESPRESSO also reduces the number of literals in each product
0 0 0
term, however, this feature is not important for PLA implementation.

Exercise 12.18:
Number of Congurable Logic Blocks for
an 8-to-1 multiplexer. Since a CLB can implement a 2-input multiplexer, and the 8-to-1
multiplexer can be designed with a tree of 7 2-input multiplexers, the total number of CLBs
required for this case is 7.
a 4-bit right/left shift register with parallel load. For this implementation, a 4-input multi-
plexer is required for each register bit. A 4-input multiplexer uses 3 CLBs (tree organization),
thus a total of 12 CLBs are needed. The ip- ops to store the register state are available in
the CLBs used to implement the multiplexers.
a modulo-9 counter with parallel load and TC. A canonical design of an autonomous modulo-
9 counter (no control input, only the sequence of states changing with the clock input) would
generate the following expressions for the next state bits:
Y3 = Q2Q1 Q0
Y2 = Q2Q1 + Q2Q1 Q0 + Q2 Q0
0 0 0
Y1 = Q1Q0 + Q1Q0
0 0
Y0 = Q3Q0
0 0
A pair of these functions can be implemented by a CLB (two 3-input functions). When we
add the inputs CNT, LD, and parallel input, to the variable Y (in order to generate the actual
i
value that is loaded as each state bit), we get a function of 4 inputs, that requires 1 CLB for
each state bit. Thus the total number of CLBs is 6. The required ip ops are available on
the CLBs used for combinational logic.
an 8-bit two's complement adder. A Carry Ripple adder will require 8 Full Adders. Each
CLB can implement 1 FA, thus, the total number of CLBs in this implementation is 8.
a 4 2 multiplier (positive integers). To generate the partial products 4 CLBs are used (2
product bits per CLB). These bits are summed in a 5-bit adder, which, based on the result
given in the previous item, will require 5 CLBs. Thus, the total number of CLBs required to
implement the multiplier is 9. The reader may also try to reduce this number by creating a
optmized mapping of the the product generation and addition funtions for the least signicant
bits.
267
Chapter 13
Exercise 13.1
Graphs for cases (a) and (b) are shown in Figure 13.1.
f0 f0
OR
f1 f3
OR OR
f2
f1 f2 Group 1
T AND
f4
T
F f4
f3 F
f5 f6 Group 2
f5
AND
f7
f6
f8
f7
f8
(a) sequential execution graph (b) group sequential execution graph

(max of 2 operations per group)
Figure 13.1: Execution Graphs for Exercise 13.1

The execution time for the concurrent graph, considering that the test done by node f4 results
true for n occurrences (and false after that), is computed as:
Tconc = 3T + 2nT + 2T = (5 + 2n)T
where 3T corresponds to the time to execute the path f0 to f4 , f5 , and f6 . Each iteration that
results from a True test at f4 has a duration of 2T , which is also the execution time of the last two
tasks to nish the computation (f7 and f8 ).
The execution time of the sequential solution shown in Figure 13.1 (a), for the same loop
condition used for the concurrent case is:
Tseq = 4T + 3nT + 5T = (9 + 3n)T
where 4T corresponds to the time to executed the path f0 to f4 for the rst time. Each iteration
takes 3T and the last sequence of tasks takes 5T .
268 Solutions Manual - Introduction to Digital Design - May 29, 2001
Exercise 13.2
Trace of variable's values for the VHDL description shown in Example 13.6, with xin = 5 and
yin = 9 is given as follows:
- Before the loop: a = 5, and w = 9
- Inside the loop:
+ rst iteration: a = 6 and w = 8
+ second iteration: a = 7 and w = 7
+ loop stops
- zout = 28
Exercise 13.3
The algorithm presented in Example 13.7 is based on the recurrence:
zi+1 = zi (2 xzi)
The algorithm stops when jzix 1j < 0:5.
When the inputs for the algorithm are:
x = 23 and = 10 5
each variable will have the values shown in the next table:
step j zj Error
0 1
1 1.3333333 0.111111
2 1.4814814 0.001234
3 1.4997714 0.000015
4 1.4999999 2 10 8
After 4 iterations, the result has an error that is smaller than 5 10 6 .
Exercise 13.4
When the input x = 1=3 is applied to the algorithm presented in Example 13.7, considering an
error = 10 5 we obtain the following execution sequence:
step j zj Error
0 1
1 1.6666666 0.444444
2 2.4074074 0.197530
3 2.8829447 0.039018
4 2.9954327 0.001522
5 2.9999930 0.000002
From this trace we can see that the algorithm will converge even with the input being out of
range (x should be in the range [1=2; 1]). A wrong estimate of the error however can happen, since
the condition zk 1=x < is equivalent to 2(zk x 1) < only when x 1=2. Another problem
happen if x is out of range, and is also too small, resulting in a reciprocal with too many integer
bits, while the circuit is designed to handle at most two integer bits.
The algorithm will not converge when x 2.
Solutions Manual - Introduction to Digital Design - May 29, 2001 269
Using prescaling, input x is multiplied by 2 until 2k x is in the proper range. The scaled value
2k x isused as input for the algorithm. For example:
x = 13 ! 2x = 32
which is in the correct range, and corresponds to the input given in Exercise 13.3. So, the algorithm
input should be 2x.
The output generated by the algorithm (z ) must be corrected by multiplying it by the same
scaling factor 2k used to prescale the input x. Based on the previous example: z = 1:5, and 2z = 3,
which corresponds to the correct result.
Exercise 13.5
p
We want to compute z = a using the recurrence equation:
zi+1 = 21 (zi + za )
i
Since z 2 = a, the stop condition is dened as z 2 a < , where is the maximum error in the
nal result. The execution graph is presented in Figure 13.2.
Input
a, error
z=1
w=z*z
Y
jw aj < error
N
a 1
output z z = (z + )
z 2
Figure 13.2: Execution graph - Exercise 13.5

The VHDL code for the algorithm is given on Figure 13.3.
-- VHDL code for Square-root computation - Exercise 13.5

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY sqroot IS
PORT (a_in: IN REAL RANGE 0.5 TO 1.0;
Error: IN REAL RANGE 0.0 TO 0.1;
z_out: OUT REAL RANGE 0.7 TO 1.0;
CLK: IN BIT);
END sqroot;
ARCHITECTURE high_level OF sqroot IS

BEGIN
PROCESS (CLK)
VARIABLE a,w: REAL RANGE 0.5 TO 1.0;
VARIABLE z: REAL RANGE 0.7 TO 1.0;
BEGIN
IF (CLK'event AND CLK='1') THEN
z := 1.0;
a:= a_in;
w := 1.0;
WHILE (ABS(w-a) > Error) LOOP
z:=(a/z+z)/2.0;
w:=z*z;
END LOOP;
z_out <= z;
END IF;
END PROCESS;
END high_level;
Figure 13.3: VHDL code for SQRT(a) - Exercise 13.5

Exercise 13.6
(a) The concurrent execution graph for the computation of 6! is given in Figure 13.4(a). The
execution time for this computation is 3T . The generalization of the factorial computation is based
on a recurrent structure as shown in Figure 13.4(b). This structure shows that 2m numbers may be
simultaneously multiplied pairwise to generate m products. The tree generated by this structure
will have 2i inputs after i levels. To compute n!, n 1 inputs are needed. Thus, dlog2(n 1)e levels
are required. An example of the computation of 11! is also shown in Figure 13.4(b). In this case 4
levels are required in the tree. The execution time for n! is given as dlog2(n 1)eT .
i 11 10 9 8 7 6 5 4 3 2
2 inputs
* * * level i
a=6*5 b=4*3
AND
c=a*b
* * level 2
c*2
* level 1
(a) computation of 6! (b) generalization for n!
Figure 13.4: Concurrent Execution Graph - Exercise 13.6(a)

(b) The sequential execution graph for the computation of n! is given in Figure 13.5. We can
see from the graph that the loop is executed (n 1) times. Thus, the total execution time is
(2 + 3(n 1))T = (3n 1)T .
Input n
r=1, f=1
r<n Y r= r+1
Output f f=f*r
Figure 13.5: Sequential execution graph - Exercise 13.6b

Exercise 13.7
Execution graph of the algorithm that obtains the maximum value among n positive integers.
All n integers are stored in a vector V . The vector is scanned from position 0 to position n 1. In
this process, the maximal value is obtained. The computation graph is shown in Figure 13.6.
Input
V,N
MAX = V(0)
I=1
N
I<N
Y
Y
Output MAX < V(I) MAX = V(I)
MAX
N
I=I+1
Figure 13.6: Execution graph - Exercise 13.7
-- VHDL code for MAX of N integers (in vector V) - Exercise 13.7

PACKAGE max_pkg IS
CONSTANT N: INTEGER := 5;
TYPE DatainT IS ARRAY (N-1 DOWNTO 0) OF INTEGER;
END max_pkg;
USE work.max_pkg.ALL;
ENTITY max IS
PORT ( V: IN DatainT := (-10,12,4,-2,34);
M: OUT INTEGER;
CLK: IN BIT);
END max;
ARCHITECTURE high_level OF max IS
BEGIN
PROCESS (CLK)
VARIABLE maxv: INTEGER;
VARIABLE i: INTEGER RANGE 0 TO N;
BEGIN
maxv := V(0); i:= 1;
WHILE (i < V'length) LOOP
IF (maxv < V(i)) THEN maxv := V(i);
END IF;
i:=i+1;
END LOOP;
M <= maxv;
END IF;
END PROCESS;
END high_level;
Exercise 13.8
The degree 9 polynomial is represented as:
9
X
P9 (x) = ai x i
i=0
The sequential and concurrent execution graphs for the polynomial computation are shown in
Figure 13.7. Using similar organization of Figure 13.5 and 13.6 of the textbook we obtain the
organizations presented in Figure 13.8.
Begin
Begin
A=a9*x+a8 B=a7*x+a6 C=a5*x+a4 D=a3*x+a2 E=a1*x+a0 F=x*x

V=a9
i=8 J=F*B+C K=F*D+E L=F*F
V = V*x + ai M=L*J+K N=L*L
Y
i>0 i=i-1 P9(x)=N*A+M
END END
Figure 13.7: Execution graphs - Exercise 13.8
Exercise 13.9
The networks generated for each case is shown in Figure 13.9.
x a9 a7 a5 a3 a1
M M M M M M
Step4
a8 a6 a4 a2 a0
Step3
F Control Step2
+ + + + + Step1
A B C D E
M M M
L x J x L
x F B x D x x N
+ + I I I I I I I I I I I I
11 21 11 21 11 21 11 21 11 21 11 21
x F a9 F a7 F a5 L a3 L a1 A
I 12 I 22 I 12 I 22 I 12 I 22 I 12 I 22 I 12 I 22 I 12 I 22
J K 0 0 a8 C a6 E a4 K a2 0 a0 M
I 13 I 23 I 13 I 23 I 13 I 23 I 13 I 23 I 13 I 23 I 13 I 23
M M O O O O O O O O O O O O
1 2 1 2 1 2 1 2 1 2 1 2
N F L A J B K C M D N E P9(x)
M +
M
+
P9(x)
Figure 13.8: Organizations for polynomial computation - Exercise 13.8
Exercise 13.10
The state diagrams corresponding to the VHDL descriptions on this Exercise are shown in
Figure 13.10.
Exercise 13.11
The state diagram for the system operation is shown in Figure 13.11.
For N = 5 the trace of the computation is shown in the following table:
clock cycle state X I ODD(X ) I > 0

0 0 undef. undef. undef. undef.
1 1 5 3 T T
2 2 26 2 F T
3 1 26 2 F T
4 2 13 1 T T
5 1 13 1 T T
6 2 66 0 F F
7 2 66 0 F F
Thus the nal value is X = 66.

For N = 7 the trace of the computation is shown in the following table:
clock cycle state X I ODD(X ) I > 0
0 0 undef. undef. undef. undef.
1 1 7 3 T T
2 2 36 2 F T
3 1 36 2 F T
4 2 18 1 F T
5 1 18 1 F T
6 2 9 0 T F
7 2 9 0 T F
Thus the nal value is X = 9.
Exercise 13.12 (a) VHDL description
entity p13_12a is
port (X: in BIT_VECTOR (0 to 7);
clk,sel,ldW: in bit;
W: out BIT_VECTOR (0 to 7));
end p13_12a;
architecture arch of p13_12a is
-- process description - Exercise 13.12(a)
BEGIN
PROCESS (CLK)
variable WIN: BIT_VECTOR (0 TO 7);
BEGIN
IF (sel = '1')
THEN WIN := X;
ELSE WIN := NOT(X);
END IF;
IF (ldw = '1')
THEN W <= WIN;
END if;
END IF;
END PROCESS;
END arch;
(b) VHDL description
entity p13_12b is
port (W,Z: in BIT_VECTOR (0 TO 15);
clk,ldXY: in BIT;
X,Y: out BIT_VECTOR (0 TO 15));
end p13_12b;
Architecture arch of p13_12b is
-- process description - Exercise 13.12(b)
begin
PROCESS (CLK)
variable XIN,YIN: BIT_VECTOR (0 TO 15);
BEGIN
IF (W>Z)
THEN XIN := W;
YIN := Z;
ELSE XIN := Z;
YIN := W;
END IF;
IF (ldxy = '1')
THEN X <= XIN;
Y <= YIN;
END IF;
END IF;
END PROCESS;
END arch;
Exercise 13.13
Control: Assume that E is connected to CNT input, and ldk is connected to the LOAD input
of the mod-4 counter. Based on these assumptions and the networks presented in Figure 13.31 of
the text we obtain the following expressions:
E = (ldk)0
ldK = (A 7:S 1) + (c out:S 2)
ldC = clrB = c out:S 2
ldA = K 10 :K 00
S1 = K 10 :K 0
S2 = K 1:K 00
ldB = K 1:K 0
The value of ldK for all possible outputs of the counter is given by the following table. This
signal will force the counter to load a zero value.
counter state ldK
0 0
1 A7
2 c out
3 0
Observe that the counter will be forced to zero in state 1 if A 7=1, or in state 2 if c out=1.
The state diagram for the control part is shown in Figure 13.12.
The high-level description of the system in VHDL follows. The signals A, B , and C represent
the output of each register.
LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
entity p13_13 is
port (X: in STD_LOGIC_VECTOR (7 downto 0);
CLK: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR (7 downto 0));
end p13_13;
architecture arch of p13_13 is
-- process description - Exercise 13.13
SIGNAL A,B,C: STD_LOGIC_VECTOR (7 downto 0):=(OTHERS=>'0');
SIGNAL state: NATURAL RANGE 0 TO 3 := 0;
SIGNAL c_out: STD_LOGIC := '0';
SIGNAL adder_out: STD_LOGIC_VECTOR (8 downto 0);
begin
adder_out <= ('0'&A) + ('0'&B);
c_out <= adder_out(8);
CTR:PROCESS (CLK)
BEGIN
CASE state is
WHEN 0 => A <= X; state <= 1;
WHEN 1 => IF (A(7) ='1')
THEN state <= 0;
ELSE state <= 2;
END IF;
WHEN 2 => IF (c_out='1')
THEN C <= B;
B <= "00000000";
state <= 0;
ELSE state <= 3;
END IF;
WHEN 3 => B <= adder_out(7 downto 0);
state <= 0;
END CASE;
Y <= C;
END IF;
END PROCESS;
end arch;
The system accumulates all entries with values less than 128, until the accumulated value cannot
absorb another input X < 128 without over owing. In this case, the internal accumulator value is
registered as output and the internal state is reset. The trace of the system operation for a chosen
sequence of inputs is shown in Figure 13.13.
Exercise 13.14
The high-level specication for the two's complement multiplier is:
Inputs: x; y 2 f (2n 1 1); : : :; 1; 0; 1; : : :; (2n 1 1)g
Output: z 2 f (2n 1 1); : : :; 1; 0; 1; : : :; (2n 1 1)g
Function: z = x y
For a 32 32 bit multiplier we have n = 5.
Considering that the inputs and output are represented in two's complement number system,
their bit-vector representations are:
x = (xn 1; : : :; x1; x0); y = (yn 1 ; : : :; y1; y0); z = (z2n 1 ; : : :; z1; z0)
P P
where x = xn 1 2n 1 + ni=02 xi 2i , y = yn 1 2n 1 + ni=02 yi 2i , and z = z2n 1 22n 1 + 2i=0
P n 2 z 2i .
i
The computation is based on the recurrence:
(
zi+1 = 11==2( 2(zi + (x 2n )yi ) if i < n 1
zi (x 2n )yi) if i = n 1
which represents the case when the most signicant bit of the multiplier is 1 (negative number).
The general architecture of the multiplier is shown in Figure 13.14.
The behavioral description of the multiplier is shown next:
LIBRARY ieee;
ENTITY multiplierTC IS
GENERIC (n: NATURAL := 32); -- number of bits in the operands
PORT (start: IN BIT;
xin,yin: IN SIGNED (n-1 downto 0);
clk: IN BIT;
zout: OUT SIGNED (2*n-1 downto 0);
done_out: OUT BIT);
END multiplierTC;
ARCHITECTURE behav OF multiplierTC IS

TYPE stateT IS (idle,setup,active,done);
SIGNAL state: stateT := idle;
SIGNAL x,y: SIGNED (n-1 downto 0);
SIGNAL z: SIGNED (2*n-1 downto 0);
begin
PROCESS (clk)
VARIABLE zero_2n : SIGNED (2*n-1 DOWNTO 0); -- constant 0
VARIABLE scale: SIGNED (n-1 DOWNTO 0); -- aligning vector
VARIABLE add_out: SIGNED (2*n DOWNTO 0);
VARIABLE count: NATURAL RANGE 0 TO n;
BEGIN
zero_2n := (OTHERS => '0');
scale := (OTHERS => '0');
IF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN idle => done_out <= '0';
IF (start='1') THEN state <= setup;
ELSE state <= idle;
END IF;
WHEN setup => x <= xin; y <= yin; z <= zero_2n; count:=0;
state <= active;
WHEN active => IF (y(count) = '0')
THEN add_out:=z(2*n-1)&z; -- range extension
ELSE IF (count = (n-1))
THEN add_out:=(z(2*n-1)&z) - (x(n-1)&x&scale);
ELSE add_out:=(z(2*n-1)&z) + (x(n-1)&x&scale);
END IF;
END IF;
z <= add_out(2*n DOWNTO 1);
IF (count /= (n-1))
THEN state <= active;
count := count + 1;
ELSE state <= done;
done_out <= '1';
END IF;
WHEN done => IF (start='1')
THEN state <= done;
ELSE state <= idle;
done_out <= '0';
END IF;
END CASE;
END IF;
END PROCESS;
zout <= z; -- update the output
END behav;
A trace of a 4-bit TC multiplier is shown in Figure 13.15.

A numerical example of the multiplier operation is shown in the following table for the values
X = 125 = (10000011)2 and Y = 37 = (11011011)2.
clk state count X Y Z
0 0 x xxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxx
1 1 x xxxxxxxx xxxxxxxx 0000000000000000
2 2 x 10000011 11011011 0000000000000000
3 2 1 10000011 01101101 1100000110000000
4 2 2 10000011 00110110 1010001001000000
5 2 3 10000011 00011011 1101000100100000
6 2 4 10000011 00001101 1010101000010000
7 2 5 10000011 00000110 1001011010001000
8 2 6 10000011 00000011 1100101101000100
9 2 7 10000011 00000001 1010011100100010
10 2 0 10000011 00000000 0001001000010001
Exercise 13.15
The high-level specication of the 3232 serial-parallel multiplier for positive integers is given
as follows, for n = log232 = 5 bits:
Input: x; y 2 f0; 1; 2; : : :; 2n 1g
Output: z 2 f0; 1; 2; : : :; 22n 2n+1 + 1g
Function: z = x y
A block diagram of the data path for the multiplier is shown in Figure 13.16. The left multiplexer
is used to select among the 4 multiples of X , that means: 0, X , 2X , and 3X . To enable the
generation of the 3X value using the same adder used during the algorithms iterations, some gates
were inserted in the path of the selection signals of this multiplexer to force the X value as an
output. Another multiplexer was placed at the other input of the adder to receive the 2X value.
After the value 3X is generated, the iterations will be executed.
The VHDL specication of the radix-4 multiplication algorithms is given next:
LIBRARY ieee;
ENTITY radix4_multiplier IS
GENERIC (n: NATURAL := 8); -- number of bits in the operands
PORT (start: IN BIT;
xin,yin: IN UNSIGNED (n-1 downto 0);
clk: IN BIT;
zout: OUT UNSIGNED (2*n-1 downto 0);
done_out: OUT BIT);
END radix4_multiplier;
ARCHITECTURE behav OF radix4_multiplier IS

TYPE stateT IS (idle,setup,gen3x,active,done);
SIGNAL state: stateT := idle;
SIGNAL x,y: UNSIGNED (n-1 downto 0);
SIGNAL z: UNSIGNED (2*n-1 downto 0);
SIGNAL XXX: UNSIGNED (n+1 downto 0);
begin
PROCESS (clk)
VARIABLE zero_2n : UNSIGNED (2*n-1 DOWNTO 0); -- constant 0
VARIABLE scale: UNSIGNED (n-1 DOWNTO 0); -- aligning vector
VARIABLE add_out: UNSIGNED (n+1 DOWNTO 0); -- adder output
VARIABLE count: NATURAL RANGE 0 TO n;
BEGIN
zero_2n := (OTHERS => '0');
scale := (OTHERS => '0');
IF (clk'EVENT AND clk='1') THEN
CASE state IS
WHEN idle => done_out <= '0';
IF (start='1') THEN state <= setup;
ELSE state <= idle;
END IF;
WHEN setup => x <= xin; y <= yin; z <= zero_2n; count:=0;
state <= gen3x;
WHEN gen3x => XXX <= ('0'&x(n-1 downto 0)&'0') + ("00"&x);
state <= active;
WHEN active => CASE conv_integer(y(count+1 downto count)) IS
WHEN 0 => add_out:="00"&z(2*n-1 downto n);
WHEN 1 => add_out:=("00"&z(2*n-1 downto n))+x;
WHEN 2 => add_out:=("00"&z(2*n-1 downto n))+('0'&x&'0');
WHEN 3 => add_out:=("00"&z(2*n-1 downto n))+XXX;
WHEN others => add_out := (others => '0');
END CASE;
z <= add_out & z(n-1 downto 2);
IF (count /= (n-2))
THEN state <= active;
count := count + 2;
ELSE state <= done;
done_out <= '1';
END IF;
WHEN done => IF (start='0')
THEN state <= done;
ELSE state <= idle;
done_out <= '0';
END IF;
END CASE;
END IF;
END PROCESS;
zout <= z; -- update zout
END behav;
A trace of this code execution for two arbitrary inputs is shown in Figure 13.17. The values are
represented in octal.
For a 88 case, with the operand values x = 135 and y = 115, this is the result of the algorithm
execution:
clk state count X Y 3X Z
0 idle x xxxxxxxx xxxxxxxx xxxxxxxxxx xxxxxxxxxxxxxxxx
1 setup x xxxxxxxx xxxxxxxx xxxxxxxxxx xxxxxxxxxxxxxxxx
2 gen3x 0 10000111 01110011 xxxxxxxxxx 0000000000000000
3 active 0 10000111 01110011 0110010101 0000000000000000
4 active 2 10000111 00011100 0110010101 0110010101000000
5 active 4 10000111 00000111 0110010101 0001100101010000
6 active 6 10000111 00000001 0110010101 0110101110010100
7 done 6 10000111 00000000 0110010101 0011110010100101
Exercise 13.16
A recongurable CS/CR adder is shown in Figure 13.18. When the control signal c = 0, the
FA's input comes from the external input, and the network implements the CSA. When c = 1, the
carry out bits of each FA is connected to one of the inputs of the neighboring module, creating
the carry ripple chain required to reduce the carry vector and sum vector. Only the sum output
of the FAs presents the addition result in this case. The delay of the recongurable adder has one
multiplexer delay longer than the simple CS adder.
The critical path of the multiplier is:
T = Tadd + TRsetup + TRprop
where Tadd is the delay of the adder (CS or CR), TRsetup and TRprop are the setup and propagation
delays of the register (Z ). The number of cycles required for multiplication is n + 1.
Assuming that the multiplexer delay (tmux ) is similar to the delay of the register (treg ), the
number of cycles for nal addition using the recongurable adder would be:
n(tFA + tmux ) n cycles
tFA + tmux + treg
giving a total of 2n +1 cycles for the multiplier using CSA. However, the cycle time of the multiplier
using CRA is ntFA + treg , while the cycle time for the multiplier using CSA is only tFA + tmux + treg .
Thus
TCRA = (n + 1)(ntFA + treg )
TCSA = (2n + 1)(tFA + tmux + treg ) = (2n + 1)(tFA + 2treg )
and it is not dicult to see that the CSA implementation is faster than the CRA implementation
for even small values of n.
A modied controller to operate with the recongurable adder is presented next:
ENTITY multctrl IS
GENERIC(n: NATURAL := 16;
-- number of bits
m: NATURAL := 16);
-- number of clock cycles for ****
-- conversion (m less equal n)****
PORT (strt : IN BIT; -- control input
ldX,ldY,ldZ: OUT BIT; -- control signals
shY, clrZ : OUT BIT; -- control signals
CRA_ctr : OUT BIT; -- control signal ****
done : OUT BIT; -- control output
clk : IN BIT);
END multctrl;
ARCHITECTURE behavioral OF multctrl IS

TYPE stateT IS (idle,setup,active,convert,store); -- ****
SIGNAL state : stateT:= idle;
SIGNAL count : NATURAL RANGE 0 TO n-1;
BEGIN
PROCESS (clk) -- transition function
BEGIN
IF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN idle => IF (strt = '1') THEN state <= setup;
ELSE state <= idle ;
END IF;
WHEN setup => state <= active; count <= 0;
WHEN convert=> IF (count = m-1) THEN -- ****
count <= 0; state <= store; -- ****
ELSE -- ****
count <= count+1; state <= store; -- ****
END IF; -- ****
WHEN store => state <= idle; -- ****
END CASE;
END IF;
END PROCESS;
PROCESS (state,count) -- output function

VARIABLE controls: Bit_Vector(6 DOWNTO 0); -- modified ****
-- code = (CRA_ctr,done,ldX,ldY,ldZ,shY,clrZ)
BEGIN
CASE state IS
WHEN idle => controls := "0100000"; -- ****
WHEN setup => controls := "0011001"; -- ****
WHEN active => controls := "0000110"; -- ****
WHEN convert=> controls := "1000000"; -- ****
WHEN store => controls := "1000100"; -- ****
END CASE;
done <= controls(5);
CRA_ctr <= controls(6); -- ****
ldX <= controls(4); ldY <= controls(3); ldZ <= controls(2);
shY <= controls(1); clrZ<= controls(0);
END PROCESS;
END behavioral;
Lines marked with four asterisks were modied or inserted in the original VHDL code for the
multiplier control section (as shown in the text). A new control signal CRA ctr was included in the
controller interface. This signal is 1 when we want the carry bit to propagate on the adder. Two
other states were also included: convert and store. During the convert state, CRA ctr is activated
for a given number of cycles m n (m is dened based on the delay of the carry propagation
through the adder when the carry ripples). In the convert state, there is no shift in the Y register,
and no load on the Z register. Once the controller waited enough for the carry to propagate, it
moves to state store, where the ldZ control signal is activated to store the non-redundant addition
result into the Z register. The Z register for a CS representation of the partial product is composed
of two sub-registers: PS (sum vector) and C (carry vector). The non-redundant result will be
available on the PS register only.
a b c
A B
Comparator
AB
0 1 0 1
MUX MUX
a b
Part (a)
16 temp count
0 1
Decrementer MUX
1
15
NOT temp
least significant
bit 15
AND
c count-1=1
Part (b)
a b
b a
+ d
0 1 0 1
c c
MUX MUX
c d
0 1 0 1
MUX MUX
c
d
c d
Part (c)
Figure 13.9: Networks for Exercise 13.9

start N<>0
(a)
start C=1 N=0
1 2 3 4
C=0
start
(b) start MP_0<>0

0 1 2 3
MP_0=0
end
end 4
5
start
(c)
start
0 1 2 3
done
done 4
6 5
Figure 13.10: State diagrams for Exercise 13.10
odd(X)/X=5X+1,
I=I-1
/X=N,
I=3 I>0/
0 1 2 I=0/
odd(X)/X=X/2,
I=I-1
Figure 13.11: State Diagram for the system in Exercise 13.11

0/ldA 1/
A_7=1/
c_out=1/ldC,
clrB A_7=0
c_out=0/
3/ldB 2/
/p13_13/x 01101000 01001001 10010111 01101001

/p13_13/clk
/p13_13/y 00000000
/p13_13/a 01101000 01001001 10010111 01101001
/p13_13/b 00000000 01101000 10110001 00000000
/p13_13/c 00000000 10110001
/p13_13/state 0 1 2 3 0 1 2 3 0 1 0 1 2 0 1 2
/p13_13/c_out
/p13_13/adder_out 001101000 010110001 101001000 100011010 001101001
0 500 1 us 1500
Entity:p13_13 Architecture:arch Date: Mon Nov 22 16:45:36 PST 1999 Row: 1 Page: 1
Figure 13.13: Trace of execution - Exercise 13.13

ldX xin ldY yin ldZ

n n xin yin
X Y Shift Reg. Z Reg.

Reg. ldX
xreg_out n shY clrZ
2n zout ldY
y_0
AND gates shY Data
n Control ldZ
and_out n+1 n-1
clrZ
Path
Complement ls bit is last_bit
duplicate discarded
compl_out ms bit
last_bit n+1
clk start zout
last_bit
Adder done_out
n
(a) Data path (b) system’s block diagram
Figure 13.14: Architecture of the two's complement multiplier - Exercise 13.14
/multipliertc/start
/multipliertc/xin 1001
/multipliertc/yin 1101
/multipliertc/clk
/multipliertc/zout UUUUUUUU 00000000 11001000 11100100 10111010 00010101
/multipliertc/done_out
/multipliertc/state idle setup active done idle
/multipliertc/x UUUU 1001
/multipliertc/y UUUU 1101
/multipliertc/z UUUUUUUU 00000000 11001000 11100100 10111010 00010101
0 200 400 600 800
Entity:multipliertc Architecture:behav Date: Sun Nov 21 20:30:24 PST 1999 Row: 1 Page: 1
Figure 13.15: Trace of execution of a 4-bit Two's complement multiplier - Exercise 13.14
ldX xin ldY yin ldZ

n n xin yin
Right 2-Shift Z Reg.
X Reg. Y
Reg. ldX
xreg_out n shY clrZ ldY
2n
shY Data
Reg. 00....0 2 Control ldZ Path
ld3X n+2 0 0 00 n+2 gen3X n-2
n clrZ
0 0 00
3 2 1 0 2 last_bit
MUX A
1 0 gen3X A
n+2 MUX
n+2 gen3X
clk start zout
Adder 0
n+2
(b) system’s block diagram
(a) Data path
Figure 13.16: Block Diagram for the Data path of the radix-4 multiplier
/radix4_multiplier/start
/radix4_multiplier/xin 262
/radix4_multiplier/yin 330
/radix4_multiplier/clk
/radix4_multiplier/zout XXXXXX 000000 054400 041300 113060
/radix4_multiplier/done_out
/radix4_multiplier/state idle setup gen3x active done
/radix4_multiplier/x XXX 262
/radix4_multiplier/y XXX 330
/radix4_multiplier/z XXXXXX 000000 054400 041300 113060
/radix4_multiplier/xxx XXXX 1026
0 200 400 600 800
Entity:radix4_multiplier Architecture:behav Date: Sun Nov 21 20:24:21 PST 1999 Row: 1 Page: 1
Figure 13.17: Trace of execution - 8-bit radix-4 multiplier - Exercise 13.15
c c c c
FA FA FA FA
Figure 13.18: Recongurable CS/CR adder

289
Chapter 14
Exercise 14.1 The design of the 2-read/1-write register le can be implemented with registers
with 2 tristate outputs (A and B ), as shown in Figure 14.1. We call these registers: RF Registers.
Besides the two tristate outputs, they have one input din, a write enable input EWi, and two
\enable output" inputs: EOA and EOB to control each of the register tristate outputs. The
design of this component based on a conventional register and tristate buers is also shown. The
interconnection of all the A outputs of the RF registers forms the RBUSA (read bus A). Similarly
for the B outputs. All the RF register inputs are also interconnected, forming the write bus WBUS.
The binary decoders are used to generate the control signals for writing and reading the register
le.
IN
WBUS
8 8 8 RF Reg.
din din din
EW0 EW1 EW15 EW LD din
RF RF RF REG.
CLK
Reg Reg Reg
EOA0 EOA1 EOA15
0 1 15
EOB0 A B EOB1 EOB15
8 8 RBUS B
RBUS A EOA
clock EOB
A B
EW0 EOA0 EOB0
4 EW1 4 EOA1 4 EOB1

WR Binary RA Binary RB Binary
Dec Dec Dec
EW15 EOA15 EOB15
8
IN
4 WR
4 RA Register
4 RB File
A B
8 8
Figure 14.1: 2-read/1-write register le

Exercise 14.2 The correct equation for this exercise is

T = C1((j i) mod 2n) + C2
(a) computation sequence for READ/WRITE operations
We use VHDL to describe the system operation. The READ/WRITE is executed at a position
that is ready for access, pointed by the Current Access Pointer (P). This pointer stays static when
no access is requested. Either READ or WRITE requests must remain asserted while the operation
is in progress. After the operation is performed, an ACK signal is issued and the control block
waits for the READ/WRITE request to be removed before another memory cycle can start. When
the READ/WRITE input is activated, the given address (A) is compared with P and the shift is
activated while P 6= A. The system interface is shown in Figure 14.2.
data_in
n
Address
CLK
Rd SAM
ACK
Wr
data_out
m
Figure 14.2: SAM block diagram

The VHDL description for SAM memory system using a circular shift register and a counter
follows.
-- VHDL code for SAM - Sequential Access Memory - Exercise 14.2
LIBRARY ieee;
PACKAGE sam_pkg IS
CONSTANT N: NATURAL := 4; -- number of address bits
CONSTANT M: NATURAL := 4; -- number of bits per word
SUBTYPE word is BIT_VECTOR (M-1 DOWNTO 0);
TYPE mem_array IS ARRAY (2**N-1 DOWNTO 0) OF word;
SUBTYPE addressT IS NATURAL RANGE 0 TO 2**N-1;
END sam_pkg;
USE work.sam_pkg.ALL;
ENTITY sam IS
PORT ( data_in: IN word;
address: IN addressT;
Rd,Wr: IN BIT;
CLK: IN BIT;
data_out: OUT word;
ack: OUT BIT);
END sam;
ARCHITECTURE high_level OF sam IS

SIGNAL shift, ready: BIT;
SIGNAL DATA: mem_array;
SIGNAL access_addr: addressT;
BEGIN
-- This process controls the data portion of the memory.
-- when the shift input is activated, the access pointer
-- is moved to the required address, one position at a time.
-- the ready signal indicates that the required position
-- was reached. This is the behavioral description of a
-- circular shift register.
DATA_REG: PROCESS (CLK,shift,address,access_addr)
VARIABLE same_adr: BIT;
BEGIN
IF (CLK'event and (CLK='1') and (shift='1'))
THEN -- shift the data one position
IF (same_adr='0')
THEN IF (access_addr=2**N-1)
THEN access_addr<= 0;
ELSE access_addr<= access_addr+1;
END IF;
END IF;
END IF;
IF (access_addr /= address)
THEN same_adr := '0';
ELSE same_adr := '1';
END IF;
ready <= same_adr;
END PROCESS;
data_out <= data(access_addr);
-- This process controls the access to the data portion
-- The read/write controls are monitored and the ack signal
-- is activated to indicate that the operation was completed
CTR: PROCESS (CLK,Rd,Wr,ready)
BEGIN
IF (Rd'event OR Wr'event OR ready'event) THEN
IF (Rd='1' OR Wr='1')
THEN
IF (ready='0')
THEN shift <='1';
ELSE shift <='0';
END IF;
ELSE
ack <= '0';shift <= '0';
END IF;
END IF;
IF (CLK'event and (CLK='1') )
THEN
IF ((Wr='1') and (ready='1'))
THEN data(address) <= data_in;ack <= '1' after 2 ns;
ELSE
IF ((Rd='1') and (ready='1'))
THEN ack<='1' after 2 ns;
ELSE ack<='0' after 2 ns;
END IF;
END IF;
END IF;
END PROCESS;
END high_level;
A timing diagram of the system operation is shown in Figure 14.3.
/sam/data_in 1101 0110
/sam/address 4 6 8 4
/sam/rd
/sam/wr
/sam/clk
/sam/data_out 0000 1101 0000 0110 0000 1101
/sam/ack
/sam/shift
/sam/ready
/sam/data
/sam/access_adr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
0 500 1 us 1500 2 us 2500 3 us

Entity:sam Architecture:high_level Date: Tue Oct 19 15:31:12 1999 Page 1
Figure 14.3: Timing
(b) The data path that supports the computation described in the VHDL code is shown in
Figure 14.4. The following table list the control points and conditions for the data path:
data_in
shift m
SHIFT data_in
Circular Shift Reg. CNT Binary

load_data LOAD CLK Counter address
CLK data_out n n
access_addr
m
A B
data_out Compare
A=B
ready
data_in
m m m m m
0 m 0 m 0 m 0 m 0
m m m m m
1 1 1 1
1 m
Reg. Reg. Reg. Reg. m
2
m
3
Reg.
shift
CLK
data_out
load_data
circular shift register (5 positions)
Figure 14.4: Data section for SAM computation
Signal Description
load data control signal - loads the data in into the current (accessible)
position of the circular shift register.
shift control signal - forces the circular register to shift the infor-
mation while the current address (access addr) is dierent
than the requested address.
data in data input and output for the circular shift register.
data out
ready condition signal - when 1 indicates that the requested position
in the circular shift register was reached.
Exercise 14.3
(a)
2n 1
X
T= (dC1 + C2 )p(d)
d=0
where p(d) is the probability of distance d. As distances are uniformly distributed, we get:
p(d) = 21n
Based on the previous equations we obtain:
n 1
2X n
T = (dC1 + C2 ) 21n = 21n 2n C2 + C1 22 (2n 1)
d=0
n
T = C2 + C1(22 1)
(b) when (
p(d) = 1 if d = 1 (14:1)
0 otherwise
the average time becomes:
2n 1
X
T= (dC1 + C2)p(d) = C1 + C2
d=0
(c) Block access. Time to access a block of k words is kC1 + C2 (when assuming pipelined
execution C2 is absorbed in intermediate steps). The average time to go from block position i to
block at position j , and access k consecutive positions is given as:
2n 1
X
T Block = (dC1 + (k 1)C1 + C2)p(d)
d=0
n
= 21n 22 (2n 1)C1 + 2n ((k 1)C1 + C2)
n
= (2 1) C1 + (k 1)C1 + C2
2
(2
1 n 1)
= k 2 C 1 + (k 1)C 1 + C 2
Exercise 14.4
Direct-access memory: address A = (Ar ; As ), where Ar = A=M is a random access and As =
A mod M is a sequential address.
(a) design of direct-access memory with 16K words (14-bit address). Each word has 8 bits.
The random address selects one among 210 = 1K sequential memory blocks of M = 16 words. A
block diagram of the circuit is shown in Figure 14.5. Each SAM module is designed as described
in Exercise 14.2. All SAM modules receive the same address, read, clock, and data input signals.
Depending on Ar , one of the modules are selected by the signal selm. When a module is selected, a
write or read cycle may be performed. When reading, all modules will start accessing the requested
address position, but only the module that is selected will generate the acknowledgement signal
4
As addr
data_in 8 data 8
in 16-word
Write Read SAM
Rd
Wrm0 M0 selm0
selm0 Wr
ack
clock
4 selm0
As addr
data_in 8 data
in 16-word 8 8 data_out
Read Rd SAM
Wrm1 Wr M1 selm1
selm1 ack
clock
selm1
4
As addr
data_in 8 selm0
data 8
in 16-word 10
selm1
Read SAM Ar Binary
Rd
Wrm15 M1023 selm15 decoder
selm1023 Wr
ack selm1023
clock
14 4 selm1023 implemented using tree

A As or coincident decoding
10 ACK
Ar
Figure 14.5: Direct-access Memory block diagram
(ACK) and the output data. When writing, only the selected module will search the correct address
position and perform the storage of the data input.
(b) average access time. The time to access a position from the direct-access memory will
depend on the time to access the SAM. The access time for a SAM with 1K words is given as:
T = C1((j i) mod 24) + C2
where i is the current address, j is the requested address, C1 and C2 are implementation-dependent
constants.
case (a) distance between addresses of consecutive accesses is uniformly distributed:
X
24 1
T= (dC1 + C2)p(d)
d=0
where p(d) is the probability of distance d. As distances are uniformly distributed, we get:
p(d) = 214
Based on the previous equations we obtain:

!
X
24 1
1 1 2 4
T = (dC1 + C2 ) 24 = 24 2 C2 + C1 2 (2 1)
4 4
d=0
T = C2 + C1 (22 1)
4
case (b) when the distance between addresses is given by the function:
(
d=1
p(d) = 10 ifotherwise (14:2)
the average time becomes:

X
24 1
T= (dC1 + C2)p(d) = C1 + C2
d=0
case (c) Block access. Time to access a block of k words is kC1 + C2 (when assuming pipelined
execution C2 is absorbed in intermediate steps). The average time to go from block position
i to block at position j , and access k consecutive positions is given as:
X
24 1
T Block = (dC1 + (k 1)C1 + C2)p(d)
d=0" #
1 2 4
= 24 2 (2 1)C1 + 2 ((k 1)C1 + C2)
4 4
= (2 2 1) C1 + (k 1)C1 + C2
4
" 4 #
= 1 (2 1) C1 + (k 1)C1 + C2
k 2
Exercise 14.5
R3 <= R1; LP1 <= R2; RP1 <= R1; R1 <= P1;
LP2 <= R3; RP2 <= R4; R4 <= P2;
R2 <= R4; LP1 <= R2; RP1 <= R1; R1 <= P1;
LP2 <= R2; RP2 <= R3; R2 <= P2
The datapath for this computation is shown in Figure 14.6.

Exercise 14.6
R{1,2} <= X -- load R1, R2 with X

R6 <= R{1,2,3,4,5,7} -- load R6 with any register {1,2,3,4,5,7}
R7 <= OP{src1, R6} -- load R7 with the OP result
R{3,4,5} <= R7 -- load R3, R4, or R5 with register R7
R1 R2 R3 R4
P1 P2
Figure 14.6: Datapath for Exercise 14.5
S A(7)=0 A=A+1
0 1 2 3 4
B=X A=A+B A=A
A=Y
A(7)=1
5 6 C=A+B
B=B+1
Figure 14.7: State Diagram for System in Exercise 14.7
where src1 2 fR1; R2; R3; R4; R5; R7g and OP = fadd; sub; incl; AND; XORg.
Exercise 14.7 A state diagram for the control subsystem is shown in Figure 14.7.
(a) execution of the computation for X = 00101110 and Y = 11100010.
state A B C
0/1 xxxxxxxx xxxxxxxx xxxxxxxx
2 11100010 00101110 xxxxxxxx
5 00010000 00101110 xxxxxxxx
6 00010000 00101111 xxxxxxxx
0 00010000 00101111 00111111
Observe that the value of A(7) tested in state 2, corresponds to the present value of the variable
A (1110010), not the value that is going to be valid when the machine leaves state 2 (00010000).
(b) The data section that is required by the system is shown in Figure 14.8.
(c) The state diagram that describes the control behavior and the control signals activation is
shown in Figure 14.9. For convenience, we replace the s input by start.
The implementation of the control circuit using a counter, multiplexer, a decoder, and gates is
Y X
8 8
selA 0 1 selB 0 1
ldA ldB
clk Reg A clk Reg B
A(7)
8 8
A B 2
Operator OP
8
ldC
clk Reg C OP={add,incrA,incrB,notA}
8
Figure 14.8: Datapath for Exercise 14.7
start’
start A(7)=0
0 1 2 3 4
OP={notA} OP={incrA}
ldA OP={+}
ldA ldA
ldB ldA
A(7)=1
5 6
ldB ldC
OP={incrB} OP={+}
Figure 14.9: State diagram for the control section - Exercise 14.7
The parallel load of the counter is dened as:
8
>
< 0 if S0 or S6
I = > 5 if S2 (14:3)
: 6 if S4
A table that represents these values in a table is:
state code I
S0 000 000
S1 001 - - -
S2 010 101
S3 011 - - -
S4 100 110
S5 101 - - -
S6 110 000
S7 111 - - -
Minimal expressions are obtained with the following Kmaps:
S2 S1’ S2’ S1
S1
S2 ldA
S3
S4
S5 ldB
start 0
S6 ldC
1 1
not A(7) 2 S2 {+}
1 3 MUX cnt I2 I1 I0 S6
0 4 ld counter
1 5 CK Q2 Q1 Q0 S3 notA
0 6 S4 incrA
d.c. 7 S5 incrB
decoder
01234567
S0 ..... S7
Figure 14.10: Control network for Exercise 14.7

s0 s0 s0

0 -
- 1 0 - - 0 0 -
- 1

s2
1 - - 0

s2
1 - - 0 s2 0 - - 0
I2: s1 I1: s1 I0 : s1
I2 = s02 s1 + s2s01 = s2 s1
I1 = s2 s01
I0 = s02 s1
The counter enable input is activated according to the expression:
CNT = start:S0 + S1 + S2 A(7)0 + S3 + S5
and
LD = CNT 0
Another implementation of the control system using one FF per state approach is shown in
Figure 14.11.
start’
S1
S2 ldA
S3
CK S4
S0
S5 ldB
start S6 ldC
S2 {+}
S6
CK
S1
S3 notA
CK S4 incrA
S2
A(7)’ A(7) S5 incrB
CK CK
S3 S5
CK
S4
CK
S6
Figure 14.11: One- ip- op-per-state implementation of control system - Exercise 14.7
Exercise 14.8 The data section of the system is shown in Figure 14.12.
A state diagram for the control part is shown in Figure 14.13. In this diagram we used the
signal names presented in the data section block diagram.
The implementation of the control section using PLA is based on the following expressions:
ldmax = newmax:delimiter0 + S1
ldmin = newmin:delimiter0 + S1
end = delimiter:S0
ecnt = S0:delimiter0 + S1
nextstate = S0:delimiter = end
where S0 corresponds to state = 0, and S1 corresponds to state = 1. The network for this implemen-
tation of the control section is shown in Figure 14.14. The one- ip- op-per-state implementation
is given in Figure 14.15.
X
7
127
7
A B A B A B
Comparator Comparator Comparator
A<B A<B A=B
newmax newmin 0
X delimiter 6
ldmax ldmin end LD Binary

CLK CLK ecnt Cnt
Reg. Reg. CLK Counter
end end end

CLK Reg. CLK Reg. CLK Reg.
7 7 6
MAX MIN COUNT
Figure 14.12: Data Section of system for Exercise 14.8
newmin and delimiter’/

ldmin,ecnt delimiter/end
newmax and delimiter’/

S0 S1
ldmax, ecnt
/ldmax,ldmin,ecnt
newmax’ and newmin’ and delimiter’/

ecnt
Figure 14.13: State Diagram for the Control Section - Exercise 14.8
newmax newmin delimiter state
state
D Q
ldmax ldmin ecnt end
Figure 14.14: Control section implementation using PLA - Exercise 14.8
Exercise 14.9 The datapath for the system is shown in Figure 14.16.
The state diagram that describes the control section is shown in Figure 14.17. We consider that
the system has a start input that indicates when another calculation must begin.
(a) implementation of the control section using D-type FFs. The states are encoded as:
state y1 y0
S0 00
S1 01
S2 10
From these state codes we determine the binary transition table as follows:
ecnt
delimiter
D Q
S0
CK
end
D Q newmax ldmax
S1
CK
newmin ldmin
delimiter
Figure 14.15: Control section implementation using one--per-state approach - Exercise 14.8
C
Reg, MUL
CK
root**2
eps
DIV DIV
C
-1 Reg,
CK
ADD ADD
1.0
ABS
A MUX
A B
B Compare
Reg, A<B
CK serror
ROOT
Figure 14.16: Datapath for the system in Exercise 14.9
start’ activates serror’

A,B,C
start
S0 S1 S2 activates
B
serror
Figure 14.17: State Diagram for control section - Exercise 14.9
Input (start/serror)
y1 y0 00 01 11 10
00 00,000 00,000 01,000 01,000
01 10,111 10,111 10,111 10,111
10 10,010 00,010 00,010 10,010
NS(Y1 Y0 ; ABC )
These are minimal expressions for the next state and output signals:
Y1 = y1 serror0 + y0
Y0 = y10 y00 start
A = y0 = C
B = y1 + y0
The gate network for the control section is shown in Figure 14.18.
(b) implementation of the control section using PLA. For this case we use the same expressions
obtained for solution (a). The implementation is presented in Figure 14.19.
Y1 Y0 y0 A,C
y1 D Q
D Q
1 start 0
serror y1’ y0’
CK CK
Figure 14.18: Gate Network for control section - Exercise 14.9
y1 y0 serror start
y0
D Q
Y1 Y0 A,C B CK
y1
D Q
CK
Figure 14.19: PLA implementation of control section - Exercise 14.9
Exercise 14.10
(a) two counters and one shift register. With these components we have a better datapath for
testing the bit value (using the shift register), counting the number of bits already tested in the
input vector and counting the number of ones in the input vector (counters), when compared the
the original data section. The data section of the system is presented in Figure 14.20(a). The
control sequence for the control section is described in VHDL as follows:
PROCESS (clk)
TYPE stateT IS (idle,loadval,count);
VARIABLE state: stateT := idle;
BEGIN
IF (clk'event and clk='1') THEN
CASE state IS
WHEN idle => load <= '0'; shift <= '0';
IF (start='0') THEN state := loadval;
ELSE state := idle;
END IF;
WHEN loadval => load <= '1'; state := count;
X
8
load
shift Shift Reg.
clk 0
clear 4
cnt
ld Counter.
clk
4 num_ones
0
clear
cnt
ld Counter.
clk
end
(MSBit)
Figure 14.20: Data section for Exercise 14.10a
WHEN count => load <= '0'; shift <= '1';

IF (end='1') THEN state := idle;
ELSE state := count;
END IF;
END CASE;
END IF;
END PROCESS;
The implementation of a microprogrammed control circuit is shown in Figure 14.21. Since the
datapath is so especialized, the control circuit becomes very simple. There is no need for two
instruction formats. The instruction format and the sequence of instructions in the microprogram
is as follows:
address shift load cond branch address
0 0 0 01 0
1 0 1 00 {
2 1 0 10 2
3 0 0 00 0
The COND eld (cond) uses the codes: 00 for \no condition", 01 for start = 0, and 10 for
end = 0. It would be better to use a simple sequential circuit to generate the control signals based
on the data part conditions.
(b) Using one counter and a shift register. Dierently from part (a), this design needs the
function provided by the original datapath. The shift register is used the same way as in part (a).
The counter can be used to count the number of ones in the input X , or to control the number of
bits already tested. In the rst case, we need to use the ALU to keep track of the number of bits
tested. In the second approach, the ALU is used to test the end condition. We are going to use
the rst solution. The data path for the system is shown in Figure 14.22 together with the state
diagram for the control subsystem.
+1
0
Adr Ctr. shift
Mux ROM
Reg. Reg. load
1
0 0
Branch address
start’ 1
Mux
end’ 2
d.c. 3
cond
Figure 14.21: Microcontroller network - Exercise 14.10a
The approach requires some modications on the instruction format presented in example 14.3
of the text:
need to add one extra condition bit to test the bitval and end values. The conditions are:
start - 00, bitval - 01, end - 10, and unconditional branch - 11.
need to add the two control bits load and shift for the shift register and counter.
The following is the micro-program for the unit:
Adr Mode ALU-op FLD ldRF ldR sel s d r d load shift Note
A B C in out R in
0 0 sub=01 0 0 0 1 - 0 0 - - 0 0 R0 0
1 1 (start,0)=000 1
2 0 add=00 0 0 7 1 - 0 0 - - 1 0 R7 0
3 1 (bitval,0)=010 5
4 0 inc=11 7 0 7 1 - 0 0 - - 0 0
5 0 nop x x x 0 - 0 0 - - 0 1
6 1 (end,0)=100 3
7 0 add=00 7 0 7 1 - 1 0 - - 0 0 Rout R7
8 1 (unconditional,0)=110 1
(c) just one counter. This situation forces the shifting of bits in the ALU. The counter is used
to monitor the number of bits already scanned. The modications on the original program are:
merge instructions at addresses 4 and 2 (remove R3 <= 1)
change instruction at address 8 to test the end signal (coming from the counter)
the instruction format must include a counter increment signal, which is activated in instruc-
tion at address 5.
Exercise 14.11
(a) R0 maxfR0; R1; : : :; R7g, R8 and R9 don't need to be preserved, fR1; R2; : : :; R7g
should be preserved.
X
8
load start’
shift Shift Reg.
Data portion CLK bitval=1/ R7=R7+1,
start/ load, test1
of example idle shift
R7=0
14.3 bitval bitval=0/
0 shift
4 end=0
cnt
ld Counter end=1/ Rout=R7 test2
CLK
4
end
(msbit)
(a) data section (b) state diagram for control section behavior
Figure 14.22: Datapath and control sequence for the system Exercise 14.10b
Considering that the values are already in the registers, the control signals S; L1; : : :; and L7
will have a value zero all the time. Since there is no \compare" operation, the comparison between
two values x and y must be made by add/sub operation. When the operation x y is executed,
the carry out bit (cy ) is 0 only for the case y x.
The RTL description of the computation is as follows:
R9 <- R0
R8 <- R0 - R0 -- R8=0
R0 <- R1 - R9
if cy=0 R9 <- R1
R0 <- R2 - R9
if cy=0 R9 <- R2
.
.
.
R0 <- R7 - R9
if cy=0 R9 <- R7
R0 <- R9 + R8 -- R0=R9
If the registers were mapped to an array, we would be able to index each register, and this way
use the FOR ... LOOP structure.
(b) micro-instructions (horizontal/ implicit addressing)
We use a two-format instruction. The condition eld is dened as: 000-add, 001-sub, 010-incl,
011-xor, 100-and. The instruction formats and the instruction sequence is shown in the next table.
Since the values of S and L1 to L7 are always zero, we don't show these signals in the microcode.
Since there is only one condition to be tested, basically, the (cy; 0) eld could be eliminated. We
kept the condition in the instruction to keep the format similar to the one shown in the text.
addr Mode source Register OP destination register

0 E0 E1 E2 E3 E4 E5 E6 E7 E8 L0 L8 L9
1 (condition,value) address
0 0 1 0 0 0 0 0 0 0 0 --- 0 0 1
1 0 1 0 0 0 0 0 0 0 0 001 0 1 0
2 0 0 1 0 0 0 0 0 0 0 001 1 0 0
3 1 (cy,0) 5
4 0 0 1 0 0 0 0 0 0 0 --- 0 0 1
5 0 0 0 1 0 0 0 0 0 0 001 1 0 0
6 1 (cy,0) 8
7 0 0 0 1 0 0 0 0 0 0 --- 0 0 1
8 0 0 0 0 1 0 0 0 0 0 001 1 0 0
9 1 (cy,0) 11
10 0 0 0 0 1 0 0 0 0 0 --- 0 0 1
11 0 0 0 0 0 1 0 0 0 0 001 1 0 0
12 1 (cy,0) 14
13 0 0 0 0 0 1 0 0 0 0 --- 0 0 1
14 0 0 0 0 0 0 1 0 0 0 001 1 0 0
15 1 (cy,0) 17
16 0 0 0 0 0 0 1 0 0 0 --- 0 0 1
17 0 0 0 0 0 0 0 1 0 0 001 1 0 0
18 1 (cy,0) 20
19 0 0 0 0 0 0 0 1 0 0 --- 0 0 1
20 0 0 0 0 0 0 0 0 1 0 001 1 0 0
21 1 (cy,0) 23
22 0 0 0 0 0 0 0 0 1 0 --- 0 0 1
23 0 0 0 0 0 0 0 0 0 1 000 1 0 0
Exercise 14.12 Bubblesort algorithm

The block diagram for the datapath and the control circuit is shown in Figure 14.23. Shaded
boxes represent registers. These are some of the components in the data section, and their function
in the computation of the sorting algorithm:
Register AD is used to store the previous address used to access the RAM. It is needed to
perform the switch operation between two memory addresses.
Registers A and B are used to store the information in the two positions being switched. Reg.
A, in particular, stores one of the elements, while the comparison is made against another
element in the RAM to detect if the element in position cnt1 is less than the element in
position cnt1-1 (in this case the two elements are switched).
The Up Counter starts from position 0, and scan the elements in the RAM, until it reaches
the value of the Down Counter. This condition is indicated by the condition equal = 1.
The Down Counter starts from the end of the list of elements, remains xed during a scan
done with the up counter, and is decremented after each scan. It goes from the end to the
top of the list of elements. The last value for this counter is 1.
The state diagram of the control subsystem that operates on the proposed data path in order
to implement the bubblesort algorithm is shown in Figure 14.24.
0
ld1 8
cnt1
up 8
0 8
counter AD ADR 8
clk dout
1
clk RAM lda ldb
n-1 ea Reg A eb Reg B
ld2 8 s din
ldad
EN
cnt2
down 8
equal ew
counter Compare 8
clk
A B
upcountone compare
Equals1 A<B
test
control
ROM signals
adr. reg,
branch cond
1
0 sequence
0 0
1 equal
2
3 test
upcountone
Figure 14.23: Block diagram for Exercise 14.12
The microprogram that implements the operations shown in the state diagram is stored in the
ROM of a microcontroller, and is given in the following table. The explicit instruction format has
both the branch (used when the condition tested is true) and the regular sequence address. The
test conditions are represented by the codes: 00 - no branch, 01 - equal = 1, 10 - test = 1, 11 -
upcountone = 1.
adr. ld1 cnt1 ld2 cnt2 ldad lda ea ldb eb ew s cond branch seq.
0 0 0 1 0 0 0 0 0 0 0 0 00 { 1
1 1 0 0 0 0 0 0 0 0 0 0 00 { 2
2 0 1 0 0 1 1 0 0 0 0 0 00 { 3
3 0 0 0 0 0 0 1 1 0 0 0 10 6 4
4 0 0 0 0 0 0 1 0 0 1 0 00 { 5
5 0 0 0 0 0 0 0 0 1 1 1 00 { 6
6 0 0 0 0 0 0 0 0 0 0 0 01 7 2
7 0 0 0 1 0 0 0 0 0 0 0 11 stop 1
/ld2 /ld1
/ldad,cnt1,lda
test’/
test/ea,ldb
upcountone’/cnt2
/ew,ea
/ew,eb,s
equal’/
upcountone equal/
Figure 14.24: State diagram for the control section - Exercise 14.12
Exercise 14.13 FIFO implementation.

Based on the VHDL description of the FIFO operation, the data section must be able to store
an input to any of the queue positions (following a given insertion order). This feature can be
obtained with a broadcast of the input signal to all memory elements, and the control over the
write enable signal of each element. Another required property is the ability to shift the information
one position when a FIFO element is read. The proposed data section is shown in Figure 14.25.
The shift signal is used in the read operation, to remove one element from the queue. The vector
of control signals (wn 1 ; :::; w1; w0) is used to select one of the registers that will receive the input
element during a write operation.
The control section for the FIFO receives the Rd and Wr signals from the FIFO interface and
generate the output signal Empty and Full, besides the internal control signals (wn 1 ; :::; w1; w0).
The network for the control section is shown in Figure 14.26. It corresponds to a bidirectional shift
register with parallel output and some additional control for the cases when the FIFO is empty or
full. Some aspects of the design are important:
1. a reset signal was introduced to initialize the state of the FIFO control section, making w0 = 1.
2. instead of having a reference to the position of the last inserted element, we opted to have a
reference to the next free position for writing (wi ).
3. when the FIFO is full (wn 1 ; :::; w1; w0) = (0; :::; 0; 0), and Full = 1.
X
16
0 0
16 16
0
16 16
0
16 16
Reg Reg Reg Z
1 1 1
n-1 1 0
LD LD LD
shift
clk
w1 w0
w
n-1
Figure 14.25: Data section for the FIFO memory - Exercise 14.13
4. the empty condition is true when w0 = 1.
Wr Full
w D Q Rd
n-1
FF dir=1 -> right shift
clk
Ir shift dir Il
reset
Bidirectional Shift Register
Rd clk
Empty shift Empty
reset
w
0
Wr
Full
wn-1 wn-2 wn-3 w1 w0
Figure 14.26: Control section for the FIFO memory - Exercise 14.13
Exercise 14.14 LIFO implementation.

Based on the VHDL description of the LIFO memory operation we should have a data path
where we could read/write from/to dierent memory positions. The description keeps the elements
on the position where they are written, and move the TOP of the stack after each PUSH or POP.
However, a simpler implementation would be possible if the data input access only one memory
element (TOP of the stack), and the data already stored in the memory were shifted to other
positions in the stack. The data section to accomplish these tasks is shown in Figure 14.27. It is
basically a bidirectional shift register where the input data is inserted in the rightmost position.
X
16
0 0
16 16
0
16 16
0
16 16
Reg Reg Reg Z
1 1 1
n-1 1 0
LD LD LD
dir
clk
shift
Figure 14.27: Data section for the LIFO memory - Exercise 14.14
The control section must generate the signals shift and dir to control the data section, based
on the LIFO memory control inputs Rd and Wr. It also must generate the status signals for Full
and Empty conditions. The network that implements the control section for the LIFO is shown
in Figure 14.28. Since there is no pointer required to the address the TOP of the stack, a counter
is used to monitor the number of elements in the stack. In order to have n elements in the stack,
a k = dlog2(n)e-bit counter is required. The shift and dir control signals are easily obtained from
the Wrlifo and Rdlifo signals. A clear signal is necessary to reset the counter before the LIFO is
used.
clear k=log2(n)
Wrlifo up down Rdlifo

up/down
0 ld
clk counter
k
0 n Wrlifo dir
Wr
shift
Rdlifo
A B A B
compare compare Rd
A=B A=B
Full
Empty
Figure 14.28: Control section for the LIFO memory - Exercise 14.14
313
Chapter 15
Exercise 15.1
Addr
Enable
5ns 30ns
Rd 10ns
50ns
Data
Rdy
t=0 t=65ns
Figure 15.1: Single memory read - Exercise 15.1
Rdy becomes active at time t = 55 ns. The enable signal may become low at time t = 65 ns.
For a sequence of read operations, one read may follow the other keeping enable = 1 and issuing
one Rd pulse for each new access. Addr may change after Rdy = 1, so the timing diagram presented
in Figure 15.2 is possible. The cycle time for this case is 55 ns and the number of memory accesses
per second is given as:
1 18:2 106 memory accesses/sec
55 10 9
Addr
5ns 30ns
Rd
50ns
Data
Rdy
t=0
Figure 15.2: Multiple read access - Exercise 15.1

Exercise 15.2 The format for the three instructions used in this exercise is shown in Figure 15.3.
31 25 20 15 10 0
add Opcode RT RA RB ----
31 25 20 15 0
ldw Opcode RT RA D
31 25 20 15 0
brn Opcode --- --- D
Figure 15.3: Instruction format - Exercise 15.2

add R5,R7,R9 | add RT,RA,RB
Add opcode = 010000
Using the instruction format shown in the Figure we obtain:
010000 00101 00111 01001 00000000000
ldw R7,1200(R8) | ldw RT,D(RA)
Ldw opcode = 100001
100001 00111 01000 0000010010110000
brn 1000 | brn D
Brn opcode = 110001
110001 00000 00000 0000001111101000
Exercise 15.3 Consider these registers' contents:

PC = 5321
R1 = 10
R5 = 1250
R7 = 110
for the execution of the following instructions:
(a) stw R5, 1300(R7) { store word { format: stw RS, D(RA), which performs the operation:
MEM(RA+D):=RS(31 downto 0). The eective address computed is:
RA + D = R7 + 1300 = 110 + 1300 = 1190
(b) brn 1250 { branch on negative { format: brn D, which performs the operation PC := PC +
D + 4, changing the program counter value to: PC := 5321 + 1250 + 4 = 6575.
(c) bri R7 { branch indirect { format: bri RA, which performs the operation PC := RA. The
number 110 is represented in two's complement using 32 bits. However the PC precision is
only 24 bits, thus the actual value stored in the PC is: 224 110.
Exercise 15.4 The sequence of branches to branch-on-negative a distance 220 from the present
instruction location is given as:
Address A: brn D
.
.
.
Address A'=A+D+4: br D
.
.
.
Address A''=A'+D+4: br D
.
.
.
After the instruction brn D, the PC value is adjusted to PC := PC + D +4. After the execution
of n branches with the same displacement value D, the PC value is:
PC := A + n(D + 4)
For this exercise it is required that the last PC value be A + 220, thus:
A + n(D + 4) = A + 220
D = 2 n 4n
20
Using the maximum positive value for D (signed integer using 16 bits), which is 215 1, it is
possible to calculate the number of branch instructions as n = 2215 = 25 = 32. As a result:
20
D = 2 32 2 = 32764
20 7
Thus, a set of 32 branch instructions with the same displacement D will result in the movement
of the program counter 220 locations from the address of the rst branch instruction. This solution
does not depend on the location A.
Exercise 15.5 Assembly code to add an array of 105 integers stored consecutively starting at
location 1000. The result is stored in location 2000.
-- R0
- pointer to the elements in the array
-- R1
- number of elements already read
-- R2
- accumulator
-- R3
- value to add in each program iteration
xor R0,R0,R0 -- R0=0
adi R1,R0,105 -- R1=105
xor R2,R2,R2 -- R2=0
A: ldw R4,1000(R0) -- load R4 with integer value located at R0+1000
add R2,R2,R4 -- add R4 to accumulator (R2)
adi R0,R0,4 -- adjust pointer to reference next integer
sbi R1,R1,1 -- decrement number of integers to be added
A+16: bnz -20 -- branch to location A if there are more integers
stw R2,1580(R0) -- store accumulator in location 2000
The value of the displacement (D1) for the bnz instruction was obtained using the relation:
A + 16 + 4 + D1 = A, which results in 20. The displacement (D2)for the stw instruction
was calculated using the information that R0 = 105 4 = 420, then to reach location 2000,
D2 = 2000 420 = 1580.
The binary code for this program is:
xor 011000 00000 00000 00000 00000000000
adi 010001 00001 00000 00000 00001101001
xor 011000 00010 00010 00010 00000000000
ldw 100001 00100 00000 00000 01111101000
add 010000 00010 00010 00100 00000000000
adi 010001 00000 00000 00000 00000000100
sbi 010011 00001 00001 00000 00000000001
bnz 110010 00000 00000 11111 11111101100
stw 100011 00010 00000 00000 11000101100
Exercise 15.6 Simulation of XMC instructions. Figures 15.4 and 15.5 shows the simulation results
of the instructions given in Exercise 15.2.
/computer/reset
/computer/clk
/computer/memaddr 000000 000004 000008
/computer/memlength
/computer/memrd
/computer/memwr
/computer/memenable
/computer/memrdy
/computer/memdata 00000000 40A74800 84E804B0
/computer/ioaddr XXX
/computer/iolength
/computer/iord
/computer/iowr
/computer/ioenable
/computer/iordy
/computer/iodata XXXXXXXX
/computer/status undef p_reset fetch execute fetch execute
/computer/u3/p2/ng
/computer/u3/p1/gpr/gpr(5) 00000000 000000A5
/computer/u3/p1/gpr/gpr(7) 00000000
/computer/u3/p1/gpr/gpr(8) 00000000 00000017
/computer/u3/p1/gpr/gpr(9) 00000000 000000A5
0 200 400
Entity:computer Architecture:structural Date: Tue Dec 21 18:38:17 PST 1999 Row: 1 Page: 1
Figure 15.4: Simulation of instructions using VHDL - 0-500 ns

The contents of the memory was initialized with the binary code for the three instructions, by
the following modication in the memory.vhd le:
VARIABLE Mem : MemArrayT
--******** memory contents, used for exercise 15.6
:= (-- program
-- add R5,R7,R9
3=>"01000000", 2=>"10100111", 1=>"01001000", 0=>"00000000",
-- ldw R7,1200(R8)
7=>"10000100", 6=>"11101000", 5=>"00000100", 4=>"10110000",
-- brn 1000
11=>"11000100", 10=>"00000000", 9=>"00000011", 8=>"11101000",
OTHERS => "00000000");
For the simulation the clock cycle time was set to 100ns to make it easier to read the memory
data information. Recall that a minimum cycle time of 17.5ns would be possible, based on the
/computer/reset
/computer/clk
/computer/memaddr 000008 0004C7 000008 00000C 0003F4 0003F8
/computer/memlength
/computer/memrd
/computer/memwr
/computer/memenable
/computer/memrdy
/computer/memdata 00000000 C40003E8 00000000
/computer/ioaddr XXX
/computer/iolength
/computer/iord
/computer/iowr
/computer/ioenable
/computer/iordy
/computer/iodata XXXXXXXX
/computer/status execute memop fetch execute fetch execute
/computer/u3/p2/ng
/computer/u3/p1/gpr/gpr(5) 000000A5
/computer/u3/p1/gpr/gpr(9) 000000A5
600 800 1 us
Entity:computer Architecture:structural Date: Tue Dec 21 18:39:12 PST 1999 Row: 1 Page: 1
Figure 15.5: Simulation of instructions using VHDL - 500-1000 ns
calculations done in the text (Example 15.1). The values in registers 8 and 9 were forced to
R(8) = (17)16 and R(9) = (A5)16. After the instruction add R5,R7,R9 is executed, the value in
R(5) becomes a copy of the R(9) (time 350ns). The next instruction: ldw R7,1200(R8), at address
4 access the location R8 + (4B 0)16 = (4C 7)16 to read the value that is stored in R7. The contents
of this memory location is zero, so there is no change in R7.
The instruction at location 8 (brn 1000) should test the condition for negative result (signal ng ),
which is zero, indicating that the last operation on the ALU resulted in a positive value. However,
the branch was taken, showing that there is a mistake in the processor's VHDL description. The
target address for the branch is correct: 03E 8+0008+0004 = 03F 4 (values in hexadecimal), where
the rst value is the displacement in the branch instruction (D), the second is the location of the
brn instruction, and the last value is the automatic increment of the PC value during the fetch
state.
Exercise 15.7 The new instruction ldwa automaticaly increments by 4 the index register used to
compute the eective address. Let us dene the instruction assembly as:
ldwa RT; D(RA)
Its execution results in RT (31 downto 0) := Mem(RA + D; 4); and RA := RA + 4.
The modication of the VHDL code given on page 453 of the text adds the following condition
to the Opcode test:
CASE Opcode IS
...
...
WHEN ``ldwa opcode'' => -- ldwa
Phase <= MemOp;
Status <= MemOp;
tMemAddr <= RA_data + D; -- mem. address
GPR(RA_addr) <= RA_data + 4; -- increment index register
WAIT until MemRdy='1';
WHEN ...
...
Exercise 15.8 Figure 15.10 in the text shows a 16MB memory. A 4 times bigger memory is asked
in this Exercise. Assuming that the 4MB modules are available (4 of these modules were used to
design the 16MB memory in the text), 16 of them are required for this memory design, as shown
in Figure 15.6. Each row of modules has 16MB. A row is selected by the two most signicant bits
of the address vector. The two least signicant address bits are used to select one of the bytes that
compose a word. The remaining bits are used to address a byte inside a 4MB module.
Exercise 15.9 PC=1500 for all cases
(a) add R7,R5,R8
instruction is read form the memory and the program counter is incremented by 4. The
instruction value (signal instr) is sent to the control subsystem for decoding.
{ path is set: sin sout=0, ALU PC=1, PC RA=0
{ PC=PC+4: ALUop=1110 (no condition coming from the ALU is stored)
{ values are stored in the destination registers: WrPC=1, WrIR=1
after decoding, the signals that control the data subsystem are activated to implement the
requested operation (addition):
{ indicates the source and destination of the operation: AddrA=R5, AddrB=R8, Ad-
drC=R7
{ path control: Mem ALU=0, sin sout=0, PC RA=1, IR RB=1
{ operation: ALUop=0001 (addition)
{ results and conditions are stored in registers: WrC=1, WrCR=1
(b) stw R3,11300(R2) | Mem(R2+11300):=R3

Rd MRdy
Wr controller
Enable
Adr(25:0) Adr(23:2)
controls 4MB
module
Byte 3 Byte 2 Byte 1 Byte 0
Adr(23:2)
Adr(23:2)
Adr(23:2)
Adr(25:24)
2
8 8 8 8
2
Selector/Distributor
Adr(1:0)
32
data
Figure 15.6: 64MB Memory - Exercise 15.8

instruction fetch is the same as presented for part (a)
decode the instruction, compute and send the memory address to be used for memory write,
combining the value in register R2 and the displacement value 11300 in the instruction. Send
R3 to the data bus.
{ register access: AddrA=R2, AddrB = R3
{ path setup: PC RA=1, IR RB=0, ALU PC=0, sin sout=1
{ operation: ALUop=0001 (addition), ZE SE=1 (sign extension)
(c) brn 10000 | PC := PC+4+10000

instruction fetch is the same as presented for part (a)
decode the instruction, compute the branch target address, test the condition and write the
target value into the program if condition is true.
{ register control: (
N =1
WrPC = 10 ifotherwise (15:1)
{ path setup: PC RA=0, IR RB=0, ALU PC=1.
{ operation: ALUop=0001 (addition of PC+4 and 10000), ZE SE=1 (sign extension)
Exercise 15.10 The signals that are active during the execution (no fetch cycle) of both instruc-
tions are shown in Figure 15.7.
clk execute memop

instr load word instruction
AddrA
Mem_ALU
AddrC
ALUop addition
WrC
WrCR
DataA
IR_RB
DataC
ALU_PC
MemAddr
instruction register ALU op ctr memory

decode read delay delay delay access delay
(a) ldw RT,D(RA)
clk
instr branch instruction
SE_ZE sign extension
IR_RB
PC_RA
ALUop addition
WrC
WrCR
WrPC
ALU_PC
ALUdata
instruction ALU delay to tsu

decode compute nex PC value PC reg.
(b) br D
Figure 15.7: Timing diagram for signals in data subsystem - Exercise 15.10
Exercise 15.11 Based on the VHDL description on page 474 of the text we obtain the state-
transition diagram and one-hot implementation of the control subsystem as shown in Figure 15.8.
The state change from ffetch; execute; memopg states to p reset is not synchronous, for this reason
we are indicating the transition with dashed lines.
reset
reset
reset load/store
P_reset Fetch Execute Memop
others
Memop
reset
Execute
P Q P_reset R Q fetch D R Q R Q
0 D D D
P_reset Fetch Exec. Memop
clk
load/store
Opcode[5:2]=1000
Figure 15.8: Control subsystem for Exercise 15.11 (without the output)
The generation of control signals (control subsystem outputs) is based on the VHDL description
on pages 476 and 477 of the text, and the control signal table Ctrl Table shown on page 475. The
table is implemented in hardware by a ROM. A row of the table, addressed by the opcode value, is
referenced in this exercise as ROMline = ROM (Opcode). Each line is composed of several control
signals, and it is represented as: ROMline[< controlsignal >]. The expressions for the control
signals are:
IR RB = ROMline[IR RB]
WrCR = ROMline[WrCR]:fetch0
WrC = ROMline[WrC ]:(ROMline[Memop]0:execute + memop)
ALUop = (\111000):fetch + ROMline[ALUop]:fetch0
MemRd = fetch + ROMline[WrMem]0:memop footnote 1 ****
MemWr = ROMline[WrMem]:memop
MemEnable = fetch + memop
MemLength = fetch + Opcode(0):memop
IORd = 0
IOWr = 0
IOEnable = 0
IOLength = 0
ALU PC = fetch + execute
sin sout = ROMline[WrMem]:MemRdy0:memop
PC RA = ROMline[WrPC ]0:fetch0
WrIR = fetch
WrPC = fetch + ROMline[WrPC ]:condition ****** NOT DONE IN uVHDL
****** Error in page 477 of the text
Mem ALU = ROMline[WrMem]
ZE SE = ROMline[ZE SE ]
AddrA = instr(20 : 16)
AddrB = instr(25 : 21):(RS RB =0 00) + instr(15 : 11):(RS RB =0 10)
AddrC = instr(25 : 21)
where the condition value is computed from the condition signals from the ALU and the value to
be tested, which is specied in the conditional branch opcode.
The network that implements the generation of the control signals is shown in Figure 15.9.
Values of the control signals for the instructions in Exercise 15.2 are shown in the following
table, for each processor state. Recall that the binary code for these instructions are:
add = 01000000101001110100100000000000
ldw = 10000100111010000000010010110000
brn = 11000100000000000000001111101000
Signal add ldw brn
Fetch Exec Fetch Exec Memop Fetch Exec
IR RB - 1 - 0 0 - 0
WrCR 0 1 0 0 0 0 0
WrC 0 1 0 0 1 0 0
ALUop 1110 0001 1110 0001 10001 1110 0001
MemRd 1 0 1 0 1 1 0
MemWr 0 0 0 0 0 0 0
MemEnable 1 0 1 0 1 1 0
MemLength 1 0 1 0 1 1 0
IORd 0 0 0 0 0 0 0
IOWr 0 0 0 0 0 0 0
IOEnable 0 0 0 0 0 0 0
IOLength 0 0 0 0 0 0 0
ALU PC 1 1 1 1 0 1 1
sin sout 0 0 0 0 0 0 0
PC RA 0 1 0 1 1 0 0
WrIR 1 0 1 0 0 1 0
WrPC 1 0 1 0 0 1 condition
Mem ALU - 0 - 0 0 - 0
ZE SE - 0 - 1 1 - 1
AddrA - 00111 - 01000 01000 - 00000
AddrB - 01001 - 00111 00111 - 00000
AddrC - 00101 - 00111 00111 - 00000
1
Both MemRd and MemWr signals should be implemented as pulses, according to the VHDL description. The
solution for this exercise simplies this aspect, making the signals active for a complete clock cycle.
memop
Opcode ROMline execute
ROM WrC
6 12 1
Romline[Memop]
1
Romline[WrMem]
1
Romline[RS_RB] IR_RB
1
Romline[IR_RB]
1
Romline[WrC]
1 PC_RA
Romline[WrPC]
1 fetch’
Romline[WrCR]
1
Romline[ZE_SE] WrPC
4 condition
Romline[ALUop]
ZE_SE
fetch
MemEnable
memop
ROMline[ALUop] Memlength
0 opcode(0)
4
ALUop
1110 1
MemRd
fetch MemWr
instr(25:2) 0
5 ALU_PC
AddrB execute
instr(15:11) 1
MemRdy
Sin_Sout
ROMline[RS_RB]
Mem_ALU
WrIR=fetch fetch’ WrCR

AddrC = instr(25:21) Romline[WrCR]
AddrA = instr(20:16)
Figure 15.9: Network used for control signal generation - Exercise 15.11.
The d.c.'s on the table represent information that is based on the instruction bits, and is valid
only after the fetch state. The condition included in the table (signal WrPC) is given by the test
of the ALU cond signal, based on the conditional branch opcode. For example, for the branch on
zero instruction (brz): condition = 1 if (Opcode = 110011 and Z = 1).
Exercise 15.12 Cycle time (based on Example 15.1 in the text)
tR = 2ns
tRF = 4ns
tALU = 4ns
tmux = 0:5ns
tZSE = 0:5ns
tsw = 0:5ns
tctl = 0:5ns
tdec = 3ns
tmem = 10ns
tfetch = tR + tctl + tmux + tmem + tsw = 2 + 0:5 + 0:5 + 10 + 0:5 = 13:5ns
texecute = tR + tctl + tRF + tmux + tALU + tmux + tRF = 2 + 0:5 + 4 + 0:5 + 4 + 0:5 + 4 = 15:5ns
tmemop = tR + tctl + tmem + tsw + tmux + tRF = 2 + 0:5 + 10 + 0:5 + 0:5 + 4 = 17:5ns
Based on these values, the critical path is in the memop state. The clock cycle is 17.5ns, limiting
the clock frequency to 57MHz, same as the system in Example 15.1 in the text.
Exercise 15.13 Modication to XMC architecture to have only two instruction formats with 2
bytes (F1) and 4 bytes (F2).
(a) The format for the instruction groups are:
Group Operation type Number of bits (actual) Format
Unary RT := op(RA) 16 F1
Binary RT := RAopRB 20 F2
RT := RAopSI 32 F2
RT := RAopUI 32 F2
Memory RT := M [RA + D] 32 F2
M [RA + D] := RS 32 F2
I/O RT := IO[PN ] 27 F2
IO[PN ] := RS 27 F2
Branch PC := PC + 4 + D 22 F2
(indirect) PC := RA 11 F1
NOP 6 F1
(b) One possible solution to modify the opcode is to use opcodes with the msbit = 1 for the
2-byte instructions and opcodes with the msbit = 0 for the 4-byte instructions. The opcodes used
for the load/store/I/O operations and unary/nop/branchindirect operations could be exchanged,
such that their opcode values would be:
load=store = 00xxxx; I=O = 00xxx; unary=nop=branchindirect = 10xxxx
The instruction format would be detected testing the most signicant bit of the opcode.
(c) With two instruction formats there is a problem with instruction alignment. The memory
is byte addressed but the processor reads words (4 bytes). Thus, an instruction may start in the
middle of a word and go over the next word. This problem is dicult to solve and to simplify the
solution of this exercise lets consider that instructions in the F2 format are always aligned. Thus,
it is the responsibility of the compiler to insert NOP instructions when necessary to create groups
with an even number of F1 format instructions, this way aligning instructions in the F2 format. It
is also the case that the processor does not need to read an instruction from memory every fetch
cycle, it may be available in a word already read from memory in the previous cycle. The processor
doesn't read another instruction word from the memory when the present instruction is in the F1
format and its address has bit 1 is 0 (that means, the half-word instruction is aligned with the word
address).
The modication in the IR register part is shown in 15.10. The 16-shift register enables the
data section to send to the control section the rst or second half word in the instruction register.
from memory
WrIR clk
32-bit register
reset
32 16-shift register
ls half word 16 0
ms half 16
16
word
0 1 0 1
Mux Mux
selhalfword
32
to control section
Figure 15.10: New Instruction Register - Exercise 15.13

Since now the adjustment of the PC value depends on the instruction format, it is not possible
to update it at the end of the fetch cycle. During the execute state, it is not always possible to use
the ALU for this purpose, thus, the solution is to include a dedicated adder to the data section,
only to enable the addition of 2, 4, or D (displacement in the instruction register) to the PC value,
during the instruction execution phase. Figure 15.11 shows the inclusion of the adder to the PC
area of the data section. Observe that relieving the ALU from this task removes the need for
MUX2. The path from the PC to the ALU input is not necessary. The PC may be loaded with
a value coming from the register le (indirect branch), for this reason, Mux4 was used to create
an alternative path to load the PC with the ALU output. Mux5 is used to select one of the three
possible values added to PC. The selection is controlled by signal sel24D. To avoid a path through
the ALU, the D value is obtained from the ZE SE module directly.
DataB
DataA from extender
module
Mux3
ALUop Cond to condition

ALU
register
to Mux1 ALUdata
2 4
2 0 1 2 3
sel24D Mux5
Adder
selPC
Mux4
WrPC
clk
Reset PC
ALU_PC
Figure 15.11: Modications to the PC update network - Exercise 15.13
Exercise 15.14 If it is not possible to read the register le (RF) during the execution state, the
delay computed in Example 15.1 of the text would be slightly modied. Instruction decoding and
RF reading couldn't be done in parallel (as presented in Example 15.1), and the RF read will need
to wait for the decoding phase to nish. Thus, the delay for the exec state would be:
texec = tR + maxftctl ; tdec g + tRF + tmux + tALU + tmux + tRF
texec = 2 + 3 + 4 + 0:5 + 6 + 0:5 + 4 = 20:5ns
The computation of tmemop doesn't change. The execution time gets worse for this situation,
when compared to the case analyzed in Example 15.1. Again exec is the critical state. It imposes
a minimum clock cycle time of 20.5ns, and a maximum clock frequency of 48.7MHz.
Exercise 15.15 Introduce a register at the ALU output. To avoid an increase in the number of
cycles for the PC update also, we introduce the register in the path between the ALU and mux1,
after the PC input. This way, the PC value continues to be updated in one clock cycle. Now there
are two execute states:
execute1: terminates when the ALU output (result) is ready.
execute2: the result generated by the ALU is stored back into the register le.
(a) cycle time:
texec1 = tR + tctl + tRF + tmux + tALU = 2 + 0:5 + 4 + 0:5 + 6 = 13ns
texec2 = tR + tmux + tRF = 2 + 0:5 + 4 = 6:5ns
The time to execute a memory operation and perform an instruction fetch are still the same
and are given at Example 15.1 as: tfetch = 11:5ns and tmemop = 15ns. The memory operation will
limit the minimum clock cycle time to 15 ns.
(b)
Number of cycles per instruction type
Instruction cycles
Unary (one operand - register) 3
Binary (two operands - registers) 3
Memory 3
I/O 3
Branch 2
NOP 2
(c) Following the same calculation done in Example 15.1, the execution time for register and
memory operations is 3 15 = 45ns. There was an improvement in the memory operations, but
the register operations was degraded. The average execution time is 45 ns, which is worse than the
case shown in Example 15.1.
Exercise 15.16: Spliting the memory operation cycle.
(a) Insert a register after the switch, before mux1, isolating the access delay to the register le.
The new memory cycles are:
tmemop1 = tR + tctl + tmem + tsw = 2 + 0:5 + 8 + 0:5 = 11ns
tmemop2 = tR + tmux + tRF = 2 + 0:5 + 4 = 6:5ns
For this modication, the minimum clock cycle is given by the exec1 cycle time (13 ns, computed
in Exercise 15.15).
(b)
Number of cycles per instruction type
Instruction cycles
Unary (one operand - register) 3
Binary (two operands - registers) 3
Memory 4/3
I/O 4/3
Branch 2
NOP 2
where the two number x/y represent the number of cycles for reading data into a register (x) and
number of cycles for writing data to the memory (y).
(c) Execution time: Following the same calculation done in Example 15.1, the execution time
for register and memory write operations is 3 13 = 39ns, and for memory read operations is
4 13 = 52ns. There was an improvement in the register and memory write operations compared
to Exercise 15.15. However, memory read operations present a worse execution time. Keeping
the same proportion of memory and register operations in a given program mix, the same used
in Example 15.1, and also considering that half of the memory operations are read operations, we
obtain the average instruction execution time of:
0:9 39 + 0:1 52 = 40:3ns
Thus, the average instruction execution for this alternative is worse than the one presented in
Example 15.1, and better than the alternative analyzed in Exercise 15.15.
Exercise 15.17 Using instruction and data caches. The access time to caches depends on the
availability of the requested data. For this exercise, we are assuming that the data being accessed
is in the cache. The time to read an instruction from the instruction cache is: tim = 6ns, and the
time to read data from the data cache is: tdm = 8ns. Since only the time to fetch an instruction is
aected (the access time for data continues the same as tmem ), we get:
tfetch = tR + tctl + tmux + tim + tsw = 2 + 0:5 + 0:5 + 6 + 0:5 = 9:5ns
Thus, although the alternative reduces the instruction fetch time, it is not going to improve
the clock cycle time, since the clock period is determined by the memop state time (provided in
Example 15.1 and Exercise 15.15) and the execution state time (evaluated in Exercise 15.16).

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SOLUTIONS TO EXERCISES

Alexandre F. Tenca, Tomas Lang, Milos D. Ercegovac, and J.H. Moreno

Los Angeles, California

( x22 f0; 1; :::; 9g

a b f1(a; b) f2(b; f1(a; b))

decimal digit 2-4-2-1

Table 2.1: Valid 2-out-of-5 combinations { Exercise 2.12(a)

M [0; 1; M (c; d; e)] = M (c; d; e)

The conclusion is:

The conclusion is:

and interchange the variables x and z .

From these equations, we get:

These conditions are incompatible, we can't nd such a threshold function.

 z2 = one set(6; 12; 17; 24);

a + a0 b + a0 b0c + a0b0c0d + a0b0c0d0e =

Exercise 2.27 (a) With the assumption that c = a b we obtain

abc a#(b&c) (a#b)&(a#c)

Table 2.2: Proof of distributivity for system in Exercise 2.29

Equivalent expressions: Expr a and Expr d, Expr b and Expr c.

E (a; b; c; d) = c0 d(ab + b) + ab0(c + c0) + (a + a0b)cd

E (a; b; c; d) = bc0(d + d0 ) + b0c0(a0 + ad0 ) + acb + ac0d

[((a + b + a0 c0)c + d)0 + ab]0 =

[(w0 + (xy + xyz 0 + (x + z )0)0 )(z 0 + w0 )]0 =

= wxy (z + z 0 ) + wxyz 0 + wx0 z 0(y + y 0)wz (x + x0 )(y + y 0 )

E (a; b; c; d) = (a0 + b0 + c0)(a0 + b)(a0 + c0 )(b + c0)

one-set(z1 )=f3; 5; 6; 7; 9; 10; 11; 12; 13; 14g

Exercise 2.50 (a) A conditional expression is

dec x = (x3; x2; x1; x0) z = (z3; z2; z1 ; z0)

z3 = x03x02 x01 + x03x02 x1x00 + x03x2 x01 x00 + x3 x02x01 x0

b4) Tabular description of the function using 8,-2,2,-1 code.

dec x = (x3; x2; x1; x0) z = (z3; z2; z1 ; z0)

a = (a3; a2; a1; a0); b = (b3; b2; b1; b0)

g = a3 b03 + e3 a2 b02 + e3e2 a1b01 + e3e2 e1 a0 b00

z2 = a3b03 + e3 a2 b02 + e3e2a1 b01 + e3e2e1 a0b00

Chapter 3 (October 3, 2000)

Exercise 3.1 (a) logic values

0.3 0.2 0.5 0 0 0 1 1 1

For positive logic, the module is a XOR gate. z = x0  x1 .

Figure 3.1: Network the implements the function z = (a + b )c d { Exercise 3.2

(a) using AND and NOR circuits

(b) using complex gate approach

Figure 3.2: Function (abc + d) { Exercise 3.3

Figure 3.3: Exercise 3.4 - Circuit that implements z = (x0 + x1 )

tpHL (NOR) = 4:5ns

Figure 3.4: Timing diagram, Exercise 3.8

Exercise 3.11 Noise margins are de ned as:

we obtain the noise margins:

Figure 4.1: Network for Exercise 4.4

Figure 4.2: Network for Exercise 4.5

Figure 4.4: NAND-NOR network for Exercise 4.9

Figure 4.5: Mixed Logic Notation - Exercise 4.9

The analysis turns out to be less complex.

These switching functions are shown in the next table:

The delays of the critical path become:

(d) Timing diagram, see gure 4.6:

Figure 4.6: Timing diagram of Exercise 4.13

Exercise 4.14 (a) The switching expression for output z is

where s = 4s2 + 2s1 + s0 .

Figure 4.7: Timing diagram of Exercise 4.14

Module M1 implements a 3-input even-parity function which we denote EP (a; b; c).

Figure 4.8: Modules used in Exercise 4.15

TpLH (I2 z1) = tpLH (NOT ) + tpHL(OR-4) + tpHL(AND-3) + tpHL(NOT) +

Exercise 4.16 We partition the network as shown in Figure 4.9.

Alexandre F. Tenca, Tomas Lang, Milos D. Ercegovac, and J.H. Moreno

z2 = one set(6; 12; 17; 24);

For positive logic, the module is a XOR gate. z = x0 x1 .

Exercise 3.11 Noise margins are dened as:

Exercise 5.12 A high-level specication for this exercise is:

Exercise 5.18 A high-level specication for the system is:

Exercise 5.20 A high-level specication for this system is: