TEZPUR UNIVERSITY

1. Introduction:
A digital stop watch can be a circuit displaying the actual time in minutes, hours and seconds
or a circuit displaying the number of clock pulses. Here we design the second type wherein
the circuit displays count from 0 to 99. The digital stop watch circuit can be worked as a
clock which will advance after every one second. When power supply is applied, it starts
counting from zero and it counts till 99 seconds. It can be used while cooking or while doing
exercise. It can be used by students preparing for competitive exams. This circuit can also be
used during playing game like teams have to complete the task and the team which have done
it in shortest period of time first will be the winner. In such type of game we can easily record
the time of individual team.

2. Components Used:

 555 Timer
 BCD Up/Down Counter (IC 74192)
 BCD to7-Segment Decoder/Driver (IC 7447)
 Common Anode Seven Segment Display

3. 555 Timer:

The 555 timer IC is an integrated circuit used in a variety of timer, pulse generation and
oscillator applications. The 555 can be used to provide time delays, as an oscillator and as a
flip-flop element.

It has three basic operating modes :–

 Bistable
 Monostable
 Astable

Fig 1: Pin Configuration of 555 timer

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The pin configuration are described below :–

PIN NAME PURPOSE

1 GND Ground reference voltage, low level (0 V)

2 TRIG The OUT pin goes high and a timing interval starts when this input falls
below 1/2 of CTRL voltage (which is typically 1/3 VCC, CTRL being
2/3 VCC by default if CTRL is left open).

3 OUT This output is driven to approximately 1.7 V below +VCC, or to GND.

4 RESET A timing interval may be reset by driving this input to GND, but the
timing does not begin again until RESET rises above approximately 0.7
volts. Overrides TRIG which overrides THR.

5 CTRL Provides "control" access to the internal voltage divider (by default,
2/3 VCC).

6 THR The timing (OUT high) interval ends when the voltage at THR
(‘threshold’) is greater than that at CTRL (2/3 VCC if CTRL is open).

7 DIS Open collector output which may discharge a capacitor between intervals.
In phase with output.

8 VCC Positive supply voltage, which is usually between 3 and 15 V depending

on the variation.

In this circuit, we are using the 555 timer in astable mode.

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3.1. Astable Mode:

Fig 2: 555 Timer in Astable Mode

In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a
specified frequency. Resistor R1 is connected between VCC and the discharge pin (pin 7) and
another resistor (R2) is connected between the discharge pin (pin 7), and the trigger (pin 2)
and threshold (pin 6) pins that share a common node. Hence the capacitor is charged through
R1 and R2, and discharged only through R2, since pin 7 has low impedance to ground during
output low intervals of the cycle, therefore discharging the capacitor.
In the astable mode, the frequency of the pulse stream depends on the values of R1, R2 and C.
𝟏
𝒇=
𝟎. 𝟔𝟗𝟑(𝑹𝟏 + 𝟐𝑹𝟐 )𝑪

4. BCD Up/Down Counter (IC 74192):

The 74192 is an UP/DOWN BCD Decade (8421). Separate Count Up and Count Down
Clocks are used and in either counting mode the circuits operate synchronously. The outputs
change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate
Terminal Count Up and Terminal Count Down outputs are provided which are used as the
clocks for a subsequent stage without any extra logic, thus simplifying multistage counter
designs. Individual preset inputs allow the circuits to be used as programmable counters.
Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the
clocks.

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4.1. Pin Configuration:

Fig 3: Pin Configuration of IC 74192

The pin configuration are described below –

PIN NAME PURPOSE

5 UP Count Up Clock Pulse Input

4 DOWN Count Down Clock Pulse Input

14 CLR Clear Input (Asynchronous)

11 ̅̅̅̅̅̅̅̅
𝑳𝑶𝑨𝑫 Parallel Load Input

12 ̅̅̅̅
𝑪𝑶 Terminal Count Up (Carry output)

13 ̅̅̅̅̅
𝑩𝑶 Terminal Count Down (Borrow output)

8 GND Ground

16 VCC Positive supply voltage

15, 1, 10, 9 A, B, C, D Parallel Data Input

3, 2, 6, 7 QA, QB, QC, QD Flip-flop Output

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The mode selection table of IC 74192 is drawn below –

CLR ̅̅̅̅̅̅̅̅
𝑳𝑶𝑨𝑫 UP DOWN MODE
H X X X Reset (Asynchronous)
L L X X Preset (Asynchronous)
L H H H No Change
L H Low to High Clock H Count Up
L H H Low to High Clock Count Down

5. BCD to7-Segment Decoder/Driver (IC 7447):

7447 is a BCD to 7-segment decoder/driver IC. It accepts a binary coded decimal as input
and converts it into a pattern to drive a seven-segment for displaying digits 0 to 9. The input
to the 7447 is a binary number DCBA where D is 8s, C is 4s, B is 2s and A is 1s. The inputs
DCBA often come from a binary counter. It accepts four lines of BCD (8421) input data and
generates their complements internally. The outputs correspond to Common anode (CA)
configuration of seven segments.

Pin Configuration

Fig 4: Pin Configuration of IC 7447

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The pin configuration are described below –

PIN NO FUNCTION NAME

1 BCD Input 2 B
2 BCD Input 3 C
̅̅̅̅
𝑳𝑻
3 Display Test; Active Low
̅̅̅̅̅̅̅
̅̅̅̅/𝑹𝑩𝑶
𝑩𝑰
4 Ripple Blanking Output; Active Low
̅̅̅̅̅̅
𝑹𝑩𝑰
5 Ripple Blanking Input; Active Low
6 BCD Input 4 D
7 BCD Input 1 A
8 Ground GND
9 e
10 d
11 c
12 Segment Outputs; Active Low b
13 a
14 g
15 f
16 Supply Voltage; 5V Vcc

6. Common Anode Seven Segment Display:

The 7-segment display, also written as “seven segment display”, consists of seven LEDs
arranged in a rectangular fashion as shown. Each of the seven LEDs is called a segment
because when illuminated the segment forms part of a numerical digit to be displayed. An
additional 8th LED is sometimes used within the same package thus allowing the indication
of a decimal point, (DP) when two or more 7-segment displays are connected together to
display numbers greater than ten.

Fig 5: 7-Segment Display

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Each one of the seven LEDs in the display is given a positional segment with one of its
connection pins being brought straight out of the rectangular plastic package. These
individually LED pins are labeled from ‘a’ through to ‘g’ representing each individual LED.
The other LED pins are connected together and wired to form a common pin.
So by forward biasing the appropriate pins of the LED segments in a particular order, some
segments will be light and others will be dark allowing the desired character pattern of the
number to be generated on the display. This then allows us to display each of the ten decimal
digits 0 through to 9 on the same 7-segment display.
The displays common pin is generally used to identify which type of 7-segment display it is.
As each LED has two connecting pins, one called the “Anode” and the other called the
“Cathode”, there are therefore two types of LED 7-segment display called: Common
Cathode (CC) and Common Anode (CA).
In this project, we are using Common Anode 7-segment display. In general, common anode
displays are more popular as many logic circuits can sink more current than they can source.
Also note that a common cathode display is not a direct replacement in a circuit for a
common anode display and vice versa, as it is the same as connecting the LEDs in reverse
and hence light emission will not take place.
Depending upon the decimal digit to be displayed, the particular set of LEDs is forward
biased. For instance, to display the numerical digit 0, we will need to light up six of the LED
segments corresponding to a, b, c, d, e and f.

6.1 Pin Configuration:

Fig 6: Pin Configuration of Common Anode 7-Segment Display

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The pin configuration are described below :–

PIN NO NAME
1 Cathode E
2 Cathode D
3 Common Anode
4 Cathode C
5 Cathode DP
6 Cathode B
7 Cathode A
8 Common Anode
9 Cathode F
10 Cathode G

7. Block Diagram:

Fig 7: Block Diagram of Digital Stop Watch

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8. Circuit Diagram:

Fig 8: Circuit Diagram of Digital Stop Watch

9. Principle:
This circuit is based on the principle of 2 stage counter operation, based on synchronous
cascading. The idea is to display clock pulses count from 0 to 99. This is done by using a 555
Timer IC connected in astable mode to produce the clock pulses of 1 second interval each.
While the first counter counts from 0 to 9, the second counter starts its counting operation
every time the count value of first counter reaches 9. The counter ICs connected in cascading
format and each counter output is connected to BCD to 7 segment decoder used to drive the 7
segment displays.

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10. Snapshot of Simulation:

Fig 9: Snapshot of Simulation

12. Power Consumption:

IC Theoractical Measured

555 30 mW
74192 100 uW *2 =200 uW
7447 125 uW *2 =250 uW
7 segment display 250 mW *2 = 500 mW
Total 530.45 mW 577 mW

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13. Propagation Delay:

Fig 10: Snapshot showing Propagation Delay

Thus,

Delay = 5 division

Delay = 1 ms

13. Conclusion:
The prototype of the Digital Stop Watch is efficiently designed. The project “Digital Stop
Watch” has been successfully completed. Finally it can be concluded that this project
application gives a very good feature.

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