THE PROJECT ENTITLED

Control of Single-Stage Single-Phase

PV Inverter
Submitted in partial fulfilment of the requirement for the degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRICAL ENGINEERING

Submitted By

Ys Pavan kumar (U15EE105)

Chetan zinzala (U15EE033)
Uday ghantala (U15EE029)
Kiran prajapati (U15EE051)
Aman mistry (U15EE028)

Supervisor
Dr. M A Mulla

2018-19

DEPARTMENT OF ELECTRICAL ENGINEERING

SARDAR VALLABHBHAI NATIONAL INSTITUTE OF TECHNOLOGY

SURAT – 395007, GUJARAT, INDIA

1
 SVNIT
SARDAR VALLABHBHAI NATIONAL INSTITUTE OF TECHNOLOGY

SURAT-395 007, GUJRAT, INDIA

DEPARTMENT OF ELECTRICAL ENGINEERING

CERTIFICATE
This is to certify that the project report entitled “Control of Single-Stage Single-Phase PV
Inverter” submitted by
Ys Pavan kumar (U15EE105)
Chetan zinzala (U15EE033)
Uday ghantala (U15EE029)
Kiran prajapati (U15EE051)
Aman mistry (U15EE028)
is a record of bonafide work carried out by them in partial fulfilment of the requirement for
the award of the degree of “BACHELOR OF TECHNOLOGY IN ELECTRICAL ENGI-
NEERING”.

Date:

Place: Surat

Dr. M A Mulla

Faculty Supervisor

Examiners

Dr. S N Sharma
Head of Department

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 Acknowledgements
We would like to offer our very great appreciation to our guide Dr. M.A. Mulla for his constant
and patient guidance and constructive suggestions during the preparation of this report.

We wish to acknowledge the help provided by Dr. S N Sharma, Head of the Department for
supporting us by providing useful resources to carry out our project work.

We appreciate all our colleagues whose direct and indirect contribution helped us a lot to ac-
complish this report. We would also like to thank all the teaching and non-teaching staffs for
cooperating with us and providing valuable advice which helped us in the completion of this
work.

At last, We would like to thank our families for their immense support and encouragement in
writing this report.

Ys Pavan kumar (U15EE105)

Chetan zinzala (U15EE033)
Uday ghantala (U15EE029)
Kiran prajapati (U15EE051)
Aman mistry (U15EE028)

3
 Abstract
In this project, A control strategies for single-stage photovoltaic (PV) inverter is addressed.
Two different current controllers (the classical proportional-integral (PI) and the novel pro-
portional-resonant (PR) controllers) have been implemented and an experimental comparison
between them has been made. A complete control structure for the singlephase PV system is
also presented. The superiority of the PR controller is demonstrated with respect to the PI
controller in terms of harmonic current rejection and the capability to remove the steady-state
error without using the voltage feedforward (VFF). The control strategy was successfully
tested on a real 3.5 kW PV inverter.

4
TABLE OF CONTENTS
ACKNOWLEDGEMENT................................................................................................................................3

ABSTRACT......................................................................................................................................................4

TABLE OF CONTENTS..................................................................................................................................5

ACRONYMS.....................................................................................................................................................6

LIST OF TABLES AND FIGURES..................................................................................................................7

CHAPTER 1: INTRODUCTION.....................................................................................................................8

CHAPTER 2: MUTILEVEL INVERTER TOPOLOGIES..............................................................................9

2.1 Diode clamped MLI..........................................................................................................................10

2.2Flying capacitor MLI.........................................................................................................................11

2.3 Cascaded H Bridge MLI...................................................................................................................13

2.3.1 Types of cascaded H-Bridge MLI.......................................................................................14

2.3.2 Comparison of symmetric and Asymmetric inverters..........................................................15

CHAPTER 3: SINE PWM TECHNIQUE.....................................................................................................16

3.1 Level shifted...................................................................................................................................17

3.2 Phase shifted...................................................................................................................................18

3.3 THD analysis..................................................................................................................................19

3.4 Comparison of Phase Disposed and Phase Shifted.........................................................................19

3.5 Conclusion......................................................................................................................................23

CHAPTER 4: INTRODUCTION TO PLL...................................................................................................24

4.1 Working Principle of Pll.................................................................................................................24

4.2 Application of Pll............................................................................................................................24

4.3 SOGI Pll..........................................................................................................................................25

4.4 Conclusion......................................................................................................................................26

CHAPTER 5: GRID CONTROL MECHANISM........................................................................................27

5.1 Clarke and Parke Transformation...................................................................................................27

5.2 Current Control Strategy For Grid Connected Converters............................................................29

5
 5.2.1 Calculation of reference current..........................................................................................29

5.2.2 Calculation of reference voltage ........................................................................................31

CHAPTER 6: SIMULATIONS AND RESULTS

6.1 Analysis of 5 level CHB MLI

6.2 SOGI FLL

6.3 Park Transformation

6.4 Grid Side Control

6.5 Analysis of Grid Control Mechanism with different Id and Iq

6.6 Final Inverter plus Grid

CONCLUSION

REFERENCES

6
ACRONYMS
PR=Portional-Resonant

PI= Proportional-Integral

PWM= Pulse Width Modulation

THD = Total Harmonic Distortion

PLL= Phase Locked Loop

7
List of Figures
2.1 5 L evel diode clamped inverter..........................................................................................................10

2.2 Flying capacitor MLI....................................................................................................................12

2.3 Single leg of CHB MLI..................................................................................................................13

2.4 Double leg of CHB MLI................................................................................................................13

2.5 Five level cascaded H bridge MLI.....................................................................................................14

3.1 Classification of PWM.........................................................................................................................16

3.2 PD-PWM........................................................................................................................................17

3.3 POD-PWM....................................................................................................................................17

3.4 APOD-PWM.................................................................................................................................18

3.5 Bipolar PSWM.............................................................................................................................18

3.6 Unipolar PSPW............................................................................................................................18

3.7 Phase disposed PWM.......................................................................................................................20

3.8 Phase shifted PWM........................................................................................................................21

4.1 Block Diagram of PLL...................................................................................................................24

4.2 SOGI based QSG..........................................................................................................................26

4.3 SOGI based PLL...........................................................................................................................26

5.1 Current space vector and projection...............................................................................................27

5.2 General rotating frame of reference..................................................................................................29

5.3 dq rotating frame of reference.........................................................................................................29

5.4 Current control scheme.................................................................................................................32

6.1 Phase disposed inverter......................................................................................................................34

6.2 Pulse generation of PD...................................................................................................................35

6.3 Pulse generation of PS scheme.........................................................................................................36.

6.4 Phase shifted inverter....................................................................................................................36

6.5 Pulses for phase shifted inverter....................................................................................................37

6.6 SOGI FLL........................................................................................................................................37

8
6.7 Grid voltage, wt...........................................................................................................................38

6.8 Park transformation.........................................................................................................................38

6.9 Inverter output,wt,dq0 output....................................................................................................39

6.10 Current control scheme............................................................................................................39

6.11 id,iq voltage waveforms............................................................................................................41

6.12 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)..................................................42

6.13 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)..................................................44

6.14 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)...................................................46

6.15 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)...................................................48

6.16 Inverter with synchronised grid..................................................................................................48

6.17 One phase of 3 phase inverter.....................................................................................................49

List of Tables
2.1 Switching of diode clamped inverter..,.........................................................................................10

2.2 Switching of flying capacitor MLI...............................................................................................12

2.3 Switching of 5 CHB MLI............................................................................................................14

3.1 THD at MI=1.............................................................................................................................20

3.2 THD at MI=0.8............................................................................................................................20

3.3 THD at MI=0.6............................................................................................................................20

3.4 THD at MI=0.9.............................................................................................................................21

3.5 THD at MI=1.1...........................................................................................................................21

3.6 THD at MI=1.2..........................................................................................................................21

3.7 THD at MI=1.2..........................................................................................................................22

3.8 THD at MI=0.8............................................................................................................................22

3.9 THD at MI=0.9............................................................................................................................22

3.10 THD at MI=0.6..........................................................................................................................22

3.11 THD at MI=1............................................................................................................................22

7.1 Response of grid and converter at different id and iq....................................................................48

9
Chapter 1
INTRODUCTION

With restructuring and deregulation of power system, distributed energy resources are becoming more popu-
lar. The conventional power plants are often centralized and use non-renewable energy resources such as
coal, petroleum, natural gas etc. In distributed energy resources, renewable source of energy is used such as
solar, wind, biomass etc. With the increase in pollution and depleting conventional sources of energy, a lot
of focus is on renewable sources.

Recently a tremendous amount of attention is paid to PV connected solar inverter by researchers. The mar-
ket for PV power applications continues to develop at a high rate [1]. Moreover, the price level of the PV
modules and the system costs (inverter included) has decreased significantly [2]. The use of PV systems
connected in parallel with the mains was simplified and is often supported by incentives from utilities and/or
governmental bodies. Before connecting a PV system to the power network, the d.c. voltage of the solar
modules must be converted into an a.c. voltage. Some protection systems are required to prevent damage in
the PV system caused by the utility network and vice versa. The PV systems require standards addressing
the use and the performance of grid-connected PV inverters, thus ensuring the safety and quality of the prod-
ucts.

The purpose of the power electronics in PVPS is to convert the d.c. current from the PV panels into an a.c.
current to the grid, with the highest possible efficiency, the lowest cost and keep a superior performance. The
basic interfacing is shown in Fig. 1.

Fig. 1: Power electronic system with the grid, source (PV array),
power converter and control
10
The objective of work done in this report is to develop a control loop for solar inverter working in
standalone mode. The aim is to propose a simple, stable control loop for getting the constant ac output volt-
age from inverter. The input of solar inverter is connected with solar panel. As solar irradiation level keeps
changing throughout the day, the output of solar panel changes, consequently the input of inverter changes.
To maintain the output constant a closed loop is implemented using a PI controller. The peak value of in-
verter output is compared with a reference signal. The error is fed to PI controller. Duty cycle of inverter
switch is varied with error so as to make the output voltage constant. For current-controlled PV inverters in
most of the cases a PI controller with grid voltage feed-forward (VFF) is used [3], [4], A perturb & observe
method has been used in order to track the Maximum Power Point Tracker (MPPT) of the PV characteristic.
In order to get a clean sinusoidal current reference (synchronized with the grid voltage) a phase locked loop
(PLL) based on a delay structure is used. The conclusions are presented in the final part of the report.

11
CHAPTER 2
System description and Control strategy

2.1 System description

Usually the power converter interface from the d.c. source to the load and/or to the grid consists of a two
stage converter: the d.c.- d.c. converter and the d.c -a.c. converter. An alternative solution could be the use
of a single-stage converter where the d.c.-d.c. converter is avoided and in order to ensure the necessary d.c.
voltage level the PV array can be a string of PV panels or a multitude of parallel strings of PV panels. In the
classical solution with two stage converter, the d.c.-d.c. converter requires several additional devices produc-
ing a large amount of conduction losses, sluggish transient response and high cost while the advantages of
the single stage converters are: good efficiency, a lower price and easier implementation. The disadvantages
of the single-stage converter are the fact that the PV panels are in series and if shading occurs on one or sev-
eral PV panels then the efficiency of the whole system is reduced.

Fig. 2: The voltage source PV inverter connected to the grid

through an LCL filter

As shown in Fig. 2, the PV inverter system consists of a solar panel string and a d.c. link capacitor Cdc on
the d.c. side with an output a.c. filter (LCL), insulation transformer and grid connection on the a.c. side. The
number of panels in the string has to ensure a d.c. voltage higher than the a.c. peak voltage at all time. The

12
energy conversion from d.c. to a.c. side is made by a single-phase voltage source inverter. The used solar
panel string consists of sixteen uniserial PV panels (300 W for each panel).

2.2 Control strategy

For the grid-connected PV inverters in the power range of 1-5 kW, the most common control structure for
the d.c.-a.c. grid converter is a current-controlled H-bridge PWM inverter having a low-pass output filter.
Typically L filters are used but the new trend is to use LCL filters that have a higher order (3rd) which leads
to more compact design. The drawback is its resonance frequency which can produce stability problems and
special control design is required [7]. The control structure of the PV power conversion system is shown in
Fig. 3.

Fig. 3: Control diagram of the PV energy conversion system

The main elements of the control structure are the synchronization algorithm based on PLL, the MPPT, the
input power control, the grid current controller including PWM.

2.2.1 PLL structure

13
The PLL is used to provide a unity power factor operation which involves synchronization of the inverter
output current with the grid voltage and to give a clean sinusoidal current reference. The PI controller param-
eters of the PLL structure are calculated in such a way that the settling time and the damping factor of this
PLL structure can be set directly. The PLL structure is also used for grid voltage monitoring in order to get
the amplitude and the frequency values of the grid voltage. The general form of the PLL structure including
grid voltage monitoring is presented in Fig. 4 [8].

Fig. 4:General structure of a single phase PLL including grid voltage and current monitoring.

2.2.2 MPPT algorithm

Maximum power point tracking (MPPT)[1][2] or sometimes just power point tracking (PPT)[3][4]) is a tech-
nique used commonly with wind turbines and photovoltaic (PV) solar systems to maximize power extraction
under all conditions.

PV solar systems exist in many different configurations with regard to their relationship to inverter systems,
external grids, battery banks, or other electrical loads.[5] Regardless of the ultimate destination of the solar
power, though, the central problem addressed by MPPT is that the efficiency of power transfer from the solar
cell depends on both the amount of sunlight falling on the solar panels and the electrical characteristics of the
load. As the amount of sunlight varies, the load characteristic that gives the highest power transfer efficiency
changes, so that the efficiency of the system is optimized when the load characteristic changes to keep the
power transfer at highest efficiency. This load characteristic is called the maximum power point (MPP) and

14
MPPT is the process of finding this point and keeping the load characteristic there. Electrical circuits can be
designed to present arbitrary loads to the photovoltaic cells and then convert the voltage, current, or frequency
to suit other devices or systems, and MPPT solves the problem of choosing the best load to be presented to
the cells in order to get the most usable power out.

Solar cells have a complex relationship between temperature and total resistance that produces a non-linear
output efficiency which can be analyzed based on the I-V curve.[6][7] It is the purpose of the MPPT system
to sample the output of the PV cells and apply the proper resistance (load) to obtain maximum power for any
given environmental conditions.[8] MPPT devices are typically integrated into an electric power converter
system that provides voltage or current conversion, filtering, and regulation for driving various loads, includ-
ing power grids, batteries, or motors.

Photovoltaic solar cell I-V curves where a line intersects the knee of the curves where the maximum power
transfer point is located.

2.2.2.1 Implementation

When a load is directly connected to the solar panel, the operating point of the panel will rarely be at peak
power. The impedance seen by the panel derives the operating point of the solar panel. Thus by varying the
impedance seen by the panel, the operating point can be moved towards peak power point. Since panels are
DC devices, DC-DC converters must be utilized to transform the impedance of one circuit (source) to the
other circuit (load). Changing the duty ratio of the DC-DC converter results in an impedance change as seen
by the panel. At a particular impedance (i.e. duty ratio) the operating point will be at the peak power transfer
point. The I-V curve of the panel can vary considerably with variation in atmospheric conditions such as ra-
diance and temperature. Therefore, it is not feasible to fix the duty ratio with such dynamically changing op-
erating conditions.

15
MPPT implementations utilize algorithms that frequently sample panel voltages and currents, then adjust the
duty ratio as needed. Microcontrollers are employed to implement the algorithms. Modern implementations
often utilize larger computers for analytics and load forecasting.

2.2.2.2 Classification

Controllers can follow several strategies to optimize the power output of an array. Maximum power point
trackers may implement different algorithms and switch between them based on the operating conditions of
the array.[12]

(1) Incremental conductance:

In the incremental conductance method, the controller measures incremental changes in PV array current
and voltage to predict the effect of a voltage change. This method requires more computation in the control-
ler, but can track changing conditions more rapidly than the perturb and observe method (P&O). Like the
P&O algorithm, it can produce oscillations in power output.[18] This method utilizes the incremental con-
ductance (dI/dV) of the photovoltaic array to compute the sign of the change in power with respect to volt-
age (dP/dV).[19]

The incremental conductance method computes the maximum power point by comparison of the incremen-
tal conductance (IΔ / VΔ) to the array conductance (I / V). When these two are the same (I / V = IΔ / VΔ),
the output voltage is the MPP voltage... The controller maintains this voltage until the irradiation changes
and the process is repeated.[13]

The incremental conductance method is based on the observation that at the maximum power point dP/dV =
0, and that P = IV. The current from the array can be expressed as a function of the voltage: P = I(V)V.
Therefore, dP/dV = VdI/dV + I(V). Setting this equal to zero yields: dI/dV = -I(V)/V. Therefore, the maxi-
mum power point is achieved when the incremental conductance is equal to the negative of the instantane-
ous conductance.

16
(2) Perturb and observe :

In this method the controller adjusts the voltage by a small amount from the array and measures power; if
the power increases, further adjustments in that direction are tried until power no longer increases. This is
called the perturb and observe method and is most common, although this method can result in oscillations
of power output.[13][14] It is referred to as a hill climbing method, because it depends on the rise of the
curve of power against voltage below the maximum power point, and the fall above that point.[15] Perturb
and observe is the most commonly used MPPT method due to its ease of implementation.[13] Perturb and
observe method may result in top-level efficiency, provided that a proper predictive and adaptive hill climb-
ing strategy is adopted.[16][17]

17
The perturb and observe algorithm has been chosen as a MPPT strategy in this report. In this method the
controller adjusts the voltage by a small amount from the array and measures power; if the power increases,
further adjustments in that direction are tried until power no longer increases. This is called the perturb and
observe method and is most common, although this method can result in oscillations of power output.[13][14] .It
is referred to as a hill climbing method, because it depends on the rise of the curve of power against voltage
below the maximum power point, and the fall above that point.[15] Perturb and observe is the most commonly
used MPPT method due to its ease of implementation.[13] Perturb and observe method may result in top-level
efficiency, provided that a proper predictive and adaptive hill climbing strategy is adopted.[16][17]

The flowcharts of the perturb & observe algorithm are shown in Fig. 5 [10], where Vk and Ik are the momentary
voltage and current of the PV array and Vk-1, Ik-1 are the previous sampled voltage and current, respectively.
The dP/dV term can be replaced by I + (∆I/∆V) ⋅ V. The output of the MPPT is the d.c. voltage reference (V*pv).

2.2.2.3 Comparison of methods

Both perturb and observe, and incremental conductance, are examples of "hill climbing" methods that can
find the local maximum of the power curve for the operating condition of the PV array, and so provide a true
maximum power point.[6][15][18]

The perturb and observe method requires oscillating power output around the maximum power point even
under steady state irradiance.

18
The incremental conductance method has the advantage over the perturb and observe (P&O) method that it
can determine the maximum power point without oscillating around this value.[13] It can perform maximum
power point tracking under rapidly varying irradiation conditions with higher accuracy than the perturb and
observe method.[13] However, the incremental conductance method can produce oscillations (unintention-
ally) and can perform erratically under rapidly changing atmospheric conditions. The sampling frequency is
decreased due to the higher complexity of the algorithm compared to the P&O method.[19]

2.2.2.4 Advantages

 Simplicity: This algorithm solves one linear equation. Therefore, it does not consume much compu-
tational power.
 Can be implemented as analog or digital circuits.
 Since temperature varies slowly with time, there are no steady-state oscillation and instability.
 Low cost: temperature sensors are usually very cheap.
 Robust against noise.

2.2.2.5 Disadvantages

 Estimation error might not be negligible for low irradiation levels (e.g. below 200 W/m²).

2.2.2.6 MPPT Code:(Perturb & observe)

function D = PandO(Param, Enabled, V, I)

% MPPT controller based on the Perturb & Observe algorithm.
% D output = Reference for DC link voltage (Vdc_ref)
% Enabled input = 1 to enable the MPPT controller
% V input = PV array terminal voltage (V)
% I input = PV array current (A)
% Param input:
Dinit = Param(1); %Initial value for Vdc_ref
Dmax = Param(2); %Maximum value for Vdc_ref
Dmin = Param(3); %Minimum value for Vdc_ref
deltaD = Param(4); %Increment value used to increase/decrease Vdc_ref
persistent Vold Pold Dold;
dataType = 'double';
if isempty(Vold)

19
 Vold=0;
Pold=0;
Dold=Dinit;
end
P= V*I;
dV= V - Vold;
dP= P - Pold;
if dP ~= 0 & Enabled ~=0
if dP < 0
if dV < 0
D = Dold + deltaD;
else
D = Dold - deltaD;
end
else
if dV < 0
D = Dold - deltaD;
else
D = Dold + deltaD;
end
end
else D=Dold;
end
if D >= Dmax | D<= Dmin
D=Dold;
end
Dold=D;
Vold=V;
Pold=P;

b) Asymmetrical type cascaded H-Bridge MLI

20
In this type of inverter different valued sources are used. Main advantage is we can increase no. of levels
without changing no. of H-Bridges. Referring to figure 5 keeping source values different i.e. for 1st H-
Bridge dc voltage is kept V and for 2nd H-Bridge 2V. With different switching patterns 7 levels can be ob-
tained; values of voltage will vary from 3V,2V,V,0,-V,-2V,-3V. In this when switches S1,S4 conducts output
will be V and simultaneously with operation of switches S1*,S4* output of 2nd H- Bridge will be 2V; Result-
ant inverter output will be 3V. When S1,S3, S1*,S4* will conduct the resultant output will be 2V;as switches
S1*,S4* will give output 2V while S1,S3 will give zero. When switches S2,S3,S2*,S3* will conduct equiva-
lent output at each bridge will be -V and -2V; inverter output will be -3V.

2.3.2 Comparison of Symmetrical and Asymmetrical Cascaded H-Bridge

MLI
It's preferable to choose asymmetrical type inverter to obtain higher voltage levels with keeping no. of H-
bridge same. While in symmetrical type inverter in order to increase voltage levels no. of H-Bridge has to be
increased and that leads to increased no. of components. That leads to some disadvantages like reduced effi-
ciency and increased losses. In case of asymmetrical inverter switching pattern becomes difficult as compared
to symmetrical one.

Chapter 3
SINE PWM TECHNIQUES

21
 PWM technique play an important role in obtaining desired output from MLI. Several PWM schemes have
been proposed for different application with different approach. This different PWM techniques involve sin-
gle pulse modulation technique, Multicarrier PWM technique, sine PWM technique, space vector PWM tech-
nique, selective harmonic elimination technique etc.

The multicarrier inverter technique is widely used because it is simplest technique to generate multiple pulses
to control individual power switches. It works on a basic principle of comparison of different carrier waves
with reference signal. They are mainly classified into two categories: i) Level Shift ii)Phase Shift Multicarrier
PWM technique involve different techniques like Phase disposed (PD), Phase Opposition Disposition(POD),
Alternate Phase Opposition Disposition(APOD), Phase shift(PS)etc.

Fig 3.1 Classification of SPWM

Referring to fig. above different modulating signals are used like pure sinusoidal, Third Harmonic Injection
etc.

In Sinusoidal Pulse Width Modulation (SPWM) technique, the signal is generated by comparing a sinusoidal
reference signal with a triangular carrier wave of frequency, fc. The frequency of the reference signal, fr
determines the output frequency fo and its peak amplitude, Ar controls the modulation index MI.

MI= Ar ÷ Ac Ac= carrier wave amplitude

There are two approaches i) Unipolar ii) bipolar. In unipolar carrier wave above zero or below zero are com-
pared with two sine reference signal which are 180◦ out of phase. In bipolar all the carrier waves are compared
with reference signal.

22
3.1 Level Shifted PWM Techniques:
In Level shifted technique N-1 levels are used and are compared with reference signal and pulses are gener-
ated.

1) Phase Disposition(PD): IN this method all the carrier signals are in same phase and compared with
reference signal.

Fig 3.2 PD-PWM

2) Phase Opposition Disposition PWM (POD-PWM): In phase opposition disposition all the carrier
waves above zero are out of phase 180◦ with below zero waves.

Fig 3.3 POD PWM

3) Alternate Phase Opposition Disposition (APOD) PWM: In APOD all the adjacent carrier waves
are out of phase 180◦.

23
 Fig 3.4 APOD PWM

3.2 Phase Shifted (PS)

This technique employs a number of carriers are all phase shifted by 90◦ accordingly. In 5 Level inverter 4
waves are shifted by 90◦ with each other.

Fig 3.5 bipolar PS PWM

Fig 3.6 Unipolar PS PWM

3.3 THD Analysis

24
THD(Total Harmonic Distortion): Total harmonic distortion is distortion in voltage or current waveform
due to presence of lower order harmonics. For any staircase voltage profile the Fourier series expansion is
given as equation given below:
∞
𝑉𝑑𝑐
𝑉𝑎𝑛 (𝑤𝑡) = ∑ 4 (cos 𝑘𝛼1 + cos 𝑘𝛼2 + ⋯ +cos 𝑘𝛼𝑠 ) sin(𝑘𝑤𝑡)
𝑘𝜋
𝑛=1,3,5…

Where s is the no. of H bridges connected in cascade per phase and k is the order of harmonics. For a given
desired fundamental peak voltage V1 , it is required to determine switching angles such that lower harmonics
are zero. The above equation is written again as
4Vdc
V1 = (cos α1 + cos α2 + cos α3 + ⋯ + cos αs )
π

Modulation index is defined as the ratio of fundamental voltage to the maximum obtainable fundamental
voltage. The maximum fundamental voltage is obtained when all the switching angles are zero.

4Vdc
V1max =
π

V1
So, according to MI definition, MI = V
1max

THD can be calculated using formula given below:

2 − V2
Vrms 1
THD = √ 2 ∗ 100%
V1

3.4 Comparison of Phase Disposed and Phase Shifted Method

MI = Modulation Index

fc =5kHz

V0(rms)= Output voltage

Vdc =200v

V1(rms)= Fundamental value

A) Phase Disposed

25
 Fig 3.7 Phase Disposed PWM scheme

Table 3.1 THD at MI=1

MI V0(rms) V1(rrns) Frequency THD

1 146.5 141.4 26.94%
5000 17.96%
9450 4.63%
10550 4.64%

Table 3.2 THD at MI=0.8

MI V0(rms) V1(rms) Frequency THD

0.8 121.75 113.1 38.39%
5000 29.08%
9550 5.89%
10450 5.85%

Table 3.3 THD at MI=0.6

MI V0(rms) V1(rms) Frequency THD

0.6 92.88 84.86 44.54%
4700 9.04%
5000 28%
5300 9.04%
9650 7%

Table 3.4 THD at MI=0.9

26
MI V0(rms) V1(rms) Frequency THD
0.9 134.22 127.3 33.48%
5000 24.61%
9550 5.23%
10450 5.23%

Table 3.5 THD at MI=1.1

MI V0rms V1rms Frequency THD

1.1 154.5 150.5 23.15%
4900 5.07%
5000 13.48%
5100 5.02%

Table 3.6 THD at MI=1.2

MI V0rms V1rms Frequency THD

1.2 166.7 156.5 27.75
5000 21.35%
10650 3.11%

B)Phase Shifted Method

∅ = 90°

Fig 3.8 Phase Shifted Scheme

Table 3.7 THD at MI=1.2

MI V0(rms) V1rms Frequency THD

27
1.2 166.7 156.5 27.75%
150 6.65%
9850 12.48%
9950 6.62%
10050 6.74%
10150 12.39%
10250 6.66%

Table 3.8 THD at MI=0.8

MI V0rms V1rms Frequency THD

0.8 130.5 113.1 50.23%
9850 12.41%
9950 27.6%
10050 28.03%
10150 6.66%

Table 3.9 THD at MI=0.9

MI V0rms V1rms Frequency THD

0.9 142.7 127.3 42.34%
9850 13.98%
9950 20.15%
10050 19.9%
10150 13.78%

Table 3.10 THD at MI=0.6

MI V0rms V1rms Frequency THD

0.6 102.7 84.99 71.96%
9850 8.37%
9950 43.18%
10050 43.81%
10150 8.09%

Table 3.11 THD at MI=1

MI V0rms V1rms Frequency THD

1 155.7 142.8 33.47%
9850 15.20%
9950 12.24%
10050 11.7%
10150 15.03%

3.5 Conclusion
28
In this particular section we discussed about different PWM schemes and THD. THD at different MI is meas-
ured and data has been shown in tabular form. Major difference between Phase Shifted scheme and Phase
Disposed scheme is how the carrier signals are being applied. From data shown above we can conclude that
90◦ Phase shifted carrier can produce lowest harmonic output voltage.

Chapter 4

29
INTRODUCTION TO PLL
4.1 Working Principle of PLL
A PLL is a closed loop fed-back system that sets fixed relationship between its output clock phase and phase
of a reference lock. A PLL is capable of tracking phase changes that falls in bandwidth of the PLL. A PLL
also multiplies a low frequency clock to produce high frequency clock which is known as clock synthesis. A
PLL has a negative feedback control system circuit. The main objective of PLL is to generate a signal in which
the phase is the same as reference signal. This is achieved after many iterations of comparisons of reference
and feedback signal. In this lock mode the phase of reference and feedback signal is zero. After this PLL
continues to compare the two signals but since they are in lock mode the output becomes constant. The basic
block diagram is shown below. Basically PLL consists of five main blocks.

i)Phase Detector (PD) or Phase Frequency Detector(PFD)

ii)Charge Pump (CP)

iii)Low Pass Filter (LPF)

iv)Voltage Controlled Oscillator(VCO)

v) Divide by N counter

Fig 4.1 Block Diagram of PLL

The PFD is one of the main parts in the PLL. It compares the phase and frequency difference between the
reference clock and feedback clock. Depending upon the phase and frequency deviation, it generates two
output signals "up" and "down". The charge pump circuit is used in PLL to combine both the output of PFD
and give a signal output. Output signal is fed to LPF to generate a DC control voltage. The Phase and frequency
of VCO output depends upon generated DC control voltage. If the PFD generates an "up" signal error voltage
at output of LPF increases which in turn increases VCO o/p signal frequency. If the "down" signal is generated
VCO o/p signal frequency decreases. The o/p of VCO is then fed back to PFD in order to recalculate the
phase difference and then we can create closed loop control frequency system.

4.2 Application of PLL

i)Frequency synthesis: A frequency synthesizer is an electronic system for generating a range of frequencies
from a single fixed time base or oscillator.

30
ii)Clock Generation : Many electronic systems include processors of various sorts that operate at hundreds of
megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs , which mul-
tiply a lower frequency clock up to the operating frequency of the processor. The multiplication factor can be
quite large in cases where operating freq. is multiple GHz and crystal freq. is tens or hundreds of MHz.

iii)Carrier Recovery: Some data streams, especially high speed serial data streams, are sent w/o an accompa-
nying clock. The receiver generates a clock from an approximate frequency reference and then phase aligns
to the transition in a data stream in PLL. This process is referred to clock recovery.

iv)Skew Reduction: This is one of the very popular and earliest use of PLL. Suppose a synchronous pair of
data and clock line enters a large digital chip. Since clock typically drives a large no. of transistors and logic
interconnects, it is first applied to large buffer. Thus, clock distributed on chip may suffer from substantial
skew with respect to data. This is an undesirable effect which reduces timing budget for ON chip operations.

v) Noise and Jitter Reduction: One desirable property of all PLLs is that the reference and feedback clock
edges be brought into very close alignment. The average difference in time between the phases of the two
signals when the PLLs has achieved lock is called static phase effect. The variance between this phases is
called tracking jitter. Ideally, the static phase offset should be zero and tracking should be as low as possible.

4.3 SOGI PLL

Phase Locked Loops (PLLs) are used as an important technique for grid synchronization and to track the phase
angle. For single phase synchronization Linear PLL is used, whereas for three phase grid synchronization,
PLLs based on Synchronous Reference Frame (SRF) are used. But SRF PLL fails to detect the phase angle
for unbalanced conditions . To detect the phase angle in abnormal grid conditions various advanced PLL
algorithms have been proposed like Double Synchronous Reference Frame (DSRF) PLL based on synthesis
circuit , Decoupled Double Synchronous Reference Frame (DDSRF) PLL etc. Enhanced PLL (EPLL) was
proposed that synchronizes the three phases separately and does not use the Synchronous Reference Frame .
The PLLs based on Synchronous Reference Frame uses Park’s Transformation which takes two orthogonal
signals as inputs and generates constant voltages. To generate orthogonal components Clarke’s transformation
is employed . The use of Second Order Generalized Integrator (SOGI) was proposed as an alternative of
Clarke’s transformation to generate orthogonal signals and then to use it for grid synchronization. Dual Second
Order Generalized Integrator – Frequency Locked Loop (FLL) was proposed as an advanced method for grid
synchronization. Other than orthogonal signal generation SOGIs can be used as current controller, to eliminate
harmonics and to detect multiple grid frequencies. Multiple Second Order Generalized Integrator – Frequency
Locked Loop (MSOGI FLL) was proposed in which estimate not only the positive and negative sequence
components at fundamental frequency but also other sequence components at multiple frequencies.

The PLL based on Second Order Generalized Integrator (SOGI) also separates and perfectly detects the phase
angle of positive and negative sequence components but with a much better dynamic response. The PLL struc-
ture involves Quadrature Signal Generation (QSG) with the use of SOGI as shown in Fig. 4. Two SOGI based
QSGs are used to obtain the in phase and quadrature components of the α axis (represented by αv' and α qv'
respectively) and β axis (represented by β v' and β qv' respectively) voltages.

31
 Fig 4.2 SOGI based Quadrature Signal Generation

Fig 4.3 SOGI based PLL structure

1
𝑣𝛼+ = 2 (𝑣𝛼′ − 𝑞𝑣𝛽′ )

1
𝑣𝛼− = (𝑣𝛼′ + 𝑞𝑣𝛽′ )
2

1
𝑣𝛽+ = 2 (𝑣𝛽′ + 𝑞𝑣𝛼′ )

1
𝑣𝛽− = 2 (𝑣𝛽′ − 𝑞𝑣𝛼′ )

The α and β axis voltages of positive and negative sequence components so obtained are fed two separate
conventional SRF PLLs which separately obtain d and q axis voltages of two sequence components and hence
the corresponding phase angles are properly detected. The d and q axis voltage of the positive sequence com-
ponents are given by eqn given below

𝑣𝑑+ cos 𝜃ˆ+ sin 𝜃ˆ+ 𝑈+ cos 𝜃+

( + ) = [−sin 𝜃ˆ ]( )
𝑣𝑞 + cos 𝜃ˆ+ 𝑈− cos 𝜃−

𝑈 𝐶𝑂𝑆(𝜃 −𝜃ˆ )
= (𝑈+ 𝑆𝐼𝑁 (𝜃+ −𝜃ˆ+ ))
+ + +

4.4 Conclusion:
In this section introduction of PLL has been discussed. A brief introduction to SOGI PLL and mathematical
interpretation has been discussed.


32
Chapter 5
GRID CONTROL MECHANISM
5.1 Clarke and Park Transformation
Clarke and Park transformation are used in high performance architectures in three phase power system anal-
ysis. Current and voltage are represented in terms of space vector which is represented in a stationary reference
frame. Through the use of the Clarke transformation, the real and imaginary currents can be identified. The
Park transformation is used to realize the transformation of those real and imaginary currents from the station-
ary to the rotating reference frame.

A) Clarke Transformation
Let, iR, iY and iB are the instantaneous balanced three-phase currents. Then

𝑖𝑅 + 𝑖𝑌 + 𝑖𝐵 = 0

Current space vector can be represented in terms of phase currents as

𝑖̅ = 𝑘(𝑖𝑅 + 𝛼𝑖𝑌 + 𝛼 2 𝑖𝐵 )

where, α is an operator described earlier and k = Transformation constant. Figure shows space current vector
and its projection.

Fig 5.1 Current space vector and its projection

Space reference frame
The space vector defined can be expressed utilizing two-axis theory. The real part of the space vector
is equal to the instantaneous value of the direct-axis current component iα, and imaginary part is equal
to the quadrature-axis current component, iβ.
Current space vector in syn. Reference frame can be expressed as :
𝑖̅ = 𝑖𝛼 + 𝑖𝛽

33
 In symmetrical 3-phase machines, the direct and quadrature axis currents iα and iβ are fictitious quad-
rature-phase (2-phase) current components, which are related to the actual 3-phase currents as
1 1
𝑖𝛼 = 𝑘(𝑖𝑅 − 𝑖𝑌 − 𝑖𝐵 )
2 2
√3
𝑖𝛽 = 𝑘 (𝑖 − 𝑖𝐵 )
2 𝑌
In matrix form it can be written as

𝑖𝛼 𝑖𝑅
1 −0.5 −0.5
( )=𝑘∗ ∗ 𝑖𝑌
𝑖𝛽 0 0.866 −0.866 𝑖
𝐵

If 3 phase system is symmetrical

𝑖𝑅 + 𝑖𝑌 + 𝑖𝐵 = 0

Then,

1 1
𝑖𝛼 𝛼 = 𝑘(𝑖𝑅 − 𝑖𝑌 − 𝑖𝐵 )
2 2
The recommended value of
2
k=3

Thus, transformations from a 3-phase (R, Y, B) to a 2-phase (α,β) system is commonly known as Clarke
transformation.

𝑖𝛼 2 1 𝑖𝑅
−0.5 −0.5
( )= ∗ ∗ 𝑖𝑌
𝑖𝛽 3 0 0.866 −0.866 𝑖
𝐵

𝑖𝛼 𝑖𝑅
( ) = [clarke matrix] ∗ 𝑖𝑌
𝑖𝛽 𝑖𝐵

B)Park Transformation
General Rotating Reference Frame
Besides the stationary reference frame attached to the stator, current space vector equations can be formulated
in a general reference frame which rotates at a general speed wg as shown in Fig.5.2

34
 Fig 5.2 General Rotating Frame of Reference

If a general reference frame is used, with direct and quadrature axes x, y rotating at a general instantaneous
speed, , as shown in Fig.5.2 where 𝜃𝑔 is the angle between the direct axis of the stationary reference frame (α)
attached to the real axis (x) of the general reference frame, then, the current space vector in general reference
frame can be written as

𝑖̅𝑔 = 𝑖̅ 𝑒 −𝑗𝜃𝑔 = (ix + iy)

d-q Rotating Frame:

Fig 5.3 d-q rotating frame of reference

In (α,β) plane

𝜓 = 𝜓𝛼 + 𝜓𝛽

in (d,q) plane

𝜓 = 𝜓𝑑 + 𝜓𝑞

Angle between (d,q) and (α,β) is 𝜃

𝜓𝛽
sin𝜃=
𝜓𝑑

𝜓𝛼
cos𝜃=
𝜓𝑑

The following transformations are involved due to rotation of orthogonal d-q system

a) αβ to d-q : Park transformation

b) d-q to α-β: Clarke transformation

35
Transformation of α-β to d-q is done by

𝑑 𝑐𝑜𝑠𝜃 𝑠𝑖𝑛𝜃 𝛼
( )=[ ]∗ ( )
𝑞 −𝑠𝑖𝑛𝜃 𝑐𝑜𝑠𝜃 𝛽

Transformation of d-q to α-β is done by

𝛼 𝑐𝑜𝑠𝜃 −𝑠𝑖𝑛𝜃 𝑑
( )=[ ]∗ ( )
𝛽 𝑠𝑖𝑛𝜃 𝑐𝑜𝑠𝜃 𝑞

𝑐𝑜𝑠𝜃 𝑠𝑖𝑛𝜃
Park matrix= [ ]
−𝑠𝑖𝑛𝜃 𝑐𝑜𝑠𝜃

𝑑 𝑅
( ) = (𝑃𝑎𝑟𝑘 𝑀𝑎𝑡𝑟𝑖𝑥) ∗ (𝐶𝑙𝑎𝑟𝑘𝑒 𝑀𝑎𝑡𝑟𝑖𝑥) ∗ 𝑌
𝑞
𝐵

5.2 Current Control Strategy For Grid Connected Converters

SINGLE-PHASE grid-connected voltage-source converters (VSCs) are widely used in numerous applications,
e.g., active rectifiers , power quality improvement, distributed generation , more recently in battery chargers
of electric vehicles , and solid-state transformers . The control structures of such converters are normally of
the cascade configuration, where the outer loops are the dc-link voltage, or power controllers, and the inner
loop is the line current controller. Controlling the line current of such VSCs is very challenging as the reference
signal is time varying. A steady-state error normally arises if the proportional-integral (PI) regulator with the
feed forward line voltage in the stationary reference frame is used . Various approaches have been proposed
to enhance the tracking ability of the ac reference signal, e.g., hysteresis, variable band hysteresis , deadbeat ,
predictive, repetitive and proportional-resonant (PR) control schemes. among these stationary frame control-
lers, the PR scheme has been widely adopted as it provides an infinite gain at the operating frequency and can
be equipped with a standard pulse width modulation (PWM) with a fixed switching frequency. Although the
PR regulator has a simple structure and is well suited to both single- and three-phase systems, it also has some
inherit disadvantages. In practice, the non ideal PR regulator with a damping ratio is normally used to ensure
stable operation over a typical grid frequency variation range, while the controller gain at the resonant fre-
quency should be kept relatively high for enforcing a small steady-state error . Thus, the PR controller must
be carefully designed so as to avoid oscillation during the transient state and to also avoid destabilization when
the grid frequency increases beyond the cut-off frequency. Another class of the current control schemes is
based on the synchronous reference frame (dq), where the ac components in the stationary frame (αβ) are
transformed to the dc signals. Standard PI controllers can be used to obtain zero steady-state errors due to their
dc infinite gain. Then, the output components of the PI controllers in the dq-axes are transformed back to the
αβ-axes. Only the modulation signal in the real axis mα,ref is sent to the PWM.

5.2.1 Calculation of reference Current

Regulating the converter power exchange with the grid can be readily realised by controlling the phase and
amplitude of the converter current. Assuming that Vs = Vs sin(ωt) and i = I sin (ωt − θi) are the grid voltage
and converter current, respectively, the active and reactive powers can be defined as Substituting the active
and reactive powers with the corresponding reference values and performing some manipulations, gives the
reference current as , in which ωt and Vs are provided by a single-phase phase-locked loop (PLL).
36
P= 0.5*Vs I cos𝜃i

Q=0.5*Vs I sin𝜃𝑖

2 +𝑄 2
√𝑃𝑟𝑒𝑓 𝑟𝑒𝑓
𝑖𝑟𝑒𝑓 (𝑡) = 2 ∗ sin(𝜔𝑡 − arctan(𝑄𝑟𝑒𝑓 − 𝑃𝑟𝑒𝑓 )) ............................................................................[a]
𝑉𝑠

= Iref sin(𝜔𝑡 − 𝜃𝑟𝑒𝑓 )............................................................................................[b]

Besides its simplicity, providing a pure sinusoidal reference current (in condition that the PLL performs per-
fectly under non-ideal grid voltages) is another advantage of this method, which as a result the distortion of
grid voltage does not appear in the reference current.

5.2.2 Determining Reference Voltage

The reference voltage for the converter must be determined such that the converter current tracks its reference
waveform, as fast and accurate as possible. In the simplest form, that is, in an open-loop control system, the
reference voltage can be directly calculated from the voltage equation of the filter which is shown in equation
below.
𝑑𝑖(𝑡)
𝑣𝑠 (𝑡) − 𝑣(𝑡) = 𝑟𝐿 𝑖(𝑡) + 𝑙 ∗ ................................................................................................................[c]
𝑑𝑡
𝑑𝐼𝑖𝑟𝑒𝑓 [𝑛]
𝑣𝑟𝑒𝑓.𝑜𝑙 [𝑛] = 𝑣𝑠 [𝑛] − 𝐿. ..........................................................................................[d]
𝑑𝑡

Here ol stands for open loop control .The derivative part of can be calculated using the first-order approxima-
tion. This approximation may reduce the speed of the system, especially during transients and load changes.
To deal with the problem, given that the reference current of [a] is a pure sinusoidal waveform, it is possible
to directly replace the derivative of [a] in [d] and then convert it to the discrete form as

𝑣𝑟𝑒𝑓,𝑜𝑙 [𝑛] = 𝑣𝑠 [𝑛] − 𝜔𝐿𝐼𝑟𝑒𝑓 cos(𝜔𝑛𝑇𝑠 − 𝜃𝑟𝑒𝑓 )......................................................................................[e]

The open-loop current control leads to errors in the amplitude and the phase of the converter current. This
error mainly arises from modelling errors and uncertainties, such as neglecting the inductor resistance, rL, the
fact that vs[n] and vs(t) are equal only at sampling instants, and delays introduced by the analogue-to-digital
converters, the program execution and the PWM modulator. To achieve a zero steady-state error, a closed-
loop control system is mandatory. The AC-side current is a suitable feedback signal.

37
 Fig 5.4 Current control scheme

Δi[n] = i[n] − iref [n]......................................................................................................................................[f]

The current error sign determines whether the measured current is larger or smaller than the reference current.
When the current error is positive, a decrease, and when the current error is negative, an increase in the con-
verter current is required.Closed loop reference volatge can be given by

vref,cl [n] = vref.ol [n] + kΔi[n]........................................................................................................................[g]

where k is the gain of the closed-loop controller, which must be determined carefully to maintain the closed-
loop stability, while ensuring a fast and accurate tracking performance. In the proposed control law of [g], the
amplitude and the sign of the current error are both used to modify the open-loop reference voltage. For in-
stance, when the converter current is greater than the reference current, the current error will be positive and
the kΔi increases the reference voltage; therefore the converter current will be reduced. From the control point
of view, the open-loop term, vref,ol, reduces the feedback control effort, and offers faster and at the same time
smoother transient responses, especially at start-ups.

38
Chapter 6
INTRODUCTION TO WAIJUNG
"Waijung" or " ", a Thai slang for "so fast", is a Simulink Blockset that can be used to easily and automatically
generate C code from your Matlab/simulink simulation models for many kinds of microcontrollers (Targets).
Currently, Waijung has been designed specifically to support STM32F4 family of microcontrollers (STM32F4
Target) which is a Hi-Performance & DSP MCU from STMicroelectronics. Waijung Blockset and STM32F4
Target has been completely redesigned with many new features and improvements, based on our experiences
on developing RapidSTM32 Blockset and "real-world applications with ease of use" philosophy. The follow-
ings list some of the new features included in Waijung Blockset and STM32F4 Target.

6.1Features of Waijung Blockset

i) Low cost Hi-performance DSP hardware with variety of Plug-n-Play modules. Easily measure the execution time
of the target in real-time.

ii)No need to install any third party compilers.

iii)Easily add your own C code with the new Basic Custom Code block.

iv)Acquire real-time data to SD Card upto 8 GB upto 100kHz with high speed SD card write block.

v)Simple and highly flexible target setup.

vi) Improved user interface.

vii)More efficient code generation.

39
Chapter 7
SIMULATIONS AND FINAL RESULTS
7.1 Analysis of 5 level CHB Multi Level Inverter
A)Phase Disposed Control of 5 level MLI

Fig 7.1 Phase Disposed Inverter

40
 Fig 7.2 Pulse Generation for Phase Disposed scheme

Pulses Generated are as follows :

S1,S4

S6,S7

S5,S8

S2,S3
41
 Fig 7.3 Pulses for Phase disposed scheme

B)Phase Shifted MLI

Fig 7.3 Pulse generation for Phase shifted scheme

Fig 7.4 3 phase shifted inverter

42
 Fig 7.5 Pulses for Phase shifted Inverter

7.2 SOGI FLL

Fig 7.6 SOGI FLL control of grid

43
 Grid Voltage

Fig 7.7Grid voltage, Vα Vβ, wt

7.3 Analysis of Park Transformation

44
 Fig 7.8 Park Transformation

Inverter Output

wt

α-β

d-q-0 output

Fig 7.9 Inverter o/p ,wt, α-β, d-q-0 output

7.4 Grid side Control

45
Fig 7.10 current control scheme

Id

Iq

46
 abc phase voltage wave forms

Fig 7.11 Id Iq abc voltage waveforms

7.5 Analysis of Grid control mechanism at different Id Iq values

I) Id=-3 and Iq=0

Id and Iq response

47
 Grid V I

Fundamental Grid Voltage

PLL fundamental(Mag.)

48
 PLL fundamental (Angle)

Fig 7.12 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)

II) Id=+2 and Iq=0

Id and Iq response

Converter Voltage and Current

49
 Grid Voltage and current

Fundamental Grid voltage

PLL Fundamental(Mag.)

PLL Fundamental (Angle)

Fig 7.13 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)

50
III) Id=0 Iq=+3

51
 Fundamental Grid Voltage

PLL fundamental (mag.)

PLL fundamental(Angle)

Fig 7.14 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)

IV) Id=0 Iq =-3

Id and Iq

52
 converter voltage and current

Grid voltage and current

Fundamental grid volage

PLL fundamental(Mag.)

53
 PLL fundamental(Angle)

Fig 7.15 Id Iq , Grid V I, Converter V I, Fundamental (Mag and Angle)

Table 7.1 Responses of converter and grid for different Id Iq values

Id Iq Vinv Vgrid 𝛿
-3 0 90 89.81 -175◦
+2 0 90 89.81 176.15◦
0 +3 97.4 89.81 -180◦
0 -3 82.5 89.81 -180◦

7.6 Final Inverter + Grid

Fig 7.16 inverter with synchronised grid

54
Fig 7.16 one phase of 3 phase inverter

55
Chapter 8
CONCLUSIONS

56
References
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2) G. Murali Krishna, V.V.N Murthy, K. Lakshmi Ganesh:"THD Analysis of symmetrical and Asymmetrical
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3) Majid Sanatkar- Chayjani, Mohammad Monfared:"Simple digital current control strategy for single phase
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New
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58