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Experiments List
1. Realization of all Basic gates using Universal Gates (Both NAND and NOR) using multisim.
3. Realization of half/full adder and half/full subtractor using logic gates using multisim.
4. Design of a combinational circuit to convert from Binary to grey code converter and vice
versausing multisim.
6. To verify the truth table of one bit and two bit comparators by using logic Gates using multisim.
7. Design of MOD N counter (synchronos/Asynchronous) using IC 7476 using multisim.
Logic gates are primarily implemented using diodes or transistors acting as electronic switches. With
amplification, logic gates can be cascaded in the same way that Boolean functions can be
composed, allowing the construction of a physical model of all of Boolean logic, and therefore, all of
the algorithms and mathematics that can be described with Boolean logic.
Logic circuits include such devices as multiplexers, registers, arithmetic logic units (ALUs),
and computer memory, all the way up through complete microprocessors, which may contain more
than 100 million gates.
NAND and NOR gates can be used to realize all the operations of the basic gates. Hence it is called
as Universal gates.
Realisation of OR Operation
REALIZATION OF NOR As
AND Operation
OR Operation
NOT Operation
Questions:
To Simplify and realize a given Boolean Expression by using logic gates and universal gates.
BOOLEAN EXPRESSION:
1) Y A B C A BC A BC AB C AB C ABC
SIMPLIFICATION:
Y A B C A BC A BC AB C AB C ABC
A C ( B B ) A BC AB (C C ) ABC
A C A BC AB ABC
A (C BC ) A( B BC )
A (C B )(C C ) A( B B )( B C )
A C A B AB AC
C ( A A ) A B AB
C A B AB
C A B
Y C A B AB
Y C A B AB
C A B AB
C A B AB
Y Y C A B AB
A B C C A B Y=
C A B
0 0 0 1 0 1
0 0 1 0 0 0
0 1 0 1 1 1
0 1 1 0 1 1
1 0 0 1 1 1
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 0 0 0
Experiment 3
AIM:
INPUTS OUTPUTS
Realisation of Half Adder Using Basic Gates
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Realisation of Half Adder using NAND gates
A B C Sum(S) Carry(Cin)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Realisation of Full Adder using NAND gates.
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
INPUTS OUTPUTS
A B Difference(D) Borrow(Br)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Half Subtractor by using NAND gates only:
A B C Difference(D) Borrow(Br)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
Full Subtractor by using NAND gates only:
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Experiment 4
AIM:
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
CIRCUIT DIAGRAM:
B3
G3
B2
G2
B1
G1
B0
Go
Questions:
Circuit Diagram
Truth Table MUX/DEMUX
MUX USING NAND GATES ONLY:
INPUTS OUTPUT
A B I0 I1 I2 I3 Y
0 0 0 x x x 0
0 0 1 x x x 1
0 1 x 0 x x 0
0 1 x 1 x x 1
1 0 x x 0 x 0
1 0 x x 1 x 1
1 1 x x x 0 1
Questions:
Define Multiplexer
Define Demultiplexer
Explain the logic of implementing the Boolean function by using Multiplexer
AIM:
To verify the truth table of one bit comparators by using logic Gates
CIRCUIT DIAGRAM:
ONE-BIT COMPARATOR:
INPUT OUTPUT
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
EXERCISE:
Obtain the Expressions for one bit comparator by using K-Map method
Obtain the Expressions for two bit comparator by using K-Map method
Implement one bit comparator by using Nand gates only.
Implement the two bit comparator by using Nand gates only.
Define Magnitude Comparator
What are the functions of Cascading inputs in IC7485
Experiment 7
WAVE FORMS
TRUTH TABLE
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Qc Qb Qa Qc Qb Qa JC KC JB KB JA KA
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 0 0 0 X 1 0 X X 1
simplifications
CIRCUIT DIAGRAM
WAVE FORMS
Questions
Define Counter?
What is Binary ripple Counter?
What are synchronous counters?
What are Asynchronous counter?
Differentiate Between synchronous and Asynchronous counter
What are the applications of Counters?
What are the functions of MR1, MR2, MS1 and MS2 in IC7490?
What are clocked flip flop?
Define Excitation table?
Define State table?
Obtain the excitation table for JK Flip Flop , T- Flip Flop,D-Filp Flop
What are the functions of load and clear?
Experiment 8
Aim:
A. ALP to Byte and word data transfer in different addressing modes
A. ALP for the Byte and word data transfer in different addressing modes.
Question
.MODEL TINY
.CODE
MOV AX,1234h
MOV BX,7698h
ADD AL,31h ; for Division replace with
MUL BX ; DIV BX
MOV AH,4Ch
INT 21h
END
LCM of two numbers
.MODEL SMALL
.DATA
Num1 DW 0005h
Num2 DW 0002h
Ans DW ?
.CODE
MOV AX,@DATA
MOV DS, AX
MOV AX, Num1
MOV BX, Num2
MOV DX, 0000h
NEXT: PUSH AX
PUSH DX
DIV BX
CMP DX, 0000h
JZ LAST
POP DX
POP AX
ADD AX, Num1
JNC NEXT
INC DX
JMP NEXT
LAST: POP Ans+2
POP Ans
MOV AH, 4Ch
INT 21h
END
Experiment No.10