CMOS Static & Dynamic Logic Gates: NMOS Transistors in Series/Parallel Connection

NMOS Transistors in Series/Parallel Connection
Lecture 6 ◆Transistors can be thought as a switch controlled by its

gate signal
CMOS Static & Dynamic Logic ◆NMOS switch closes when switch control input is high
Gates A B
Peter Cheung X Y Y = X if A and B

Department of Electrical & Electronic Engineering
Imperial College London A
X B Y = X if A OR B
Y
Reading: Weste 1.5.5 & Rabaey pp189-210, 222-234
URL: www.ee.ic.ac.uk/pcheung/
E-mail: p.cheung@ic.ac.uk NMOS Transistors pass a “strong” 0 but a “weak” 1
PYKC 25-Jan-02 E4.20 Digital IC Design Lecture 6 - 1 PYKC 25-Jan-02 E4.20 Digital IC Design Lecture 6 - 2
PMOS Transistors in Series/Parallel Connection Static CMOS Circuit
◆ Basic CMOS combinational circuits consist of:

PMOS switch closes when switch control input is low
• Complementary pull-up (p-type) and pull-down (n-type)
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0

Static CMOS
Example Gate: NAND
Example Gate: NOR Complex Gate
◆ We can form complex combinational circuit

function in a complementary tree. The
procedure to construct a complementary tree is
as follow:-
• Express the boolean expression in an inverted
form
• For the n-transistor tree, working from the inner-
most bracket to the outer-most term, connect the
OR term transistors in parallel, and the AND
term transistors in series
• For the p-transistor tree, working from the inner-
most bracket to the outer-most term, connect the
OR term transistors in series, and the AND term
transistors in parallel
Example Gate: COMPLEX CMOS GATE Properties of Complementary CMOS Gates
V DD
1) High noise margins
:
B
V OH and V OL are at V DD and GND , respectively.
A
C 2) No static power consumption
:
There never exists a direct path betweenV DD and
D V SS ( GND ) in steady-state mode
.
OUT = D + A • (B+C)
3) Comparable rise and fall times:
A
D
(under the appropriate scaling conditions)
B C
Transistor Sizing Propagation Delay Analysis - The Switch Model
• for symmetrical response (dc, ac) R ON

=
• for performance
V DD VDD V DD
V DD
Input Dependent Rp Rp Rp
Rp
B 12
A B B
A 6 Focus on worst-case A F Rp
Rn
C 12 F CL
B A
Rn
CL F
D 6 • assume µn=3* µp (i.e. n-channel A
Rn Rn Rn
CL
A
F transistors has 3 times the A B
A 2 transconductance as that of p-
1 (b) 2-input NAND
D channel.) (a) Inverter (c) 2-input NOR
B 2 C 2 t p = 0.69 Ron C L
(assuming that C L dominates!)

What is the Value of Ron? Numerical Examples of Resistances for 1.2µm CMOS
For this process, Wp = 3*Wn for the same resistance
Analysis of Propagation Delay Design for Worst Case
V DD 1. Assume R n = R p = resistance of minimum V DD V DD

V DD
Rp Rp sized NMOS inverter
2. Determine “Worst Case Input” transition 1 1 B 4 B 12
A B
(Delay depends on input values) A 2 A 6
F A B
Rn C 4 C 12
CL 3. Example: t pL H for 2input NAND F
B - Worst case when only ONE PMOS Pulls 2
CL D 2 D 6
up the output node B
Rn F
- For 2 PMOS devices in parallel, the F
resistance is lower A 2
A A 2
2 D 1
t p L H = 0.69 R p C L D 1
A B 2 C 2
2-input NAND B 2 C 2
4. Example: t pH L for 2input NAND
- Worst case : TWO NMOS in series
t p H L = 0.69(2 R n ) C L
Here it is assumed that Rp = Rn
Fast Complex Gate - Design Techniques Fast Complex Gate - Design Techniques (2)
• Transistor Sizing: • Transistor Ordering

As long as Fan-out Capacitance dominates
critical path
• Progressive Sizing: critical path
Out CL
In 3 CL
MN M3 In 1 M1
In N CL
M1 > M2 > M3 > MN
C3 In 2 M2 C2 C2
In 3 M3 In 2 M2
Distributed RC-line
In 2 M2 C2
In 1 M1 C1 C3
In 3 M3
In 1 M1 C1
Can Reduce Delay with more than 30%!
(a) (b)
Fast Complex Gate - Design Techniques (3) Fast Complex Gate - Design Techniques (4)
• Im proved Logic Design • Buffering: Isolate Fan-in from Fan-out
CL CL
Example: Full Adder A Revised Adder Circuit
VDD
VD D V DD
Ci A B
A B VD D VDD A
A
B
Ci A B B A B Ci B
B VD D
A Kill
X
Ci "0" -Propagate A Ci
Ci A S Co
Ci S
Ci
A B B VD D A Ci
A B Ci A "1" -Propagate
Generate
Co B A B B A B Ci A
C o = AB + C i(A+B)
24 transistors
28 transistors
Ratioed Logic Ratioed Logic
VD D
V DD V DD VD D • N transistors + Load
Resistive
Resistive
Depletion PMOS
Load RL VT < 0 • V OH = V D D
Load Load Load RL
V SS
F F F
• V OL = R PN
In 1 In 1 In 1
In 2 PDN In 2 PDN In 2 PDN
In 3 In 3 In 3 F R PN + R L
V SS V SS VS S In 1
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
• Assymetrical response
In 2 PDN
In 3 • Static power consumption
Goal: to reduce the num ber of devices over complementary CMOS • t pL = 0.69 R L C L
V SS
Active Loads Psuedo NMOS
◆ Disadvantages of previous circuit :

• Almost twice as many transistors as equivalent NMOS implementation.
VD D V DD
• If there are too many series transistors in the tree, switching speed is
reduced.
Depletion PMOS ◆ Try a pseudo NMOS circuit:-
Load VT < 0 Load
V SS
F F
In 1 In 1
In 2 PDN In 2 PDN
In 3 In 3
V SS V SS
depletion load NMOS pseudo-NMOS ◆ The pull-up p-channel transistor is always conducting.
• Disadvantages: high d.c. dissipation & slow rise time.
Pseudo-NMOS NAND Gate Improved Loads (1)
V DD V DD
VDD
M1 M2
Out Out
A
A
B PDN1 PDN2
B
GND V SS V SS
Dual Cascode Voltage Switch Logic (DCVSL)

Example Dynamic Logic
◆ There is another class of logic gates which relies on the use of a clock signal. This class of
circuit is known as dynamic circuits. The clock signal is used to divide the gate operation into
two halves. In the first half, the output node is pre-charged to a high or low logic state. In the
Out second half of a clock cycle, the circuit evaluates the correct output state.
◆ When Ø is low, Z is charged to high. When Ø is high, n logic block evaluates input, and
conditionally discharges Z. This circuit adds series resistance to the pull-down n-channel
Out transistor, therefore the fall time is increased slightly.
◆ This circuit is dynamic because during evaluation, the output high level at Z is maintained by
the stray capacitance at the output node. If Ø stays high (i.e. evaluation period) for a long
time, Z may eventually discharge to a low logic level.
B B B B
A A
XOR-NXOR gate
Problem with Cascading Dynamic Logic CMOS Domino Logic
◆ Problem with cascading such as a circuit:- ◆ Solution to the above problem:-

• Inputs can only be changed when Ø is low and must be stable when Ø is high. • Add an inverter to ensure that the output is low
• When Ø is low, both P1 and P2 are precharged to a high voltage. However when Ø is during precharge, and prevent the next stage
high, delay through on the output P1 may erroneously discharge P2. from evaluating, until the current stage has
finished evaluation.
• This ensures that each stage (at the output of
the inverter) will make at most a single
transition from 0 -> 1.
• When many stages are cascaded, evaluation
proceeds from one stage to the next - similar
to dominos falling one after another.
◆ Disadvantages of domino logic:-
• Only non-inverting logic is possible, i.e. output
also high active
• Each gate needs an inverter; hence more
transistors
• Suffer from charge sharing effect (considered
later)
Alternating dynamic logic (1) Alternating dynamic logic (2)
◆ Another possible scheme is to use alternate n and p logic blocks as shown below.
◆ A slight variation of this circuit is show below, where an inverter is added per stage to
◆ In this scheme, each alternate stage is pre-charged high and low. Each stage uses
increase flexibility. Here each stage can drive either n or p blocks and both low active and
alternate n and p transistors to implement the gate function. Stage 1 makes at most one
high active logic can be implemented.
high to low transition, while stage 2 makes at most one low to high transition for each
evaluation. Since the p logic block will only change state if input is a low, this circuit
behaves like the domino logic.
Making a Dynamic Gate static Pass Transistor Logic
◆ An alternative design style is to use pass transistors. The following is an example of a

◆ Finally, by adding a feedback pullup, we can make the circuit static. multiplexer.
◆ This circuit turns the originally dynamic gate into a static gate because the feedback ◆ Complementary transmission gates are used here because n-channel pass transistors will
transistor can maintain a logic high level at the node Z for an indefinite length of time. pass 0 logic level well but, 1 logic level poorly. This is because in order for the n-transistor
Without this feedback transistor, the charge stored at the node Z will eventually leak away. to be ON, Vgs must be greater than Vth. Therefore each series n transistor will degrade the
1 logic level by Vth. The opposite is true with p-channel pass transistors: 0 logic level is
passed poorly.
Pass Transistor Logic with feedback Pass Transistor XOR gate
◆ Pass transistor logic can sometimes be very economical in implementing logic

◆ This circuit uses only n transistors, therefore it is economical on transistor count.
functions. For example, an XOR gate can be implemented with just two
In order to ensure that the 1 logic level is passed properly, a p pull-up transistor
transmission gates:-
is added. This restores the 1 logic level at the input of the inverter.
4-input NAND Gate Standard Cell Layout Methodology
Vdd
VD D
In 2 In 3 In 4 metal1 VD D
In 1
Out
In 1
Well
In 2
Out
In 3
In 4 V SS
Routing Channel
GND signals
polysilicon
In1 In2 In3 In4
Two Versions of (a+b).c Logic Graph
VD D
VD D V DD
x
b PUN
j c c
x
x a i
x VD D
GND GND x
b j a
a c b a b c c
i PDN
GND
(a) Input order {a c b} (b) Input order {a b c} a b
Consistent Euler Path Example: x = ab+cd

x x
x
b c b c
c x V DD x VD D
i a d a d
x V DD
GND GND
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d }

b a
j VD D
x
GND
GND
a b c d
{ a b c} (c) stick diagram for ordering {a b c d}

CMOS Static & Dynamic Logic Gates: NMOS Transistors in Series/Parallel Connection

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NMOS Transistors in Series/Parallel Connection

Lecture 6 ◆Transistors can be thought as a switch controlled by its

Peter Cheung X Y Y = X if A and B

PMOS Transistors in Series/Parallel Connection Static CMOS Circuit

◆ Basic CMOS combinational circuits consist of:

PMOS Transistors pass a “strong” 1 but a “weak” 0

Example Gate: NOR Complex Gate

◆ We can form complex combinational circuit

Transistor Sizing Propagation Delay Analysis - The Switch Model

• for symmetrical response (dc, ac) R ON

(assuming that C L dominates!)

For this process, Wp = 3*Wn for the same resistance

Analysis of Propagation Delay Design for Worst Case

V DD 1. Assume R n = R p = resistance of minimum V DD V DD

• Transistor Sizing: • Transistor Ordering

• Im proved Logic Design • Buffering: Isolate Fan-in from Fan-out

Ratioed Logic Ratioed Logic

◆ Disadvantages of previous circuit :

Pseudo-NMOS NAND Gate Improved Loads (1)

Dual Cascode Voltage Switch Logic (DCVSL)

Problem with Cascading Dynamic Logic CMOS Domino Logic

◆ Problem with cascading such as a circuit:- ◆ Solution to the above problem:-

Making a Dynamic Gate static Pass Transistor Logic

◆ An alternative design style is to use pass transistors. The following is an example of a

◆ Pass transistor logic can sometimes be very economical in implementing logic

4-input NAND Gate Standard Cell Layout Methodology

Consistent Euler Path Example: x = ab+cd

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d }

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