VLSI DESIGN

Design

Realization of desired specifications into configuration is a Design.

IC(Integarted Chip)

An integrated circuit (IC), sometimes called a chip or microchip, is a semiconductor wafer on which
thousands or millions of tiny resistors, capacitors, and transistors are fabricated.

IC Design Flow

 System Specifications

The specification of a system is considered based on the customer requirements and economical
viability.

(OR)

The specification of a system is considered based on the market requirements, technology and
economical viability.

The factors to be considered in this process include: performance, functionality, and physical
dimensions (size of the die (chip)). The fabrication technology and design techniques are also
considered.

 Architectural Design
The basic architecture of the system is designed in this step. This includes decisions such as RISC
(Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer), number of
ALUs, Floating Point units, number and structure of pipelines, and size of caches among others.

 Functional Design
In Functional Deisgn, main functional units of the system are identified. This also identifies the
interconnect requirements between the units. The area, power, and other parameters of each unit are
estimated.
The outcome of functional design is usually a timing diagram or other relationships between units.

 Logic Design

In Logic Design, control flow, word widths, register allocation, arithmetic operations, and logic
operations of the design that represent the functional design are derived and tested. This description is
called Register Transfer Level (RTL) description.

RTL is expressed in a Hardware Description Language (HDL), such as VHDL or Verilog. This
description can be used in simulation and verification. This description consists of Boolean
expressions and timing information. The Boolean expressions are minimized to achieve the smallest
logic design which conforms to the functional design. This logic design of the system is simulated and
tested to verify its correctness.

 Circuit Design

The purpose of circuit design is to develop a circuit representation based on the logic design. The
Boolean expressions are converted into a circuit representation by taking into consideration the speed
and power requirements of the original design. Circuit Simulation is used to verify the correctness and
timing of each component.

 Physical Design
In this step the circuit representation (or netlist) is converted into a geometric representation. As stated
earlier, this geometric representation of a circuit is called a layout. Layout is created by converting
each logic component (cells, macros, gates, transistors) into a geometric representation (specific
shapes in multiple layers), which perform the intended logic function of the corresponding
component. Connections between different components are also expressed as geometric patterns
typically lines in multiple layers.

 Fabrication
After layout and verification, the design is ready for fabrication. Since layout data is typically sent to
fabrication on a tape, the event of release of data is called Tape Out. Layout data is converted (or
fractured) into photo-lithographic masks, one for each layer. Masks identify spaces on the wafer,
where certain materials need to be deposited, diffused or even removed.
The fabrication process consists of several steps involving deposition, and diffusion of various
materials on the wafer.
  Packaging, Testing and Debugging:

Finally, the wafer is fabricated and diced into individual chips in a fabrication facility. Each chip is
then packaged and tested to ensure that it meets all the design specifications and that it functions
properly.

Processor Specifications:

 Speed-Processor speed is measured in MIPs and GFLOPS.

MIPS- It is defined as the number of machine instructions (in millions) that a processor can
execute in one second.

FLOPS- Useful in fields of scientific computations that require floating-point calculations.

 Internal registers-used internally for processor operations.

i) Instruction register, holding the instruction currently being executed.

ii) Registers related to fetching information from RAM, a collection of storage
registers located on separate chips from the CPU:

a) Memory buffer register (MBR)

b ) Memory data register (MDR)

c) Memory address register (MAR)

 Data input and output bus-the processor, main memory, and I/O devices can be
interconnected through common data communication lines which are termed as common bus.

The primary function of a common bus is to provide a communication path between the
 devices for the transfer of data. The bus includes the control lines needed to support interrupts
and arbitration.

 Memory - Semiconductor memory specifications enable the performance of a particular

memory IC to be defined.The specifications associated with different types of semiconductor
memory may also determine what family of memories should be used, and within the family,
which particular device.

1. Key memory specifications

There are many semiconductor memory parameters that can be specified. Normally these all appear in the
datasheet for a given memory. However some of the key memory specifications are outlined below:

 Memory type: Obviously the type of memory has a major bearing on the application. Different
memories have different properties and therefore significantly different specifications and parameters.
The various types of semiconductor memories are

1) RAM - Random Access Memory: As the name suggest, the RAM or random access memory is
a form of semiconductor memory technology that is used for reading and writing data in any order
as required. It is used for applications such as the computer or processor memory , where
variables and other stored and are required on a random basis. Data is stored and read many
times to and from this type of memory.
2) ROM - Read Only Memory: A ROM is a form of semiconductor memory technology used where
the data is written once and then not changed. In view of this it is used where data needs to be
stored permanently, even when the power is removed

As a result, this type of semiconductor memory technology is widely used for storing programs and
data that must survive when a computer or processor is powered down.

 Memory size specification: The specification for the memory size is possibly the most key
parameters to be specified. The way in which the memory is specified is standardized by JEDEC
(JEDEC Standard 100B.01) and this format is used virtually universally for memory specifications:

 Memory speed: Another key memory specification is the memory speed. This is normally quoted as
the rate at which the memory can be clocked and is given as a frequency, e.g. 400 MHz, etc.. Often the
speed will be incorporated into the memory type. For example for DDR style memories it is appended to
the memory style ID, e.g. DDR-400 is a 400 MHz memory. However it is important to note that the real
clock of DDR style memories is half that of the labelled clock speed - DDR-400 memories operate at
200 MHz.

 Memory timing specifications: This category of memory specifications is of great importance

because it will often determine the overall speed of operation of a processor system. If large amounts of
data need to be accessed then the speed of recovery is crucial. Delays will slow the operation of the
system. There are a number of different types of memory speed specification, and they will be
dependent upon the type of memory used.

Peripheral:-
A peripheral device is "an ancillary device used to put information into and get information out of the computer."[1]
Three categories of peripheral devices exist based on their relationship with the computer:

1) an input device sends data or instructions to the computer, such as a mouse, keyboard, graphics
tablet, image scanner, barcode reader, game controller, light pen, light gun, microphone, digital
camera, webcam, dance pad, and read-only memory.
2) an output device provides output from the computer, such as a computer monitor, projector, printer,
and computer speaker.
 3) an input/output device performs both input and output functions, such as a computer data
storage device (including a disk drive, USB flash drive, memory card, and tape drive) and
a touchscreen.
4) Many modern electronic devices, such as digital watches, smart phones, and tablet computers, have
interfaces that allow them to be used as computer peripheral devices.

Bus (computing)
In computer architecture, a bus[1] (a contraction of the Latin omnibus) is a communication
system that transfers data between components inside a computer, or between computers. This
expression covers all related hardware components (wire, optical fiber, etc.) and software, including
communication protocols.[2]
Early computer buses were parallel electrical wires with multiple hardware connections, but the term is
now used for any physical arrangement that provides the same logical function as a parallel electrical bus.
Modern computer buses can use both parallel and bit serial connections, and can be wired in either
a multidrop (electrical parallel) or daisy chain topology, or connected by switched hubs, as in the case of USB.

Types of Buses in Computer Architecture:-

There are a variety of buses found inside the computer.

1) Data Bus: The data bus allows data to travel back and forth between
the microprocessor (CPU) and memory (RAM).
2) Address Bus: The address bus carries information about the location of data in memory.
3) Control Bus : The control bus carries the control signals that make sure everything is flowing
smoothly from place to place.
4) Expansion Bus: If your computer has expansion slots, there's an expansion bus. Messages
and information pass between your computer and the add-in boards you plug in over the
expansion bus.

Low power design techniques

An integrated low power methodology requires optimization at all design abstraction layers as mentioned below.
1. System: Partitioning, Power down
2. Algorithm: Complexity, Concurrency, Regularity
3. Architecture: Parallelism, Pipelining, Redundancy, Data Encoding
4. Circuit Logic: Logic Styles, Energy Recovery, Transistor Sizing
5. Technology: Threshold Reduction, Multithreshold Devices.

Dynamic power varies as VDD2. So reducing the supply voltage reduces power dissipation. Also
selective frequency reduction technique can be used to reduce dynamic power. Multi threshold voltage can be
used to reduce leakage power at system level. Transistor resizing can be used to speed-up circuit and reduce
power. Parallelism and pipelining in system architecture can reduce power significantly. Clock disabling, power-
down of selected logic blocks, adiabatic computing, software redesign to lower power dissipation are the other
techniques commonly used for low power design
 Chipset
In a computer system, a chipset is a set of electronic components in an integrated
circuit known as a "Data Flow Management System" that manages the data flow between
the processor, memory and peripherals. It is usually found on the motherboard. Chipsets are usually
designed to work with a specific family of microprocessors. Because it controls communications
between the processor and external devices, the chipset plays a crucial role in determining system
performance.
The best chipset manufacturers:-

1) Intel
2) Qualcomm
3) Media tek
4) AMD
5) Nvidia

Snapdragon is a suite of system on a chip (SoC) semiconductor products for mobile devices
designed and marketed by QualcommTechnologies Inc. The Snapdragon central processing
unit (CPU) uses the ARM RISC instruction set, and a single SoC may include multiple CPU cores,
a graphics processing unit (GPU), a wireless modem, and other software and hardware to support a
smartphone's global positioning system (GPS), camera, gesture recognition and video.

Samsung Chipsets:-

I. It’s no secret that Samsung uses both its own Exynos chipset as well as Qualcomm’s
Snapdragon.

II. The most popular chipset, the Exynos 8890, is used in the Galaxy S7 and S7 Edge. Despite
Samsung’s effort to reduce its reliance on Qualcomm and its patents, the Snapdragon
continues to appear in various Samsung models.

Apple Chipsets :-

The Apple A4 is a package on package (PoP) system on a chip (SoC) designed by Apple Inc. and
manufactured by Samsung.

The Apple A5 is a system on a chip (SoC) designed by Apple Inc. and manufactured
by Samsung[27] that replaced the A4.

Others Chipsets :-

i. BCM2xxxx by Broadcom
ii. A31 by AllWinner
iii. Atom by Intel
iv. Exynos by Samsung
v. i.MX by Freescale Semiconductor
vi. Jaguar and Puma by AMD
vii. MTxxxx by MediaTek
viii. NovaThor by ST-Ericsson
ix. OMAP by Texas Instruments
 x. RK3xxx by Rockchip
xi. Snapdragon by Qualcomm
xii. Tegra by Nvidia

SOC(System On Chip)

An SOC (System on Chip) design of modern times consists of high level of integration of several
design components (also known as IP -Intellectual property) which is possible with the shrinking
process technologies.

A typical SOC design might include one or more programmable components such as general-purpose
processors cores, digital signal processor cores, or application-specic intellectual property (IP) cores,
as well as an analog front end, on-chip memory, IO devices, and several other application-specific
circuits.

One of the biggest challenge in SOC design is the on chip communication between the different
components. The different bus protocols used for interconnection has a big impact on the
performance of the SOC design

Most of the times, the IP cores are designed with many different interfaces and communication
protocols and this can be a problem while integrating into an SOC. To avoid this problem, standard
on-chip bus structures and protocols were developed. Some of the publicly available bus architectures
from leading manufacturers are CoreConnect from IBM , AMBA from ARM , SiliconBackplane from
Sonics.
IP/VIP(Intelluctual Property/ Verificatin Intelluctual IP)

An IP is a reusable unit of logic cell or Integrated circuit and is often used as the basic building block
in ASIC or FPGA.

Verification IP or VIP is also a reusable unit of logic often being interfaced into a Testbench
environment to verify the DUT functionality or protocols of the design unit or IP.

VIP often comes with a test suite and coverage metrics which shorten the time span for SOC and IP
Verification.

Various IP cores Available are-

HBM-High Bandwidth Memory (HBM)

It is a high-performance RAM interface for 3D-stacked DRAM from AMDand Hynix. It is to be used
in conjunction with high-performance graphics accelerators and network devices.[1] The first devices
to use HBM are the AMD Fiji GPUs.High Bandwidth Memory has been adopted by JEDEC as an
industry.
HBM achieves higher bandwidth while using less power in a substantially smaller form factor
than DDR4 or GDDR5.[6] This is achieved by stacking up to eight DRAM dies, including an optional
base die with a memory controller, which are interconnected by through-silicon vias (TSV) and
microbumps. The HBM technology is similar in principle but incompatible with the Hybrid Memory
Cube interface developed by Micron Technology.[7]
USB
USB (abbreviation of Universal Serial Bus), is an industry standard that was developed to define
cables, connectors and protocols for connection, communication, and power supply between personal
computers and their peripheral devices.[3]
There have been three generations of USB specifications:

 USB 1.x
 USB 2.0, with multiple updates and additions
 USB 3.x
Where are the USB ports?

All modern computers have at least one USB port. Below is a list of the typical locations in which you
can find them.
 Desktop computer - A desktop computer usually has two to four ports in the front and two to
eight ports in the back.

 Laptop computer - A laptop computer has between one and four ports on the left, right, or
both sides of the laptop.

 Tablet computer - The USB connection on a tablet is located in the charging port and is
usually micro USB and sometimes USB-C. Some tablets have additional ports USB ports.

 Smartphone - Similar to tablets, the USB port on smartphones is used for both charging and
data transfer in the form of USB-C or micro USB.

USB devices:-

 Digital Camera
 External drive
 iPod or other MP3 player
 Keyboard
 Keypad
 Microphone
 Mouse
 Printer
 Joystick
 Jump drive aka Thumb drive
 Scanner
 Smartphone
 Tablet
 Webcams
USB transfer speeds:-

USB 1.x---data transfer rates of 12 Mbps

USB 2.0, also known as hi-speed USB and transfer rate of up to 480 megabits per second

USB 3.0, also known as SuperSpeed USB and transfer rates up to 5.0 gigabits per second

USB 3.1, also known as SuperSpeed+ and transfer rates of up to 10 Gbps

first generation of Apple's Thunderbolt channel

DDR(Double Data Rate)

It is an advanced version of SDRAM, a type of computer memory. DDR-SDRAM, sometimes called

"SDRAM II," can transfer data twice as fast as regular SDRAM chips. This is because DDR memory
can send and receive signals twice per clock cycle. The efficient operation of DDR-SDRAM makes
the memory great for notebook computers since it uses up less power.

DDR SDRAM is a double data rate synchronous dynamic random-access memory class of
memory integrated circuits used in computers. DDR SDRAM, also called DDR1 SDRAM, has been
superseded by DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM. None of its successors
are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, and
DDR4 memory modules will not work in DDR1-equipped motherboards, and vice versa.

PCI Express:-

PCI Express, technically Peripheral Component Interconnect Express but often seen abbreviated
as PCIe or PCI-E, is a standard type of connection for internal devices in a computer.

Generally, PCI Express refers to the actual expansion slots on the motherboard that accept PCIe-based
expansion cards and to the types of expansion cards themselves.

PCI Express has all but replaced AGP and PCI, both of which replaced the oldest widely-used
connection type called ISA.

How Does PCI Express Work?

Similar to the older standards like PCI and AGP, a PCI Express based device (like the one shown in
the photo on this page) physically slides into a PCI Express slot on the motherboard.

The PCI Express interface allows high bandwidth communication between the device and the
motherboard, as well as other hardware.

While not very common, an external version of PCI Express exists as well, unsurprisingly
called External PCI Express but often shortened to ePCIe.

What Types of PCI Express Cards Exist?

1. video cards
2. sound cards
3. network interface cards
Camera Link:-
Camera Link is a serial communication protocol standard[1] designed for camera interface applications
based on the National Semiconductor interface Channel-link. It was designed for the purpose of
standardizing scientific and industrial video products including cameras, cables and frame grabbers.
The standard is maintained and administered by the Automated Imaging Association or AIA, the
global machine vision industry's trade group.

Base configuration
I. The "Base" Camera Link configuration carries signals over a single connector/cable
II. At the maximum chipset operating frequency (85 MHz), the base configuration yields a video
data throughput of 2.04 Gbit/s (255 MB/s).

Medium/Full configuration
The Camera Link specification includes higher-bandwidth configurations that provide additional
video data paths over a second connector/cable. The "Medium" configuration doubles the video
bandwidth, adding 24 bits of data and the same 4 framing/enable bits present in the "Base"
configuration.
Deca configuration
Some camera and data acquisition hardware manufacturers have extended the bandwidth of the
interface beyond the limits imposed by the Camera Link interface specification.
The 80-bit video path can carry 6.8 Gbit/s (850 MB/s).

DisplayLink:-
DisplayLink (formerly Newnham Research) is a semiconductor and software technology company.
DisplayLink USB graphics technology is designed to connect computers and displays using USB,
Ethernet, and WiFi.

Technology:-
1. The DisplayLink network graphics technology is composed of Virtual Graphics Card (VGC)
software that is installed on a PC and a Hardware Rendering Engine (HRE) embedded or
connected to a display device. The DisplayLink VGC software is based on a proprietary
adaptive graphics technology.
2. Products with DisplayLink technology are supported on Windows 10, Windows 8, Windows
7, Windows Vista, Windows XP, Mac OS X, Android, Chrome OS and Ubuntu GNU/Linux.
 VERIFICATION

Verification is to check whether a chip is designed to its functional specification. Once the
functionality is verified, the design can be sent out to fabrication. In otherwords, Verification is to
assure that Design is Without Bugs.

During fabrication, some chips will end up with defect (just like any manufacturing process). The goal
of testing is to sort out good parts from defective ones.

Verification is done before implementation of design on actual hardware to make sure the product
works BEFORE you've created the product.

Verification Methodology Timeline

Verification Environment or Test Bench

Verification Environment or Testbench is used to check the functional correctness of

the Design Under Test (DUT) by generating and driving a predefined input sequence to a design,
capturing the design output and comparing with-respect-to expected output.

Below is the list of verification environment components,

 Transaction item
 Generator
 Driver
 Monitor
 Agent
 Scoreboard
 Environment
 Test_case
 Testbench_top

Testbench_top
In verification environment, separate class's will be written to perform specific operation i.e,
generating stimulus, driving, monitoring etc. and those class will be named based on the operation.

Below is the list of class's that the typical verification environment can have,
 Synthesis

In electronics, logic synthesis is a process by which an abstract form of

desired circuit behavior, typically at register transfer level (RTL), is turned into a design
implementation in terms of logic gates, typically by a computer program called a synthesis tool.
Common examples of this process include synthesis of HDLs, including VHDL and Verilog.[1] Some
synthesis tools generate bitstreams for programmable logic devices such as PALs or FPGAs, while
others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

 Synopsys' Design Compiler family of products maximizes productivity with its complete
solution for RTL synthesis and test

There are 3 steps in Synthesis:

1. Translation: RTL code is translated to technolohgy independent representation. The converted
logic is available in boolean equation form.
2. Optimization: Boolean equation is optimized using SoP or PoS optimization methods.
3. Technology mapping: Technology independent boolean logic equations are mapped to
technology dependant library logic gates based on design constraints, library of available
technology gates. This produces optimized gate level representation which is generally
represented in Verilog.

TOOLS:-

 Design Compiler Graphical

 DC EXPORER
 DC Ultra
 POWER Compiler

Design for testability(DFT)

DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to
insert scan using top-down and bottom-up flows. The workshop explores essential techniques to
support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the
logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-
down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing
functional pins for scan testing, inserting an On-Chip Clocking (OCC) controller for At-Speed testing
using internal clocks; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to
reduce the test time and the test data volume required for a given fault coverage.

• Assure the detection of all faults in a circuit.

• Reduce the cost and time associated with test development.
• Reduce the execution time of performing test on fabricated chips.
We will focus on DFT techniques for digital logic, although it is relevant for
memory and analog/mixed-signal components as well.
An example chip level DFT technique is called Built-in self-test (BIST)
(used for digital logic and memory.)
At the system level, DFT includes boundary scan and analog test bus.
The DFT techniques discussed focus on improving testability of SAFs.
DFT for other fault models, e.g., delay faults, is described in the literature.

Synopsys Tools Used

 DFT Compiler 2017.09-SP3

 Design Vision 2017.09-SP3
 Design Compiler 2017.09-SP3
 TetraMAX 2017.09-SP3
Physical Design
1. Partitioning: A chip may contain several million transistorsDue to the limitations of memory
space and computation power available it may not be possible to layout the entire chip (or
generically speaking any large circuit) in the same step.
2. Floorplanning and Placement: This step is concerned with selecting good layout
alternatives for each block, as well as the entire chip. The area of each block can be estimated
after partitioning and is based approximately on the number and the type of components in
that block.
3. Routing: The objective of the routing phase is to complete the interconnections between
blocks according to the specified netlist. First, the space not occupied by the blocks (called
the routing space) is partitioned into rectangular regions called channels and switchboxes.
This includes the space between the blocks as well the as the space on top of the blocks.
4. Compaction: Compaction is simply the task of compressing the layout in all directions such
that the total area is reduced. By making the chip smaller, wire lengths are reduced, which in
turn reduces the signal delay between components of the circuit.
5. Extraction and Verification: Design Rule Checking (DRC) is a process which verifies that
all geometric patterns meet the design rules imposed by the fabrication process. For example,
one typical design rule is the wire separation rule. That is, the fabrication process requires a
specific separation (in microns) between two adjacent wires.
 Physical Verification

Physical verification is a process whereby an integrated circuit layout (IC layout) design is checked
via EDA software tools to see if it meets certain criteria.Verification involves design rule check
(DRC), layout versus schematic (LVS), electrical rule check (ERC), XOR (exclusive OR), and
antenna checks.

1. DRC
DRC checks determine if the layout satisfies a set of rules required for manufacturing. The most
common of these are spacing rules between metals, minimum width rules, via rules etc.There
will also be specific rules pertaining to your technology. An input to the design rule tool is a
‘design rule file’ (called a runset by Synopsys’ hercules). The design rules ensure sufficient
margins to correctly define the geometries without any connectivity issues due to proximity in
the semiconductor manufacturing processes, so as to ensure that most of the parts work correctly.
DRC checking software are Assura, Hercules or Calibre.

2.LVS
LVS is another major check in the physical verification stage. Here you are verifying that the layout
you have created is functionally the same as the schematic/netlist of the design-that you have correctly
transferred into geometries your intent while creating the design. So all the connections should be
proper and there shouldn’t any missing connections etc.

The LVS tool creates a layout netlist, by extracting the geometries. This layout netlist is compared
with the schematic netlist. The tool may require some steps to create either of these netlists(e.g.
nettran run in synopsys)
If the two netlists match, we get an LVS clean result.

Some of the LVS errors are:

 Shorts – Wires that should not be connected are overlapping.

 Opens – Connections are not complete for certain nets.
 Parameter mismatch – LVS also checks for parameter mismatches. e.g. It may match a resistor
in both layout and schematic, but the resistor values may be different. This will be reported as a
parameter mismatch.
 Unbound pins – If the pins don’t have a geometry, but all the connection to the net are made,
and unbound pin is reported.
3.ERC
ERC (Electrical rule check) involves checking a design for all electrical connections that are
considered dangerous.
 Floating gate error – If any gate is unconnected, this could lead to leakage issues.
 VDD/VSS errors – The well geometries need to be connected to power/Ground and if the PG
connection is not complete or if the pins are not defined, the whole layout can report errors
like “NWELL not connected to VDD.

4.Antenna checks

Process antenna effect or “plasma induced gate oxide damage” is a manufacturing effect. i.e. this is a
type of failure that can occur solely at the manufacturing stage. This is a gate damage that can occur
due to charge accumulation on metals and discharge to a gate through gate oxide
 An IC Fabrication

Steps for in fabrication

Step 1

Wafer production

The first step is wafer production. The wafer is a round slice of semiconductor material such as
silicon. Silicon is preferred due to its characteristics. It is more suitable for manufacturing IC. It is the
base or substrate for entire chip. First purified polycrystalline silicon is created from the sand. Then it
is heated to produce molten liquid. A small piece of solid silicon is dipped on the molten liquid. Then
the solid silicon (seed) is slowly pulled from the melt. The liquid cools to form single crystal ingot. A
thin round wafer of silicon is cut using wafer slicer. Wafer slicer is a precise cutting machine and each
slice having thickness about .01 to .025inches. When wafer is sliced, the surface will be damaged. It
can be smoothening by polishing. After polishing the wafer, it must thoroughly clean and dried. The
wafers are cleaned using high purity low particle chemicals .The silicon wafers are exposed to ultra
pure oxygen.
Epitaxial growth

It means the growing of single silicon crystal upon original silicon substrate. A uniform layer of
silicon dioxide is formed on the surface of wafer.

Step 2

Masking

To protect some area of wafer when working on another area, a process called photolithography is
used. The process of photolithography includes masking with a photographic mask and photo etching.
A photoresist film is applied on the wafer. The wafer is aligned to a mask using photo aligner. Then it
is exposed to ultraviolet light through mask. Before that the wafer must be aligned with the mask.
Generally, there are automatic tools for alignment purpose.

Step 3

Etching

It removes material selectively from the surface of wafer to create patterns. The pattern is defined by
etching mask. The parts of material are protected by this etching mask. Either wet (chemical) or dry
(physical) etching can be used to remove the unmasked material. To performetching in all directions
at same time, isotropic etching will be used. Anisotropic etching is faster in one direction. Wet etching
is isotropic, but the etching time control is difficult. Wet etching uses liquid solvents for removing
materials. It is not suited to transfer pattern with submicron feature size. It does not damage the
material. Dry etching uses gases to remove materials. It is strongly anisotropic. But it is less
selective. It is suited to transfer pattern having small size. The remaining photo resist is finally
removed using additional chemicals or plasma. Then the wafer is inspected to make sure that the
image is transferred from mask to the top layer of wafer.

Step 4

Doping

To alter the electrical character of silicon, atom with one less electron than silicon such as boron and
atom with one electron greater then silicon such as phosphorous are introduced into the area. The P-
type (boron) and N-type (phosphorous) are created to reflect their conducting characteristics.
Diffusion is defined as the movement of impurity atoms in semiconductor material at high
temperature.

Atomic diffusion

In this method p and n regions are created by adding dopants into the wafer. The wafers are placed in
an oven which is made up of quartz and it is surrounded with heating elements. Then the wafers are
heated at a temperature of about 1500-2200°F. The inert gas carries the dopant chemical. The dopant
and gas is passed through the wafers and finally the dopant will get deposited on the wafer. This
method can only be used for large areas. For small areas it will be difficult and it may not be accurate.

Ion implantation

This is also a method used for adding dopants. In this method, dopant gas such as phosphine or boron
trichloride will be ionized first. Then it provides a beam of high energy dopant ions to the specified
regions of wafer. It will penetrate the wafer. The depth of the penetration depends on the energy of the
beam. By altering the beam energy, it is possible to control the depth of penetration of dopants into
the wafer. The beam current and time of exposure is used to control the amount of dopant. This
method is slower than atomic diffusion process. It does not require masking and this process is very
precise. First it points the wafer that where it is needed and shoot the dopants to the place where it is
required.

Step 5

Metallization

It is used to create contact with silicon and to make interconnections on chip. A thin layer of
aluminum is deposited over the whole wafer. Aluminium is selected because it is a good conductor,
has good mechanical bond with silicon, forms low resistance contact and it can be applied and
patterned with single deposition and etching process.

Assembly and packaging

Each of the wafers contains hundreds of chips. These chips are separated and packaged by a method
called scribing and cleaving. The wafer is similar to a piece of glass. A diamond saw cut the wafer
into single chips. The diamond tipped tool is used to cut the lines through the rectangular grid which
separates the individual chips. The chips that are failed in electrical test are discarded. Before
packaging, remaining chips are observed under microscope.