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2
Efficiency Definitions
POUT
~ Drain Efficiency: ηD =
PDC
3
Ideal FET Input and Output Characteristics
IDS
VGS=0
Im
gm
VGS=VP
VGS VDS
2VP VP 0 0 VK VDD VDSmax
VDD − VK
κ=
VDD
4
Maximum Output Power Match
IDS
VGS=0
Im
gm
VGS=VP
VGS VDS
2VP VP 0 0 VK VDD VDSmax
VDS max − VK
ROPT =
Im
5
Class A
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
6
Class A – Circuit
VDD
G D
RL
S
η D = κ ⋅ 50%
G = G A (e.g.14 dB)
η PA = κ ⋅ 48%
7
Class B
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
8
Class C
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
9
Class B and C – Circuit
VDD
f0
G D
RL
S
Class B Class C
η D = κ ⋅ 78% η D → 100%
G = G A - 6dB (8 dB) G →1
11
Class F (HCA ... harmonic controlled amplifier)
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
12
hHCA (half sinusoidally driven HCA)
IDS IDS
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
13
Class F and hHCA – Circuit
VDD
Zo(n)
0, n=1
ID Ze(n) inf, n=odd
VDS 0, n=even
RL
inf, n=even
Class F hHCA
η D = κ ⋅100% η D = κ ⋅100%
Im Im
VGS VDS Q
2VP VP 0 0 VK VDD VDSmax 0 p 2p
VGS VDS
2p
Q
15
Third Harmonic Peaking – Circuit
VDD
G D 3f0
f0 RL
S
η D = κ ⋅ 91%
ηPA = κ ⋅ 87%
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Linearity Aspects
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Linearity Aspects
~ Class A ~ Class AB
~ Class B ~ Class C
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Linearity Aspects
19
Amplifier Design – An Example
~ Balanced Amplifier Configuration
Port 1
Z=50 Ohm Port 2
Z=50 Ohm
20
Amplifier Design – Simulation
~ Gate & Drain Waveforms
20 4000
0 500
15 3000
-1 0 10 2000
5 1000
-2 -500
-3 -1000 -5 -1000
0 500 1000 1300 0 500 1000 1300
Time (ps) Time (ps)
21
Amplifier Design – Simulation
~ Dynamic Load Line & Power Sweep
4000 50
20 40
2000
30
10 20
0
10
-2000 0 0
0 3 6 9 12 15 0 5 10 15 20 24
Voltage (V) Power (dBm)
22
Amplifier Design – Measurements
~ Single Tone & Two Tone
60 60 PAE [%]
40 80 PAE[%]
1dBCP
35 70 50 50
30 60
25 50
Pout P out
Gain IMDD
20 40 30 30
Gain
GammaIn
PAE
PAE
15 30
20 20
10 20
10 10
5 10
0 0 0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Pin[dBm] P in [dBm]
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Amplifier Nonlinearity
~ Gain and Phase depends on Input Signal
24
Amplifier Nonlinearity
~ Higher Output Level (close to Saturation) results
in more Distortion/Nonlinearity
25
Nonlinearity leads to?
~ Generation of Harmonics
~ Constellation Deformation
26
Intermodulation and Harmonics
27
Spectral Regrowth
10
ACPR1 >60dB
ACPR2 >60dB
0
ACPR1 =16dB
ACPR2 =43dB
-10
relative power / dB
-20
-30
-40
-50
-60
-15 -10 -5 0 5 10 15
relative frequency / MHz
28
Reduced NPR (Noise Power Ratio)
29
Constellation Deformation
~ Input Signal ~ Output Signal of
Nonlinear Amplifier
(with Gain- and Phase-Distortion)
30
Modeling of Nonlinearities
~ with Memory-Effects
z Volterra Series (=„Taylor Series with Memory“)
~ without Memory-Effects
αar αΘr 2
performance
z Saleh Model f (r ) = g (r ) =
1+ βar 2
1 + βΘr 2
better
z Taylor Series
z Blum and Jeruchim Model
z AM/AM- and AM/PM-conversion
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AM/AM- and AM/PM-Conversion
~ GaAs-PA
32
AM/AM- and AM/PM-Conversion
~ LDMOS-PA
33
How to preserve Linearity?
~ Backed-Off Operation of PA
z Simplest Way to achieve Linearity
34
How to preserve Efficiency?
~ Efficiency improving Concepts
z Doherty
z Envelope Elimination and Restoration
z ...
35
Direct (RF) Feedback
~ Classical Method
~ Decrease of Gain Æ Low Efficiency
~ Feedback needs more Bandwidth than Signal
~ Stability Problems at high Bandwidths
36
Distortion Feedback
37
Feedforward
38
baseband input
Cartesian Feedback
I
modulator main amp.
I RF-output
OPAs
Q
Q
local
oscillator
10
UMTS example:
original signal
I predistorted signal
Q 0
demodulator -10
relative power / dB
-20
AM/PM-correction -40
40
Analog Predistortion
41
Analog Predistortion
~ Possible Realizations:
42
LINC (Linear Amplification by Nonlinear Components)
s1(t) Ks1(t)
K
K(s1(t)+s2(t))
s(t) signal =Ks(t)
separation
s2(t) Ks2(t)
K
UMTS example:
10
~ AM/AM- and s(t)
ACPR1 >60dB
ACPR2 >60dB
AM/PM-correction
0 s 1 (t)
ACPR1 =18dB
ACPR2 =29dB
-10
~ Digital separation required
relative power / dB
(accuracy!) -20
-60
-30 -20 -10 0 10 20 30
relative frequency / MHz
43
Doherty Amplifier
~ Auxiliary amplifier supports main amplifier during saturation
~ PAE can be kept high over a 6dB range
44
Doherty Amplifier
~ Gain vs. Input Power ~ Efficiency vs. Input Power
POUT
A2)
A1+
(
n
tio main amp. (A1)
a
gur
i
onf
c
e rty aux. amp. (A2)
h
do
PIN
45
EER (Envelope Elimination and Restoration)
RF input signal
separation
phase information RF output
high efficiency
power amplifier
46
EER (Envelope Elimination and Restoration)
supply voltage
~ Analog realization peak detector amplifier
high efficiency
peak detector power amplifier
~ Digital realization
z Oversampling + high D/A- amplitude information
conversion rates required D
supply voltage amplifier
47
EER (Envelope Elimination and Restoration)
ACPR1 =51dB
relative power / dB
ACPR2 =36dB
-20 -20
ACPR1 =53dB
ACPR2 =49dB
-30 -30
-40 -40
-50 -50
-60 -60
-30 -20 -10 0 10 20 30 -30 -20 -10 0 10 20 30
relative frequency / M Hz relative frequency / MHz
48
Adaptive Bias
~ Varying/Switching of Bias-Voltage depending on
Input Power Level
~ Selection of Operating Point with high PAE
~ Applicably for nearly each type of Amplifier
peak detector
bias
control
RF input RF output
high efficiency
power amplifier
49
Adaptive Bias
~ Single tone PAE for switched ~ Simply to implement Concept
VDD with VG kept constant ~ Stability guaranteed
90 ~ Possible problems:
80 z DC-DC converter with high
efficiency necessary
power added efficiency / %
70
50
Summary
~ Digital Realization required to achieve Accuracy
51
Figure References
~ F. Zavosh et al,
“Digital Predistortion Techniques for RF Power
Amplifiers with CDMA Applications”,
Microwave Journal, Oct. 1999
~ Peter B. Kenington,
“High-Linearity RF Amplifier Design”,
Artech House, 2000
~ Steve C. Cripps,
“RF Power Amplifiers for Wireless Communications”,
Artech House, 1999
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Contact Information
+43-1-58801-35425 +43-1-58801-35420
markus.mayer@tuwien.ac.at holger.arthaber@tuwien.ac.at
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