Math1 Comput. Modelling, Vol. 14, pp. 354-358, 1990 0895-7177/9083.00+ 0.

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Printed in Great Britain Pergsmon Press plc
SIMULATION OF VLSI PROCESSING DEFICIENCIES IN DIGITAL
INTEGRATED CIRCUITS

Afzel Noore
Department of Electrical & Computer Engineering
West Virginia University

Abstract. This paper presents circuit level simulation of VLSI circuits to study the effect of
processing deficiencies prevalent in the manufacturing environment. Physical deficiencies due
to masking and etching and processing irregularities are modeled. In addition, some failures
related to non uniform distribution of oxide in polysilicon layers, variation in the channel
dimensions and stuck-open faults of CMOS gates are effectively simulated.

Keywords. Modelling; simulation; very large scale integration; processing deficiencies.

INTRODUCTION SIMULATION OF SCALING AND PROCESSING

DEFICIENCIES
With the increase in complexity of VLSI circuits, several
unconventional failure modes are manifested. This paper
presents techniques by which the processing deficiencies of The scaling of MOSFETs to near submicron feature sizes
VLSI circuits can be effectively modeled. Logic level and has given rise to very high density circuits. Memory devices
functional level simulators do not define the circuit models that are fabricated using mask sets have been scaled down
accurately. Furthermore several parameters at low level photographically from the original design dimensions by
cannot be directly varied using high level simulations. about 25 per cent. This reflects the steady growth rate of
Circuit modeling and simulation is performed with the very high density memory chips in recent years. As a result,
widely used SPICE circuit simulator [7]. SPICE is a considerable research effort has been on going and oriented
powerful tool for analyzing and designing circuits but cannot toward new mechanisms for obtaining closer component
be directly used to study the failure effects. Even simple spacing, developing metallization and lithography techniques
failure modes such as open and short circuits in MOS to facility interconnection of closely spaced components and
devices have to be modeled and simulated in a manner that designing circuits at submicron dimensions that would
SPICE can accept them as valid constructs. Deficiencies due perform reliably. The effect and implication of scaling the
to masking and etching when the thickness of the oxide in geometry of the devices together with the difficulties
polysilicon layers are not uniformly distributed, or variations encountered in processing these devices during manufacture
in substrate doping, ion implantation dose, variations in the are examined.
gate length, and the junction depth of the source and drain
can be effectively modeled. The faults and fault effects in The most common processing deficiencies encountered are
NMOS circuits and the impact on design for testability has the open and short circuits in the layers of interconnect.
been studied 121. In this paper, the effect on CMOS VLSI Simulation of these simple deficiencies using SPICE is not
circuits are investigated. The p-channel MOSFETs and the n- straightforward. The effect of an open or a short circuit
channel MOSFETs of the CMOS gates do not always cannot be strictly defined by the circuit topology. In the case
respond in an identical manner. It has been shown that of an open circuit deficiency, SPICE would regard the
CMOS circuits additionally manifest a stuck-open failure topology definition as an invalid input because every node of
mode, which causes a simple combinational logic to behave the MOSFET must have at least two connections.
like a sequential logic [8]. This failure mode is also modeled Reconfiguration of the circuit to a different but equivalent
using SPICE in addition to the conventional stuck-at-zero topology is required if simulation is to be performed using
and stuck-at-one fault classifications. SPICE. The controllability and observability of the
processing deficiencies can be improved by using
controllable gates 151. Further modifications are required as

354
 Proc. 7th Inr. Co& on Malhematical and Computer Modeiiing 355

shown in the row buffer circuit example of Figure 1 by

adding MO and MS to improve controllability. In the normal
The physical wafer level device dimensions for the width
VDD and the length of the channel are represented by the SPICE
parameters W and L. These parameters are related to the
design dimensions by process variations, AL and AW, and
compensate for mismatches in the device dimensions.
Mismatches occur due to the processing deficiencies during
the manufacturing process. They also occur due to the

+_____________+____________-l
,z”+____~_________+_____________+__________---

1‘=

Figure 1. Design augmentation to improve testability

I
mode of operation, control inputs Cl=1 and C2=0. A faulty
M2 due to a short is simulated by Cl-1 and C2=1 and a
_,“~;__________________________~____________~+~____________~~~____________~
faulty M2 due to an open is simulated by Cl-O. The addition LOMl
. . . . .Wl TIM
of extra controllable gates as illustrated are applicable to
simple circuits. But as the circuit becomes complex, the large (a)
number of MOSFETs introduce additional delays which ~~t.___.._____+_.._____-__+_____-_---_~_______-_-+-_---_----+---_
degrade the response time thereby making accurate
simulation difficult. Another problem observed with this
topology was the deterioration of logic signal levels. An
improved technique that replaces the active controllable gates
MO and MS with passive resistors, Rl and R2, yielded
better simulation results. In the normal mode of operation Rl
= IOOE-06 ohms and R2 = lOOOE+12 ohms. A faulty M2
due to a short is simulated by RI = lOOE-06 ohms and R2 =
lOOE-06 ohms. A faulty M2 due to an open is simulated by
Rl = lOOOE+12 ohms. The resistor values simulate the
MOSFET operation. Delays are minimized and the effect of
the simulated deficiency is accurately observed. The logic
signal levels were not affected. In addition to overcoming the lb)
two drawbacks, a major advantage of this approach is that
unconventional processing failures other than the common Figure 2. Effect of variation in channel length and width.
short and open circuits can be easily modeled. Failure modes
such as a MOSFET in the off state partially conducting or a source-drain node output diffusion and the polysilicon
MOSFET in the on state offering high impedance can be linewidth process bias if polysilicon gate technologies are
effectively modeled by varying the resistor values. The used [ 31. The source-drain node output diffusion depends on
upper and lower limit on the resistor values during the parameters related to ion implantation dose and
simulation is dependent on the circuit being simulated for temperature of processing. Keeping the temperature
allowing proper convergence in the DC and transient fault constant, the effect on the p-channel MOSFETs and n-
simulation using SPICE. channel MOSFETs of a generalized CMOS complex gate
 356 Proc. 7th Int. Conf on Mathematical and Computer Modelling

with variations in Land W are simulated. The simulation not
only focuses on the reduced dimensions but also enables
tolerances on the opposite end of the spectrum to be studied.
Monte Carlo simulation is performed to obtain statistical
analysis on the complex CMOS circuit with variations in the
device tolerances. Figure 2 shows the effect on the output
when it undergoes a zero to one transition and a one to zero
transition. Depending on the maximum speed of the device,
both the rise time and fall time responses are drastically
affected with increased L. If the operating frequency is high,
then the output transition from logic 0 to logic 1 would be
equivalent to a stuck-at-0 fault.
frequencies, the transition from logic 1 to logic 0 would
appear as a stuck-at- I fault. Variations of W and its effects
are also shown in Figure 2.
computation of the conduction factor, backgate bias effect
and gate-channel voltage-dependent capacitances. There are
built-in models of the charge storage effects related to the
oxide thickness available in SPICE. The SPICE input
parameter, TOX, using LEVELI model will be assumed
infinite. The gate capacitances, CGS, CGD and CGB in this
case is constant with voltage [4]. Using LEVEL2 and
LEVEL3 models, TOX defaults to IOOOAimplying that the
gate capacitances are always voltage-dependent. As before,
the TOX process parameter is statistically varied using
Monte Carlo simulation and the results are shown in Figure
Similarly, at high 3. It can be seen that for higher TOX values, the fall time is
affected more than the rise time and if the operating
frequency is high, the output of the complex CMOS circuit
would appear to be stuck-at-one.

Variation In Gate Oxide Thickness

The variation in gate oxide thickness influences the

,a”+___--_________+--__________--c_____________+_____~_______+_~_~_________~

_“~____________+_____________+_____________~____________~;_________~~ ~v,;_____________c____________~_____________~~_____
.VMIW #VI m .V(411 .VI4 n .V141U .v I$” P .vuin .vr4+4,;vun *v141gE
fp* 9rr,

63)
63)

4”+ l-M .TcD:. i

4-High lUx

_,v;__‘________‘_._._______*_________;~~________~_~~~_;______~~~~~____;~_~~
‘?%a ” :im4 . v l4%% 141‘r’,; Y I41 m

(b)

Figure 3. Effect of changes in gate oxide thickness. Figure 4. Effect of changes in transconductance.
 Proc. 7th Int. Conf on Mathematical and Computer Modelling
(4
*~+______________+_
____
________
+_____
________+_____________+_____________+
Figure 5. Effect of variation in threshold voltage.
Variation In The Transconductance
Transconductance variations of the process or the device
directly affects the current-voltage characteristics of the
MOSFETs. The parameter KP is used in the SPICE program
to study the effect on CMOS circuits due to changes in KP,
which is a function of the surface mobility. The physical
details determining variation of mobility with parameters
such as local fields and crystal structure are quite complex to
determine analytically. However through simulation, the
variations in KP can be effectively modeled. Figure 4 shows
the response from the output of a complex CMOS gate. The
variation of KP on the PMOSFETs shows that small values
of KP cause the output to be stuck-at-0 while similar
variations in the NMOSFETs did not alter the output logic
levels. Also when the output undergoes a one to zero
transition, small values of KP, cause the output to be stuck-
351
at- I, while similar variation of KP on the PMOSFETs did
not affect the output logic levels.
Variation In The Threshold Voltatze
The threshold voltage is a function of a number of
parameters including impurities at silicon-insulator interface,
channel doping, gate insulator thickness, gate material, gate
insulation material and voltage between the source and
substrate. Although the techniques used to vary the threshold
voltage is by changing the doping concentration at the
silicon-insulator interface through ion implantation, or by
choosing a different insulating material for the gate, the
effect of variations in doping can be directly simulated by
varying the SPICE threshold parameter VTO. Figure 5
shows the logic levels for a complex CMOS gate as the
threshold voltage varies. Variations in the threshold voltage
VT of the NMOSFETs changes the fall time, which
increases as VT increases. The fall time was not affected by
changes of VT of the PMOSFETs. Similarly when the
threshold voltage VT in the PMOSFETs increases, the rise
time increases. The rise time was not affected by changes of
VT in the NMOSFETs.
MODELING STUCK-OPEN PROCESSING
DEFICIENCIES
Physically as the MOS devices are scaled down to near
submicron dimensions an open in the drain or source of the
PMOSFETs or NMOSFETs of complex CMOS circuits,
causes one or more FETs to be in the non-conducting state
permanently. It has been shown that stuck-open faults in
CMOS combinational circuits causes the circuit to behave
like a sequential logic 181.Figure 6 shows the output from a
2 input AND gate in the presence of stuck-open faults. At
least two observations of the output are required in order to
detect this physical failure. In order to make the transition
from the normal circuit mode to the stuck-open failure mode,
a switch is modeled using a polynomial voltage or current -
controlled current source [I]. A voltage-controlled current
source (VCCS) can be generated so that the current through
it is the mathematical product of two voltages. In Figure 6
V(lO0) is IV, in the normal mode. The second voltage
across the VCCS is defined so that the transconductance is
very large. The product of these two voltages makes the
VCCS behave like a short circuit. When V( 100) is OV, the
358 Proc. 7th Int. Con$ on Mathematical and Computer Modelling

stuck-open failure mode is simulated because the current

through it is 0. Using specific test vectors [61, the stuck- REFERENCES
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