PREINFORME 4

SUMADORES

A) DISENO DE UN SUMADOR RESTADOR EN CODIGO 5421 DE 2 DIGITOS

QUARTUS

 MODULOS EN VHDL A USAR (tanto en Ise como en Quartus):

Sumador completo de 1 bit

--full ader 1bit
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(A,B,Ci: in std_logic;
S,Co: out std_logic);
end fulladder;
architecture fun of fulladder is
begin
S<=A xor B xor Ci;
Co<=(A and Ci)or(A and B)or(B and Ci);
end fun;

Sumador de 4 bits
--4 bit fulladder
library ieee;
use ieee.std_logic_1164.all;
entity bit4adder is
port(A,B: in std_logic_vector(3 downto 0);
Ci: in std_logic;
S: out std_logic_vector(3 downto 0);
Co: out std_logic);
end bit4adder;
architecture fun of bit4adder is
component fulladder
port(A,B,Ci: in std_logic;
S,Co: out std_logic);
end component;
Signal C: std_logic_vector(2 downto 0);
begin
bit1:fulladder port map(A(0),B(0),Ci,S(0),C(0));
bit2:fulladder port map(A(1),B(1),C(0),S(1),C(1));
bit3:fulladder port map(A(2),B(2),C(1),S(2),C(2));
bit4:fulladder port map(A(3),B(3),C(2),S(3),Co);
end fun;

Sumador de digitos en BCDN

--sumador BCD-N
library ieee;
use ieee.std_logic_1164.all;
entity BCDNadder is
port(A,B: in std_logic_vector(3 downto 0);
Ci: in std_logic;
S: out std_logic_vector(3 downto 0);
Co: out std_logic);
end BCDNadder;
architecture fun of BCDNadder is
component bit4adder
port(A,B: in std_logic_vector(3 downto 0);
Ci: in std_logic;
S: out std_logic_vector(3 downto 0);
Co: out std_logic);
end component;
signal S1: std_logic_vector(3 downto 0);
signal C1,C2,C3: std_logic;
begin
suma1: bit4adder port map(A,B,Ci,S1,C1);
C2<=(S1(3)and S1(2))or(S1(3)and S1(1))or(C1);
suma2: bit4adder port map('0'&C2&C2&'0',S1,'0',S,C3);
Co<=C2;
end fun;

Complementador a 10 de digitos BCDN

--Complementador a 10 BCDN
library ieee;
use ieee.std_logic_1164.all;
entity comp10 is
port(Sig: in std_logic;
A: in std_logic_vector(3 downto 0);
Ci: in std_logic;
B: out std_logic_vector(3 downto 0);
Co: out std_logic);
end comp10;
architecture fun of comp10 is
component bit4adder
port(A,B: in std_logic_vector(3 downto 0);
Ci: in std_logic;
S: out std_logic_vector(3 downto 0);
Co: out std_logic);
end component;
signal S1: std_logic_vector(3 downto 0);
signal C1: std_logic;
begin
suma1:bit4adder port map(A xor Sig&Sig&Sig&Sig,Sig&'0'&Sig&'0',Ci,S1);
C1<=(S1(3)and S1(2))or(S1(3)and S1(1));
suma2:bit4adder port map('0'&C1&C1&'0',S1,'0',B);
Co<=C1;
end fun;
Programa funcional

--sumador restador en codigo 5421

library ieee;
use ieee.std_logic_1164.all;
entity a1_dva is
port(Ad,Au,Bd,Bu:in std_logic_vector(3 downto 0);
Sa,Sb: in std_logic;
Sc,Sd,Su: out std_logic_vector(3 downto 0);
Signo: out std_logic);
end a1_dva;
architecture fun of a1_dva is
component fulladder
port(A,B,Ci: in std_logic;
S,Co: out std_logic);
end component;
component bit4adder
port(A,B: in std_logic_vector(3 downto 0);
Ci: in std_logic;
S: out std_logic_vector(3 downto 0);
Co: out std_logic);
end component;
component BCDNadder
port(A,B: in std_logic_vector(3 downto 0);
Ci: in std_logic;
S: out std_logic_vector(3 downto 0);
Co: out std_logic);
end component;
component comp10
port(Sig: in std_logic;
A: in std_logic_vector(3 downto 0);
Ci: in std_logic;
B: out std_logic_vector(3 downto 0);
Co: out std_logic);
end component;
signal Ado,Auo,Bdo,Buo:std_logic_vector(3 downto 0);--5421 a BCDN
signal Ad1,Au1,Bd1,Bu1:std_logic_vector(3 downto 0);--entradas al sumador
signal Co1,Co2,C11,C12,So,Cso,Sgno,C21,C22:std_logic;
signal S1,S2,S3: std_logic_vector(3 downto 0);
begin
--transcodificando 5421 a 8421
tc1: bit4adder port map(Ad,Ad(3)&Ad(3)&'0'&Ad(3),'0',Ado);
tc2: bit4adder port map(Au,Au(3)&Au(3)&'0'&Au(3),'0',Auo);
tc3: bit4adder port map(Bd,Bd(3)&Bd(3)&'0'&Bd(3),'0',Bdo);
tc4: bit4adder port map(Bu,Bu(3)&Bu(3)&'0'&Bu(3),'0',Buo);
--complementando a 10
cmp1:comp10 port map(Sa,Auo,Sa,Au1,Co1);
cmp2:comp10 port map(Sa,Ado,Co1,Ad1);
cmp3:comp10 port map(Sb,Buo,Sb,Bu1,Co2);
cmp4:comp10 port map(Sb,Bdo,Co2,Bd1);
--sumando los digitos resultantes y los signos
sum1:BCDNadder port map(Au1,Bu1,'0',S1,C11);
sum2:BCDNadder port map(Ad1,Bd1,C11,S2,C12);
sum3:fulladder port map(Sa,Sb,C12,So,Cso);
--Correcciones a los digitos resultantes
Sgno<=Sa xor Sb xor Cso;S3<=Sgno&'0'&'0'&So;
--complemento a 3 para resultados finales
cmpl1:comp10 port map(Sgno,S1,Sgno,Su,C21);
cmpl2:comp10 port map(Sgno,S2,C21,Sd,C22);
cmpl3:comp10 port map(Sgno,S3,C22,Sc);
Signo<=Sgno;
end fun;

ISE
** El código será el mismo solo cambia el test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY a1 IS
END a1;
ARCHITECTURE behavior OF a1 IS
COMPONENT a1_dva
PORT(
Ad : IN std_logic_vector(3 downto 0);
Au : IN std_logic_vector(3 downto 0);
Bd : IN std_logic_vector(3 downto 0);
Bu : IN std_logic_vector(3 downto 0);
Sa : IN std_logic;
Sb : IN std_logic;
Sc : OUT std_logic_vector(3 downto 0);
Sd : OUT std_logic_vector(3 downto 0);
Su : OUT std_logic_vector(3 downto 0);
Signo : OUT std_logic
);
END COMPONENT;
signal Ad : std_logic_vector(3 downto 0) := (others => '1');
signal Au : std_logic_vector(3 downto 0) := (others => '0');
signal Bd : std_logic_vector(3 downto 0) := (others => '1');
signal Bu : std_logic_vector(3 downto 0) := (others => '0');
signal Sa : std_logic := '1';
signal Sb : std_logic := '0';
 signal Sc : std_logic_vector(3 downto 0);
signal Sd : std_logic_vector(3 downto 0);
signal Su : std_logic_vector(3 downto 0);
signal Signo : std_logic;
BEGIN
uut: a1_dva PORT MAP (
Ad => Ad,
Au => Au,
Bd => Bd,
Bu => Bu,
Sa => Sa,
Sb => Sb,
Sc => Sc,
Sd => Sd,
Su => Su,
Signo => Signo
);
proceso1: process
begin
Ad<="0000";Au<="0000";Bd<="0000";Bu<="0000";wait for 20 ns;
Ad<="0110";Au<="0011";Bd<="0100";Bu<="0101";wait for 20 ns;
Ad<="0000";Au<="0001";Bd<="0010";Bu<="0010";wait for 20 ns;
Ad<="1010";Au<="1000";Bd<="1010";Bu<="0000";wait for 20 ns;
Ad<="0100";Au<="1010";Bd<="0011";Bu<="1001";wait for 20 ns;
Ad<="0110";Au<="0001";Bd<="0100";Bu<="0011";wait for 20 ns;
Ad<="0101";Au<="0110";Bd<="0001";Bu<="1100";wait for 20 ns;
Ad<="1000";Au<="0100";Bd<="0000";Bu<="1000";wait for 20 ns;
end process;
signos: process
begin
Sa<=not Sa; wait for 10 ns;
end process;
signos2: process
begin
Sb<=not Sb; wait for 20 ns;
end process;
END;
 PROTEUS

Sumador BCD
12
5
11 9 7
6 C4 C0
13
Complemento a 10

4
11
B3
2 15
B2
3 2
B1
1 6

12
B0
2
10 12 3
S3 A3 a7

7410
13 14 1
S2 A2 a6
1 3

U31:A
S1 A1 a5
4 5 5

7
11
15
2
6
12
14
3
5
S0 A0 a4
6
4

B3
B2
B1
B0
A3
A2
A1
A0

C0

1
2
13
U46

74283
74283
10
U38 8
9

8
6
3
C4
S3
S2
S1
S0
13

9
1
4

10
13
9 7 11
C4 C0

b7
12
11
B3
15
B2

b6
b5
b4
2
B1
U36
74283

9
4
5
1
2
6

10
B0
2
2
9 10 12 3
3 S3 A3 a3
8 13 14 1
1 S2 A2 a2
10 1 3
S1 A1 a1
4 5 5
5 S0 A0 a0
6
6
4
9 7 9 7 4
C4 C0 C4 C0 ci
10
11 11
B3 B3 b3 8
15 15
B2 B2 b2 9
2 2
co B1 B1 b1
6 6
B0 B0 b0
13
7
11
15
2
6
12
14
3
5

10 12 10 12 11
s3 S3 A3 S3 A3 a3
13 14 13 14 12
s2 S2 A2 S2 A2 a2
1 3 1 3
B3
B2
B1
B0
A3
A2
A1
A0

C0

s1 S1 A1 S1 A1 a1
4 5 4 5
U44

74283

s0 S0 A0 S0 A0 a0
C4
S3
S2
S1
S0

U30
U28

74283
74283
9
1
4

10
13
en

b3
b2
b1
b0
Detector de signos y numeros

a3
a2
a1
a0
a7
a6
a5
a4
a10
a11

a9
a8
en

13

12
2

1
10

13

12
2

9
10

13

12
2

11
3

11
3

11

15

12
14
11
7

2
6

3
5
15

12
14
11
7

2
6

3
5
15

12
14
11
7

2
6

3
5

C0

B3
B2
B1
B0

A3
A2
A1
A0
U9

C0

B3
B2
B1
B0

A3
A2
A1
A0
U25
C0

B3
B2
B1
B0

A3
A2
A1
A0

74283 U11
74283
74283

C4

S3
S2
S1
S0
C4

S3
S2
S1
S0
C4

S3
S2
S1
S0

10
13
1
4
9

10
13
1
4
U17
9

10
13
1
4

U34 U26 5 4
A0 S0 b0
5 4 3 1
5 4 b8 A0 S0 b4 A1 S1 b1
A0 S0 3 1 14 13
3 1 A1 S1 b5 A2 S2 b2
A1 S1 b9 14 13 12 10
14 13 A2 S2 b6 A3 S3 b3
A2 S2 b10 12 10
12 10 A3 S3

12

13
A3 S3 6

1
B0
b11 6 2
2

6 B0 b7 B1
2

B0 2 15
2 B1 B2
B1 15 11
15 B2 B3
B2 11
11 B3
B3 7 9
C0 C4
7 9
7 9 C0 C4
C0 C4 74283
74283
74283

11

3
3

6
3

1
10
9
10
9

3
8
8

Sintetizador de signos
U4:C
9
ci
8
s
10
U4:B
4 74136
a
6
5 U5:B
b
4
74136 6
5 U6:A
U5:A 1
1 7408 3
co
3 2
2
7432
7408
Programa general

1 1

1
0
1
0

1
0
1
0

1
0
1
0

1
0
1
0
13

16

10

13

16

10

13

16

10

13

16

10
11

11

11

11
4
7

1
3
8

4
7

1
3
8

4
7

1
3
8

4
7

1
3
8

1
C0

B4
B3
B2
B1

A4
A3
A2
A1

C0

B4
B3
B2
B1

A4
A3
A2
A1

C0

B4
B3
B2
B1

A4
A3
A2
A1

C0

B4
B3
B2
B1

A4
A3
A2
A1
1

C4

C4

C4

C4
S4
S3
S2
S1

S4
S3
S2
S1

S4
S3
S2
S1

S4
S3
S2
S1
14

15
2
6
9

14

15
2
6
9

14

15
2
6
9

14

15
2
6
9
ADDR
COMP10_2 COMP10_1
a en en
s b7 b7 a7 b7
b b6 b6 a7 a6 b6 a7
co b5 b5 a6 a5 b5 a6
ci
b4 b4 a5 a4 b4 a5
b3 b3 a4 a3 b3 a4
CCT007 b2 b2 a3 a2 b2 a3
b1 b1 a2 a1 b1 a2
b0 b0 a1 a0 b0 a1
CCT005 CCT005
2

a0 a0

b3 a3
b3 a7
b2 a2
b2 a6
co b1 a1
co
ADBCDN_2
b1 a5 ADBCDN_1
b0 a0
b0 a4 s3 s3 CCT001
s7 s3 CCT001 s2 s2
s6 s2 a3 b3
3

a3 b7 s1 s1
s5 s1 a2 b2
a2 b6 s0 s0
s4 s0 a1 b1
a1 b5
s11 a0 b0
a0 b4
5

s8
ci
ci

COM10
b11 en SIGN
b10
1 a11 s11
6

b9
a10
b8
a9
b7
a8 s8
b6
a7 s7
b5
a6 s6
SIGN

b4
a5 s5
b3
a4 s4
b2
a3 s3
b1
a2 s2
b0
a1 s1
a0 s0
CCT009

PUNTO B1)
Quartus
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY B1SUM IS
PORT (A: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
F:OUT STD_LOGIC_VECTOR (5 DOWNTO 0));
END B1SUM;
ARCHITECTURE FUNCION OF B1SUM IS
BEGIN
WITH A SELECT
F<= "000000" WHEN "0110011",--0
"000001" WHEN "0110100",--1
"000010" WHEN "0110101",--2
"000011" WHEN "0110110",--3
"000100" WHEN "0110111",--4
"000101" WHEN "0111000",--5
"000110" WHEN "0111001",--6
"000111" WHEN "0111010",--7
"001000" WHEN "0111011",--8
"001001" WHEN "0111100",--9
"001010" WHEN "1000011",--10
"001011" WHEN "1000100",--11
"001100" WHEN "1000101",--12
"001101" WHEN "1000110",--13
"001110" WHEN "1000111",--14
"001111" WHEN "1001000",--15
"010000" WHEN "1001001",--16
"010001" WHEN "1001010",--17
"010010" WHEN "1001011",--18
"010011" WHEN "1001100",--19
"010100" WHEN "1010011",--20
"010101" WHEN "1010100",--21
"010110" WHEN "1010101",--22
"010111" WHEN "1010110",--23
"011000" WHEN "1010111",--24
"011001" WHEN "1011000",--25
"011010" WHEN "1011001",--26
"011011" WHEN "1011010",--27
"011100" WHEN "1011011",--28
"011101" WHEN "1011100",--29
"011110" WHEN "1100011",--30
"011111" WHEN "1100100",--31
"100000" WHEN "1100101",--32
"100001" WHEN "1100110",--33
"100010" WHEN "1100111",--34
"100011" WHEN "1101000",--35
 "100100" WHEN "1101001",--36
"100101" WHEN "1101010",--37
"100110" WHEN "1101011",--38
"100111" WHEN "1101100",--39
"101000" WHEN "1110011",--40
"101001" WHEN "1110100",--41
"101010" WHEN "1110101",--42
"101011" WHEN "1110110",--43
"101100" WHEN "1110111",--44
"101101" WHEN "1111000",--45
"101110" WHEN "1111001",--46
"101111" WHEN "1111010",--47
"110000" WHEN "1111011",--48
"110001" WHEN "1111100",--49
"000000" WHEN OTHERS;
END FUNCION;

Ise
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY TESTBENCH IS
END TESTBENCH;
ARCHITECTURE behavior OF TESTBENCH IS
COMPONENT B1
PORT(
A : IN std_logic_vector(6 downto 0);
F : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(6 downto 0) := (others => '0');
--Outputs
signal F : std_logic_vector(5 downto 0);

BEGIN
 -- Instantiate the Unit Under Test (UUT)
uut: B1 PORT MAP (
A => A,
F => F);
PROCESO6: PROCESS
BEGIN
A(6)<= NOT A(6); WAIT FOR 800 ns;
END PROCESS;
PROCESO5: PROCESS
BEGIN
A(5)<= NOT A(5); WAIT FOR 400 ns;
END PROCESS;
PROCESO4: PROCESS
BEGIN
A(4)<= NOT A(4); WAIT FOR 200 ns;
END PROCESS;
PROCESO3: PROCESS
BEGIN
A(3)<= NOT A(3); WAIT FOR 100 ns;
END PROCESS;

PROCESO2: PROCESS
BEGIN
A(2)<= NOT A(2); WAIT FOR 50 ns;
END PROCESS;

PROCESO1: PROCESS
BEGIN
A(1)<= NOT A(1); WAIT FOR 25 ns;
END PROCESS;

PROCESO0: PROCESS
BEGIN
A(0)<= NOT A(0); WAIT FOR 12.5 ns;
END PROCESS;

END;
Wincupl
Name B1 ;
PartNo 00 ;
Date 23/4/2018 ;
Revision 01 ;
Designer Engineer ;
Company linux ;
Assembly None ;
Location ;
Device g16v8 ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* B2 */
PIN 3 = B ; /* B1 */
PIN 4 = C ; /* B0 */
PIN 5 = D ; /* A3 */
PIN 6 = E ; /* A2 */
PIN 7 = F ; /* A1 */
PIN 8 = G ; /* A0 */

/* *************** OUTPUT PINS *********************/

PIN 14 = U ; /* Z5 */
PIN 15 = V ; /* Z4 */
PIN 16 = W ; /* Z3 */
PIN 17 = X ; /* Z2 */
PIN 18 = Y ; /* Z1 */
PIN 19 = Z ; /* Z0 */

FIELD INS = [A,B,C,D,E,F,G];

FIELD OUTS =[U,V,W,X,Y,Z];
TABLE INS => OUTS{
'B' 0110011=>'B' 000000; 'B' 0110100=>'B' 000001; 'B'
0110101=>'B' 000010; 'B' 0110110=>'B' 000011;
'B' 0110111=>'B' 000100; 'B' 0111000=>'B' 000101; 'B'
0111001=>'B' 000110; 'B' 0111010=>'B' 000111;
'B' 0111011=>'B' 001000; 'B' 0111100=>'B' 001001; 'B'
1000011=>'B' 001010; 'B' 1000100=>'B' 001011;
'B' 1000101=>'B' 001100; 'B' 1000110=>'B' 001101; 'B'
1000111=>'B' 001110; 'B' 1001000=>'B' 001111;
'B' 1001001=>'B' 010000; 'B' 1001010=>'B' 010001; 'B'
1001011=>'B' 010010; 'B' 1001100=>'B' 010011;
'B' 1010011=>'B' 010100; 'B' 1010100=>'B' 010101; 'B'
1010101=>'B' 010110; 'B' 1010110=>'B' 010111;
'B' 1010111=>'B' 011000; 'B' 1011000=>'B' 011001; 'B'
1011001=>'B' 011010; 'B' 1011010=>'B' 011011;
'B' 1011011=>'B' 011100; 'B' 1011100=>'B' 011101; 'B'
1100011=>'B' 011110; 'B' 1100100=>'B' 011111;
'B' 1100101=>'B' 100000; 'B' 1100110=>'B' 100001; 'B'
1100111=>'B' 100010; 'B' 1101000=>'B' 100011;
'B' 1101001=>'B' 100100; 'B' 1101010=>'B' 100101; 'B'
1101011=>'B' 100110; 'B' 1101100=>'B' 100111;
'B' 1110011=>'B' 101000; 'B' 1110100=>'B' 101001; 'B'
1110101=>'B' 101010; 'B' 1110110=>'B' 101011;
'B' 1110111=>'B' 101100; 'B' 1111000=>'B' 101101; 'B'
1111001=>'B' 101110; 'B' 1111010=>'B' 101111;
 'B' 1111011=>'B' 110000; 'B' 1111100=>'B' 110001;}
PUNTO B2)
PROTEUS

PUNTO B3)
QUARTUS
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY L4B3 IS
PORT(
A : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
F : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END L4B3;
ARCHITECTURE FUN OF L4B3 IS
BEGIN
WITH A SELECT
F <= "001" WHEN "0000",
"110" WHEN "0001",
"010" WHEN "0010",
"100" WHEN "0011",
"001" WHEN "0100",
"110" WHEN "0101",
"011" WHEN "0110",
"000" WHEN "0111",
"001" WHEN "1000",
"101" WHEN "1001",
"010" WHEN "1010",
 "100" WHEN "1011",
"011" WHEN "1100",
"001" WHEN "1101",
"110" WHEN "1110",
"001" WHEN "1111",
"000" WHEN OTHERS;
END FUN;

ISE
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY VECTOR IS
END VECTOR;

ARCHITECTURE behavior OF VECTOR IS

COMPONENT L4B3
PORT(
A : IN std_logic_vector(3 downto 0);
F : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '1');

--Outputs
signal F : std_logic_vector(2 downto 0);

BEGIN

uut: L4B3 PORT MAP (

A => A,
F => F
 );

PROCESO3: PROCESS
BEGIN
A(3)<= NOT A(3); WAIT FOR 80 ns;
END PROCESS;

PROCESO2: PROCESS
BEGIN
A(2)<= NOT A(2); WAIT FOR 40 ns;
END PROCESS;

PROCESO1: PROCESS
BEGIN
A(1)<= NOT A(1); WAIT FOR 20 ns;
END PROCESS;

PROCESO0: PROCESS
BEGIN
A(0)<= NOT A(0); WAIT FOR 10 ns;
END PROCESS;

END;
B3) SIMPLIFICACION DE FUNCIONES

B4) CODIGO 6311 A JHONSON

C) DISENO DE UNA UNIDAD ARITMETICA LOGICA
D) DIVISOR
E) EL MULTIPLICADOR