1908 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO.
3, MARCH 2018
A Novel Carrier-Based Hybrid PWM Technique
for Minimization of Line Current Ripple in Two
Parallel Interleaved Two-Level VSIs
Kapil Shukla , Varun Malyala, and Ramkrishan Maheshwari
Abstract—A novel hybrid pulse width modulation (PWM)
technique is proposed in this paper for two parallel in-
terleaved, two-level, three-phase voltage source inverters
(VSIs). The two parallel interleaved VSIs are analyzed as
a three-level (3L) inverter. A 3L inverter provides minimum
line current ripple when nearest three voltage vectors are
applied. In this paper, a novel carrier-based PWM technique
is developed that ensures the application of nearest voltage
vectors, keeping average circulating current to zero over a
switching period. For carrier-based implementation of the
proposed PWM, generalized common-mode (CM) offsets
are derived in terms of maximum and minimum values of
reference signals. Each 3L space-vector sector is divided
into seven subsectors. For each subsector, a CM offset is
calculated, addition of which to reference signals ensures
the minimum line current ripple and zero average circulating
current. Simulation and experimental results are provided to
validate the proposed technique.
Index Terms—Interleaving, pulse width modulation
(PWM), two-level inverter (2L), voltage source inverter (VSI).
I. INTRODUCTION
ARALLEL interleaved voltage source inverters (VSIs) are
P used for different applications, such as high-power renew-
able energy power conversion system [1], shunt active power
filters, active front-end rectifiers [2], etc. The main advantages
of the parallel interleaved VSIs are reduced current stress on
the switches, reduced current ripple, modularity, improved ther-
mal management, increased power capability, redundancy, easy
maintenance, and increased efficiency [2]–[6]. Parallel inter-
leaved VSIs have common dc link, ac sides are connected
through inductors, and carrier signals are interleaved. Due to
this interleaving, ac-side harmonic distortion and line current
ripple are less [3]. However, the harmonic distortion in the
ac-side current depends on interleaving angle as well as pulse
Manuscript received January 19, 2017; revised May 6, 2017 and July
10, 2017; accepted August 6, 2017. Date of publication August 29, 2017;
date of current version December 15, 2017. (Corresponding author:
Kapil Shukla.)
The authors are with the Department of Electrical Engineering, In-
dian Institute of Technology Delhi, New Delhi 110016, India (e-mail:
kapilstriker@gmail.com; varun.malyala1993@gmail.com; rkmahesh@
ee.iitd.ac.in).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2017.2745438
0278-0046 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
, Member, IEEE
width modulation (PWM) methods [4]–[9]. In [3], the effect
of interleaving angle is analyzed, and it is recommended to
operate the inverter with 2π/N angle between the carrier sig-
nals for N parallel-connected inverter systems. The interleav-
ing angle also has impacts on the size of ac and dc passive
components [10], [11].
In addition to interleaved carrier signals, different PWM tech-
niques are also used to reduce output current harmonic dis-
tortion. Analysis of the ac-side current distortion for a single
two-level (2L) VSI is presented in [7]. It has been shown that
for lower modulation indices, conventional space-vector PWM
(SVPWM) technique provides minimum total harmonic distor-
tion (THD), while for higher modulation indices, split clamping
and advanced split clamping sequences PWM techniques should
be used. In [4], active zero-state PWM and near-state PWM
techniques are proposed for reducing line current distortion in
parallel interleaved VSIs with 180° phase shift between carrier
signals. However, the effect of different interleaving angles be-
tween the carrier signals is discussed in [5], and a hybrid PWM
technique employing multiple sequences is proposed for reduc-
ing ac-side current THD. The proposed technique in [5] imple-
ments different interleaving angles for different zones in a sector
that makes the implementation of the technique quite compli-
cated. Another PWM technique based on different common-
mode (CM) offset addition for different modulation indices for
parallel-connected VSIs is proposed in [6]. The proposed PWM
technique reduces the flux linking in the intercell transform-
ers connected to the ac side of parallel-connected VSIs, which
in turn reduces the output ac-side current ripple. The above-
mentioned techniques consider the parallel interleaved inverters
as two single VSIs.
In this paper, a new PWM technique is presented with the
following key features.
1) The two parallel interleaved 2L inverter system is an-
alyzed as a single three-level (3L) inverter instead of
treating them as two single VSIs.
2) A new hybrid PWM technique is developed for the two
parallel interleaved 2L VSIs to minimize the ac-side cur-
rent ripple.
3) The difference of CM voltages of both the inverters aver-
aged over a switching period is also kept to zero such that
the circulating current averaged over a switching period
will be zero.
SHUKLA et al.: NOVEL CARRIER-BASED HYBRID PWM TECHNIQUE FOR MINIMIZATION OF LINE CURRENT RIPPLE IN TWO PARALLEL 1909

4) The proposed PWM is implemented using a carrier-based

approach. For this, a CM offset is required to be added
to the three-phase reference signal in a switching period.
The required CM offset is also presented.
For minimization of line current ripple in a 3L inverter, three
nearest voltage vectors should be applied [12], [13]. However, in
a parallel interleaved system, there exists another problem of cir-
culating current [14]. This current is caused by the CM voltage
difference of the inverters [15]. The instantaneous CM voltage
difference cannot be avoided in interleaved carrier signals.
However, the CM voltage difference averaged over a switching
period can be made zero for reducing the average circulating
current. Another way of eliminating the circulating current is by
providing high impedances path for the circulating current that is
achieved by line frequency isolation transformer but it increases
the size and cost of the overall system and hence decreases the
power density. The circulating current could also be reduced
by the use of coupled inductors [14], integrated inductors [16], Fig. 1. Parallel interleaved inverters connected to load fed from a com-
and three limb inductors [17]. Different PWM techniques and mon dc link.
control schemes are also been developed for mitigation of
circulating current [18]–[27]. However, these techniques do
not focus on minimizing the ac-side current distortion. The
proposed PWM technique ensures the zero average circulating
current with minimization of the ac-side current distortion.
The converter topology under consideration looks similar to
the topology uses for the dual induction-fed open-end winding
induction motor drive, and it is analyzed as a 3L inverter [28]–
[32]. However, the dc link is not common in [28]–[31], and the
operation is also different. In the drive application, the average
CM voltage is kept zero [28], [32]. On the other hand, the Fig. 2. Equivalent circuit of the system considering only phase A of
system considered in this paper requires difference of the CM both inverters.
voltage averaged over a switching period to be zero to make the
average circulating current equal to zero in a switching period.
In summary, the proposed PWM technique applies three nearest
vectors of the 3L space-vector diagram to minimize the ac-side
current ripple keeping the average of the CM voltage difference
zero. In this way, the ac-side line current ripple can be kept same
as that of the 3L VSI.
The carrier-based implementation of the proposed PWM is
also presented, which ensures that no extra lookup tables are Fig. 3. Thevenin equivalent circuit of phase A.
required for sector identification and CM offset signal addition.
The proposed PWM requires multiple switching of a phase in II. 2L INVERTERS AS A 3L INVERTER
a switching period. The carrier-based implementation of PWM
A. Parallel Interleaved 2L Inverters as a 3L Inverter
sequence with multiple phase switching is discussed in [33] for
a single 2L inverter. However, the PWM technique used in [33] The two parallel interleaved 2L inverters with a common
has one phase clamped to a dc-link terminal for a switching pe- dc link of voltage Vdc are shown in Fig. 1. Each leg of the
riod and different CM offsets are calculated for different sector. inverter is connected through an inductor to the ac side. The
While, the technique proposed in this paper is used for two par- ac-side inductors can be realized using a CM and differential-
allel interleaved VSIs without any phase clamped to the dc-link mode chokes. Here, the inductors are connected to a common
terminal in a switching period, and the generalized CM offsets point, which could be further connected to any ac load or grid.
applicable to each sector are calculated, which ensures fast and Now, considering phase A of each parallel interleaved inverters,
simple implementation. the system could be visualized as shown in Fig. 2. Thevenin’s
This paper is organized as follows. Section II explains the equivalent circuit shown in Fig. 2 can be drawn as shown in
functioning of parallel interleaved 2L inverters as a 3L inverter. Fig. 3. Using this equivalent circuit, the equivalent output pole
Section III discusses about the proposed hybrid PWM strategy. voltage for phase A is given by [27]
Simulation and experimental results are explained in Section IV. vA1O + vA2O
Conclusions are provided in Section V. vAO = (1)
2
1910 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

TABLE I
POLE VOLTAGE COMBINATIONS

vA 1 O vA 2 O vA O

−V d c /2 −V d c /2 −V d c /2
−V d c /2 +V d c /2 0
+V d c /2 −V d c /2 0
+V d c /2 +V d c /2 +V d c /2

Fig. 5. Space-vector diagram of a 2L inverter.

to the pole voltage level of −Vdc /2 and +Vdc /2 of a phase.

There are six active vectors V12L − V62L and two zero vectors
V02L and V72L in a 2L inverter space-vector diagram. Among
these vectors, two active and both zero vectors are used to ap-
proximate a given reference vector Vref , at an angle θ, in a
conventional SVPWM technique in a switching period Ts , and
durations for which adjacent active vectors are applied (dwell
time) are given by [13], [35]
|Vref | sin (60◦ − θ) vm ax − vm id
T1 = ◦
Ts = Ts (3)
Fig. 4. Space-vector diagram using the equivalent pole voltages of two Vdc sin (60 ) Vdc
parallel interleaved inverters system.
and
|Vref | sin (θ) vm id − vm in
where vA1O is the inverter 1 pole voltage, and vA2O is the T2 = Ts = Ts . (4)
Vdc sin (60◦ ) Vdc
inverter 2 pole voltage.
Using (1), the values of equivalent pole voltages of phase
The duration for which each zero vector is applied is equal
A (vAO ) for different values of pole voltages of phase A of
and is given by
inverter 1 and 2 are listed in Table I. By looking at the combi-
nations, it is clear that the equivalent pole voltage vAO can have Ts − T1 − T2
Tz = (5)
three voltage levels. Similarly, it can be said that the equivalent 2
pole voltages of other phases, phase B and C, can also have three where vm ax , vm in , and vm id are the maximum, minimum,
voltage levels. Therefore, two parallel interleaved 2L inverters and middle values of the three-phase reference signals
could be analyzed as a single 3L inverter. The different voltage (vA,ref , vB,ref , vC,ref ), respectively, sampled in a switching pe-
levels of the equivalent pole voltage are denoted as riod. Due to the sixfold symmetry of the space-vector diagram,
Vdc Vdc (3)–(5) hold good for each sector.
2=+ , 1 = 0 V, 0=− . (2) This technique requires the calculation of T1 and T2 , which
2 2
in turn are required to calculate the ON and OFF times of the
individual switches of the inverters. However, the ON and OFF
The space-vector diagram of the two parallel interleaved sys-
times of the individual switches can be found directly using
tem is shown in Fig. 4, which is similar to a 3L inverter space-
the carrier-based approach [19]. In this approach, the reference
vector diagram. The diagram is divided into six sectors/triangles,
signals are compared with the high-frequency triangular carrier
as displayed by bold lines. Each sector could be further divided
signals. The carrier-based approach for implementing the con-
into different subsectors, as displayed by dashed lines. The mag-
ventional SVPWM technique is described in [15], as shown in
nitude of the outermost vector V13 is Vdc , while the inner middle
Fig. 6 for two parallel interleaved inverters. The carrier signals
vector V1 has magnitude equal to Vdc /2.
are interleaved and phase shifted by 180° to reduce the har-
monic components of the load-side current [3]. From Fig. 6, the
B. Equivalent 3L Inverter Switching Sequence switching sequences for both the inverters can be given as
Generation From 2L Inverter Switching Sequences
(− − −), (+ − −), (+ − −), (+ + −), (+ + +) and
The parallel interleaved system can be represented as a 3L
inverter, and each inverter is modulated as a 2L inverter for gen- reverse for Inv.−1
erating switching sequences of equivalent 3L inverter. The 2L
(+ + +), (+ + −), (+ − −), (+ − −), (− − −) and
inverter space-vector diagram is shown in Fig. 5 and is divided
into six sectors. Here, “−” and “+,” respectively, correspond reverse for Inv.−2.
SHUKLA et al.: NOVEL CARRIER-BASED HYBRID PWM TECHNIQUE FOR MINIMIZATION OF LINE CURRENT RIPPLE IN TWO PARALLEL 1911

Fig. 7. Error voltage vectors.

Fig. 8. Proposed hybrid PWM subsector division.

Fig. 6. Switching waveforms for parallel interleaved inverters using

SVPWM.

From above-mentioned switching sequences, (1) and Table I,

the equivalent pole voltages of the parallel interleaved inverters
system can be calculated that yield the following switching
sequence:
(111) , (210) , (200) , (210) , (111) and reverse. (6)
In a similar manner, the equivalent 3L switching sequences
for different 2L PWM sequences could be determined. However,
it is not feasible to apply any PWM sequence in the parallel
interleaved system due to the circulating current. The circulating
current is caused by the difference between the CM voltages of
the inverters, as given by [15]
iA 1 + iB 1 + iC1 iA 2 + iB 2 + iC2
iCC = = −
3 3

1
= (vcm 1 − vcm 2 ) dt (7)
Ls
where iA 1 , iB 1 , and iC 1 are the three phase currents of inverter
1, and iA 2 , iB 2 , and iC 2 are the three phase currents of inverter 2.
vcm ,1 and vcm ,2 are the CM voltages of inverter 1 and inverter 2,
respectively. Rs is neglected in (7). From (7), if the CM voltage
difference averaged over a switching period Ts is zero, i.e.,
Fig. 9. Flowchart for sector identification.
vcm ,1 − vcm ,2 T s = 0 (8)
1912 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

TABLE II
PROPOSED HYBRID PWM TECHNIQUE SWITCHING SEQUENCES (SECTOR-I)

Sub-Sector 2L PWM Switching Sequence (Inverter 1) Equivalent 3L PWM Switching Sequence

p p1 (− − −), (− − −), (− − −),(− − −), (− − −), (+ − −), (+ + −), (+ + +)
p2 (+ − −), (− − −), (− − −),(− − −), (+ − −), (+ + −), (+ + +), (+ + +)
p3 (− − −), (− − −), (+ − −),(+ + −), (+ + +), (+ + +), (+ + +), (+ + −)
q q1 (+ − −), (+ − −), (− − −),(− − −), (+ − −), (+ + −), (+ + −), (+ + +)
q2 (− − −), (+ − −), (+ − −),(+ + −), (+ + +), (+ + +), (+ + −), (+ + −)
r (+ − −), (+ − −), (+ − −),(− − −), (+ − −), (+ − −), (+ + −), (+ + +)
s (− − −), (+ − −), (+ + −),(+ + +), (+ + −), (+ + −), (+ + −), (+ + −)
(111), (110), (100), (000), (000), (100), (110), (111)
(211), (111), (110), (100), (100), (110), (111), (211)
(110), (111), (211), (221), (221), (211), (111), (110)
(211), (210), (110), (100), (100), (110), (210), (211)
(110), (210), (211), (221), (221), (211), (210), (110)
(211), (210), (200), (100), (100), (200), (210), (211)
(110), (210), (220), (221), (221), (220), (210), (110)

Fig. 10. Voltage waveforms for subsector r (H—High; L—Low).

the circulating current averaged over a switching period will also
be zero. The above-mentioned constraint is met for SVPWM as
displayed in Fig. 6.
III. PROPOSED HYBRID PWM TECHNIQUE
Different 3L switching sequences could be generated from
different switching sequences of parallel interleaved 2L invert-
ers. Now, when the conventional SVPWM technique is applied
to 2L parallel interleaved inverters, the equivalent 3L switching
states for (0° ࣘ θ ࣘ 30°) would be (111), (210), (200), (210),
and (111), as given by (6). For these equivalent 3L switch-
ing states, the error voltage vectors are shown in Fig. 7(a).
Now, if the switching sequences of 2L inverters are made such
that the nearest three voltage vectors are applied for the same
Fig. 11. Line current ripple per unit (p.u.). (a) m a = 0.4, (b) m a = 0.7,
(c) m a = 1.0.
reference vector [see Fig. 7(b)], the error voltage vectors will
reduce, which in turn reduces the ac-side line current ripple [8].
The proposed PWM technique ensures the application of three
nearest voltage vectors.
A. Selection of the 3L Switching Sequences
In the equivalent 3L space-vector diagram (see Fig. 4), there
are six voltage vectors V1 − V6 with even redundancy and one
zero vector V0 with odd redundancy. Redundancy provides the
degree of freedom, which could be utilized for reducing the error
vectors or ac-side line current ripple to a great extent [12], [13].
SHUKLA et al.: NOVEL CARRIER-BASED HYBRID PWM TECHNIQUE FOR MINIMIZATION OF LINE CURRENT RIPPLE IN TWO PARALLEL
TABLE III
CM OFFSET SIGNAL FOR THE PROPOSED HYBRID PWM TECHNIQUE
TABLE IV
SYSTEM PARAMETERS
Parameter Value
R 60 Ω
Rs 2.5 Ω
Ls 24 mH
Vd c 600 V
Ts 200 μs
Fig. 12. Line current ripple (p.u.) variation w.r.t. modulation index m a .
If the reference vector lies in sector-1 and the middle value of the
given reference signals is negative, i.e., vm id < 0, redundancy
of middle voltage vector V1 (211, 100) is utilized. However,
when vm id > 0, redundancy of middle voltage vector V2 (110,
221) is utilized. Similarly, the redundancy of middle voltage
vectors in other sectors is utilized for minimizing the ac-side
line current ripple.
In the proposed technique, the equivalent space-vector sec-
tor of the two parallel interleaved inverters system is divided
into seven subsectors (see Fig. 8). Method of sector identifi-
cation from the three-phase reference signals is displayed in
Fig. 9. For each subsector, a switching sequence is found out
purely on the basis of minimum error voltage vectors, satisfy-
ing the constraint given in (8). However, it is observed that one
cannot achieve maximum possible reduction of ac-side line cur-
rent ripple as well as reduction of the circulating current with
the same PWM sequence. So, a PWM technique with mini-
mum line current ripple and zero average circulating current is
1913
Fig. 13. Line current ripple (p.u.) variation of the proposed hybrid PWM
technique for different modulation index m a values.
Fig. 14. Experimental setup.
presented. The equivalent 3L switching sequences for the pro-
posed hybrid PWM technique are displayed in Table II. To
generate the equivalent 3L switching sequence, the required 2L
switching sequence for inverter 1 is shown in the second column
of Table II, and the required 2L switching sequence for inverter
2 is the reverse of the switching sequence of inverter 1. The pro-
posed PWM technique applies different switching sequences
for difference reference vectors whose tips lie in Sector I, as
shown in Table II, depending on its position in the sector. So,
the proposed technique is named as a hybrid PWM technique.
The proposed hybrid PWM technique is implemented using
the carrier-based approach. For implementing the conventional
PWM techniques using the carrier-based approach, a CM offset
is added to the given reference signals. However, the proposed
hybrid PWM technique is composed of the sequence with a
phase switching four times in a switching period (see Table II).
For implementing these sequences using the carrier-based ap-
proach, the reference-phase voltage signal that switches four
times in a switching period is divided into two signals that are
compared with the carrier signal. The output of the comparison
is passed through an EX-NOR or EX-OR logic gate to obtain the
desired switching sequence. The type of gate to be used would
depend on the magnitude of the middle value of the three-phase
reference voltage signals. For vm id < 0, EX-NOR gate is used,
while for the remaining conditions EX-OR gate is utilized.
1914
Fig. 15. Normalized total switching loss P S U B , T O T variation over a
sector.
Fig. 16. Experimental result of SVPWM, m a = 0.4. (a) Line currents
(2, 2, and 5 A/div). (b) 3·circulating current (1 A/div).
Fig. 17. Experimental result of SVPWM, m a = 0.7. (a) Line currents
(2, 2, and 5 A/div). (b) 3·circulating current (1 A/div).
Now, let the voltage reference vector Vref lies in sector r (see
Fig. 8). The voltage waveforms corresponding to the switching
sequence used in sector r are displayed in Fig. 10. Here, two
interleaved carriers corresponding to each inverter and magni-
tudes of the updated reference signals (vA1,ref , vB1,ref , vC1,ref )
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018
Fig. 18. Experimental result of SVPWM, m a = 1.0. (a) Line currents
(2, 2, and 5 A/div). (b) 3·circulating current (1 A/div).
are displayed. As phase A is to be switched four times within a
switching period, so two reference signals vA1,ref1 and vA1,ref2
are generated. These two reference signals are used to gener-
ate two pulses gvA1O1 and gvA1O2 , which may have high and
low levels. These pulses are passed through an EX-NOR gate to
get the desired gate signal and the pole voltage signal vA1O for
phase A of inverter 1. Similarly, signals for inverter 2 vA2O are
generated. The generated signals keep the average value of the
CM voltages difference over a switching period to zero (see
Fig. 10).
The error vectors produced by the proposed hybrid PWM
technique are similar to the error vectors generated by a 3L
inverter using conventional SVPWM technique [13]. Therefore,
the root mean square (rms) ac-side line current ripple produced
by the proposed PWM technique is same as that of a 3L inverter,
as displayed in Fig. 11.
B. CM Offset Calculation
For better dc-link utilization, a CM offset voff is added to the
reference phase signals. To modulate the parallel interleaved 2L
inverters as a single 3L inverter using the carrier based approach,
the CM offset is added to the reference signals which ensures
that the dwell times of redundant middle vectors are divided
equally. Using this CM offset, the updated reference signals are
generated for the phase switching four times, which will make
sure that the equivalent 3L switching sequence for minimum
line current ripple is generated. The switching waveforms over
a switching period Ts for the given reference signals (subsector
r) are displayed in Fig. 10. The corresponding 2L switching
sequences for parallel interleaved inverters are as follows:
(+ − −), (+ − −), (+ − −), (− − −), (+ − −), (+ − −),
(+ + −), (+ + +)................Inv1
(+ + +), (+ + −), (+ − −), (+ − −), (− − −), (+ − −),
(+ − −), (+ − −)...............Inv2.
SHUKLA et al.: NOVEL CARRIER-BASED HYBRID PWM TECHNIQUE FOR MINIMIZATION OF LINE CURRENT RIPPLE IN TWO PARALLEL 1915

Fig. 20. Experimental result of the proposed hybrid PWM technique,

m a = 0.4. (a) Line currents (2, 2, and 5 A/div). (b) 3·circulating current
(1 A/div).

Fig. 19. FFT analysis of line current iA for SVPWM, (a) m a = 0.4, (b)
m a = 0.7, (c) m a = 1.0. Fig. 21. Experimental result of the proposed hybrid PWM technique,
m a = 0.7. (a) Line currents (2, 2, and 5 A/div). (b) 3·circulating current
(1 A/div).
Let T1 3 , T2 3 , and Tz 3 be the dwell times of the equivalent
3L voltage vectors V13 , V7 , and V1 (see Fig. 8), respectively.
Let Ts 3 be the switching time of the equivalent 3L inverter. Equation (12) can be generalized as
The point to be noted here is that the 3L inverter switching time −vm ax − vm in
voff = . (13)
period will be half that of the 2L inverter, i.e., Ts 3 = Ts /2 (see 2
Fig. 6). From similar triangle and volt-sec balance approach, This CM offset will be added to phase B and C reference sig-
the required CM offset can be easily calculated. For the given nals. As phase A is to be switched four times within a switching
reference phase signals, using similar triangles approach (see period, so two reference signals are required. To summarize for
Fig. 10) sector 1, subsector r, modified reference signals for 2L parallel
Vd c
+ (vc,ref + voff ) Vdc interleaved inverters are
2
= (9) Vdc
T7 Ts /2 vA1,ref1 = 0, vA1,ref2 = − (voff + vA,ref )
2
where T7 is dwell time for switching state (+++).
Also, from switching sequences of 2L parallel interleaved vB1,ref = vB2,ref = (voff + vB,ref )
inverters and equivalent 3L switching sequence vC1,ref = vC2,ref = (voff + vC,ref ). (14)
Tz 3 The CM offsets are calculated in terms of maximum and
T7 = (10)
2 minimum values of the reference signals for each subsector of
2Tz = Tz 3 . (11) a sector and due to the sixfold symmetry, these signals could be
used in all six sectors, as shown in Table III. The reference sig-
Using (3)–(5) and (9)–(11), the CM offset is given by nal having maximum value or minimum value will switch four
−vA,ref − vC,ref times in a switching period. Therefore, two reference signals are
voff = . (12) required for the phase that switches four times, which are de-
2
1916 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 3, MARCH 2018

Fig. 22. Experimental result of the proposed hybrid PWM technique,

m a = 1.0. (a) Line currents (2, 2, and 5 A/div). (b) 3·circulating current
(1 A/div).

noted by vm ax1ref and vm ax2ref if phase having maximum value

switches four times or vm in1ref and vm in2ref if phase having
minimum value switches four times.

IV. SIMULATION AND EXPERIMENTAL RESULTS

A MATLAB-Simulink model of the parallel interleaved 2L
inverter system has been developed. The system parameters are
shown in Table IV. A MATLAB code using error vectors [8] is
developed for calculating normalized rms ac-side line current
ripple computed over a switching period Ts . The normalized
rms ac-side line current ripple of different PWM schemes for
different modulation indices ma for a sector is shown in Fig. 11.
The rms ac-side line current ripple remains minimum for the
proposed hybrid PWM technique compared to other PWM tech- Fig. 23. FFT analysis of line current iA for the proposed hybrid PWM
niques used in [8] as displayed in Fig. 11. The comparison of technique, (a) m a = 0.4, (b) m a = 0.7, (c) m a = 1.0.
normalized rms ac-side line current ripple w.r.t. modulation in-
dices ma for different PWM techniques is also carried out and TABLE V
is displayed in Fig. 12. The variation of normalized rms ac-side COMPARISON OF SVPWM AND PROPOSED PWM TECHNIQUE
line current ripple for the proposed hybrid PWM technique at
different modulation indices is shown in Fig. 13. Here, modula- Modulation index m a RMS ripple current (mA)
tion index ma is defined as the ratio of peak of reference signal
SVPWM Proposed PWM
and Vdc /2. 0.4 167 100
Effectiveness of the proposed technique is also examined 0.7 174 118
experimentally. The experimental implementation of the sys- 1.0 156 120
tem is done with the help of the digital signal processor
TMS320F28335 from Texas Instruments. Enhanced pulse width
modulation (EPWM) A and EPWM B channels are used for to the multiple switching of a phase in a switching period, the
generating the gate signals of inverter 1 and inverter 2, re- normalized total switching loss for the proposed PWM tech-
spectively. The software code execution time for the proposed nique is increased by nearly 8%, as compared to conventional
PWM technique is 5 μs as compared to the 4 μs required by SVPWM. This increase in switching loss could be treated as
the carrier-based SVPWM technique. A general-purpose in- a disadvantage of the proposed PWM technique. However, the
put/output (GPIO) signal is toggled for switching the logic gate ac-side line current ripple for the proposed PWM technique re-
operation (EX-OR to EX-NOR and vice versa). Same parameters duces by more than 40% at lower ma values and reduces nearly
are used for experimental purpose as applied in case of simu- by 24% at higher ma values as compared to the conventional
lation. A picture of the experimental setup is shown in Fig. 14. SVPWM technique.
The normalized total switching loss PSUB,TOT variation over Experimental results for SVPWM and proposed PWM tech-
a switching period [9] for a single inverter with load power nique are shown in Figs. 16–23. At all modulation indices, using
factor angle of 30° (lagging) is also displayed in Fig. 15. Due the proposed PWM technique, ripple content in the ac-side line
SHUKLA et al.: NOVEL CARRIER-BASED HYBRID PWM TECHNIQUE FOR MINIMIZATION OF LINE CURRENT RIPPLE IN TWO PARALLEL
TABLE VI
RMS AND PEAK–PEAK CIRCULATING CURRENT
Modualtion index ma RMS circulating current (mA)
SPWM SVPWM Proposed PWM
0.4 337 330
0.7 275.1 271.4
1.0 187.46 180.43
current iA turns out to be lower as compared to the commonly
used PWM technique [8]. In fast Fourier transform (FFT) plots
(see Figs. 19 and 23), the fundamental component is scaled
down by three to focus on harmonic components. The domi-
nant harmonics are displayed separately in the FFT plots. The
comparison of rms ac-side ripple current for different modu-
lation indices is displayed in Table V. The circulating current
produced by the proposed PWM technique also turns out to be
lower than the SVPWM technique at all different values of mod-
ulation indices. The comparison of circulating current applying
different PWM sequences for different modulation index values
is shown in Table VI. Both experimental and simulated results
accompany each other.
V. CONCLUSION
In this paper, a novel hybrid PWM technique is developed for
reducing the ac-side line current ripple in a parallel interleaved
inverter system. Here, two parallel interleaved 2L inverters are
analyzed as a single 3L inverter. Since the proposed technique
is carrier-based implemented, and the required subsector identi-
fication is done using the three-phase reference signals, the pro-
posed PWM technique requires less computational effort. The
updated reference signals for the proposed switching sequences
are calculated in terms of maximum and minimum values of
reference signals. Hence, the updated reference signals could
be used for each sector, for reducing the line current ripple. The
ac-side line current ripple is lower than the most commonly used
PWM techniques. The circulating current is also lower than the
conventional sinusoidal pulse width modulation (SPWM) and
SVPWM techniques for all modulation indices. However, the
number of switching in a switching period is increased, which
causes higher switching losses as compared to the conventional
SVPWM technique. The simulation and experimental results
also verify the proposed PWM technique.
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Kapil Shukla was born in Dungarpur, India. He
received the B.Tech. degree in electrical en-
gineering from Rajasthan Technical University,
Kota, India, in 2010, and the M.Tech. degree in
power systems from Delhi Technological Univer-
sity, New Delhi, India, in 2012. Since 2015, he
has been working toward the Ph.D. degree in the
Department of Electrical Engineering, Indian In-
stitute of Technology Delhi, New Delhi, India.
From 2012 to 2014, he was with the Depart-
ment of Electrical and Electronics Engineering,
Galgotias University, Greater Noida, India, as an Assistant Professor. He
then joined the Electrical Engineering Department, Manipal University
Jaipur, India, as an Assistant Professor. His research interests include
parallel operation of voltage source inverters and pulse width modulation
techniques.
Varun Malyala was born in Mahabubnagar, In-
dia. He received the B.E. degree in electrical en-
gineering from Osmania University, Hyderabad,
India, in 2014, and the M.Tech. degree in power
electronics, electrical machines and drives from
the Indian Institute of Technology Delhi, New
Delhi, India, in 2016.
His research interests include parallel opera-
tion of voltage source inverters and pulse width
modulation techniques.
Ramkrishan Maheshwari (S’10–M’11) was
born in Allahabad, India. He received the M.E.
degree in electrical engineering from the Indian
Institute of Science, Bangalore, India, in 2005,
and the Ph.D. degree in electrical engineering
from Aalborg University, Aalborg, Denmark, in
2012.
From 2005 to 2008, he was with Honey-
well Technology Solution Lab, Bangalore, India.
From 2012 to 2014, he was with the Department
of Energy Technology, Aalborg University, Den-
mark. He is currently an Assistant Professor with the Department of
Electrical Engineering, Indian Institute of Technology Delhi, New Delhi,
India. His research interests include modeling and control of power
converters.