Design and Implementation of 1 MHz
Active-Clamped Resonant Flyback Converter
Fu-Ciao Syu, Shang-Che Yeh, Yu-Chen Chang, Jing-Yuan Lin, Yao-Ching Hsieh, Huang-Jen Chiu,
Masahide Hojo, Kenji Yamanaka
Department of Electronic and Computer Engineering
National Taiwan University of Science and Technology, Taipei, Taiwan
il
Abstract—This paper aims to study an active-clamped resonant
flyback converter. The proposed resonant technique can
increase the zero-voltage switching (ZVS) range. Gallium
Nitride high electron mobility transistor (GaN HEMT) devices
are also applied in this study to reduce the switching losses at
high-frequency operation. Synchronous rectifier is designed on
secondary side to minimize the conduction losses resulted from
the high output current. A planar transformer is designed to
achieve low profile and high power density. A 65 W/ġ1ġMHz
prototype converter is implemented and tested under 90 VAC̚
264 VAC input and 19.5 V output condition. The experimental
resultsġare shown to verify the feasibility of the studied scheme.
The measured efficiency can be up to 90 %.
Index Terms—Active-clamped resonant flyback, GaN-HEMT,
planar transformer
I. INTRODUCTION
Low profile is a trend in the future adaptor design. Due to the
requirements of high efficiency and high power density, the
thermal issue is the most important design consideration. Zero-
voltage-switching (ZVS) and zero-current-switching (ZCS)
techniques are popular to reduce switching losses and achieve
low-profile design. Resonant techniques are commonly used to
meet the requirement [1]-[4]. For the active-clamped flyback
converter [5]-[7], by using GaN devices as the power switches
operated at 1 MHz can keep a good efficiency and good thermal
performance [8]-[10]. To realize high frequency operation, the
magnetics must be also optimized and miniaturized. Fig. 1
shows a schematic diagram of the studied active-clamped
resonant flyback converter with a lower clamping capacitance
Cr. Magnetizing inductance Lm and transformer leakage
inductance Lr resonant with Cr as the main switch S1 turned off.
That means the resonant circuit operated like a LLC converter
[11]-[13]. This resonant technique provides some advantages:
S1 and S2 are ZVS on the primary side while S3 on the
secondary side remains ZCS. Based on both results, increasing
switching frequency can minimize the converter size. The ZVS
turn-on of both switches can be achieved at wide range of input
voltage and load variations due to bidirectional magnetizing
inductor current. In comparison with the conventional flyback
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converter [14]-[16], the S1 duty cycle loss can be reduced due
to lower reverse resonant current. Table I compares the
differences between the conventional and proposed schemes.
Unlike LLC converter, the proposed converter’s voltage covers
both LLC region and SRC region (Fig.2). The circuit is
operated at SRC region under low input voltage condition while
operated at LLC region under high input voltage condition. In
short, with LLC converter’s advantages, the proposed converter
not only has a better efficiency but also a smaller size than the
conventional one by only changing its Cr value.
Fig. 1. Schematic diagram
Table I Comparison between the conventional and proposed schemes
Item Conventional Proposed
S3 switching condition hard switching ZCS
Soft switching condition related to load unrelated to load
Reversed resonant
current
higher lower
II. CIRCUIT CONFIGURATION AND OPERATION
The proposed converter schematic diagram is shown in Fig.
1. In the diagram, S1 is a main switch; S2 is an auxiliary active-
clamp switch. Both S1 and S2 are GaN transistors. S3 is a
synchronous rectification (SR) switch, adopting an small size
enhancement mode GaN (E-GaN) transistor. Cr is a resonant
capacitor. T1 is a transformer with turns ratio n, magnetizing
inductance Lm and equivalent leakage inductance Lr. As for the
switch, only the equivalent parasitic capacitors Coss1, Coss2, Coss3
and body diodes are taken into considerations. Co is an output
capacitor. Ro is an equivalent resistive load. The operating
principles are analyzed with following assumptions:
1) Lm value is greater than Lr value, and the secondary leakage
inductance is ignored.
2) The output capacitor Co is large enough that voltage is a
constant dc voltage with a negligible ripple.

3) The proposed converter operation is at steady-state. of S1, and iLr is equal to the negative iLm. iLr is linearly increased.
The iLr equation is:
The steady-state waveform can be seen in Fig. 2. There are
7 intervals (t0-t7) in SRC mode while there are 8 intervals (t0-t8)
Vin
in LLC mode. The difference between SRC and LLC is the last i Lr (t) u t  i Lr (t1 )
interval (t7-t8). L r +L m   

Fig. 4. T2 [t1-t2]
Stage T3 [t2 -t3]:
The current path is shown as Fig. 5. At t2, the S1 arrives ZVS.
The input voltage Vin charges Lm, and the magnetizing current
increases linearly from t1 to t3 . The iLm equation can be
calculated as follows:

V in
i L m (t) u ( t  t 1 )  i L m (t 1 )
Lm  

Fig. 2 Steady-state waveform

Stage T1 [t0 -t1]:
Fig. 3 shows the current path. At t0, the switch S2 is turned
off during stage T1. The negative iLm discharges Coss1. Since
Coss1 value is low, the interval of this period is negligibly short,
which leads to an approximately liner charging and discharging
characteristic. Thus, iLm can be seen as a constant in this interval.
The iLr equation is: Fig. 5. T3 [t3-t4]
Fig. 6 is a proposed converter compared with a conventional
C oss1
i Lr (t)  nVo sinω o t  i Lr (t 0 )  cosωo t flyback. The conventional flyback in this moment is displayed
L r +L m (1) in Fig. 6(a), iLr is a greater negative value, and iLr continually
ω0, here in the equation, refers to a resonant frequency. increases until it equals iLm. The proposal circuit is shown as
1 Fig. 6(b). A low negative current exists as iLr is at t3-t4 internal,
ωo which causes its duty loss to decrease.
(Lr +Lm ) u Coss1 Effective duty loss:
(2)
Deff D  ΔD (5)
ΔD refers to a duty cycle loss, and the calculation formula
derivation is as:

Lr u (Δi)
ΔD
Vin u TS   
Fig. 3 T1 [t0-t1]
Vin is an input voltage, TS is a switch cycle.
Stage T2 [t1-t2]:
The current path is shown as Fig. 4. At t1, the voltage VDS1 is
reduced to zero. The current iLr flows through the body diode

 The current path shows in Fig. 9. At t5, the switch S2 turns
on with ZVS. The current iS2 is the negative current iLm, which
continue charging Cr. In this condition, the clamp capacitor
voltage is lower than nVo, VCr < nVo , and S3 has no body diode
because EGaN causes no energy pass to load, and the load is
provided by the output capacitor Co instead. Since the capacitor
voltage ripple value is low and the charge time is short, the iLm
is considered to be a constant in this interval.
'

(a)

Fig. 9. T6 [t5-t6]
Stage T7 [t6-t7]:
The current path shows in Fig. 10. At t6 , iLm continues
(b) charging the clamp capacitor Cr until VCr is greater than nVo.
Fig. 6 Duty cycle loss: (a) Tradition AT clamped flyback (b) AT clamped Cr provides positive voltage, then passes energy to secondary
resonant flyback by T1 through S3 to load. In this condition, Lr and Cr are taken
Stage T4 [t3 -t4]: as series resonant type, passing energy to load. In addition, Lm
The current path shows in Fig. 7. At t4, the main switch S1 is does not attend this resonant. iLr is changed from positive to
turned off. Coss1 is charged to Vin+nVo ≈Vin+VCr and S2 is negative current. It will cycle to Stage T1 [t0 -t1] condition when
discharged from Vin+nVo to zero by iLm. The interval of this the input voltage is at low line (SRC mode). The iLr equation in
period is so brief that results in an approximately linear this interval is as follows:
charging and discharging characteristic. The iLm is considered C
to be a constant in this interval. i Lr (t) i L r (t 6 )cosω r t  [nVo  VCr (t 6 )] r sinω r t
Lr (8)
where ω is resonant frequency:
1
ωr
Lr u Cr (9)

Fig. 7 T4 [t3-t4]
Stage T5 [t4 -t5]:
The current path can be seen in Fig. 8. At t5, the body diode
of S2 is conducted by iLm. Thereafter, the resonant capacitor Cr
is charged with iLm .
Fig. 10. T7 [t6-t7]
i Lr (t) i Lr (t 4 )cosω0 t Stage T8 [t7-t8]:
(7)
iLr Lr T1 iS3 The current path can be seen in Fig. 11. At t6, the resonant
n:1
iS2 iLm iP current iLr is lower than iLm. Therefore, S3 resonates to zero and
Cr
DB2 Coss2
it is turned off with ZCS. From t6 to t7, the voltage applied on
Lm
S2
Co Ro Vo the magnetizing inductor is nVo, and the magnetizing current
vds2 Coss3
iLm becomes negative, thus providing a ZVS turn-on condition
Vin for the main switch S1. The state equations of iLm from t4 to t8
iS1
S3 can be calculated as follows:
S1 vds1
DB1 Coss1

Fig. 8. T5 [t4-t5]
Stage T6 [t5-t6]:


  nVo Vo u n
i L m (t) i Lm (t 4 )  (t  t 4 ) Dmin
Lm (10) Vin-max  Vo u n (16)
iLr Lr T1 iS3
iS2 n:1
iLm iP IV. EXPERIMENTAL RESULTS
Cr
DB2 Coss2 Lm Table II shows the specification of an active clamped flyback
Co Ro Vo
S2 vds2 Coss3 with resonant technique at 65W. The result of S1 remains ZVS
V in (as shown in Fig. 12 and Fig. 13). Then, a higher efficiency is
iS1
S3
noticed as well, as presented in Fig. 14. Last but not least, Fig.
S1
15 demonstrates a proposed convert prototype.
vDS1
Table II Circuit Specifications
DB1 Coss1
AC input voltage 90 VAC-264 VAC
Fig. 11. T8 [t7 -t8] AC line frequency 60 Hz
With an assumption that t0-t1 and t3-t4 are relatively short, DC output voltage 19.5 V
these two intervals are ignored. Voltage gain M can be found Output Power 65 W
Switch frequency 1MHz
by two magnetic flux balance condition formula at stable state.
The first equation, derived from formula (4) and (10), is a
magnetic inductor in a switch cycle, as shown in (11).
TS t3 t8
³ 0
L m u i Lm (t)dt ³t1
Vin dt  ³ (  nVo )dt
t4
0
(11)
The other equation is derived from t6 to t7 (8), as the flux
balances on resonant inductor Lr:
t7 ­° Cr ½°
³ L u®°[nV V (t )]
r o Cr 6
Lr
sinωr (t t6) iLm (t6)cosωr (t t6)¾dt 0
¿°
t6
¯ (12) (a) (b)
The ripple voltage on the resonant capacity Cr is usually lower Fig. 12. The VGS and VDS of two sets of switch at VACɨ115 Vˣ(a)IOɨ0.8 A
than the average voltage Vcr. Based on equation (11) and (b)IOɨ3.3 A
(12), voltage gain M is found.
Vo 1 D
M u
Vin n 1 D (13)
NP
n
And,
NS

III. DESIGN CONSIDERATION

iLr equals iLm when the transformer is decoupling. Then, S3 (a) (b)
arrives ZCS, shown as Fig.2 (t6-t7). According to formula (8), Fig. 13. The VGS and VDS of two sets of switch at VACɨ230 V: (a)IOɨ0.8 A
the iLr have resonant period cycle 2π × . Because iLm is (b)IOɨ3.3 A
a negative slope, t6-t7 needs to be shorter than the resonant
period cycle this time.
In the other word, t6-t7 period ≤ 2π × , ZCS
condition follows as (14):
1 D
fs d
2S u L r u C r
(14)
To arrange (14), it is found that Cr design is as (15):
(1  D ) 2 (15)
C r d 2 min
2 S u f s2 u L r
As Dmin exists at high line, and the main switch S1 operates a
minimum duty. According to formula (13), the
calculation is found as: Fig 14 Efficiency to output current


 VAC=230V efficiency is lower than VAC=115V because of
switching loss. In spite of the proposal circuit arrives has ZVS
but still have switching loss at EGaN transistor. The proposal
converter like LLC topology, Turn off loss need to consider.
Actually, the higher input voltage, the higher switching loss.
The condition loss and switching loss at VAC=230V, switching
loss weight ratio is higher than condition loss at low load.
Finally VAC=230V efficiency is positive slope when load
increase, the main loss change from switching to condition loss.
7.8 (cm)
6.1 (cm)
[8] X. Huang, W. Du, F. C. Lee, and Q. Li, “A novel driving scheme for
synchronous rectifier in MHz CRM flyback converter with GaN
devices,” in proc. IEEE ECCE, 2015, pp. 5089-5095
[9] Z. Zhang, K. D. T. Ngo, and J. L. Nilles, “A 30-W flyback converter
operating at 5 MHz,” in proc. IEEE APEC, 2014, pp. 1415-1421.
[10] X. Huang, J. Feng, W. Du, F. C. Lee, and Q. Li, "Design consideration
of MHz active clamp flyback converter with GaN devices for low
power adapter application," in proc. IEEE APEC, 2016, pp. 2334-2341.
[11] R. Liu and C. Q. Lee, “The LLC-type series resonant converter-
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range application,” IEEE Trans. Power Electron., vol. 28, no. 4, pp.
1946-1960, Apr. 2013.
[13] Z. Fang, S. Duan, C. Chen, X. Chen, and J. Zhang, “Optimal design
method for LLC resonant converter with wide range output voltage,” in
Applied Power Electronics Conf. and Exposition, 2013, pp. 2106-2111.
[14] Robert Watson, Fred C. Lee, and Guichao Hua, "Utilization of an
active-clamp circuit to achieve soft switching in flyback converters,"
IEEE Trans. Power Electronics, vol. 11, pp. 162-169, Jan. 1996.
[15] C. T. Choi, C. K. Li, and S. K. Kok, “Control of an active clamp
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Fig. 15. Proposed converter hardware prototype.

V. CONCLUSION
In this paper, an active-clamped resonant flyback converter
is studied and designed to realize ZVS turn-on under wide input
voltage and load variations. According to the experimental
results of a 65 W/ 1 MHz prototype, the measured efficiency
can be up to 90 %.

ACKNOWLEDGMENT
The authors would like to acknowledge the financial support
of the Ministry of Science and Technology of Taiwan through
grant number MOST 106-3113-E-007-001-CC2, MOST 106-
2221-E-011-095-MY3.

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