EE 3CL4, §6

1 / 63
Tim Davidson

Compensators

Lead
compensation
Design via Root
EE3CL4:
Locus
Lead Compensator
example
Introduction to Linear Control Systems
Cascade
compensation
Section 6: Design of Lead and Lag Controllers using
and
steady-state
Root Locus
errors

Lag
Compensation
Design via Root
Tim Davidson
Locus
Lag compensator
example
McMaster University
Prop. vs Lead
vs Lag

Concluding Winter 2014

Insights
EE 3CL4, §6
2 / 63
Tim Davidson Outline
Compensators

Lead 1 Compensators
compensation
Design via Root
Locus
Lead Compensator
2 Lead compensation
example
Design via Root Locus
Cascade
compensation Lead Compensator example
and
steady-state
errors
3 Cascade compensation and steady-state errors
Lag
Compensation
Design via Root
Locus
4 Lag Compensation
Lag compensator
example Design via Root Locus
Prop. vs Lead Lag compensator example
vs Lag

Concluding
Insights 5 Prop. vs Lead vs Lag

6 Concluding Insights
EE 3CL4, §6
4 / 63
Tim Davidson Compensators
Compensators • Early in the course we provided some useful guidelines
Lead regarding the relationships between the pole positions
compensation
Design via Root of a system and certain aspects of its performance
Locus
Lead Compensator
example
• Using root locus techniques, we have seen how the
Cascade pole positions of a closed loop can be adjusted by
compensation
and varying a parameter
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example • What happens if we are unable to obtain that
Prop. vs Lead performance that we want by doing this?
vs Lag
• Ask ourselves whether this is really the performance
Concluding
Insights that we want
• Ask whether we can change the system,
say by buying different components
• seek to compensate for the undesirable aspects of the
process
EE 3CL4, §6
5 / 63
Tim Davidson Cascade compensation
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state • Usually, the plant is a physical process
errors

Lag
• If commands and measurements are made electrically,
Compensation
Design via Root
compensator is often an electric circuit
Locus
Lag compensator • General form of the compensator is
example

Kc M
Q
Prop. vs Lead
(s + zi )
vs Lag
Gc (s) = Qn i=1
Concluding j=1 (s + pj )
Insights

• Therefore, the cascade compensator adds open loop

poles and open loop zeros
• These will change the shape of the root locus
EE 3CL4, §6
6 / 63
Tim Davidson Compensator design
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation • Where should we put new poles and zeros to achieve
and
steady-state desired performance?
errors

Lag
• That is the art of compensator design
Compensation
Design via Root
Locus
• We will consider first order compensators of the form
Lag compensator
example
Kc (s + z) K̃c (1 + s/z)
Prop. vs Lead Gc (s) = = , where K̃c = Kc z/p
vs Lag (s + p) (1 + s/p)
Concluding
Insights • with the pole −p in the left half plane
• and the zero, −z in the left half plane, too
• For reasons that will soon become clear
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
EE 3CL4, §6
8 / 63
Tim Davidson Lead compensation
Compensators

Lead
compensation
Design via Root
Locus
Kc (s + z)
Lead Compensator
example Gc (s) =
Cascade
(s + p)
compensation
and
with |z| < |p|. That is, zero closer to origin than pole
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
Let p = 1/τp and z = 1/(αlead τp ). Since z < p, αlead > 1.
Define K̃c = Kc z/p = Kc /αlead . Then
Kc (s + z) K̃c (1 + αlead τp s)
Gc (s) = =
(s + p) (1 + τp s)
EE 3CL4, §6
9 / 63
Tim Davidson Lead compensation
Kc (s+z) K̃c (1+αlead τp s)
With |z| < |p|, αlead > 1, Gc (s) = (s+p) = (1+τp s)
Compensators

Lead • Frequency response:

compensation
Design via Root
Locus K̃c (1 + jωαlead τp )
Lead Compensator Gc (jω) =
example (1 + jωτp )
Cascade
compensation
and • Bode diagram (in the figure, K1 = K̃c )
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
• Between ω = z and ω = p, |Gc (jω)| ≈ K̃c ωαlead τp
• What kind of operator has a frequency response with
magnitude proportional to ω? Differentiator
• Note that the phase is positive. Hence “phase lead”
EE 3CL4, §6
10 / 63
Tim Davidson A passive phase lead network
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag
V2 (s)
Concluding
Insights
Homework: Show that V1 (s) has the phase lead
characteristic
EE 3CL4, §6
11 / 63
Tim Davidson Active lead and lag networks
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example Here’s an example of an active network architecture.
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
12 / 63
Tim Davidson Principles of Lead design via
Compensators Root Locus
Lead
compensation • The compensator adds poles and zeros to the P(s) in
Design via Root
Locus
Lead Compensator
the root locus procedure.
example

Cascade
• Hence we can change the shape of the root locus.
compensation
and
steady-state • If we can capture desirable performance in terms of
errors
positions of closed loop poles
Lag
Compensation • then compensator design problem reduces to:
Design via Root
Locus • changing the shape of the root locus so that these
Lag compensator
example desired closed-loop pole positions appear on the root
Prop. vs Lead locus
vs Lag
• finding the gain that places the closed-loop pole
Concluding
Insights positions at their desired positions

• What tools do we have to do this?

• Phase criterion and magnitude criterion, respectively
EE 3CL4, §6
13 / 63
Tim Davidson Root Locus Principles
Compensators • The point s0 is on the root locus of P(s) if 1 + KP(s0 ) = 0.
KG M
Q
Lead (s+zi )
compensation • In first order compensator design with G(s) = Qn i=1
j=1 (s+pj )
Design via Root QM
Locus Kc (s+z) (s+z) Qi=1 (s+zi )
Lead Compensator and Gc = (s+p) , we have P(s) = (s+p) n and
example j=1 (s+pj )

Cascade K = Kc KG . We will restrict attention to the case of K > 0

compensation
and
steady-state
• Phase cond. s0 is on root locus if ∠P(s0 ) = 180◦ + k 360◦ :
errors
M n
Lag X X
Compensation (angle from −zi to s0 ) − (angle from −pj to s0 )
Design via Root
Locus i=1 j=1
Lag compensator
example
+ (angle from −z to s0 ) − (angle from −p to s0 )
Prop. vs Lead
vs Lag = 180◦ + k 360◦
Concluding
Insights • Mag. cond. If s0 satisfies phase condition, the gain that puts
a closed-loop pole at s0 is K = 1/|P(s0 )|:
Qn
j=1 (dist from −pj to s0 ) (dist from −p to s0 )
K = QM ×
(dist from −zi to s0 ) (dist from −z to s0 )
i=1
EE 3CL4, §6
14 / 63
Tim Davidson RL design: Basic procedure
Compensators 1 Translate design specifications into desired positions of
Lead dominant poles
compensation
Design via Root 2 Sketch root locus of uncompensated system to see if desired
Locus
Lead Compensator
example
positions can be achieved
Cascade 3 If not, choose the positions of the pole and zero of the
compensation
and compensator so that the desired positions lie on the root
steady-state
errors
locus (phase criterion), if that is possible
Lag 4 Evaluate the gain required to put the poles there
Compensation
Design via Root
(magnitude criterion)
Locus
Lag compensator
example
5 Evaluate the total system gain so that the steady-state error
Prop. vs Lead
constants can be determined
vs Lag
6 If the steady state error constants are not satisfactory, repeat
Concluding
Insights
This procedure enables relatively straightforward design of
systems with specifications in terms of rise time, settling time, and
overshoot; i.e., the transient response.
For systems with steady-state error specifications, Bode (and
Nyquist) methods may be more straightforward (later)
EE 3CL4, §6
15 / 63
Tim Davidson Lead Comp. example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade 1
compensation Consider a case with G(s) = s(s+2) and H(s) = 1.
and
steady-state Design a lead compensator to achieve:
errors

Lag
• damping coefficient ζ = 0.5 and
Compensation
Design via Root • velocity error constant Kv = lims→0 sGc (s)G(s) > 20
Locus
Lag compensator
example • swift transient response (small settling time)
Prop. vs Lead
vs Lag
What to do?
Concluding
Insights
• Can we achieve this with proportional control?
• If not we will attempt lead control
EE 3CL4, §6
16 / 63
Tim Davidson Attempt prop. control
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation 1
Design via Root • Sketch root locus of s(s+2)
Locus
Lag compensator
example • Sketch rays of angle cos (0.5) = 60◦ to neg. real axis
−1

Prop. vs Lead • Are there intersections? Yes

vs Lag

Concluding
• If so, what is the corresponding value of K = KP KG ?
Insights K = d1 d2 = 5
• Does that K generate a large enough velocity error const.?
No, Kv = 2.5 :(
• Do the closed-loop poles have responses that decay
quickly? No, Ts ≈ 4s
EE 3CL4, §6
17 / 63
Tim Davidson Prop. control, step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Lead compensated design
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus • Plot poles of G(s).
Where should the closed-loop poles be? cos−1 (0.5) = 60◦
Lag compensator
example

Prop. vs Lead
vs Lag
• Note that the settling time is not specified; it only needs to be
Concluding
small. This provides design flexibility.
Insights • However, we need a large Kv which will require large gain.
Need desired positions far from open loop poles.
• Let’s start with desired roots at −4 ± j8
√
• This pair has Ts = 1s and ωn = 42 + 82 ≈ 8.9
EE 3CL4, §6
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Tim Davidson Lead Comp. example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation • Now where to put the zero and pole? (Centroid denoted ca )
Design via Root
Locus
Lag compensator
• Rule of thumb: put zero under desired root, or just to the left
example

Prop. vs Lead
• Determine position of the pole using angle criterion
vs Lag X X
Concluding
angles from OL zeros − angles from OL poles = 180◦
Insights
∼ 90 − (116 + 104 + θp ) = 180
=⇒ θp ≈ 50

• Hence pole at −p ≈ −10.86

EE 3CL4, §6
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Tim Davidson Lead Comp. example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
• Gain of compensated system:
Lag compensator
example
Prod. dist. from open-loop poles d1 d2 dp
Prop. vs Lead =
vs Lag Prod. dist. from open-loop zeros dz
Concluding 8.94(8.25)(10.54)
Insights ≈ ≈ 97.1
8
97.1(s+4)
• Hence compensated open loop: Gc (s)G(s) = s(s+2)(s+10.86)

• Velocity constant: Kv = lims→0 sGc (s)G(s) ≈ 17.9 :(

EE 3CL4, §6
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Tim Davidson What to do now?
Compensators
• We tried hard, but did not achieve the design specs
Lead
compensation • Let’s go back and re-examine our choices
Design via Root
Locus
Lead Compensator • Zero position of compensator was chosen via rule of
example

Cascade
thumb
compensation
and • Can we do better?
steady-state
errors Yes, but two parameter design becomes trickier.
Lag • What were other choices that we made?
Compensation
Design via Root
Locus • We chose desired poles to be of magnitude ωn ≈ 8.9
Lag compensator
example
• We could choose them to be further away
Prop. vs Lead
vs Lag (faster transient response)
Concluding • By how much?
Insights
• Show that when desired poles have ωn = 10 as well as
the required ζ = 0.5, then the choice of z ≈ 4.47,
p ≈ 12.5 and KC ≈ 125 results in Kv ≈ 22.3
EE 3CL4, §6
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Tim Davidson Root Locus, new lead comp.
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Centroid denoted ca
EE 3CL4, §6
23 / 63
Tim Davidson New lead comp.
Compensators Prop.-contr. Lead contr.
Lead
125(s+4.47)
compensation Controller, GC (s) 5 (s+12.5)
Design via Root
Locus
Lead Compensator 5 125(s+4.47) 1
example OL TF, GC (s)G(s) s(s+2) (s+12.5) s(s+2)
Cascade
compensation Y (s) 5 125(s+4.47)
and
CL TF, R(s) s(s+2)+5 s(s+2)(s+12.5)+125(s+4.47)
steady-state
errors
CL poles −1 ± j2 −4.47 ± j8.94, −5.59
Lag
Compensation
Design via Root
CL zeros ∞, ∞ −4.47, ∞, ∞
Locus
Lag compensator 5 131(1+0.013s) 1.71
example CL TF, again s2 +2s+5 s2 +8.94s+100
− s+5.59
Prop. vs Lead
vs Lag

Concluding
Insights
• Complex conjugate poles still dominate
• Closed-loop zero at -4.47 (which is also an open-loop
zero) reduces impact of closed-loop pole at -5.59; see
also slide 48 of Section 3: Fundamentals of Feedback
EE 3CL4, §6
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Tim Davidson New lead comp., ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson New lead comp., ramp
Compensators response, detail
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson New lead comp., step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
Note faster settling time than prop. controlled loop,
However, the CL zero has increased the overshoot a little
Perhaps we should go back and re-design for ζ = 0.45
in order to better control the overshoot
EE 3CL4, §6
27 / 63
Tim Davidson Outcomes
Compensators • Root locus approach to phase lead design was
Lead reasonably successful in terms of putting dominant
compensation
Design via Root poles in desired positions; e.g., in terms of ζ and ωn
Locus
Lead Compensator
example • We did this by positioning the pole and zero of the lead
Cascade
compensation
compensator so as to change the shape of the root
and
steady-state
locus
errors

Lag
• However, root locus approach does not provide
Compensation
Design via Root
independent control over steady-state error constants
Locus
Lag compensator
(details upcoming)
example

Prop. vs Lead • That said, since lead compensators reduce the DC gain
vs Lag
(they resemble differentiators), they are not normally
Concluding
Insights used to control steady-state error.
• The goal of our lag compensator design will be to
increase the steady-state error constants, without
moving the other poles too far
EE 3CL4, §6
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Tim Davidson Cascade compensation
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors
• Throughout this lecture, and all the discussion on cascade
Lag
Compensation compensation, we will consider the case in which H(s) = 1.
Design via Root
Locus
Lag compensator
• We will consider first order compensators of the form
example

Prop. vs Lead K (s + z)
vs Lag Gc (s) =
(s + p)
Concluding
Insights
with the pole, −p, and the zero, −z, both in the left half plane
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
EE 3CL4, §6
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Tim Davidson Steady-state errors
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator If closed loop stable, steady state error for input R(s):
example

Cascade R(s)
compensation ess = lim e(t) = lim s
and t→∞ s→0 1 + GC (s)G(s)
steady-state Q
errors KG i (s+zi ) KC (s+z)
Let G(s) = Q and consider GC (s) =
Lag j (s+pj ) (s+p)
Compensation
Design via Root • Consider the case in which G(s) is a type-0 system.
Locus
Lag compensator
example
• Steady state error due to a step r (t) = Au(t):
Prop. vs Lead ess = 1+KAposn , where
vs Lag Q
Concluding KC z KG i zi
Insights
Kposn = GC (0)G(0) = Q
p j pj

• Note that for a lead compensator, z/p < 1,

• So lead compensation may degrade steady-state error
performance
EE 3CL4, §6
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Tim Davidson Steady-state error
Compensators • Now, consider the case
Q in which G(s) is a type-1
Lead KGQ i (s+zi )
compensation system, G(s) = s j (s+pj )
Design via Root
Locus
Lead Compensator • Steady-state error due to a ramp r (t) = At: ess = A/Kv ,
example

Cascade
where the velocity constant is
compensation
and
Q
steady-state KC z KG i zi
errors Kv = lim sGc (s)G(s) = Q
s→0 p j pj
Lag
Compensation
Design via Root
Locus
Lag compensator
example
• Once again, lead compensation may degrade
Prop. vs Lead steady-state error performance
vs Lag

Concluding
Insights • Is there a way to increase the value of these error
constants while leaving the closed loop poles in
essentially the same place as they were in an
uncompensated system? Perhaps |z| > |p|?
EE 3CL4, §6
33 / 63
Tim Davidson Lag compensation
Compensators

Lead
compensation
Design via Root
Locus
Kc (s + z)
Lead Compensator
example Gc (s) =
(s + p)
Cascade
compensation
and
with |z| > |p|. That is, pole closer to origin than zero
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights Let z = 1/τz and p = 1/(αlag τz ). Since z > p, αlag > 1.
Define K̃c = Kc z/p = Kc αlag . Then
Kc (s + z) K̃c (1 + τz s)
Gc (s) = =
(s + p) (1 + αlag τz s)
EE 3CL4, §6
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Tim Davidson Frequency response
Compensators
K̃C (1 + jωτz )
Lead
compensation
Gc (jω) =
Design via Root
(1 + jωαlag τz )
Locus
Lead Compensator
example Magnitude
Cascade
compensation
• Low frequency gain: K̃C
and
steady-state • Corner freq. in denominator at ωp = p = 1/(αlag τz )
errors

Lag
• Corner freq. in numerator at ωz = z = 1/τz
Compensation
Design via Root
• ωp < ωz
Locus
Lag compensator
example • High frequency gain: K̃C /αlag = KC
Prop. vs Lead
vs Lag
Phase
Concluding • φ(ω) = atan(ωτz ) − atan(αlag ωτz )
Insights
• At low frequency: φ(ω) = 0
• At high frequency: φ(ω) = 0
√
• In between: negative, with max. lag at ω = zp
EE 3CL4, §6
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Tim Davidson Bode Diagram, with K̃c = 1
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Note integrative characteristic

EE 3CL4, §6
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Tim Davidson A passive phase lag network
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Active lead and lag networks
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example Here’s an example of an active network architecture.
Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Lag compensator design
• Lag compensator: Gc (s) = Kc s+z
Compensators
s+p . with |z| > |p|.
Lead
compensation • Recall position error constant for compensated type-0
Design via Root
Locus system and velocity error constant for compensated type-1
Lead Compensator
example system:
Cascade Q Q
compensation KC z KG i zi KC z KG i zi
and Kposn = Q , Kv = Q
steady-state p j pj p j pj
errors

Lag where in the latter case the product in the denominator is

Compensation
Design via Root over the non-zero poles.
Locus
Lag compensator
example

Prop. vs Lead
Design Principles
vs Lag
• We don’t try to reshape the uncompensated root locus.
Concluding
Insights
• We just try to increase the value of the desired error constant
by a factor αlag = z/p without moving the poles (well not
much)
• Reshaping was the goal of lead compensator design
EE 3CL4, §6
39 / 63
Tim Davidson Lag compensator design
Compensators

Lead
compensation Design principles:
Design via Root
Locus • Don’t reshape the root locus
Lead Compensator
example
• Adding the open loop pole and zero from the
Cascade
compensation
compensator should only result in a small change to the
and angle criterion for any point on the uncompensated root
steady-state
errors locus
Lag • Angles from compensator pole and zero to any point on
Compensation
Design via Root
the locus must be similar
Locus
Lag compensator
• Pole and zero must be close together
example

Prop. vs Lead • Increase value of error constant:

vs Lag

Concluding
• Want to have a large value for αlag = z/p.
Insights • How can that happen if z and p are close together?
• Only if z and p are both small, i.e., close to the origin
EE 3CL4, §6
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Tim Davidson Lag comp. design via Root
Compensators Locus
Lead
compensation
1 Obtain the root locus of uncompensated system
Design via Root
Locus
2 From transient performance specs, locate suitable
Lead Compensator
example dominant pole positions on that locus
Cascade 3 Obtain the loop gain for these points, K = KP KG ;
compensation
and hence the (closed-loop) steady-state error constant
steady-state
errors 4 Calculate the necessary increase. Hence αlag = z/p
Lag
Compensation
5 Place pole and zero close to the origin (with respect to
Design via Root
Locus
desired pole positions), with z = αlag p.
Lag compensator
example Typically, choose z and p so that their angles to desired
Prop. vs Lead poles differ by less than 1◦ .
vs Lag
6 Set KC = KP
Concluding
Insights
What if there is nothing suitable at step 2?
• Perhaps do lead compensation first,
• then lag compensation on lead compensated plant.
i.e., design a lead-lag compensator
EE 3CL4, §6
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Tim Davidson Example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors 1
Let’s consider, again, the case with G(s) = s(s+2) .
Lag
Compensation Design a lag compensator to achieve damping coefficient
Design via Root
Locus ζ = 0.5 and velocity error constant Kv > 20
Lag compensator
example

Prop. vs Lead
vs Lag
Note: we will get a different closed loop from our lead
Concluding
design.
Insights

First step, obtain uncompensated root locus, and locate

desired dominant pole locations
EE 3CL4, §6
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Tim Davidson Example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator • Gain required to put closed loop poles in desired position =
example
prod. distances from open loop poles
Prop. vs Lead
vs Lag
• That is, K = 2.242 = 5. Therefore KP = K /KG = 5
Concluding
Insights • Velocity error const: Kv ,unc = lims→0 sKP G(s) = K /2 = 2.5
• The increase required is 20/2.5 = 8
• That implies must choose p = z/8, where z is chosen to be
close to the origin with respect to dominant closed-loop poles
EE 3CL4, §6
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Tim Davidson Example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Let’s choose z = 0.1. Hence, p = 1/80.

EE 3CL4, §6
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Tim Davidson Example
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag
KC (s+0.1)
Concluding Root locus of lag comp’d system with GC (s) = (s+1/80)
Insights
• ’s: closed-loop poles for prop.-control with KP = 5
• ×’s: open-loop poles of lag comp’d system
• ◦: OL zero of lag comp’d system; also a CL zero
• 4’s: Closed-loop poles for lag-control with KC = 5
EE 3CL4, §6
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Tim Davidson Example
Compensators Prop.-contr. Lag contr.
Lead
5(s+0.1)
compensation Controller, GC (s) 5 (s+1/80)
Design via Root
Locus
5 5(s+0.1) 1
Lead Compensator
example OL TF, GC (s)G(s) s(s+2) (s+1/80) s(s+2)
Cascade
Y (s) 5 5(s+0.1)
compensation
and
CL TF, R(s) s(s+2)+5 s(s+2)(s+1/80)+5(s+0.1)
steady-state
errors CL poles −1 ± j2 −0.955 ± j1.979, −0.104
Lag
Compensation
Design via Root
CL zeros ∞, ∞ −0.1, ∞, ∞
Locus
Lag compensator 5 4.999(1+7×10−4 s) −0.004
example CL TF, again s2 +2s+5 s2 +1.909s+4.827
+ s+0.104
Prop. vs Lead
vs Lag

Concluding
Insights
• Complex conjugate poles still dominate
• Closed-loop zero at -0.1 (which is also an open-loop
zero) reduces impact of closed-loop pole at -0.104; see
also slide 48 of Section 3: Fundamentals of Feedback
EE 3CL4, §6
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Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Note longer settling time of lag controlled loop,

and slight increase in overshoot, due to CL zero
EE 3CL4, §6
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Tim Davidson Design Comparisons
Compensators
1
Lead
For given design example: G(s) = s(s+2) , ζ ≈ 0.5, Kv ≥ 20.
compensation
Design via Root Prop.-contr. Lead contr. Lag contr.
Locus
Lead Compensator
125(s+4.47) 5(s+0.1)
example
GC (s) 5 (s+12.5) (s+1/80)
Cascade
compensation Y (s) 5 131(1+0.013s) 1.71 4.999(1+7×10−4 s) −0.004
and R(s) s2 +2s+5 s2 +8.94s+100
− s+5.59 s2 +1.909s+4.827
+ s+0.104
steady-state
errors CL poles −1 ± j2 −4.47 ± j8.94, −5.59 −0.955 ± j1.979, −0.104
Lag
Compensation CL zeros ∞, ∞ −4.47, ∞, ∞ −0.1, ∞, ∞
Design via Root
Locus
Lag compensator
1/Kv 0.4 0.045 0.05
example

Prop. vs Lead • Lag design retains similar CL poles to prop. design,

vs Lag

Concluding
plus a “slow” pole
Insights
• CL poles of lead design quite different
• Lead and lag meet Kv specification (1/Kv = ess,ramp )
EE 3CL4, §6
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Tim Davidson Ramp response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Ramp response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Step response
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Step response, detail
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Anything else to consider?
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Anything else to consider?
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state With H(s) = 1,
errors

Lag Gc (s)G(s) G(s)

Compensation Y (s) = R(s) + Td (s)
Design via Root
Locus
1 + Gc (s)G(s) 1 + Gc (s)G(s)
Lag compensator
Gc (s)G(s)
example
− N(s)
Prop. vs Lead 1 + Gc (s)G(s)
vs Lag

Concluding
Insights 1 G(s)
E(s) = R(s) − Td (s)
1 + Gc (s)G(s) 1 + Gc (s)G(s)
Gc (s)G(s)
+ N(s)
1 + Gc (s)G(s)
EE 3CL4, §6
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Tim Davidson Response to step disturbance
Compensators

Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Response to step disturbance,
Compensators detail early
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Response to step disturbance,
Compensators detail late
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights

Homework: Show that ess for a step disturbance is 0.2,

0.0225 and 0.025 for prop., lead, lag, resp.
EE 3CL4, §6
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Tim Davidson Error due to Gaussian sensor
Compensators noise
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Bode diagram of
Compensators GC (s)G(s)/(1 + GC (s)G(s))
Lead
compensation
Design via Root
Locus
Lead Compensator
example

Cascade
compensation
and
steady-state
errors

Lag
Compensation
Design via Root
Locus
Lag compensator
example

Prop. vs Lead
vs Lag

Concluding
Insights
EE 3CL4, §6
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Tim Davidson Insights
Compensators • If we would like to improve the transient performance of
Lead
compensation
a closed loop
Design via Root
Locus
• We can try to place the dominant closed-loop poles in
Lead Compensator
example
desired positions
Cascade • One approach to doing that is lead compensator design
compensation • However, that typically requires the use of an amplifier
and
steady-state in the compensator, and hence requires a power supply
errors
• Broadening of bandwidth improves transient
Lag
Compensation performance but exposes loop to noise
Design via Root
Locus
Lag compensator
example
• If we would like to improve the steady-state error
Prop. vs Lead
vs Lag
performance of a closed loop without changing the
Concluding
dominant transient features too much
Insights • We can consider designing a lag compensator to
provide the required gain
• However, that typically produces a “weak” slow pole that
slows the decay to steady state