Maes Final

CHAPTER 1
INTRODUCTION
Internet of Things (IoT) is the next revolution of the internet which brings
profound impact on our everyday lives. IoT is the extension of the Internet to
connect just about everything on the planet. This includes real and physical objects
ranging from household accessories to industrial engineering.
As such these “things” that are connected to the Internet will be able to take actions
or make decisions based on the information they gather from the Internet with or
without human interaction. In addition, they also update the Internet with real-time
information with the help of various sensors.
They communicate through the wireless communication channel which is not
secured and transmit real-time information through the treacherous wireless
medium. In certain applications, confidentiality, authentication, data freshness,
and data integrity might be extremely important. Therefore, encryption of data is
becoming a major concern.
The more popular and widely adopted symmetric encryption algorithm likely to
be encountered nowadays is the Advanced Encryption Standard AES. It is found
at least six times faster than triple DES (data encryption standard). A replacement
for DES was needed as its key size was too small. With increasing computing
power, it was considered vulnerable against exhaustive key search attack.
Triple DES was designed to overcome this drawback but it was found slow. THE
Internet of Things is said to revolutionize the way in which individuals and
organizations interact with the physical world.
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According to, IoT is regarded as an extension of Internet to the real world of
physical objects, usually associated with “cyber physical system”. Everyday smart
objects could become information-security risks, and the IoT could distribute
those risks more widely than the conventional Internet.
However, it is particularly difficult to support security and privacy in the IoT. One
reason of this is due to the large amount of sensitive data in the network
Military, Health Care, Financial, Among Others.
As the multipliers dominate the hardware resource of the IIR filters, a large
number of multipliers required cause large power dissipation and large area.
An important aspect to be considered with the evolution of internet in the current
information age is secrecy and privacy. Cryptography provides confidentiality and
reliability to data during communication. It is used in different application which
includes e-commerce, wireless communications, cellular networks, online
banking, computerized networks etc.
Cryptography is related to the study of secret writing i.e. conversion of plaintext

into cipher-text, so that the information can only be retrieved by the desired entity
over an unsecured channel. The cipher text cannot be transform into intelligible
form (plaintext) unless receiver has a cipher key.
Since a few decades, digital hardware design technology has become more similar
to software design and has evolved tremendously with the introduction of
reconfigurable platforms like FPGA.
However, ASICs do not provide hardware reconfiguration flexibility. Software

provides reprogrammable flexibility for different applications but lacks in
performance and efficiency as compared to ASICs. The reconfigurable platform
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like FPGA fills the gap to achieve a balance between hardware and software in
terms of performance and flexibility.
1.1 PROPOSED SYSTEM:
According to previous research observation, we have found out that S-Box

and Mix Columns are the most energy consuming stages in encryption and
decryption process.
We have analyzed the S-Box generation process of the Rijndael AES. The 16x16
2-dimensional lookup tables are formed through the multiplicative inverse phase
and affine transformation phase in the original AES.
We are proposing a new 1-dimensional lookup table as S-Box. It also follows the
same generation process as the original one. However, substitution of one
complete byte requires two times substitution from the SBox.
First four bits of the state byte is replaced first then the remaining four bits are
substituted from the S-Box.
1.2 MODIFICATION:
Thus during the encryption and decryption process, to secure the data around 6
rounds are performed earlier, now thus proposing around 10 rounds to get the
secure information during encryption and also in decryption using aes algorithm.
1.3 ADVANTAGES:
 We propose 1-dimensional Substitution Box (S-Box) which is constructed
by formulating a novel equation for constructing a square matrix in affine
transformation phase of MAES.
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 We implement both original AES and MAES algorithms using Verilog and
implement in FPGA Spartan-6.
 After analyzing the result of our experiment we conclude that MAES is well
efficient than AES around in terms of area, number of packet transmission
and latency, respectively.
1.4 APPLICATIONS:
 In certain applications, confidentiality, authentication, data freshness, and
data integrity might be extremely important.
 It is used in Internet of Things (IoT), which is the next revolution of the
internet which brings profound impact on our everyday lives.
 It is used in Cryptography.
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CHAPTER 2
LITERATURE SURVEY
Beaulieu, Ray, et al (2003) [2] explains that to offer security on constrained

devices, where simplicity of design is crucial. However, the intended use cases are
diverse and demand flexibility in implementation. Simplicity, security, and
flexibility are ever-present yet conflicting goals in cryptographic design. This
paper outlines how these goals were balanced in the design of Simon and Speck.
Borghoff, Julia, et al (2006) [3] interprets that block cipher that optimized with
respect to latency when implemented in hardware. Such ciphers are desirable for
many future pervasive applications with real-time security needs. Our cipher,
named PRINCE, allows encryption of data within one clock cycle with a very
competitive chip area compared to known solutions. The fully unrolled fashion in
which such algorithms need to be implemented calls for innovative design choices.
The number of rounds must be moderate and rounds must have short delays in
hardware. At the same time, the traditional need that a cipher has to be iterative
with very similar round functions disappears, an observation that increases the
design space for the algorithm. An important further requirement is that realizing
decryption and encryption results in minimum additional costs. PRINCE is
designed in such a way that the overhead for decryption on top of encryption is
negligible. More precisely for our cipher it holds that decryption for one key
corresponds to encryption with a related key. This property we refer to as α-
reflection is of independent interest and we prove its soundness against generic
attacks.
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Bogdanov, Andrey et al, (2006)[4] stated that the establishment of the AES the
need for new block ciphers has been greatly diminished; for almost all block
cipher applications the AES is an excellent and preferred choice. However,
despite recent implementation advances, the AES is not suitable for extremely
constrained environments such as RFID tags and sensor networks. In this paper
we describe an ultra-lightweight block cipher. Both security and hardware
efficiency have been equally important during the design of the cipher and at
1570 GE, the hardware requirements are competitive with today’s leading
compact stream ciphers.
Daemen, Joan and Rijmen, Vincent (2007)[5] stated that AES is expected to
gradually replace the present Data Encryption Standard (DES) as the most widely
applied data encryption technology.| The designers of the block cipher presents
Rijndael from scratch. The underlying mathematics and the wide trail strategy as
the basic design idea are explained in detail and the basics of differential and linear
cryptanalysis are reworked. Subsequent chapters review all known attacks against
the Rijndael structure and deal with implementation and optimization issues.
Suzaki Tomoyasu(2012)[8] illustrated that linear layer is a core component in any

substitution permutation network block cipher. Its design significantly influences
both the security and the efficiency of the resulting block cipher. Surprisingly, not
many general constructions are known that allow to choose trade-offs between
security and efficiency. Especially, when compared to Sboxes, it seems that the
linear layer is crucially understudied. In this paper, we propose a general
methodology to construct good, sometimes optimal, linear layers allowing for a
large variety of trade-offs. We give several instances of our construction and on
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top underline its value by presenting a new bloc cipher. PRIDE is optimized for
8-bit micro-controllers and significantly outperforms all academic solutions both
in terms of code size and cycle count
Shibutani, Kyoji, Takanori Isobe, Harunaga Hiwatari, Atsushi Mitsuda, Toru

(2012) [10] described that by adopting several novel design and implementation
techniques, Piccolo achieves both high security and notably compact
implementation in hardware. We show that Piccolo offers a sufficient security
level against known analyses including recent related-key differential attacks and
meet-in-the-middle attacks. In our smallest implementation, the hardware
requirements for the 80 and the 128-bit key mode are only 683 and 758 gate
equivalents, respectively. Moreover, Piccol requires only 60 additional gate
equivalents to support the decryption function.
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CHAPTER 3
MODULE EXPLANATION
3.1 ALGORITHM AND MODULES:
Figure.3.1 Algorithm and Module
The most representative realizations of this cipher are

 Encryption Process
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1. Add Round Key
2. S-Box Layer (substitution box)
3. P-Layer (Shift rows)
 Decryption Process
The process of decryption of an AES cipher text is similar to the encryption
process in the reverse order shown in Figure 3.1.
1. Add round key
2. Shift rows
3. Byte substitution
Figure 3.2 Encryption Process

• Here, we restrict to description of a typical round of AES encryption as
shown in Figure 3.2. Each round comprise of four sub-processes. The first
round process is depicted below
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3.2 ENCRYPTION PROCESS:
1. Add-round key
• The 8 bytes of the matrix are now considered as 64 bits and are XORed to
the 64 bits of the round key as shown 3.3.
• If this is the last round then the output is the ciphertext.Otherwise,in
Figure 3.3 Add Round Key

64 bit as 8 bytes and we begin another similar round.
• 2. S-Box Layer (substitution box)
• The 16 input bytes are substituted by looking up a fixed table (S-box) given
in design. The result is in a matrix of four rows and four columns.
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Figure 3.4 S-box Layer Substitution Box
• Is a basic component of symmetric key algorithms which performs
substitution as shown in Figure 3.4. In block ciphers, they are typically used
to obscure the relationship between the key and the cipher
text — Shannon's property of confusion.
• In general, an S-box takes some number of input bits, m, and transforms
them into some number of output bits, n, where n is not necessarily equal
to m. An m × n S-box can be implemented as a lookup table with 2m words
of n bits each as shown in Figure 3.5.
• Fixed tables are normally used, as in the Data Encryption Standard (DES),
but in some ciphers the tables are generated dynamically from the key (e.g.
the Blowfish and the two fish encryption algorithms).
• One good example of a fixed table is the S-box from DES (S5), mapping 6-
bit input into a 4-bit output:
Figure 3.5 Look-Up Table for S-Box

3. S-Layer (Shift rows)
• 1st row is unchanged row is unchanged
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• 2nd row does 1 byte circular shift to left row does 1 byte circular shift to
left
• 3rd row does 2 byte circular shift to left 3rd row does 2 byte circular shift
to left
• 4th row does 3 byte circular shift to left as shown in Figure 3.6
Figure 3.6 Shift Rows
3.3 DECRYPTION PROCESS:

• The process of decryption of an AES cipher text is similar to the encryption
process in the reverse order.
• Each round consists of the four processes conducted in the reverse order
• Add round key
• Mix columns
• Shift rows
• Byte substitution
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• Since sub-processes in each round are in reverse manner, unlike for a Feistel
Cipher, the encryption and decryption algorithms need to be separately
implemented, although they are very closely related.
3.4 APPLICATIONS:
 Digital signal processing

Digital signal processing (DSP) is the mathematical manipulation of
information signal to modify or improve it in some way. It is characterized by
the representation of discrete time, discrete frequency, or other discrete domain
signals by a sequence of numbers or symbols and the processing of these
signals. Digital signal processing and analog signal processing are subfields of
signal processing.
DSP includes subfields like: audio and speech signal processing, Sonar and
radar signal processing, sensor array processing, spectral estimation, statistical
signal Processing, digital image processing, signal processing for
communications, control of systems, Biomedical signal processing, seismic
data processing, etc.
The goal of DSP is usually to measure, filter, and/or compress continuous

real-world analog signals. Digital signal processor (DSP) is a specialized
microprocessor with an architecture optimized for the fast operational needs of
digital signal processing.
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 Mobile phone:
A mobile phone is a device that can make and receive telephone calls
over a radio link whilst moving around a wide geographic area. It does so
by connecting to a cellular network provided by a mobile phone operator,
allowing access to the public telephone network. In these mobile phones
they want to reduce the area as well as the power. So our adder design is
used to mobile phones.
 Satellite application:
Satellites are used for a large number of purposes. Common types
include military and Civilian Earth observation satellites, communications
satellites, navigation satellites weather satellites, and research satellites.
Space stations and human spacecraft in orbit are also satellites.
Satellite orbits vary greatly, depending on the purpose of the satellite, and
are classified in number of ways. Well-known (overlapping) classes include
low Earth orbit, polar orbit, and geostationary orbit.
Satellites are usually semi-independent computer-controlled systems.
Satellite subsystems attend many tasks, such as power generation, thermal
control, telemetry, attitude control, and orbit control. In this control unit,
our adder will be used for some area efficient products.
3.5 MODIFIED ADVANCED ENCRYPTION STANDARD:
 According to previous research observation, we have found out that S-Box

and Mix Columns are the most energy consuming stages in encryption and
decryption process. We have analyzed the S-Box generation process of the
Rijndael AES.
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 The 16x16 2-dimensional lookup table is formed through the multiplicative
inverse phase and affine transformation phase in the original AES. We are
proposing a new 1-dimensional lookup table as S-Box. It also follows the
same generation process as the original one.
 Substitution of one complete byte requires two times substitution from the
S-Box. First four bits of the state byte is replaced first then the remaining
four bits are substituted from the S-Box.
3.5.1 Rijndael S-Box Generation Method:

The Rijndael S-Box is a square matrix which is used in the Rijndael cipher. The
S- Box serves as a lookup table. It is generated by determining the
multiplicative inverse for a given number in GF (28) and then transforming the
multiplicative inverse using affine transformation as shown in Figure 3.7.
3.5.1.1 Multiplicative Inverse Phase:

In multiplicative inverse phase, the input byte is inversed by substituting value
from multiplicative inverse table.
3.5.1.2 Affine Transformation:

Selection of the irreducible polynomial and the designated byte are the two
most important factors of affine transformation phase. In Rijndael AES, x8 + x4
+ x3 + x + 1 is used as the irreducible polynomial and as the constant column
matrix 0x63 specially designated byte is chosen. Basically, the affine
transformation consists of two operations. Firstly, 8x8 square matrix’s
multiplication and secondly, 8x1 constant column matrix addition. The 8x8
square matrix is constructed using the following.
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Figure 3.7 Original S-Box Generation Process Figure 3.8 Proposed MAES
S-box Generation Process
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3.5.2 Modified AES S-Box Generation:
Our modified AES S-Box generation process follows the construction

procedure of the original AES. The whole process differs only in the selection of
the irreducible polynomial and specially designated byte as shown in Figure 3.8.
3.5.2.1 Multiplicative Inverse Table: In the Rijndael AES, all the
arithmetic operations are performed over the Galois Field. In our work, the Galois
Field (24) is considered. The number of irreducible polynomials of degree 4 over
GF (2) are x4 + x + 1, x4 + x3 + x2 + x + 1 and x4 + x3 + 1.
All the generated values of the multiplicative inverse table and substitution box
depend on the selection of irreducible polynomial. For our experiment purpose,
we choose x4+x+1 as our irreducible polynomial but we can select any of the
irreducible polynomials which are mentioned above. Following the Extended
Euclidean Algorithm, 1-dimensional multiplicative inverse table is formed. Figure
7 illustrates the multiplicative inverse table of the proposed algorithm.
3.5.2.2 Affine Transformation: This affine transformation process also
follows two phases. Firstly, 4x4 square matrix’s multiplication and secondly, 4x1
constant column matrix addition. The 4x4 square matrix is constructed following
the equation 1 and equation 2 refers to the value of di :Ci = ITH bit of a specially
designated byte which is hexadecimal of 3; 8; 10; 13; 15 as they don0t generate
any fixed points: Selection of the constant value is a little bit precarious. As we
are calculating over the GF (24) where the value of the constant column matrix
ranges from 0x00 to 0x0F, we can only select 5 values from there as these values
do not generate any fixed point after transformation. The fixed point refers to the
generation of the output value same as the input value. Figure 8 shows the
generation process of proposed MAES.
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CHAPTER 4
REQUIREMENTS
4.1 SOFTWARE REQUIREMENTS
4.1.1 XILINX ISE 13.2/14.5
INTRODUCTION:
For two-and-a-half decades, Xilinx has been at the forefront of the

programmable logic revolution, with the invention and continued migration of
FPGA platform technology. During that time, the role of the FPGA has evolved
from a vehicle for prototyping and glue-logic to a highly flexible alternative to
ASICs and ASSPs for a host of applications and markets. Today, Xilinx® FPGAs
have become strategically essential to world-class system companies that are
hoping to survive and compete in these times of extreme global economic
instability, turning what was once the programmable revolution into the
“programmable imperative” for both Xilinx and our customers.
4.1.2 Programmable Imperative:
When viewed from the customer's perspective, the programmable

imperative is the necessity to do more with less, to remove risk wherever possible,
and to differentiate in order to survive. In essence, it is the quest to simultaneously
satisfy the conflicting demands created by ever-evolving product requirements
(i.e., cost, power, performance, and density) and mounting business challenges
(i.e., shrinking market windows, fickle market demands, capped engineering
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budgets, escalating ASIC and ASSP non-recurring engineering costs, spiralling
complexity, and increased risk). To Xilinx, the programmable imperative
represents a two-fold commitment. The first is to continue developing
programmable silicon innovations at every process node that deliver industry-
leading value for every key figure of merit against which FPGAs are measured:
price, power, performance, density, features, and programmability. The second
commitment is to provide customers with simpler, smarter, and more strategically
viable design platforms for the creation of world-class FPGA-based solutions in a
wide variety of industries—what Xilinx calls targeted design platforms.
Base Platform:
The base platform is both the delivery vehicle for all new silicon offerings from
Xilinx and the foundation upon which all Xilinx targeted design platforms are
built. As such, it is the most fundamental platform used to develop and run
customer-specific software applications and hardware designs as production
system solutions. Released at launch, the base platform comprises a robust set of
well-integrated, tested, and targeted elements that enable customers to
immediately start a design. These elements include:
• FPGA silicon
• ISE® Design Suite design environment
• Third-party synthesis, simulation, and signal integrity tools
• Reference designs common to many applications, such as memory interface and

configuration designs.
• Development boards that run the reference designs
• A host of widely used IP, such as GigE, Ethernet, memory controllers, and PCIe.
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4.1.3 XILINX ISE Design Tools:
Xilinx ISE is the design tool provided by Xilinx. Xilinx would be virtually
identical for our purposes.
There are four fundamental steps in all digital logic design. These consist of:
1. Design – The schematic or code that describes the circuit.
2. Synthesis – The intermediate conversion of human readable circuit

description to FPGA code (EDIF) format. It involves syntax checking
and combining of all these design files into a single file.
3. Place Route– Where the layout of the circuit is finalized. This is the
translation of the EDIF into logic gates on the FPGA.
4. Program – The FPGA is updated to reflect the design through the
use
programming (.bit) files.
Test bench simulation is in the second step. As its name implies, it is used for
testing the design by simulating the result of driving the inputs and observing the
outputs to verify your design.
ISE has the capability to do a variety of different design methodologies
including: Schematic Capture, Finite State Machine and Hardware Descriptive
Language(VHDL or Verilog).
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4.2 VERILOG –LANGUAGE:
Hardware description languages such as Verilog are similar

to software programming languages because they include ways of describing the
propagation time and signal strengths (sensitivity). There are two types
of assignment operators; a blocking assignment (=), and a non-blocking (<=)
assignment. The non-blocking assignment allows designers to describe a state-
machine update without needing to declare and use temporary storage variables.
Since these concepts are part of Verilog's language semantics, designers

could quickly write descriptions of large circuits in a relatively compact and
concise form. At the time of Verilog's introduction (1984), Verilog represented a
tremendous productivity improvement for circuit designers who were already
using graphical schematic capture software and specially written software
programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C

programming language, which was already widely used in engineering software
development. Like C, Verilog is case-sensitive and has a
basic preprocessor (though less sophisticated than that of ANSI C/C++).
Its control flow keywords (if/else, for, while, case, etc.) are equivalent, and
its operator precedence is compatible with C.
Syntactic differences include: required bit-widths for variable declarations,

demarcation of procedural blocks (Verilog uses begin/end instead of curly braces
{}), and many other minor differences. Verilog requires that variables be given a
definite size. In C these sizes are assumed from the 'type' of the variable (for
instance an integer type may be 8 bits).
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A Verilog design consists of a hierarchy of modules. Modules
encapsulate design hierarchy, and communicate with other modules through a set
of declared input, output, and bidirectional ports.
Internally, a module can contain any combination of the following:

net/variable declarations (wire, reg, integer, etc.), concurrent and
sequential statement blocks, and instances of other modules (sub-hierarchies).
Sequential statements are placed inside a begin/end block and executed in
sequential order within the block. However, the blocks themselves are executed
concurrently, making Verilog a dataflow language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0,

floating, undefined") and signal strengths (strong, weak, etc.). This system allows
abstract modeling of shared signal lines, where multiple sources drive a common
net. When a wire has multiple drivers, the wire's (readable) value is resolved by a
function of the source drivers and their strengths.
A subset of statements in the Verilog language is synthesizable. Verilog

modules that conform to a synthesizable coding style, known as RTL (register-
transfer level), can be physically realized by synthesis software. Synthesis
software algorithmically transforms the (abstract)
Verilog source into a netlist, a logically equivalent description consisting

only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are
available in a specific FPGA or VLSI technology. Further manipulations to the
net list ultimately lead to a circuit fabrication blueprint (such as a photo mask
set for an ASIC or a bit stream file for an FPGA).
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4.3 HARDWARE REQUIREMENT
GENERAL
An integrated circuit or monolithic integrated circuit (also referred to as IC,

chip, or microchip) is an electronic circuit manufactured by the patterned diffusion
of trace elements into the surface of a thin substrate of semiconductor material.
Additional materials are deposited and patterned to form interconnections between
semiconductor devices. Integrated circuits are used in virtually all electronic
equipment today and have revolutionized the world of electronics. Computers,
mobile phones, and other digital appliances are now inextricable parts of the
structure of modern societies, made possible by the low cost of production of
integrated circuits. ICs were made possible by experimental discoveries showing
that semiconductor devices could perform the functions of vacuum tubes and by
mid-20th-century technology advancements in semiconductor device fabrication.
4.3.1 INTRODUCTION TO ASICS AND PROGRAMMABLE LOGIC:
The last 15 years have witnessed the demise in the number of cell-based
ASIC designs as a means for developing customized SoCs. Rising NREs,
development times and risk have mostly restricted the use of cell-based ASICs to
the highest volume applications; applications that can withstand the multi-million
dollar development costs associated with 1-2 design re-spins. Analysts estimate
that the number of cell based ASIC design starts per year is now only between
2000-3000 compared to ~10,000 in the late 1990s. The FPGA has emerged as a
technology that fills some of the gap left by cell-based ASICs. Yet even after 20+
years of existence and 40X more design starts per year than cell-based ASICs, the
size of the FPGA market in dollar terms remains only a fraction that of cell-based
ASICs.
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This suggests that there are many FPGA designs that never make it into
production and that for the most part, the FPGA is still seen by many as a vehicle
for prototyping or college education and has perhaps even succeeded in actually
stifling industry innovation. This paper introduces a new technology, the second
generation Structured ASIC that is tipped to reenergize the path to innovation
within the electronics industry. It brings together some of the key advantages of
FPGA technology (i.e. fast turnaround, no mask charges, no minimum order
quantity) and of cell-based ASIC (i.e. low unit cost and power) to deliver a new
platform for SoC design. This document defines requirements for development of
Application Specific Integrated Circuits (ASICs). It is intended to be used as an
appendix to a Statement of Work. The document complements the ESA ASIC
Design and Assurance Requirements (AD1), which is a precursor to a future ESA
PSS document on ASIC design.
Structured ASICs:
A new alternative has recently emerged to address the market void between
FPGAs and cell-based ASICs. Analysts term this as the Structured ASIC.
First Generation Structured ASICs:
Like the FPGA market, the Structured ASIC market had a flurry of early
entrants many of who have departed the market. Examples include respectable
semiconductor companies like NEC, LSI logic and EDA vendors such as
Simplicity.
First Generation Structured ASICs provided designers with considerable power

and cost improvements over FPGAs but failed to remove many barriers to entry
that existed with traditional cell-based ASICs. First generation Structured ASICs
had the following characteristics:
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 Turn-around times were still 2-5 months from tape-out to silicon
 NREs were still in the range of $150-$250K or more making the technology
difficult to access for mainstream users.
 Minimum order quantities were required as wafers could not be shared
amongst projects or customers
 Development costs and time were also very high and long respectively, as
designers were expected to undergo rigorous verification down to the
transistor level
 Designers transitioning from prototyping devices like FPGAs to first
generation Structured ASICs were still expected to redesign the product into
a completely new device, revisit timing closure and re-qualify the new
device before it production ready.
While some companies still offer first generation Structured ASICs today,
market acceptance has been severely limited as a result of these barriers to entry.
However, these first generation Structured ASICs paved the way for a new
generation that would combine the benefits of both FPGAs and cell-based ASICs.
Second Generation Structured ASICs:

A new generation of Structured ASICs has emerged on the market and is
gaining traction. This generation utilizes a single via mask for configuring the
device. In doing so, it removes the need for the massive amounts of SRAM
configuration elements and metal interconnect that plagues today’s FPGAs. The
benefits to designers are delivered through a device that provides up to 20X lower
device power consumption and up to 80% lower unit cost than FPGAs, depending
on device density, (larger FPGAs have more configuration elements and metal
interconnect).
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This new generation of Structured ASICs, available from ASICs
Corporation, and named Extreme also removes the barriers of traditional cell
based ASICs and also first generation Structured ASICs. With Extremes
Structured ASICs advantages include:
 Turn-around times from tape-out to silicon is only 3-4 weeks

 There are zero mask charges as multiple projects can be shared on a wafer
 There is no minimum order quantity
 Development tools costs are low (analogous to FPGA type tools)
 Development time is short as designers need not perform verification
down to the transistor level or perform exhaustive test coverage
 Coarse FPGA-like architecture based on calls which provides
manufacturing yield advantages.
There are device options for both prototyping and mass production.
Designers transitioning from prototyping N extreme Structured ASICs to mass
production N extreme Structured ASICs need not revisit timing closure or re-
qualify the production device.
4.3.2 FIELD-PROGRAMMABLE GATE ARRAY (FPGA):

Prompted by the development of new types of sophisticated field-
programmable devices (FPDs) shown in Figure 4.1, the process of designing
digital hardware has changed dramatically over the past few years. Unlike
previous generations of technology, in which board-level designs included large
numbers of SSI chips containing basic gates, virtually every digital design
produced today consists mostly of high-density devices. This applies not only to
custom devices like processors and memory, but also for logic circuits such as
state machine controllers, counters, registers, and decoders. When such circuits
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are destined for high-volume systems they have been integrated into high-density
gate arrays. However, gate array NRE costs often are too expensive and gate arrays
take too long to manufacture to be viable for prototyping or other low-volume
scenarios. For these reasons, most prototypes, and also many production designs
are now built using FPDs. The most compelling advantages of FPDs are instant
manufacturing turnaround, low start-up costs, low financial risk and (since
programming is done by the end user) ease of design changes. The market for
FPDs has grown dramatically over the past decade to the point where there is now
a wide assortment of devices to choose from.
Figure.4.1 FPGA Board

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Definitions of Relevant Terminology
The most important terminology used below.
Field-Programmable Device (FPD) :
A general term that refers to any type of integrated circuit used for
implementing digital hardware, where the chip can be configured by the end user
to realize different designs. Programming of such a device often involves placing
the chip into a special programming unit, but some chips can also be configured
“in-system”. Another name for FPDs is programmable logic devices (PLDs);
although PLDs encompass the same types of chips as FPDs, we prefer the term
FPD because historically the word PLD has referred to relatively simple types of
devices.
Programmable Logic Array (PLA):
A Programmable Logic Array (PLA) is a relatively small FPD that contains

two levels of logic, an AND-plane and an OR-plane, where both levels are
programmable (note: although PLA structures are sometimes embedded into full-
custom chips, we refer here only to those PLAs that are provided as separate
integrated circuits and are user-programmable).
Programmable Array Logic (PAL):
A Programmable Array Logic (PAL) is a relatively small FPD that has a

programmable AND-plane followed by a fixed OR-plane.
Simple PLD:
Refers to any type of Simple PLD, usually either a PLA or PAL.
28
Complex PLD:
A more Complex PLD that consists of an arrangement of multiple SPLD-

like blocks on a single chip. Alternative names (that will not be used in this paper)
sometimes adopted for this style of chip are Enhanced PLD (EPLD), Super PAL,
Mega PAL, and others.
Field-Programmable Gate Array (FPGA):
A Field-Programmable Gate Array is an FPD featuring a general structure

that allows very high logic capacity. Whereas CPLDs feature logic resources with
a wide number of inputs (AND planes), FPGAs offer more narrow logic resources.
FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.
High-Capacity PLDs (HCPLD):
High-capacity PLDs: a single acronym that refers to both CPLDs and

FPGAs. This term has been coined in trade literature for providing an easy way to
refer to both types of devices. PAL is a trademark of Advanced Micro Devices.
 Interconnect - the wiring resources in an FPD.

 Programmable Switch- a user-programmable switch that can connect a
logic element to an interconnect wire, or one interconnect wire to another
 Logic Block- a relatively small circuit block that is replicated in an array in
an FPD. When a circuit is implemented in an FPD, it is first decomposed
into smaller sub-circuits that can each be mapped into a logic block. The
term logic block is mostly used in the context of FPGAs, but it could also
refer to a block of circuitry in a CPLD.
29
 Logic Capacity- the amount of digital logic that can be mapped into a single
FPD. This is usually measured in units of “equivalent number of gates in a
traditional gate array”. In other words, the capacity of an FPD is measured
by the size of gate array that it is comparable to. In simpler terms, logic
capacity can be thought of as “number of 2-input NAND gates”.
 Logic Density - the amount of logic per unit area in an FPD.
 Speed-Performance- measures the maximum operable speed of a circuit
when implemented in an FPD. For combinational circuits, it is set by the
longest delay through any path, and for sequential circuits it is the maximum
clock frequency for which the circuit functions properly. In the remainder
of this section, to provide insight into FPD development the evolution of
FPDs over the past two decades is described. Additional background
information is also included on the semiconductor technologies used in the
manufacture of FPDs.
Evolution of Programmable Logic Devices:
 The first type of user-programmable chip that could implement logic

circuits was the Programmable Read-Only Memory (PROM), in which
address lines can be used as logic circuit inputs and data lines as outputs.
 Logic functions, however, rarely require more than a few product terms, and
a PROM contains a full decoder for its address inputs. PROMS are thus an
inefficient architecture for realizing logic circuits, and so are rarely used in
practice for that purpose.
 The first device developed later specifically for implementing logic circuits
was the Field-Programmable Logic Array (FPLA), or simply PLA for short.
 A PLA consists of two levels of logic gates: a programmable “wired” AND-
plane followed by a programmable “wired” OR-plane. A PLA is structured
30
so that any of its inputs (or their complements) can be AND’ed together in
the AND-plane; each AND-plane output can thus correspond to any product
term of the inputs. Similarly, each OR plane output can be configured to
produce the logical sum of any of the AND-plane outputs.
 Both disadvantages were due to the two levels of configurable logic,
because programmable logic planes were difficult to manufacture and
introduced significant propagation delays. To overcome these weaknesses,
Programmable Array Logic (PAL) devices were developed. PALs feature
only a single level of programmability, consisting of a programmable
“wired” AND plane that feeds fixed OR-gates.
 To compensate for lack of generality incurred because the OR- Outputs
plane is fixed, several variants of PALs are produced, with different
numbers of inputs and outputs, and various sizes of OR-gates. PALs usually
contain flip-flops connected to the OR-gate outputs so that sequential
circuits can be realized.
 PAL devices are important because when introduced they had a profound
effect on digital hardware design, and also they are the basis for some of the
newer, more sophisticated architectures that will be described shortly.
 Variants of the basic PAL architecture are featured in several other products
known by different acronyms. All small PLDs, including PLAs, PALs, and
PAL-like devices are grouped into a single category called Simple PLDs
(SPLDs), who’s most important characteristics are low cost and very high
pin-to-pin speed-performance.
 As technology has advanced, it has become possible to produce devices
with higher capacity than SPLDs..
31
CHAPTER 5
RESULTS AND CONCLUSION
5.1 IMPLEMENTATION OF ENCRYPTION PROCESS (AES)

a= input; ak= key; output= cipher text;
Figure 5.1 Implementation for S-box (AES)
32
RTL VIEW
Figure 5.2 RTL View
DESIGN SUMMARY (AREA) & TIMING REPORT
Table 5.1 Implementation of Encryption Process (AES)

33
\
34
5.2 IMPLEMENTATION OF ENCRYPTION PROCESS(MAES)
Figure 5.3 Implementation for S-box (MAES)
35
RTL SCHEMATIC:
Figure 5.4 RTL Schematic
Table 5.2 Implementation of Encryption Process (MAES)
36
37
5.3 IMPLEMENTATION OF BOTH ENCRYPTION AND
DECRYPTION PROCESS (AES)
Figure 5.5 Implementation of Both Encryption and Decryption S-box (AES)

38
RTL VIEW AND RTL SCHEMATIC:
Figure 5.6 RTL View and Schematic
39
Table 5.3 Implementation of both Encryption and Decryption S-box (MAES)
40
5.4 IMPLEMENTATION OF BOTH ENCRYPTION AND DECRYPTION
PROCESS (MAES):
Figure 5.7 Implementation of Both Encryption and Decryption S-box (MAES)
41
RTL VIEW AND RTL SCHEMATIC:
Figure 5.8 RTL view and Schematic

42
Table 5.4 Implementation of both encryption and decryption S-box (Maes)
43
44
DESCRIPTION AREA TIMING
ANALYSIS ANALYSIS
BOTH 191LUT’s 13.817 ns

ENCRYPTION AND
DECRYPTION AES
BOTH 175LUT’s 10.635 ns

ENCRYPTION AND
DECRYPTION
MAES
Table 5.5 Comparsion for Area and Timing Analysis
5.5 CONCLUSION:
In this project, we present a modified version of AES for Resource-Constraint

Environments. A new Substitution Box is proposed which works over the Galois
Field by constructing a unique affine transformation equation. One notable feature
of MAES is extending the battery life of low powered devices by consuming less
amount of energy. And reduces the total area.
This method shows efficiency when encrypted packets are transmitted using the
proposed MAES to the sink node and the number of transmitted packets has
increased. In future, the security issue and space complexity will be considered to
make the proposed modification more applicable.
Also, we plan to investigate multipath routing scheme while transmitting the

encrypted data to the sink node. We will further delve to integrate Public Key
45
Cryptosystem, especially Elliptic-curve cryptography (ECC) to achieve
comparable efficiency in terms of number of packet transmission and latency with
better security.
46
APPENDIX
1. AES PROGRAM:
`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:04:54 03/05/2019
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module both_aes(a,ak,ciphertext,decryption);
//////////////////////////////////////////////
input [127:0]a; // plaintext
input [127:0]ak; //key
output [127:0]ciphertext, decryption ;//cipher text
wire [127:0]
round0,round1,round2,round3,round4,round5,round6,round7,round8,
47
round9,round10,round11,round12,round13,round14;
// addroundkey(round 1)
wire [127:0] z,
z1,z2,z4,z5,z6,z8,z9,z10,z12,z14,z15,z17,z18,z19,z23,z24,z25,z27,z28,z29,z30,z3
2,z33,z34,z35,
z36,z40,z41,z42,z43,z44,z45,z46,z47,z48,z49,z50,z51,z52,z53,z54,z55,z56,z57,z5
8,z59,z60,z61,z62,z63,z64,z65,z66;
addroundkey k1 (.a(a),.b(ak),.y(z));
subbyte k2 (.a(z),.c(z1));
shiftrows k3(.a(z1),.y(z2));
mix_columns k4 (.a(z2),.y(round0));
//
addroundkey k5 (.a(round0),.b(ak),.y(z4));
subbyte k6 (.a(z4),.c(z5));
//
//

//

48
//

//
//

//

mix_columns k36 (.a(z36),.y(ciphertext));
//////////////////////////////////////////////////////////////////////////////DECR
YPTION
inversemix_columns h26(.a(ciphertext),.y(z40));
inverse_shift_rows h36 (.a(z40),.y(z41));
inverse_subbyte h46 (.a(z41),.c(z42));
inverse_addroundkey h16 (.a(z42),.b(ak),.y(round8));
//////////////////////
49
inversemix_columns h25(.a(round8),.y(z43));
////////////////////
////////////////
////////////////////////////
///////////////////////////////
wire [127:0] decrypt;

assign decryption = a;
///
50
///////////////
inverse_addroundkey h108 (.a(z63),.b(ak),.y(decrypt));
endmodule
2.MAES PROGRAM:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:33:08 03/06/2019
// Design Name:
// Module Name: bothmaes
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bothmaes(a,ak,ciphertext,decryption);
51
//////////////////////////////////////////////
input [127:0]a; // plaintext
input [127:0]ak; //key
output [127:0]ciphertext, decryption ;//cipher text
wire [127:0]
round0,round1,round2,round3,round4,round5,round6,round7,round8,
round9,round10,round11,round12,round13,round14;
// addroundkey(round 1)
wire [127:0] z,
z1,z2,z4,z5,z6,z8,z9,z10,z12,z14,z15,z17,z18,z19,z23,z24,z25,z27,z28,z29,z30,z3
2,z33,z34,z35,
z41,z42,z43,z44,z45,z46,z47,z48,z49,z50,z51,z52,z53,z54,z55,z56,z57,z58,z59,z6
0,z61,z62,z63;
addroundkey k1 (.a(a),.b(ak),.y(z));
subbyte_maes k2 (.a(z),.c(z1));
//
subbyte_maes k6 (.a(z4),.c(z5));
//
52
//

//

//

//
//

//

53
shiftrows k35(.a(z35),.y(ciphertext));
/////////////////////////////////////////////////////////////////////////////
inverse_shift_rows h36 (.a(ciphertext),.y(z41));

inverse_subbyte_maes h46 (.a(z41),.c(z42));
//////////////////////
////////////////////
////////////////
////////////////////////////
wire [127:0] decrypt;
assign decryption = a;
///////////////////////////////
54
///
///////////////
inverse_addroundkey h108 (.a(z63),.b(ak),.y(decrypt));
endmodule
55
REFERENCES
[1] Banik,Subhadeep,Andrey Bogdanov, and Francesco Regazzoni. “Exploring
energy efficiency of lightweight block ciphers.” Inter.Conf.contr. on Selected
Areas in Cryptography. Springer, Cham (2003).
[2] Beaulieu, Ray, et al. “The SIMON and SPECK lightweight block ciphers.”
Design Automation Conference (DAC), 52nd ACM/EDAC/IEEE. IEEE (2003).
[3] Borghoff, Julia, et al. “low-latency block cipher for pervasive computing
applications.” International Conference on the Theory and Application of
Cryptology and Information Security. Springer, Berlin, Heidelberg (2006).
[4] Bogdanov, Andrey, et al. “PRESENT: An ultra-lightweight block cipher.”

CHES.Vol. 4727 (2006).
[5] Daemen, Joan and Rijmen, Vincent. “The design of Rijndael: AES-the
advanced encryption standard.”, Springer Science & Business Media (2007).
[6] Eisenbarth, Thomas, and Sandeep Kumar.“A survey of lightweight

cryptography implementations.” IEEE Design & Test of Computers Vol 24.6
(2007).
56
[7] Madakam, Somayya, R. Ramaswamy, and Siddharth Tripathi. “Internet of
Things (IoT): A literature review.” Journal of Computer and Communications 3,
no. 05 (2015): p.164 (2010).
[8] Li, Wei, et al. “Security analysis of the LED lightweight cipher in the internet
of things.” Jisuanji Xuebao(Chinese Journal of Computers) 35.3: p.434-445
(2011).
[9] Suzaki, Tomoyasu (2012). “TWINE: A Lightweight Block Cipher for Multiple
Platforms.” Selected Areas in Cryptography. Vol. 7707 pp.227-248.
[10] Shibutani, Kyoji, Takanori Isobe, Harunaga Hiwatari, Atsushi Mitsuda, Toru
Akishita, and Taizo Shirai. “Piccolo: An ultra-lightweight blockcipher.” In CHES,
vol. 6917, pp. 342-357 (2012).
[11] Veeramallu, B., S. Sahitya, and Ch LavanyaSusanna. Veeramallu, B., S.

Sahitya, and Ch Lavanya Susanna January. “Confidentiality in Wireless sensor
Networks.” International Journal of Soft Computing and Engineering (IJSCE,
Volume-2, Issue-6 ) ISSN: 2231-2307 (2013).
[12] Wang, Yong, Garhan Attebury, and Byrav Ramamurthy). “A survey of

security issues in wireless sensor networks.” IEEE Communications Surveys
Tutorial pp.234-265 (2015).
[13] Wu, Wenling, and Lei Zhang “LBlock: a lightweight block cipher.” In
Applied Cryptography and Network Security. Springer Berlin/Heidelberg, pp.
327-344 (2015).
57
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CHAPTER 1

Cryptography is related to the study of secret writing i.e. conversion of plaintext

However, ASICs do not provide hardware reconfiguration flexibility. Software

1.1 PROPOSED SYSTEM:

According to previous research observation, we have found out that S-Box

Beaulieu, Ray, et al (2003) [2] explains that to offer security on constrained

Suzaki Tomoyasu(2012)[8] illustrated that linear layer is a core component in any

Shibutani, Kyoji, Takanori Isobe, Harunaga Hiwatari, Atsushi Mitsuda, Toru

3.1 ALGORITHM AND MODULES:

Figure.3.1 Algorithm and Module

The most representative realizations of this cipher are

Figure 3.2 Encryption Process

Figure 3.3 Add Round Key

Figure 3.5 Look-Up Table for S-Box

Figure 3.6 Shift Rows

3.3 DECRYPTION PROCESS:

 Digital signal processing

The goal of DSP is usually to measure, filter, and/or compress continuous

3.5 MODIFIED ADVANCED ENCRYPTION STANDARD:

 According to previous research observation, we have found out that S-Box

3.5.1 Rijndael S-Box Generation Method:

3.5.1.1 Multiplicative Inverse Phase:

3.5.1.2 Affine Transformation:

Our modified AES S-Box generation process follows the construction

4.1 SOFTWARE REQUIREMENTS

4.1.1 XILINX ISE 13.2/14.5

For two-and-a-half decades, Xilinx has been at the forefront of the

4.1.2 Programmable Imperative:

When viewed from the customer's perspective, the programmable

• ISE® Design Suite design environment

• Third-party synthesis, simulation, and signal integrity tools

• Reference designs common to many applications, such as memory interface and

• Development boards that run the reference designs

2. Synthesis – The intermediate conversion of human readable circuit

Hardware description languages such as Verilog are similar

Since these concepts are part of Verilog's language semantics, designers

The designers of Verilog wanted a language with syntax similar to the C

Syntactic differences include: required bit-widths for variable declarations,

Internally, a module can contain any combination of the following:

Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0,

A subset of statements in the Verilog language is synthesizable. Verilog

Verilog source into a netlist, a logically equivalent description consisting

An integrated circuit or monolithic integrated circuit (also referred to as IC,

4.3.1 INTRODUCTION TO ASICS AND PROGRAMMABLE LOGIC:

First Generation Structured ASICs:

First Generation Structured ASICs provided designers with considerable power

Second Generation Structured ASICs:

 Turn-around times from tape-out to silicon is only 3-4 weeks

4.3.2 FIELD-PROGRAMMABLE GATE ARRAY (FPGA):

Figure.4.1 FPGA Board

The most important terminology used below.

Field-Programmable Device (FPD) :

Programmable Logic Array (PLA):

A Programmable Logic Array (PLA) is a relatively small FPD that contains

Programmable Array Logic (PAL):

A Programmable Array Logic (PAL) is a relatively small FPD that has a

Refers to any type of Simple PLD, usually either a PLA or PAL.

A more Complex PLD that consists of an arrangement of multiple SPLD-

Field-Programmable Gate Array (FPGA):

A Field-Programmable Gate Array is an FPD featuring a general structure

High-Capacity PLDs (HCPLD):

High-capacity PLDs: a single acronym that refers to both CPLDs and

 Interconnect - the wiring resources in an FPD.