Computer Architecture

Assignment 2

Q1. Suppose that we are considering an enhancement to the processor of a server system used
I/O. The new CPU is 15 times faster on computation in the Web serving application that the
original processor. Assuming that the original CPU is busy with computation 75% of the time and
is waiting for I/O 25% of the time, what is the overall speedup gained by incorporating the
enhancement?
Q2. A certain application runs in 10 seconds on a computer M1, which is taking 400X106 cycles. I
want to build a machine M2 that will run the same application in 6 seconds. I have determined I
need a double clock rate as compared to machine M1. How many clock cycles machine M2 will
take to execute the application?
Q3. A C++ program runs in 15 seconds on computer A, which has a 300 Mhz. clock. We are
trying to help a computer designer build a new machine B that will run this program in 4 seconds.
The designer can use new (or perhaps more expensive) technology to substantially increase the
clock rate, but has informed us that this increase will affect the rest of the CPU design, causing
machine B to require 1.6 times as many clock cycles as machine A for the same program. What
clock rate should we tell the designer to target?
Q4. A compiler designer is trying to decide between two code sequences for a particular machine.
Based on the hardware implementation, there are three different classes of instructions: Class A,
Class B, Class C, and Class D, and they require two, four, one, and three cycles (respectively).
The first code sequence has 12 instructions: 4 of A, 2 of B, 2 of C and 4 of D. The second
sequence has 14 instructions: 3 of A, 3 of B, 6 of C and 2 of D. Which sequence will be faster?
How much? What is the CPI for each sequence?
Q5. A machine is running an application in 100 seconds, which spends 70% of time processing
and 30% of the time doing disk operations. Now you have two options to increase the
performance, either buy a new processor that is 50% faster that will cost 10,000 or upgrade the
disk for 7,000 that will increase performance by 25%. Which would you choose to yield best
performance for least amount of money and why?
Q6. Two enhancements with the following speedups are proposed for a new architecture:
Speedup1 = 3 Speedup2 = 2; the two enhancements are non-overlapping i.e., only one
enhancement is usable at any point in time. If enhancement 1 is usable for 30% of the time, and
enhancement 2 is usable for 40% of the time. What is the overall speedup gained by incorporating
both enhancements?
Q7. A certain application runs in 10 seconds on a computer M1, which is taking 400X106 cycles. I
want to build a machine M2 that will run the same application in 6 seconds. I have determined I
need a double clock rate as compared to machine M1. How many clock cycles machine M2 will
take to execute the application?
Q8. Processor X has a clock speed of 1 GHz, and takes 1 cycle for integer operations, 2 cycles for
memory operations, and 4 cycles for floating point operations. Empirical data shows that programs
run on Processor X typically are composed of 35% floating point operations, 30% memory
operations, and 35% integer operations. You are designing Processor Y, an improvement on
Processor X which will run the same programs and you have 2 options to improve the
performance:
1. Increase the clock speed to 1.2 GHz, but memory operations take 3 cycles
2. Decrease the clock speed to 900 MHz, but floating point operations only take 3 cycles
Compute the speedup for both options and decide the option Processor Y should take.
Q9. A common transformation required in graphics processors is square root. Implementations of
floating-point (FP) square root vary significantly in performance, especially among processors
designed for graphics. Suppose FP square root (FPSQR) is responsible for 20% of the execution
time of a critical graphics benchmark. One proposal is to enhance the FPSQR hardware and
speed up this operation by a factor of 10. The other alternative is just to try to make all FP
instructions in the graphics processor run faster by a factor of 1.6; FP instructions are responsible
for half of the execution time for the application. The design team believes that they can make all
FP instructions run 1.6 times faster with the same effort as required for the fast square root.
Compare these two design alternatives.
Q10. Fill the columns:
A-C Trip C-B Trip Total Time C-B Speedup Overall Speedup
20 50
20 20
20 4
20 1.7
20 0.3