T40 E41 M46 G NPB Ver.c PDF

5 4 3 2 1
http://shop61976717.taobao.com
Topstar Digital technologies Co.,LTD
D D
Board name: MotherBoard Schematic 02. System block & Index

Project name: M42G 03. PWR Block & Description
Version: VerB 04. Notes & Annotations
Initial Date: MAY.9, 2008 05. Schematic Modify and History
54. CLOCK Distribution
C
55. Power Distribution C
56. Power on & off Sequence

57. ACPI Mode Switch Timings
58. Power On Sequence & Reset Map
Topstar Confidential
B
Hardware drawing by: Hardware check by: EMI Check by: B
Power drawing by: Power check by:
Manager Sign by:
TOPSTAR TECHNOLOGY
A bent A
Page Name Title
Size Project Name Rev
B M46G
B
Date: Thursday, August 27, 2009 Sheet 1 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
Topstar Confidential
D
ShenZhen Topstar Industry Co.,LTD D
CONTENT
01 Title
M46G SYSTEM BLOCK Ver:B 02 System Block & Index
03 PWR Block & Description
04 Notes and Annotations
05 Schematic Modify and History
06 CK505M(CY28516&ICS9LPR365)
07 PENRYN CPU(Host BUS)(1of 2)
CPU Penryn CK505M
08 PENRYN CPU(PWR&GND)(2 of 2)
Thermal Clocking 09 CANTIGA (HOST)(1 of 6)
478 uFCPGA 10 CANTIGA (Graphic)(2 of 6)
Sensor CY28548
ASC7525 11 CANTIGA (DDRII)(3 of 6)
+VCC_CORE,+VCCP /ICS9LPRS365
Backlight +V3.3S +VCCA1.5
12 CANTIGA (DMI&CLK)(4 of 6)
Connector +V3.3S,+V1.25S 13 CANTIGA (VSS&NCTF)(5 of 6)
+VDC 14 CANTIGA (Power)(6 of 6)
15 DDR2 SODIMM0
FSB 16 DDR2 SODIMM1
667MHz/800MHz/1066MHz 17 DDR2 Series Termination
18 DDR2 Decoupling
TFT 19 LVDS&INVERTER CONN
+V3.3S DDR2 SODIMM0
DDR2 667/800 667/800 20 VGA&SVIDEO&DC-IN
21 HDMI
C
LVDS CANTIGA GM +V0.9S,+V1.8,+V3.3S
22 ICH9_M(1 of 3) C
PCI-Express X16 1329 FCBGA DDR2 SODIMM1 23 ICH9_M(2 of 3)

VGA R/G/B DDR2 667/800 667/800 24 ICH9_M(3 of 3)
TMDS +V3.3S,+V1.5S, +V0.9S,+V1.8,+V3.3S 25 SATA CONN(ODD&DVD)
+V5S
+VGFX_1_05S,
+V1.05S,+V1.8
26 Card Reader(UB6232 USB)
RTL8102E 27 EXPRESS CARD
HDMI +V3.3AL 28 PCIE MINI SLOT1
PCIE 1X
RJ45 29 PCIE MINI SLOT2
30 LAN/POWER Connector
Control DMI 31 ALC662 AZALIA CODEC
Link 0 x2/x4 32 MDC & BT & FAN & OTP
33 USB2.0 & TPM & Gsensor & LED Conn
SATA ODD
PCIE mini Card PCIE mini Card for 3G +V5S
34 KBC(W83L951ADG)
BIOS 35 ADAPTER IN
8Mbit
SPI ICH9-M 36 BATTERY IN
676 PBGA S-ATA
+V3.3AL 37 +V3.3AL +V5AL
+V1.05S,+V3.3S 2.5" HDD SD/MMC/MS CARD 38 +V1.8/+V0.9S DDR
PCIE 1X
+V3.3AL,+V5AL Card Reader
+V1.5S,+V5S +V5S,+V3.3S
ENE UB6232 39 +V1.5S/+V1.05S CHIPSET
+V3.3A_RTC USB1.1/2.0 40 +V1.5AL
USB1.1/2.0 +V3.3S,+V3.3AL
41 Power Good Logic/OVP
42 +VCC_CORE
USB PORT2 BLUE USB PORT1 43 SYSTEM/DISCHARGE
+V5AL TOOTH(V1.2) Camera +V5AL LPC 44 CHARGER
1.3M/2.0M AZALIA 45 THROUGH HOLE/EMI
BTM-203/CCOM
B MODULE B
NEW CARD(Type II) +V3.3AL +V3.3S 46 ACPI mode switch timings
47 Clock Distribution
48 Power ON/OFF & Reset seq
KB Controller/EC 49 Power On/off Sequence
W83L951ADG/DG 50 Power Distribution
USB PORT3 +V3.3AL,+V3.3S,+V5AL
+V5AL
TCM L
R
MiC
AZALIA
LED/TouchPAD/Button/ ALC662
Q-key/LID +V5S,+V3.3S
DAUGHTER BOARD DAUGHTER BOARD
KB Matrix
A A
TOPSTAR TECHNOLOGY
bent
Page Name System Block
C M46G
B
5 4 3 2 1
5 4 3 2 1
M46G POWER BLOCK Ver:B
注意:
Platform
虚线表示电源电压信号。 Logic
VR_ON
D
Charge Battery D
ISL6251 44A VR_TT#

Page 55 +VCC_CORE VIN
Vcc_core
V_5 IMVP-6 VID[6...0]
PSI#
V_3
DPRSTP#
VCC_CORE
Adapter Power +VDC ISL6262A
CLK_ENABLE#
65W Switch 5A Page 48,49
IMVP6_PWRGD
DPRSLPVR
Vcc_sense
Vss_sense
Page 38
DPRSTP# PSI# PROCHOT#
Always_On ICH-M CPU_PWRGD CPU-M

DDR Power
Power
C
TPS51116 C
Chipset PWR ISL62382 Page 42

Page 41 +V5S
TPS51124
+V3.3S
Page 43
+V3.3AL +V1.8
+V0.9S CLK
+V5AL +V1.5AL 4A/2.5A
+V1.5S 3A/5A CHIP
+V1.05S System Power
4A/12A
+V_S
Page 46
+V1.8GDDR
4A
B B
BATT+ +V5AL +V3.3AL +V1.8 +V1.5S +V1.05S +VCC_CORE
OVP Circuit
Page 43,52
A A
TOPSTAR TECHNOLOGY
bent
Page Name PWR Block & description
OVP OVP OVP OVP OVP OVP OVP Size Project Name Rev
A3 M46G
16.5V 5.6V 3.6V 2.0V 2.0V 2.0V 2.0V B
5 4 3 2 1
5 4 3 2 1
Voltage Rails
+VDC Primary DC system power supply(9V-19V) I2C SMB Address
+VCC_CORE Core voltage for processor Device Address Hex Bus Master
1.5V for CPU PLL Clock Generator 1101 001x D2 SMB_ICH_S ICH9M
D +V1.5S
SO-DIMM0
D
1010 000x A0 SMB_ICH_S ICH9M
+V1.05S 1.05V for FSB VTT SO-DIMM1 1010 010x A4 SMB_ICH_S ICH9M
+V0.9S 0.9V DDR2 Termination voltage NEW CARD Variable Variable SMB_ICH_S ICH9M
Variable
+V1.8 1.8V power rail for DDR2 PCIE Mini CARD Variable SMB_ICH_S ICH9M
+V3.3AL 3.3V always on power rail KB3926

Smart Battery 0001 011x 16 I2C
+V3.3S 3.3V main power rail CPU Thermal 1001 100x 98 I2C KB3926
Sensor(ASC7525)
+V5AL 5V for USB Device
+V5S 5V main power rail
+V1.5AL 1.5AL for HDMI
C Board stack up description C
PCB Layers
TOP
GND
IN1
IN2 Trace Impedence:55ohm +/-15%(Default) Power States/AC mode

VCC Signal SLP_S3# SLP_S4# SLP_S5# +V*AL +V* +V*S Clock
IN3 S0(Full On) HIGH HIGH HIGH ON ON ON ON
GND S3(STM) LOW HIGH HIGH ON ON OFF OFF
Bottom S4(STD) LOW LOW HIGH ON OFF OFF OFF

B B
S5(SoftOff) LOW LOW LOW ON OFF OFF OFF
USB Table
USB Port# Function Description
0 Express Card Wake up Events

1 RESERVED
2 USB Port(on Main Board) LID switch from EC

Power switch from EC
3 Mini PCIE Card(WLAN & ROBSON)
4 Mini PCIE Card(WLAN & ROBSON)
5 Bluetooth ns: Component marked "ns" is not stuff

6 USB Port(on I/O Board)
A TOPSTAR TECHNOLOGY A
bent
7 USB CAMERA(On VGA Board) This is a lead free project,all component must be LF Page Name
NOTE
8 CARD Reader Size
A3
Project Name
M46G
Rev
B
9 USB Port(on I/O Board) Date: Thursday, August 27, 2009 Sheet 4 of 51
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Schematic modify Item and history:

2007-10-26 Ver A initial release
Cost Down list
2009-07-28 Ver B
1. 3.3AL/5AL电换phath,改用62382的电源芯片--PG 36
D 2.EC ROM封装colay。改上64K的EC ROM--PG 33 D
3.LIDR信号到EC 的电阻上上去。--PG33
4.RGB ESD管子上上去。--PG20
5.LVDS由双单通道改为双通道。并更换LCDCON。--PG20
6.增加TCM功能--PG31
7.CLK的驱动电阻由33ohm改为0ohm--PG6
8.HDMI做成CH7318与PS8101COLAY--PG21
9.更改PCB Mark 电阻--PG33
10.TP_CON1的footprint改为CNS6_1_R1--PG32
11.五个LED均更改成M12上所用，与S46P一致---PG50
12.3G开关第一版接法有误，更改；3G_LED的作用是反映硬件开关，故不由PCIE插槽引出，改由3G开关引出--PG28
13.调整TPA6017A2的增益倍数为10dB,与M12一致--PG30
14.南桥32.768K采用插件晶振--PG22
15.TP_CON1采用下接触，故将其连接关系反转--PG32
16.SATA_CON1更改footprint为SATA_S_50G--PG25
C 17.R645改为976OHM使VGA信号的上升时间与幅值满足规范--PG10 C
18.R211改为20ohm以改善眼图效果，同时预留一个并联电阻以备调节--PG23
19.C503更改为更低的电容以满足机构要求--PG13
20.去掉CR的12MHZ的晶振预留方案，以满足机构限高的要求--PG29
21.删除E2,H14,H19改为TH_197_88类型孔
22.改用AO4468的2S SI4800,在第一版用AO4468时上电不正常--PG42
23.CR改用+V3.3AL电，预留+V5AL--PG29
24.3.3AL，5AL，+V1.8预留RC
25.更改H4的footprint
26.将网卡TVS管改到靠近RJ45--PG51
27.LCDCON仍然改回第一版所用物料--PG20
28.BT_CON更改为X01所用--PG31
29.pc237与PC238colay，ns PC237
B
2009-08-27 Ver C release B
1.HDMI Level shifter CH7318的第四pin由PU改为PD--PG21

2.WIFI改变symbol,改变螺柱定位孔的形状--PG27
3.3G卡槽增加一个定位螺柱PCIE_NUT3,预留，增加3G卡的接地效果--PG28
4.3G开关的信号只连到EC，并改由EC控制3G灯的状态--PG28,PG50,PG33
5.蓝牙增加预留线路，以满足不同的蓝牙模组信号和时序要求--PG31
6.改变3G与WIFI 指示灯的亮度，R881-->330 ohm,R719-->220 ohm--PG50
7.改变PCB Mark电阻--PG33
8.SIM卡改用X01所用的物料--PG28
9.LVDS connector 换成40PIN立式的，屏线也与S46P一致
A A
TOPSTAR TECHNOLOGY
bent
Page Name Sch Modify and history
Custom M46G
B
Date: Tuesday, September 01, 2009 Sheet 5 of 51
5 4 3 2 1
5 4 3 2 1
+V3.3S
+V3.3S
+V1.05S
{7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
{7,8,9,12,13,14,22,24,31,38,40,41,42,44}
FB271 2 FB0805 +V3.3S_CK_VDD

+V3.3S
100ohm@100MHz,3A C348 C349
100ohm@100MHz,3A
C0805
10UF/6.3V,X5R C346
FB26 C350 0.1UF/25V,Y5V
1
D FB0805 C351 C347 C0805 +V3.3S_CK_VDD D

4.7UF/10V,Y5V 0.047uF/16V,Y5V
+V3.3S_CK_VDD U4
0.1UF/25V,Y5V 0.1UF/25V,Y5V
2
2 VDD_PCI
+VDDIO_CLK 9 48
C344 C341 +VDDIO_CLK VDD_48 IO_VOUT
16 VDD_PLL3
C343 C335 +V3.3S_CK_VDD 61 63
VDD_REF SMB_DATA SMB_DATA_S {15,16,23,26,27,28}
C0805 10UF/6.3V,X5R 0.1UF/25V,Y5V C115 0.047uF/16V,Y5V 64
SMB_CLK SMB_CLK_S {15,16,23,26,27,28}
C0805 39
ns +V3.3S_CK_VDD VDD_SRC
55 VDD_CPU
10UF/6.3V,X5R 0.1UF/25V,Y5V 38
SRC5/PCI_STOP# PM_STPPCI# {23}
C336 C337 +VDDIO_CLK +VDDIO_CLK 12 37
VDD_IO SRC5#/CPU_STOP# PM_STPCPU# {23}
+VDDIO_CLK 20
10UF/6.3V,X5R 0.1UF/25V,Y5V +VDDIO_CLK VDD_PLL3_IO CPU0 RN11 1
26 VDD_SRC_IO_1 CPU0 54 2 0 CLK_CPU_BCLK {7}
C0805 ns 36 53 CPU#0 3 4 RA0402_4
VDD_SRC_IO_2 CPU0# CLK_CPU_BCLK# {7}
45 VDD_SRC_IO_3
+VDDIO_CLK 49 51 CPU1 RN9 1 2 0
VDD_CPU_IO CPU1 CLK_MCH_BCLK {9}
50 CPU#1 3 4 RA0402_4
CPU1# CLK_MCH_BCLK# {9}
C338 C333 C339 C340 +VDDIO_CLK SATA_CLKREQ#R180475,1% 1
{23} SATA_CLKREQ# PCI0/OE#_0/2_A
SRC8/CPU2_ITP 47
10UF/6.3V,X5R R884 22 TCM 3 46
{31} CLK_TCMPCI PCI1/OE#_1/4_ASRC8#/CPU2#_ITP
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V
0.1UF/25V,Y5V TME 4 34 RN5 3 4 0 MiniCard CLK_PCIE_MINICARD {27}
PCI2/TME SRC10
SRC10# 35 1 2 RA0402_4 CLK_PCIE_MINICARD# {27}
R173 22 5
{33} CLK_591PCI PCI3/FSD
C345 C342 +VDDIO_CLK 33 EXP_CLKREQ R147 475,1%R0402 ns
SRC11/OE#_10 EXPCARD_CLKREQ# {26}
R412 22 27M_SEL 6 32 MPCIE_CLKREQ R137 475,1%R0402
{28} CLK_debugPCI PCI4/SRC5_SEL SRC11#/OE#_9 PCIE_CLKREQ# {12}
10UF/6.3V,X5R 0.1UF/25V,Y5V 不支持NEW CARD request
C C0805 ns R171 22 PCIF_ITP_EN 7 30 RN2 3 4 0 C
C122 {23} CLK_ICHPCI PCIF5/ITP_EN SRC9 CLK_MCH_3GPLL {12}
SRC9# 31 1 2 RA0402_4 CLK_MCH_3GPLL# {12}
XTAL_IN 60 XTAL_IN RN6
1 SRC7/OE#_8 44 1 2 0 3G
CLK_PCIE_3G {28}
27pF/50V,NPO Y3 XTAL_OUT 59 43 3 4
XTAL_OUT SRC7#/OE#_6 CLK_PCIE_3G# {28}
{29} CLK_CR_48M R761 22 RA0402_4
XS2 41 RN3 1 2 0
C121 SRC6 CLK_PCIE_GLAN {51}
R164 22 10 40 3 4
{23} CLK_USB48 USB_48/FSA SRC6# CLK_PCIE_GLAN# {51}
14.318180MHz RA0402_4
2
CLK_BSEL0 R166 2.2K 27 RN4 3 4 0

SRC4 CLK_PCIE_EXPCARD {26}
+V3.3S 27pF/50V,NPO CLK_BSEL1 57 28 1 2 RA0402_4
FSB/TEST_MODE SRC4# CLK_PCIE_EXPCARD# {26}
R172 33 62
{23} CLK_ICH14 REF0/FSC/TEST_SEL
24 RN8 3 4
SRC3/OE#_0/2_B CLK_PCIE_ICH {23}
CLK_BSEL2 R176 10K 25 1 2 0
SRC3#/OE#_1/4_B CLK_PCIE_ICH# {23}
R411 RA0402_4
8 21 RN7 3 4 0
VSS_PCI SRC2/SATA CLK_ICH_SATA {22}
10K 11 22 1 2 RA0402_4
VSS_48 SRC2#/SATA# CLK_ICH_SATA# {22}
R168 15
ns VSS_IO RN26 3
19 VSS_PLL3 SRC1/SE1 17 4 0 DREFSSCLK {12}
10K 52 18 1 2 RA0402_4
VSS_CPU SRC1#/SE2 DREFSSCLK# {12}
27M_SEL 23 VSS_SRC_1 RN10 3
29 VSS_SRC_2 SRC0/DOT96 13 4 0 DREFCLK {12}
58 VSS_REF SRC0#/DOT96# 14 1 2 DREFCLK# {12}
R410 42 RA0402_4
VSS_SRC3
CK_PWRGD/PWRDWN# 56 CLK_PWRGD {23}
10K
CY28548
VerB:change the drive resistors from 33 ohm to 0ohm
TSSOP64_0D5_6D1
B C736 B
0.1UF/25V,Y5V
CLK_ICH14 C118 10PF/50V,NPO ns

+V1.05S
缝合电容 +V3.3S
CLK_USB48 C112 18pF/50V,NPO
C0402
R408
56 SATA_CLKREQ# R181 10K
ns
CLK_BSEL0 R165 1K EXP_CLKREQ R143 10K CLK_debugPCI C353 10PF/50V,NPO ns
MCH_BSEL0 {12}
CLK_BSEL0 {7}
MPCIE_CLKREQ R138 10K CLK_591PCI C119 10PF/50V,NPO ns
R409 +V1.05S CLK_ICHPCI C117 10PF/50V,NPO ns

1K +V3.3S
ns
C113
+V1.05S 0.1UF/25V,Y5V TME R177 10K
+V1.05S
A
R179 A
R170 1K TOPSTAR TECHNOLOG
1K ns
bent
ns
CLK_BSEL1 R167 1K CLK_BSEL2 R178 1K Page Name CK505M
MCH_BSEL1 {12} MCH_BSEL2 {12}
CLK_BSEL1 {7} CLK_BSEL2 {7} Size Project Name Rev
A3 M46G B
R169 R175
1K 1K Date: Thursday, August 27, 2009 Sheet 6 of 51
ns ns PROPERTY NOTE: this document contains information confidential and property to
5 4 3 2 1
5 4 3 2 1
+V3.3S {6,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
http://shop61976717.taobao.com +V1.05S {6,8,9,12,13,14,22,24,31,38,40,41,42,44}
U10A ICTP ns
{9} H_A#[35:3] T10 +V1.05S {9} H_D#[63:0]
H_A#3 J4 H1 U10B
A[3]# ADS# H_ADS# {9} H_D#[63:0] {9}
ADDR GROUP 0
H_A#4 L5 E2 H_D#0 E22 Y22 H_D#32
A[4]# BNR# H_BNR# {9} D[0]# D[32]#
H_A#5 L4 G5 H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# {9} D[1]# D[33]#
H_A#6 K5 R65 H_D#2 E26 V24 H_D#34
H_A#7 A[6]# 56 H_D#3 D[2]# D[34]# H_D#35
D
M3 A[7]# DEFER# H5 H_DEFER# {9} G22 D[3]# D[35]# V26 D
DATA GRP 0
H_A#8 N2 F21 R0402 H_D#4 F23 V23 H_D#36
A[8]# DRDY# H_DRDY# {9} Place testpoint on D[4]# D[36]#
H_A#9 J1 E1 H_D#5 G25 T22 H_D#37
A[9]# DBSY# H_DBSY# {9} H_IERR# with a GND D[5]# D[37]#
H_A#10 N3 H_D#6 E25 U25 H_D#38
H_A#11 A[10]# 0.1" away H_D#7 D[6]# D[38]# H_D#39
P5 A[11]# BR0# F1 H_BREQ#0 {9} E23 D[7]# D[39]# U23
H_A#12 P2 H_D#8 K24 Y25 H_D#40 H_DSTBN#/H_DSTBP# should route
A[12]# D[8]# D[40]#
DATA GRP 2
as differential pair
CONTROL
H_A#13 L2 D20 H_IERR# H_D#9 G24 W22 H_D#41
H_A#14 A[13]# IERR# H_D#10 D[9]# D[41]# H_D#42
P4 A[14]# INIT# B3 H_INIT# {22} J24 D[10]# D[42]# Y23
H_A#15 P1 H_D#11 J23 W24 H_D#43
H_A#16 A[15]# H_D#12 D[11]# D[43]# H_D#44
R1 A[16]# LOCK# H4 H_LOCK# {9} H22 D[12]# D[44]# W25
M1 H_D#13 F26 AA23 H_D#45
{9} H_ADSTB#0 ADSTB[0]# T17ICTP ns D[13]# D[45]#
C1 H_D#14 K22 AA24 H_D#46
{9} H_REQ#[4:0] RESET# H_CPURST# {9} D[14]# D[46]#
H_REQ#0 K3 F3 H_RS#0 H_D#15 H23 AB25 H_D#47
REQ[0]# RS[0]# H_RS#0 {9} D[15]# D[47]#
H_REQ#1 H2 F4 H_RS#1 J26 Y26
REQ[1]# RS[1]# H_RS#1 {9} {9} H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 {9}
H_REQ#2 K2 G3 H_RS#2 H26 AA26
REQ[2]# RS[2]# H_RS#2 {9} {9} H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 {9}
H_REQ#3 J3 G2 H25 U22
REQ[3]# TRDY# H_TRDY# {9} {9} H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 {9}
H_REQ#4 L1 REQ[4]#
{9} H_A#[35:3] HIT# G6 H_HIT# {9} {9} H_D#[63:0] H_D#[63:0] {9}
H_A#17 Y2 E4 H_D#16 N22 AE24 H_D#48
A[17]# HITM# H_HITM# {9} +V3.3S D[16]# D[48]#
H_A#18 U5 H_D#17 K25 AD24 H_D#49
H_A#19 A[18]# H_BPM#0 ICTP ns H_D#18 D[17]# D[49]# H_D#50
R3 A[19]# BPM[0]# AD4 T1 P26 D[18]# D[50]# AA21
ADDR GROUP 1
H_A#20 W6 AD3 H_BPM#1 ICTP ns H_D#19 R23 AB22 H_D#51

A[20]# BPM[1]# T4 D[19]# D[51]#
H_A#21 U4 AD1 H_BPM#2 ICTP ns H_DBR# R61 1K ns H_D#20 L23 AB21 H_D#52
A[21]# BPM[2]# T3 D[20]# D[52]#
DATA GRP 1
H_A#22 H_BPM#3 ICTP ns H_D#21 H_D#53
XDP/ITP SIGNALS
Y5 A[22]# BPM[3]# AC4 T2 M24 D[21]# D[53]# AC26

H_A#23 U1 AC2 H_PRDY# T7 ICTP ns H_D#22 L22 AD20 H_D#54
H_A#24 A[23]# PRDY# H_FREQ# +V1.05S H_D#23 D[22]# D[54]# H_D#55
R4 A[24]# PREQ# AC1 M23 D[23]# D[55]# AE22
H_A#25 T5 AC5 H_TCK H_D#24 P25 AF23 H_D#56
H_A#26 A[25]# TCK H_TDI H_D#25 D[24]# D[56]# H_D#57 Layout note:
T3 A[26]# TDI AA6 P23 D[25]# D[57]# AC25
H_A#27 W2 AB3 H_TDO T6 ICTP ns H_TMS R16 54.9,1% R0402 H_D#26 P22 AE21 H_D#58 Comp0,2 connec with Zo=27.4ohm,make
DATA GRP 3
A[27]# TDO D[26]# D[58]#
H_A#28 W5 AB5 H_TMS H_FREQ# R15 54.9,1% R0402 H_D#27 T24 AD21 H_D#59 trace length shorter than 0.5"
H_A#29 A[28]# TMS H_TRST# H_TDI H_D#28 D[27]# D[59]# H_D#60
Y4 A[29]# TRST# AB6 R21 54.9,1% R0402 R24 D[28]# D[60]# AC22 Comp1,3 connec with Zo=55ohm,make
H_A#30 U2 C20 H_DBR# +V1.05S H_D#29 L25 AD23 H_D#61 trace length shorter than 0.5"
H_A#31 A[30]# DBR# H_TCK R19 54.9,1% R0402 H_D#30 D[29]# D[61]# H_D#62
V4 A[31]# T25 D[30]# D[62]# AF22
H_A#32 W3 H_TRST# R20 54.9,1% R0402 H_D#31 N25 AC23 H_D#63
H_A#33 A[32]# D[31]# D[63]#
AA4 THERMAL L26 AE25
H_A#34 AB2
A[33]# Layout Note: Z=55ohm,{9} H_DSTBN#1
M26
DSTBN[1]# DSTBN[3]#
AF24
H_DSTBN#3 {9}
H_A#35 AA3
A[34]#
D21 VR_PROCHOT# R341 0.5" max for GTLREF {9} H_DSTBP#1
N24
DSTBP[1]# DSTBP[3]#
AC20
H_DSTBP#3 {9}
A[35]# PROCHOT# {9} H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 {9}
V1 A24 H_THERMDA 1K,1%
{9} H_ADSTB#1 ADSTB[1]# THERMDA R0402 +V1.05S
C B25 H_THERMDC AD26 R26 COMP_CPU0 R343 27.4,1% R0402 C
THERMDC GTLREF COMP[0] COMP_CPU1 R342 54.9,1% R0402
{22} H_A20M# A6 A20M# C23 TEST1 MISC COMP[1] U26
ICH
A5 C7 D25 AA1 COMP_CPU2 R17 27.4,1% R0402

{22} H_FERR# FERR# THERMTRIP# PM_THRMTRIP# {12,22,31} TEST2 COMP[2]
C4 PM_THRMTRIP# should R340 ns ICTP T14 CPU_TEST3 C24 Y1 COMP_CPU3 R18 54.9,1% R0402
{22} H_IGNNE# IGNNE# TEST3 COMP[3] Remove H_PWRGD
ns ICTP T20 connect to ICH9 and 2K,1% CPU_TEST4 AF26 R38
R0402 TEST4 PU Resistor.
{22} H_STPCLK#
R60 D5 GMCH without ns ICTP T5 CPU_TEST5 AF1 E5 H_DPRSTP# {12,22,41}
200,1%
STPCLK# CPU_TEST6 TEST5 DPRSTP#
{22} H_INTR
0 C6 LINT0 H CLK T-ing(No stub) ns ICTP T80 A26 TEST6 DPSLP# B5 H_DPSLP# {22} T12
ICTP ns R0402
B4 A22 ns ICTP T18 CPU_TEST7 C3 D24 ns
{22} H_NMI LINT1 BCLK[0] CLK_CPU_BCLK {6} TEST7 DPWR# H_DPWR# {9}
{22} H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# {6} {6} CLK_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGD {22}
B23 D7 H_CPUSLP# {9}
ns ICTP T9 TP_CPU_RSVD01 M4 R52 R49 C248{6} CLK_BSEL1
C21
BSEL[1] SLP#
AE6
RSVD[01] {6} CLK_BSEL2 BSEL[2] PSI# PM_PSI# {41}
ns ICTP TP2 TP_CPU_RSVD02 N5
ns ICTP TP1 TP_CPU_RSVD03 RSVD[02] 1K 1K C0402 Place C30 close to Penryn
T2 RSVD[03]
ns ICTP T8 TP_CPU_RSVD04 V3 CLK_CPU_BCLK R0402 R0402 0.1UF/10V,X7R the CPU_TEST4 pin.
ns ICTP T19 TP_CPU_RSVD05 RSVD[04] ns ns ns Make sure CPU_TEST4
B2 B1
RESERVED
ns ICTP T13 TP_CPU_RSVD06 RSVD[05] NC R589 routing is reference

D2 RSVD[06]
ns ICTP T16 TP_CPU_RSVD07 D22 100,1% to GND and away from
ns ICTP T15 TP_CPU_RSVD08 RSVD[07] other noisy signals.
D3 RSVD[08] R0402
ns ICTP T11 TP_CPU_RSVD09 F6 CLK_CPU_BCLK#
RSVD[09]
change ns to
install Hads length:<0.5 inch
2008-5-10
Penryn width>7mil,Space>10mil
B B
+V3.3S
NOTE
VDD_1 R347 1.H_THERMDA/C线宽10 MILS,并配对走线,
220 然后再包地处理.
会用到新的支持BJT
BI-DIRECTIONAL C279 R0402
MODEL的TS 0.1UF/25V,Y5V
2.H_THERMDA/C走线远离19V及VGA或高速线走线
C0402
PROCESSOR HOT H_THERMDA
EC SMBUS ADD:1001 100X

I2C_CLK
I2C_DATA
I2C_CLK {33}
C281 I2C_DATA {33}
OVT_SHUTDOWN#
2200PF/25V,X7R OVT_SHUTDOWN# {31}
C0402
H_THERMDC
+V3.3S THERM#
delete for DFX

R57 By Johan 071228 C291 C290
10K R350 R371
R0402 10K 10K 27pF/50V,NPO 27pF/50V,NPO
R0402 R0402 C0402 C0402
ns ns
EC_PROCHOT# {33} Change to 75393
A +V1.05S By Johan 071228 A
+V1.05S Q6 +V1.05S
U11
3
Q4 MMBT2222A
R31 1K R0402 1 MMBT2222A 1 R64 R0402 VDD_1 1 8 I2C_CLK
SOT23 1K H_THERMDA VDD SCL I2C_DATA
2 D+ SDA 7
R37 SOT23 H_THERMDC 3 6 OVT_SHUTDOWN# +V3.3S TOPSTAR TECHNOLOGY
2
1K THERM# D- ALERT#
4 THERM# GND 5
R0402 bent
VR_PROCHOT# {41} F75393S Page Name PENRYN(Host Bus)
C M46G
B
Date: Friday, August 28, 2009 Sheet 7 of 51
5 4 3 2 1
5 4 3 2 1
+VCC_CORE {40,41}
+V1.5S
+V1.05S
{14,22,24,26,27,28,30,38,40,42}
{6,7,9,12,13,14,22,24,31,38,40,41,42,44}
Demo:22uF*32 3mOhm 0.6nH U10D

Caps VerB cost down A4 P6
VSS[001] VSS[082]
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
+VCC_CORE A14 R2
VSS[004] VSS[085]
A16 VSS[005] VSS[086] R5
D
A19 VSS[006] VSS[087] R22 D
C269 C270 C267 C268 C266 C258 C265 C43 C42 C257 A23 R25
10uF/6.3V,X5R ns 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R VSS[007] VSS[088]
AF2 VSS[008] VSS[089] T1
C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 B6 T4
ns VSS[009] VSS[090]
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
+VCC_CORE +VCC_CORE +VCC_CORE B21 U24
VSS[015] VSS[096]
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C22 C23 C41 C40 C259 C13 C14 C16 C256 C251 C8 V22
U10C 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R 10uF/6.3V,X5R ns 10uF/6.3V,X5R 10uF/6.3V,X5R ns 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R VSS[018] VSS[099]
C11 VSS[019] VSS[100] V25
A7 AB20 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C14 W1
VCC[001] VCC[068] VSS[020] VSS[101]
A9 VCC[002] VCC[069] AB7 C16 VSS[021] VSS[102] W4
A10 VCC[003] VCC[070] AC7 C19 VSS[022] VSS[103] W23
A12 VCC[004] VCC[071] AC9 C2 VSS[023] VSS[104] W26
A13 VCC[005] VCC[072] AC12 C22 VSS[024] VSS[105] Y3
A15 VCC[006] VCC[073] AC13 C25 VSS[025] VSS[106] Y6
A17 AC15 +VCC_CORE VerB cost down D1 Y21
VCC[007] VCC[074] VSS[026] VSS[107]
A18 VCC[008] VCC[075] AC17 D4 VSS[027] VSS[108] Y24
A20 VCC[009] VCC[076] AC18 D8 VSS[028] VSS[109] AA2
B7 AD7 C24 D11 AA5
VCC[010] VCC[077] C262 C255 C252 C15 C254 C261 C25 C253 C260 VSS[029] VSS[110]
B9 VCC[011] VCC[078] AD9 D13 VSS[030] VSS[111] AA8
B10 AD10 10uF/6.3V,X5R 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns D16 AA11
VCC[012] VCC[079] C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 VSS[031] VSS[112]
B17 VCC[016] VCC[083] AD17 E3 VSS[035] VSS[116] AA22
B18 VCC[017] VCC[084] AD18 E6 VSS[036] VSS[117] AA25
B20 VCC[018] VCC[085] AE9 E8 VSS[037] VSS[118] AB1
C9 VCC[019] VCC[086] AE10 E11 VSS[038] VSS[119] AB4
C C18 VCC[025] VCC[092] AE20 F5 VSS[044] VSS[125] AB23 C
D9 VCC[026] VCC[093] AF9 F8 VSS[045] VSS[126] AB26
D10 VCC[027] VCC[094] AF10 F11 VSS[046] VSS[127] AC3
D17 AF17 +V1.05S F2 AC14
VCC[031] VCC[098] +V1.05S VSS[050] VSS[131]
E7 VCC[033] VCC[100] AF20 F25 VSS[052] VSS[133] AC19
E9 VCC[034] G4 VSS[053] VSS[134] AC21
E10 VCC[035] VCCP[01] G21 C34 C20 C18 C27 C31 C19 G1 VSS[054] VSS[135] AC24
E12 VCC[036] VCCP[02] V6 G23 VSS[055] VSS[136] AD2
E13 J6 C17 C21 C33 +V1.5S 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R G26 AD5
VCC[037] VCCP[03] 10uF/6.3V,X5R C0402 C0402 C0402 C0402 C0402 C0402 VSS[056] VSS[137]
E15 VCC[038] VCCP[04] K6 H3 VSS[057] VSS[138] AD8
E17 M6 10uF/6.3V,X5R 10uF/6.3V,X5R C0805 H6 AD11
VCC[039] VCCP[05] C0805 C0805 VSS[058] VSS[139]
E18 VCC[040] VCCP[06] J21 H21 VSS[059] VSS[140] AD13
E20 VCC[041] VCCP[07] K21 H24 VSS[060] VSS[141] AD16
F7 VCC[042] VCCP[08] M21 J2 VSS[061] VSS[142] AD19
F9 VCC[043] VCCP[09] N21 J5 VSS[062] VSS[143] AD22
F10 N6 +VCCA_PROC R345 0 J22 AD25
VCC[044] VCCP[10] R0603 VSS[063] VSS[144]
F12 VCC[045] VCCP[11] R21 J25 VSS[064] VSS[145] AE1
F14 R6 C272 C274 K1 AE4
VCC[046] VCCP[12] 0.01uF/16V,X7R 10uF/6.3V,X5R VSS[065] VSS[146]
F15 VCC[047] VCCP[13] T21 K4 VSS[066] VSS[147] AE8
F17 T6 C0402 C0805 K23 AE11
VCC[048] VCCP[14] Place near PIN B26 change to bi-sticky mylar VSS[067] VSS[148]
F18 VCC[049] VCCP[15] V21 K26 VSS[068] VSS[149] AE14
F20 W21 By Johan 071224 L3 AE16
VCC[050] VCCP[16] VSS[069] VSS[150]
AA7 VCC[051] L6 VSS[070] VSS[151] AE19
AA9 B26 BRACKET BRACKET1_Mylar L21 AE23
VCC[052] VCCA[01] VSS[071] VSS[152]
AA10 VCC[053] VCCA[02] C26 L24 VSS[072] VSS[153] AE26
AA12 VCC[054] M2 VSS[073] VSS[154] A2
AA13 AD6 +VCC_CORE M5 AF6
VCC[055] VID[0] H_VID0 {41} VSS[074] VSS[155]
AA15 VCC[056] VID[1] AF5 H_VID1 {41} M22 VSS[075] VSS[156] AF8
AA17 VCC[057] VID[2] AE5 H_VID2 {41} M25 VSS[076] VSS[157] AF11
AA18 VCC[058] VID[3] AF4 H_VID3 {41} N1 VSS[077] VSS[158] AF13
AA20 AE3 R338 N4 AF16
AB9 AF3 100,1% N23 AF19
AC10 AE2 R0402 N26 AF21
B
AB10 VCC[062] P3 VSS[081] VSS[162] A25 B
AB12 VCC[063] VSS[163] AF25
AB14 VCC[064] VCCSENSE AF7 VCCSENSE {41}
AB15 Penryn
VCC[065]
AB17 VCC[066]
AB18 VCC[067] VSSSENSE AE7 VSSSENSE {41}
Penryn VCC_Sense/VSS-Sense lines
between the Penryn processor R339
and the VR should have a 100,1%
trace width of 18 mils on R0402
7-mil spacing, with trace
impedance of Zo=27.4 Ω.
The
VCC_Sense/VSS-Sense should
be length matched to within CPU_BRACKET Mylar
25 mils. ASSY ASSY Change to ESD dischange point
By Johan 071224
HCPU1 HCPU2 HCPU3 HCPU4
CPU_HOLE CPU_HOLE CPU_HOLE CPU_HOLE

ns ns ns ns
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A Note : using ESD prtection Hole A
TOPSTAR TECHNOLOGY
bent
Page Name PENRYN(POWER&GND)
C M46G
B
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +V1.05S {6,7,8,12,13,14,22,24,31,38,40,41,42,44}
D D
U13A
H_A#[35:3] {7}
A14 H_A#3
{7} H_D#[63:0] H_A#_3
H_D#0 F2 C15 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 H_D#_1 H_A#_5 F16
H_D#2 F8 H13 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
E6 H_D#_3 H_A#_7 C18
H_D#4 G2 M16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H6 H_D#_5 H_A#_9 J13
H_D#6 H2 P16 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 H_D#_7 H_A#_11 R16
H_D#8 D4 N17 H_A#12
H_D#9 H_D#_8 H_A#_12 H_A#13
H3 H_D#_9 H_A#_13 M13
H_D#10 M9 E17 H_A#14
+V1.05S H_D#11 H_D#_10 H_A#_14 H_A#15
M11 H_D#_11 H_A#_15 P17
H_D#12 J1 F17 H_A#16
H_D#13 H_D#_12 H_A#_16 H_A#17
J2 H_D#_13 H_A#_17 G20
H_D#14 N12 B19 H_A#18
R391 H_D#15 H_D#_14 H_A#_18 H_A#19
J6 H_D#_15 H_A#_19 J16
221,1% H_D#16 P2 E20 H_A#20
R0402 H_D#17 H_D#_16 H_A#_20 H_A#21
L2 H_D#_17 H_A#_21 H16
H_D#18 R2 J20 H_A#22
H_D#19 H_D#_18 H_A#_22 H_A#23
N9 H_D#_19 H_A#_23 L17
H_SWING H_D#20 L6 A17 H_A#24
H_D#21 H_D#_20 H_A#_24 H_A#25
M5 H_D#_21 H_A#_25 B17
Close to the pin! H_D#22 J3 H_D#_22 H_A#_26 L16 H_A#26
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
R384 C299 H_D#25 N5 H20 H_A#29
100,1% 0.1UF/10V,X7R H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
R0402 C0402 H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
C Y3 H_D#_32
C
H_D#33 AD14 H12
H_D#_33 H_ADS# H_ADS# {7}
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 {7}
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 {7}
H_D#36 Y12 A9
H_D#_36 H_BNR# H_BNR# {7}
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# {7}
H_D#38 Y7 G12
HOST
H_D#_38 H_BREQ# H_BREQ#0 {7}
H_RCOMP H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# {7}
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# {7}
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK {6}
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# {6}
Trace should be 10mil H_D#43 AA9 H_D#_43 H_DPWR# J11 H_DPWR# {7}
wide with 20mil H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# {7}
R385 H_D#45 AD11 H9
24.9,1% spacing! H_D#46 AD10
H_D#_45 H_HIT#
E12
H_HIT# {7}
H_D#_46 H_HITM# H_HITM# {7}
R0402 H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# {7}
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# {7}
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
AA3 H_D#_52
H_D#53 AD3 J8 H_DINV#0
H_D#_53 H_DINV#_0 H_DINV#0 {7}
H_D#54 AD7 L3 H_DINV#1
H_D#55 AE14 Y13 H_DINV#2
H_D#56 AF3 Y1 H_DINV#3
H_D#57 AC1
H_D#58 H_D#_57
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 {7}
H_D#59 AC3 M7
H_D#_59 H_DSTBN#_1 H_DSTBN#1 {7}
H_D#60 AE11 AA5
H_D#61 AE8 AE6
H_D#62 AG2
H_D#63 H_D#_62
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 {7}
H_DSTBP#_1 M8 H_DSTBP#1 {7}
H_DSTBP#_2 AA6 H_DSTBP#2 {7}
H_SWING C5 AE5
H_SWING H_DSTBP#_3 H_DSTBP#3 {7}
H_RCOMP E3
+V1.05S H_RCOMP H_REQ#[4:0] {7}
B15 H_REQ#0
H_REQ#_0 H_REQ#1
B H_REQ#_1 K13 B
F13 H_REQ#2
H_REQ#_2 H_REQ#3
H_REQ#_3 B13
R360 C12 B14 H_REQ#4
{7} H_CPURST# H_CPURST# H_REQ#_4
1K,1% E11
{7} H_CPUSLP# H_CPUSLP#
R0402 B6
H_RS#_0 H_RS#0 {7}
H_RS#_1 F12 H_RS#1 {7}
H_RS#_2 C8 H_RS#2 {7}
A11 H_AVREF
R372 0 R0402 B11 H_DVREF
R361 C285 C286 CANTIGA_1p2
2K,1% 0.1UF/10V,X7R 0.1UF/10V,X7R
R0402 C0402 C0402
ns
Loyout note:
Place C76 with
100mils from GMCH
A A
TOPSTAR TECHNOLOGY
bent
Page Name CANTIGA(Host BUS)
C M46G
B
5 4 3 2 1
5 4 3 2 1
+VCC_PEG {14}
+V3.3S {6,7,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
+V3.3S
D D
R627 R628
10K 10K +VCC_PEG
U13C
+V3.3S
R630
LCTL_DATA 49.9,1%
{19} LVDS_BKLTCTL L32 L_BKLT_CTRL
LCTL_CLK G32 T37 Place the resistor within 300 mils
R631 R629 {19} LVDS_BKLTEN LCTL_CLK L_BKLT_EN PEG_COMPI PEG_COMP (1.27 mm) of the (G)MCH.Homy 1019
M32 L_CTRL_CLK PEG_COMPO T36
2.2K 2.2K
LCTL_DATA M33
L_DDC_CLK L_CTRL_DATA
K33 L_DDC_CLK PEG_RX#_0 H44
L_DDC_DATA J33 J46
L_DDC_DATA PEG_RX#_1
L_DDC_DATA {19} PEG_RX#_2 L44
PEG_RX#_3 L40
L_DDC_CLK {19} {19} LVDS_VDDEN M29 L_VDD_EN PEG_RX#_4 N41
LVDS_IBG C44 P48
T156 LVDS_VBG LVDS_IBG PEG_RX#_5
B43 LVDS_VBG PEG_RX#_6 N44
ns E37 T43
R632 LVDS_VREFH PEG_RX#_7
E38 LVDS_VREFL PEG_RX#_8 U43
LVDS
2.37K,1% C41 Y43
{19} LVDS_CLKAM LVDSA_CLK# PEG_RX#_9
{19} LVDS_CLKAP C40 LVDSA_CLK PEG_RX#_10 Y48
B37 Y36 +V3.3S
{19} LVDS_CLKBM LVDSB_CLK# PEG_RX#_11
{19} LVDS_CLKBP A37 LVDSB_CLK PEG_RX#_12 AA43
PEG_RX#_13 AD37
{19} LVDS_YAM0 H47 LVDSA_DATA#_0 PEG_RX#_14 AC47
E46 AD39 R633HDMI
{19} LVDS_YAM1 LVDSA_DATA#_1 PEG_RX#_15
G40 20K
{19} LVDS_YAM2 LVDSA_DATA#_2
T157 A40 H43
LVDSA_DATA#_3 PEG_RX_0
GRAPHICS
ns J44
PEG_RX_1 R634HDMI R636
{19} LVDS_YAP0 H48 LVDSA_DATA_0 PEG_RX_2 L43
D45 L41 0 0
{19} LVDS_YAP1 LVDSA_DATA_1 PEG_RX_3
C F40 N40 R0402 R0402 C
{19} LVDS_YAP2 LVDSA_DATA_2 PEG_RX_4
T161 B40 P47 ns
LVDSA_DATA_3 PEG_RX_5
3
ns N43 HDMI
PEG_RX_6 R635
{19} LVDS_YBM0 A41 LVDSB_DATA#_0 PEG_RX_7 T42
H38 U42 7.5K,1% HDMI
{19} LVDS_YBM1 LVDSB_DATA#_1 PEG_RX_8
{19} LVDS_YBM2 G37 LVDSB_DATA#_2 PEG_RX_9 Y42 1 MCH_HDMI_HPD# {21}
T158 J37 W47
ns LVDSB_DATA#_3 PEG_RX_10 Q41 R637HDMI
Y37
2
PEG_RX_11 2N7002 100K
{19} LVDS_YBP0 B42 LVDSB_DATA_0 PEG_RX_12 AA42
{19} LVDS_YBP1 G38 LVDSB_DATA_1 PEG_RX_13 AD36
{19} LVDS_YBP2 F37 LVDSB_DATA_2 PEG_RX_14 AC48
T159
PCI-EXPRESS
K37 LVDSB_DATA_3 PEG_RX_15 AD40
ns
TVA_DAC R638 75,1% J41 C496 0.1UF/10V,X7RHDMI
PEG_TX#_0 IN_D2- {21}
M46 C495 0.1UF/10V,X7RHDMI
R639 PEG_TX#_1 IN_D1- {21}
TVB_DAC 75,1% TVA_DAC F25 M47 C497 0.1UF/10V,X7RHDMI
TVA_DAC PEG_TX#_2 IN_D0- {21}
TVB_DAC H25 M40 C498 0.1UF/10V,X7RHDMI
R640 TVB_DAC PEG_TX#_3 MCH_CLK_D4- {21}
TVC_DAC 75,1% TVC_DAC K25 M42
TVC_DAC PEG_TX#_4
TV
PEG_TX#_5 R48
根据车checklist H24 TV_RTN PEG_TX#_6 N38
T40
HOMY1109 PEG_TX#_7
PEG_TX#_8 U37
靠近MCH HOMY1109 PEG_TX#_9 U40
C31 TV_DCONSEL_0 PEG_TX#_10 Y40
E32 TV_DCONSEL_1 PEG_TX#_11 AA46
PEG_TX#_12 AA37
PEG_TX#_13 AA40
PEG_TX#_14 AD43
PEG_TX#_15 AC46
E28 J42 C499 0.1UF/10V,X7R

{20} MCH_BLUE CRT_BLUE PEG_TX_0 IN_D2+ {21}
L46 C500 0.1UF/10V,X7R
PEG_TX_1 IN_D1+ {21}
G28 M48 C501HDMI
0.1UF/10V,X7R
{20} MCH_GREEN CRT_GREEN PEG_TX_2 IN_D0+ {21}
M39 C502HDMI
0.1UF/10V,X7R
PEG_TX_3 MCH_CLK_D4+ {21}
{20} MCH_RED J28 CRT_RED PEG_TX_4 M43 HDMI
VGA
PEG_TX_5 R47 HDMI
G29 CRT_IRTN PEG_TX_6 N37
MCH_BLUE R641 150,1% T39
B PEG_TX_7 B
{20} CRT_DDC_CLK H32 CRT_DDC_CLK PEG_TX_8 U36
MCH_GREEN R642 150,1% J32 U39
{20} CRT_DDC_DATA R644 24.9,1%R0402 CRT_DDC_DATA PEG_TX_9
{20} CRT_HSYNC J29 CRT_HSYNC PEG_TX_10 Y39
MCH_RED R643 150,1% E29 Y46
R64624.9,1% R0402 CRT_TVO_IREF PEG_TX_11
{20} CRT_VSYNC L29 CRT_VSYNC PEG_TX_12 AA36
150ohm电阻到GMCH R645 PEG_TX_13 AA39
AD42
走线阻抗37.5ohm homy 1109 976 change 33 to 24.9 hads 080514
PEG_TX_14
PEG_TX_15 AD46
150ohm电阻到VGA口 VerB:chang to 976 to improve VGA signal
走线阻抗50ohm homy 1109 CANTIGA_1p2
PLACE 150 OHM
RESISTORS CLOSE TO 1.02k demo
靠近MCH ，远离高速信号
GMCH Homy 1109 HOMY1109
A A
TOPSTAR TECHNOLOGY
bent
Page Name CANTIGA(GRAPHIC)
C M46G
B
5 4 3 2 1
5 4 3 2 1
U13D U13E
{15} MA_DATA[63:0] {16} MB_DATA[63:0]
MA_DATA0 AJ38 BD21 MB_DATA0 AK47 BC16
SA_DQ_0 SA_BS_0 MA_A_BS#0 {15,17} SB_DQ_0 SB_BS_0 MB_B_BS#0 {16,17}
MA_DATA1 AJ41 BG18 MB_DATA1 AH46 BB17
D SA_DQ_1 SA_BS_1 MA_A_BS#1 {15,17} SB_DQ_1 SB_BS_1 MB_B_BS#1 {16,17} D
MA_DATA2 AN38 AT25 MB_DATA2 AP47 BB33
SA_DQ_2 SA_BS_2 MA_A_BS#2 {15,17} SB_DQ_2 SB_BS_2 MB_B_BS#2 {16,17}
MA_DATA3 AM38 MB_DATA3 AP46
MA_DATA4 SA_DQ_3 SB_DQ_3
AJ36 BB20 MA_A_RAS# {15,17} MB_DATA4 AJ46
MA_DATA5 SA_DQ_4 SA_RAS# SB_DQ_4
AJ40 BD20 MA_A_CAS# {15,17} MB_DATA5 AJ48 AU17
MA_DATA6 SA_DQ_5 SA_CAS# SB_DQ_5 SB_RAS# MB_B_RAS# {16,17}
AM44 AY20 MA_A_WE# {15,17} MB_DATA6 AM48 BG16
MA_DATA7 SA_DQ_6 SA_WE# SB_DQ_6 SB_CAS# MB_B_CAS# {16,17}
AM42 MB_DATA7 AP48 BF14
MA_DATA8 SA_DQ_7 SB_DQ_7 SB_WE# MB_B_WE# {16,17}
AN43 MB_DATA8 AU47
AN44 MB_DATA9 AU46
AU40 MA_DM[7:0] {15} MB_DATA10 BA48
MA_DATA11 SA_DQ_10 MA_DM0 SB_DQ_10
AT38 AM37 MB_DATA11 AY48
MA_DATA12 SA_DQ_11 SA_DM_0 MA_DM1 SB_DQ_11
AN41 AT41 MB_DATA12 AT47 AM47 MB_DM0
MA_DATA13 SA_DQ_12 SA_DM_1 MA_DM2 SB_DQ_12 SB_DM_0
AN39 AY41 MB_DATA13 AR47 AY47 MB_DM1
AU44 AU39 MB_DATA14 BA47 BD40 MB_DM2
AU42 BB12 MB_DATA15 BC47 BF35 MB_DM3
AV39 AY6 MB_DATA16 BC46 BG11 MB_DM4
AY44 AT7 MB_DATA17 BC44 BA3 MB_DM5
SA_DQ_17 SA_DM_6 SB_DQ_17 SB_DM_5
A
MA_DATA18 BA40 AJ5 MA_DM7 MB_DATA18 BG43 AP1 MB_DM6
SA_DQ_18 SA_DM_7
B
MA_DATA19 MB_DATA19 SB_DQ_18 SB_DM_6 MB_DM7
BD43 SA_DQ_19 MA_DQS[7:0] {15} BF43 AK2
MA_DATA20 MA_DQS0 MB_DATA20 SB_DQ_19 SB_DM_7
AV41 SA_DQ_20 SA_DQS_0 AJ44 BE45 MB_DM[7:0] {16}
MA_DATA21 MA_DQS1 MB_DATA21 SB_DQ_20 MB_DQS0
AY43 SA_DQ_21 SA_DQS_1 AT44 BC41 AL47
MA_DATA22 MA_DQS2 MB_DATA22 SB_DQ_21 SB_DQS_0 MB_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 AV48
MA_DATA23 BC40 MEMORY BC37 MA_DQS3 MB_DATA23 BF41
SB_DQ_22 SB_DQS_1
BG41 MB_DQS2
MEMORY
MA_DATA24 SA_DQ_23 SA_DQS_3 MA_DQS4 SB_DQ_23 SB_DQS_2
AY37 AW12 MB_DATA24 BG38 BG37 MB_DQS3
BD38 BC8 MB_DATA25 BF38 BH9 MB_DQS4
AV37 AU8 MB_DATA26 BH35 BB2 MB_DQS5
AT36 AM7 MA_DQS#[7:0] {15} MB_DATA27 BG35 AU1 MB_DQS6
MA_DATA28 SA_DQ_27 SA_DQS_7 MA_DQS#0 SB_DQ_27 SB_DQS_6
AY38 AJ43 MB_DATA28 BH40 AN6 MB_DQS7
MA_DATA29 SA_DQ_28 SA_DQS#_0 MA_DQS#1 SB_DQ_28 SB_DQS_7
BB38 AT43 MB_DATA29 BG39 AL46 MB_DQS#0
MA_DATA30 SA_DQ_29 SA_DQS#_1 MA_DQS#2 SB_DQ_29 SB_DQS#_0 MB_DQS[7:0] {16}
AV36 BA44 MB_DATA30 BG34 AV47 MB_DQS#1
MA_DATA31 SA_DQ_30 SA_DQS#_2 MA_DQS#3 SB_DQ_30 SB_DQS#_1
AW36 BD37 MB_DATA31 BH34 BH41 MB_DQS#2
BD13 AY12 MB_DATA32 BH14 BH37 MB_DQS#3
AU11 BD8 MB_DATA33 BG12 BG9 MB_DQS#4
BC11 AU9 MB_DATA34 BH11 BC2 MB_DQS#5
BA12 AM8 MB_DATA35 BG8 AT2 MB_DQS#6
SYSTEM
MA_DATA36 SA_DQ_35 SA_DQS#_7 SB_DQ_35 SB_DQS#_6

AU13 MB_DATA36 BH12 AN5 MB_DQS#7
SYSTEM
SA_DQ_36 MA_A_A[13:0] {15,17} SB_DQ_36 SB_DQS#_7
MA_DATA37 AV13 BA21 MA_A_A0 MB_DATA37 BF11
MA_DATA38 SA_DQ_37 SA_MA_0 MA_A_A1 SB_DQ_37 MB_DQS#[7:0] {16}
BD12 BC24 MB_DATA38 BF8 AV17 MB_B_A0
MA_DATA39 SA_DQ_38 SA_MA_1 MA_A_A2 SB_DQ_38 SB_MA_0
C BC12 BG24 MB_DATA39 BG7 BA25 MB_B_A1 C
BB9 BH24 MB_DATA40 BC5 BC25 MB_B_A2
BA9 BG25 MB_DATA41 BC6 AU25 MB_B_A3
AU10 BA24 MB_DATA42 AY3 AW25 MB_B_A4
AV9 BD24 MB_DATA43 AY1 BB28 MB_B_A5
BA11 BG27 MB_DATA44 BF6 AU28 MB_B_A6
BD9 BF25 MB_DATA45 BF5 AW28 MB_B_A7
AY8 AW24 MB_DATA46 BA1 AT33 MB_B_A8
BA6 BC21 MB_DATA47 BD3 BD33 MB_B_A9
DDR
AV5 BG26 MB_DATA48 AV2 BB16 MB_B_A10

MB_DATA49 MB_B_A11
DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 AW33
MA_DATA50 MA_A_A13 MB_DATA50 SB_DQ_49 SB_MA_11 MB_B_A12
AT9 SA_DQ_50 SA_MA_13 BH17 AR3 AY33
MA_DATA51 MA_A_A14 MB_DATA51 SB_DQ_50 SB_MA_12 MB_B_A13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 BH15
MA_DATA52 MB_DATA52 SB_DQ_51 SB_MA_13 MB_B_A14
AU5 SA_DQ_52 AY2 AU33 MB_B_A[13:0] {16,17}
MA_DATA53 MB_DATA53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1
MA_DATA54 MB_DATA54 SB_DQ_53
AT5 SA_DQ_54 AP3
AN10 SA_DQ_55 AR1
MA_DATA56 MA_A_A14 MB_DATA56 SB_DQ_55
AM11 SA_DQ_56 MA_A_A14 {15,17} AL1
AM5 SA_DQ_57 AL2
MA_DATA58 MB_B_A14 MB_DATA58 SB_DQ_57
AJ9 SA_DQ_58 MB_B_A14 {16,17} AJ1
AJ8 SA_DQ_59 AH1
AN12 SA_DQ_60 AM2
AM13 SA_DQ_61 AM3
AJ11 SA_DQ_62 AH3
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p2 CANTIGA_1p2
B B
A A
TOPSTAR TECHNOLOGY
bent
Page Name CANTIGA(DDRII)
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3S {6,7,10,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50
+V1.8 {13,14,15,16,37,40,42}
+V1.05S {6,7,8,9,13,14,22,24,31,38,40,41,42,44}
+V3.3AL {19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
U13B
+V3.3S ns ICTP T32 RSVD1 M36

ns ICTP T35 RSVD2 RSVD1
N36 AP24
DDR CLK/ CONTROL/COMPENSATION

RSVD2 SA_CK_0 M_CLK_DDR0 {15}
ns ICTP T40 RSVD3 R33 AT21
D RSVD3 SA_CK_1 M_CLK_DDR1 {15} D
ns ICTP T43 RSVD4 T33 AV24
RSVD4 SB_CK_0 M_CLK_DDR2 {16}
R123 ns ICTP T46 RSVD5 AH9 AU20
RSVD5 SB_CK_1 M_CLK_DDR3 {16}
10K ns ICTP T49 RSVD6 AH10
R0402 ns ICTP T48 RSVD7 RSVD6
AH12 RSVD7 SA_CK#_0 AR24 M_CLK_DDR#0 {15}
ns ICTP T47 RSVD8 AH13 AR21
PM_EXTTS#0 R127 0 R0402 ns ICTP T31 RSVD9 RSVD8 SA_CK#_1 M_CLK_DDR#1 {15}
DIM_EXTTS#0 {15} K12 RSVD9 SB_CK#_0 AU24 M_CLK_DDR#2 {16}
ns AV20
SB_CK#_1 M_CLK_DDR#3 {16} CFG5 CFG16
SA_CKE_0 BC28 M_CKE0 {15,17}
SA_CKE_1 AY28 M_CKE1 {15,17}
ns ICTP T42 RSVD14 T24 AY36
+V3.3S RSVD14 SB_CKE_0 M_CKE2 {16,17} R364 R124
SB_CKE_1 BB36 M_CKE3 {16,17}
RSVD
ns ICTP T24 RSVD15 B31 2.2K 2.2K
RSVD15 CFG5 LOW = DMI x 2 ns LOW = Dynamic ODT ns
SA_CS#_0 BA17 M_CS#0 {15,17}
ns ICTP T33 RSVD17 M1 AY16 High =DMI x 4(Default) CFG16 Disable
RSVD17 SA_CS#_1 M_CS#1 {15,17} High = Dynamic ODT
R95 AV16 M_CS#2 {16,17}
(FSB Dynamic
SB_CS#_0 +V1.8 Enable(default)
10K AR13 M_CS#3 {16,17} ODT)
R0402 ns ICTP T54 RSVD20 SB_CS#_1
AY21 RSVD20
SA_ODT_0 BD17 M_ODT0 {15,17}
PM_EXTTS#1 R98 0 R0402 AY17
DIM_EXTTS#1 {16} SA_ODT_1 M_ODT1 {15,17}
ns ns ICTP T86 RSVD21 B2 BF15 R423 R422 +V3.3S +V3.3S
RSVD21 SB_ODT_0 M_ODT2 {16,17}
ns ICTP T120 RSVD22 BG23 AY13 80.6,1% 20,1%
RSVD22 SB_ODT_1 M_ODT3 {16,17} Low = Only Digital Display Port
ns ICTP T123 RSVD23 BF23 R0402 R0603
ns ICTP T119 RSVD24 RSVD23 SM_RCOMP ns (SDVO/DP/iHDMI) or PCIE or is
BH18 RSVD24 SM_RCOMP BG22
ns ICTP T127 RSVD25 BF18 BH21 SM_RCOMP# CFG19 LOW = Normal(Default) CFG20 operational(Default)
RSVD25 SM_RCOMP# (DMI Lane High =Lane Reversal R97 High = Digital Display
BF28 SM_RCOMP_VOH R413 R414 Loyout note: Reversal) 4.02K,1% Port(SDVO/DP/iHDMI) R96
SM_RCOMP_VOH SM_RCOMP_VOL 20,1% 80.6,1% Route as short as ns and PCIE are operating 4.02K,1%
BH28
SM_RCOMP_VOL simultaneously via PEG port
VerA:reserve Pull-up and Pull-down resistor 071026 R0603 R0402 possible ns
AV42 SM_VREF ns
SM_VREF CFG19 CFG20
SM_PWROK AR36
+V1.05S BF17 R185
SM_REXT DDR2: Leave as No Connect.
499,1%
SM_DRAMRST# BC36
B38 For DDR3:GMCH requires this pin never to be driven high CFG9
DPLL_REF_CLK DREFCLK {6} before DDR voltage has ramped to stable value. For
R151R146R156R154 A38
DPLL_REF_CLK# DREFCLK# {6} DDR2:connect to GND Design Note:
1K 1K 1K 1K E41
DPLL_REF_SSCLK DREFSSCLK {6} Only one of the CFG10/CFG12/CFG13
C
DPLL_REF_SSCLK# F41 DREFSSCLK# {6} C
ns ns ns ns CFG9 LOW = Reverse Lane(default) R362 straps can be enabled at any time
PCIe raphicsHigh = Normal opertion
ME JTAG
F43 2.2K
CLK
PEG_CLK CLK_MCH_3GPLL {6}
AL34 E43 CLK_MCH_3GPLL# {6} Lane ns CFG10 CFG12 CFG13
ME_JTAG_TCK PEG_CLK#
AK34 ME_JTAG_TDI
AN35 AE41 DMI_TXN0 R363 R135 R132
ME_JTAG_TDO DMI_RXN_0 DMI_TXN0 {23}
AE37 DMI_TXN1 2.2K 2.2K 2.2K
DMI_RXN_1 DMI_TXN1 {23}
AM35 AE47 DMI_TXN2 ns ns ns
ME_JTAG_TMS DMI_RXN_2 DMI_TXN2 {23}
AH39 DMI_TXN3
DMI_RXN_3 DMI_TXN3 {23}
R150R144R161R155 AE40 DMI_TXP0
DMI_RXP_0 DMI_TXP0 {23}
10K 10K 10K 10K T25 AE38 DMI_TXP1
{6} MCH_BSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 {23} Reference CRB 1.201a
R25 AE48 DMI_TXP2
{6} MCH_BSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 {23}
ns ns ns ns P25 AH40 DMI_TXP3
{6} MCH_BSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 {23}
P20 CFG6
ns ICTP T41 CFG_3
P24 AE35 DMI_RXN0
ns ICTP T44 CFG5 CFG_4 DMI_TXN_0 DMI_RXN1
DMI_RXN0 {23}
CFG10 Low =disabled(default)
C25 CFG_5 DMI_TXN_1 AE43 DMI_RXN1 {23}
CFG6 N24 AE46 DMI_RXN2
DMI_RXN2 {23}
CFG6 High =The iTPM Host Interface (PCIE Loopback High=enabled
CFG_6 DMI_TXN_2 (iTPM Host is disabled(default)
CFG7 M24 AH42 DMI_RXN3
DMI_RXN3 {23}
R128 enable)
CFG_7 DMI_TXN_3
ns ICTP T25 E21 Interface) Low =The iTPM Host Interface 2.2K
CFG_8 is enabled
CFG
CFG9 DMI_RXP0 ns
DMI
C23 CFG_9 DMI_TXP_0 AD35 DMI_RXP0 {23}

CFG10 C24 AE44 DMI_RXP1
CFG_10 DMI_TXP_1 DMI_RXP1 {23}
N21 AF46 DMI_RXP2
ns ICTP T36 CFG_11 DMI_TXP_2 DMI_RXP2 {23}
CFG12 P21 AH43 DMI_RXP3 CFG12 Low =disabled(default)
CFG_12 DMI_TXP_3 DMI_RXP3 {23} High=ALL Z Mode enabled
CFG13 T21 (ALL Z)
CFG_13
ns ICTP T39 R20 CFG_14
ns ICTP T34 M20 CFG_15
CFG16 L21 CFG_16
ns ICTP T27 H21 CFG_17 CFG7
GRAPHICS VID
ns ICTP T38 P29 CFG_18

CFG19 R28 CFG13 Low =disabled(default)
CFG20 CFG_19 +V3.3S CFG7 Low = AMT Firmware will use TLS cipher (XOR) High=XOR Mode enabled
T28 CFG_20 GFX_VID_0 B33
B32 Change to ns , PU at CLK GEN (Intel ME suite with no confidentiality (Isolators
GFX_VID_1 By Johan 071108 are bypassed)
G33 Crypto R126
GFX_VID_2 High = AMT Firmware will use TLS cipher +V1.8
GFX_VID_3 F33 Transport 2.2K
R0402 0 R133 R122 suite with Confidentiality {Isolators are ns
B {23} PM_SYNC# R29 PM_SYNC# GFX_VID_4 E33 Strap) active (Default)} B
R0402 0 R368 B7 10K
{7,22,41} H_DPRSTP# PM_DPRSTP#
PM_EXTTS#0 N33 R0402
PM_EXTTS#1 PM_EXT_TS#_0 ns R418
P32 PM_EXT_TS#_1
PM
R0402 0 R158 AT40 C34 PCIE_CLKREQ# 1K,1%

{23} PM_ICH_PWROK PWROK GFX_VR_EN
R0402 100 R160 AT11 +V1.05S R0402
{19,23,26,27,28,31,33,51} BUF_PLT_RST# RSTIN#
R0402 0 R130 T20
{7,22,31} PM_THRMTRIP# THERMTRIP#
R32 SM_RCOMP_VOH
{23,41} PM_DPRSLPVR DPRSLPVR
2.2uF/10V,X7R
AH37 R142 +V3.3AL C355 C359
CL_CLK CL_CLK0 {23}
AH36 1K,1%
CL_DATA CL_DATA0 {23} 0.01uF/16V,X7R
ns ICTP TP_CN1 BG48 AN36 R159 0 R0402 R0402 C0805 R419
T122 NC_1 CL_PWROK PM_ICH_PWROK {23}
ns ICTP TP_CN2 BF48 AJ35 C0402 3.01K,1%
T121 NC_2 CL_RST# CL_RST#0 {23}
ME
ns ICTP TP_CN3 BD48 AH34 MCH_CLVREF R353 R0402

T112 NC_3 CL_VREF 1.These signals serve as DDC signals
ns ICTP TP_CN4 BC48 1K
T109 NC_4 for iHDMI port C&B
ns ICTP TP_CN5 BH47 2.SDVO_CTRLDATA&DDPC_CTRLDATA should C86 R145 R356 ns SM_RCOMP_VOL
T118 NC_5 both be high to enable display port
ns ICTP TP_CN6 499,1% 1K
2.2uF/10V,X7R
T56 BG47 NC_6 MCH_TSATN# {33}
ns ICTP TP_CN7 BE47 N28 0.1UF/25V,Y5V R0402 ns C358
T114 NC_7 DDPC_CTRLCLK C0402 C354
ns ICTP TP_CN8 BH46 M28 R417
T129 NC_8 DDPC_CTRLDATA
3
ns ICTP TP_CN9 BF46 G36 0.01uF/16V,X7R C0805 1K,1%
T57 NC_9 SDVO_CTRLCLK HDMI_DDC_CLK {21}
NC
ns ICTP TP_CN10 BG45 E36 +V1.05S 1 Q16 C0402 R0402

T116 NC_10 SDVO_CTRLDATA HDMI_DDC_DATA {21}
ns ICTP TP_CN11 BH44 K36 MMBT3904-F
T125 NC_11 CLKREQ# PCIE_CLKREQ# {6}
ns ICTP TP_CN12 BH43 H36 R354 0 R0402 R369 ns
T130 MCH_ICH_SYNC# {23}
2
ns ICTP TP_CN13 NC_12 ICH_SYNC# 56
BH6
MISC
T126 NC_13
3
ns ICTP TP_CN14 BH5 use for the AUX2 trip point
T128 NC_14
ns ICTP TP_CN15 BG4 B12 R370 330 ns 1 Q20
T124 NC_15 TSATN#
ns ICTP TP_CN16 BH3 MMBT3904-F
T115 NC_16
ns ICTP TP_CN17 BF3 ns
T58
2
ns ICTP TP_CN18 NC_17 1.Checklist:500ohm CRB:511ohm 2.use 500ohm
T117 BH2 NC_18
ns ICTP TP_CN19 BG2 B28 resistor accord with the advice of KAM
T55 NC_19 HDA_BCLK AZALIA_HDMI_BITCLK {22}
ns ICTP TP_CN20 BE2 B30
T111 NC_20 HDA_RST# AZALIA_HDMI_RST# {22}
ns ICTP TP_CN21 BG1 B29 AZALIA_HDMI_SDATAIN2
T113 NC_21 HDA_SDI
ns ICTP TP_CN22 BF1 C29
T110 NC_22 HDA_SDO AZALIA_HDMI_SDOUT {22}
ns ICTP TP_CN23 BD1 A28
HDA
T108 NC_23 HDA_SYNC AZALIA_HDMI_SYNC {22}

ns ICTP TP_CN24 BC1
T107 NC_24 +V1.8
ns ICTP TP_CN25 F1
T26 NC_25
A CANTIGA_1p2 R225 A
10K,1%
ns
PR71 0 SM_VREF
{15,16,37} SM_VREF_L
TOPSTAR TECHNOLOGY
R227 NOTE:If the voltage regulator for bent
R647 33 R0402 AZALIA_HDMI_SDATAIN2 Close The CAP to GMCH C153 C155 10K,1% the system memory interface Page Name
{22} AZALIA_SDATAIN2 already supplies a VREF output CANTIGA(DMI&CLK)
0.1UF/25V,Y5V ns
HDMI 0.1UF/25V,Y5V and meets the voltage tolerance Size
and current requirements for Project Name Rev
C M46G
these pins, then a voltage B
divider would not be needed. Date: Thursday, August 27, 2009 Sheet 12 of 51
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +V1.8
+V1.05S
{12,14,15,16,37,40,42}
{6,7,8,9,12,14,22,24,31,38,40,41,42,44}
U13G
+V1.8 +V1.05S
D D
U13I U13J AP33 W28
VCC_SM_1 VCC_AXG_NCTF_1
BG21 VSS_199 VSS_297 AH8 AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28
1
AU48 AM36 L12 Y8 C125 ns BH32 W26
VSS_1 VSS_100 VSS_200 VSS_298 VCC_SM_3 VCC_AXG_NCTF_3
AR48 AE36 AW21 L8 CT7343_19 + BG32 V26
1
AL48 VSS_3 VSS_102 P36 AU21 VSS_202 VSS_300 E8 BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25
BB47 L36 AP21 B8 220UF/2.5V,POSCAP BD32 V25
2
AW47 VSS_5 VSS_104 J36 AN21 VSS_204 VSS_302 AY7 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24
AN47 VSS_6 VSS_105 F36 AH21 VSS_205 VSS_303 AU7 BB32 VCC_SM_8 VCC_AXG_NCTF_8 V24
AJ47 VSS_7 VSS_106 B36 AF21 VSS_206 VSS_304 AN7 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AF47 VSS_8 VSS_107 AH35 AB21 VSS_207 VSS_305 AJ7 AY32 VCC_SM_10 VCC_AXG_NCTF_10 V23
AD47 VSS_9 VSS_108 AA35 R21 VSS_208 VSS_306 AE7 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
AB47 VSS_10 VSS_109 Y35 M21 VSS_209 VSS_307 AA7 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
Y47 U35 J21 N7 C124 C360 AU32 AK21
VSS_11 VSS_110 VSS_210 VSS_308 C0805 C0402 VCC_SM_13 VCC_AXG_NCTF_13
T47 VSS_12 VSS_111 T35 G21 VSS_211 VSS_309 J7 AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
N47 VSS_13 VSS_112 BF34 BC20 VSS_212 VSS_310 BG6 AR32 VCC_SM_15 VCC_AXG_NCTF_15 V21
10UF/6.3V,X5R
POWER
L47 VSS_14 VSS_113 AM34 BA20 VSS_213 VSS_311 BD6 AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
G47 VSS_15 VSS_114 AJ34 AW20 VSS_214 VSS_312 AV6 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
BD46 AF34 AT20 AT6 0.1UF/10V,X7R BH31 AK20
BA46 VSS_17 VSS_116 AE34 AJ20 VSS_216 VSS_314 AM6 BG31 VCC_SM_19 VCC_AXG_NCTF_19 W20
AY46 VSS_18 VSS_117 W34 AG20 VSS_217 VSS_315 M6 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20
AV46 B34 Y20 C6 C352 BG30 AM19
VSS_19 VSS_118 VSS_218 VSS_316 C362 C0402 VCC_SM_21 VCC_AXG_NCTF_21
AR46 VSS_20 VSS_119 A34 N20 VSS_219 VSS_317 BA5 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
AM46 BG33 K20 AH5 C0805 BG29 AK19
VSS_21 VSS_120 VSS_220 VSS_318 0.1UF/10V,X7R VCC_SM_23 VCC_AXG_NCTF_23
V46 VSS_22 VSS_121 BC33 F20 VSS_221 VSS_319 AD5 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
R46 BA33 C20 Y5 10UF/6.3V,X5R BD29 AH19
VCC SM
P46 VSS_24 VSS_123 AV33 A20 VSS_223 VSS_321 L5 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19
H46 VSS_25 VSS_124 AR33 BG19 VSS_224 VSS_322 J5 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
F46 VSS_26 VSS_125 AL33 A18 VSS_225 VSS_323 H5 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
BF44 VSS_27 VSS_126 AH33 BG17 VSS_226 VSS_324 F5 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
AH44 VSS_28 VSS_127 AB33 BC17 VSS_227 VSS_325 BE4 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AD44 P33 AW17 C356 AV29 Y19
VSS_29 VSS_128 VSS_228 C0402 VCC_SM_31 VCC_AXG_NCTF_31
AA44 L33 AT17 BC3 AU29 W19
Y44
U44
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
H33
N32
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
0.1UF/10V,X7R AT29
AR29
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
V19
U19
T44 K32 H17 R3 AP29 AM17
C
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32
C17
VSS_232
VSS_233
VSS_330
VSS_331
VSS_332
P3
F3 BA36
VCC_SM_35
VCC_SM_36/NC
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AK17
AH17 C
BC43 VSS_36 VSS_135 A31 BA16 VSS_235 VSS_333 BA2 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17
AV43 VSS_37 VSS_136 AN29 VSS_334 AW2 BD16 VCC_SM_38/NC VCC_AXG_NCTF_39 AF17
AU43 VSS_38 VSS_137 T29 AU16 VSS_237 VSS_335 AU2 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
AM43 VSS_39 VSS_138 N29 AN16 VSS_238 VSS_336 AR2 AW16 VCC_SM_40/NC VCC_AXG_NCTF_41 AC17
J43 VSS_40 VSS_139 K29 N16 VSS_239 VSS_337 AP2 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
C43 VSS_41 VSS_140 H29 K16 VSS_240 VSS_338 AJ2 AT13 VCC_SM_42/NC VCC_AXG_NCTF_43 Y17
BG42 F29 G16 AH2 C105 C109 C114 C106 C101 W17
VSS_42 VSS_141 VSS_241 VSS_339 C0402 C0402 C0402 C0402 VCC_AXG_NCTF_44
AY42 A29 E16 AF2 C0402 V17
VCC GFX NCTF

VSS_43 VSS_142 VSS_242 VSS_340 ns ns ns VCC_AXG_NCTF_45
AT42 VSS_44 VSS_143 BG28 BG15 VSS_243 VSS_341 AE2 VCC_AXG_NCTF_46 AM16
AN42 BD28 AC15 AD2 0.1UF/10V,X7R 0.1UF/10V,X7R Y26 AL16
VSS_45 VSS_144 VSS_244 VSS_342 0.1UF/10V,X7R ns 0.1UF/10V,X7R ns 0.1UF/10V,X7R VCC_AXG_1 VCC_AXG_NCTF_47
AJ42 VSS_46 VSS_145 BA28 W15 VSS_245 VSS_343 AC2 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
AE42 VSS_47 VSS_146 AV28 A15 VSS_246 VSS_344 Y2 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
N42 VSS_48 VSS_147 AT28 BG14 VSS_247 VSS_345 M2 AA25 VCC_AXG_4 VCC_AXG_NCTF_50 AH16
L42 VSS_49 VSS_148 AR28 AA14 VSS_248 VSS_346 K2 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
BD41 VSS_50 VSS_149 AJ28 C14 VSS_249 VSS_347 AM1 AC24 VCC_AXG_6 VCC_AXG_NCTF_52 AF16
AU41 VSS_51 VSS_150 AG28 BG13 VSS_250 VSS_348 AA1 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
AM41 VSS_52 VSS_151 AE28 BC13 VSS_251 VSS_349 P1 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
AH41 VSS_53 VSS_152 AB28 BA13 VSS_252 VSS_350 H1 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
AD41 VSS_54 VSS_153 Y28 AC23 VCC_AXG_10 VCC_AXG_NCTF_56 AA16
AA41 VSS_55 VSS_154 P28 VSS_351 U24 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
Y41 K28 AN13 U28 +V1.05S AA23 W16
VSS_56 VSS_155 VSS_255 VSS_352 VCC_AXG_12 VCC_AXG_NCTF_58
U41 VSS_57 VSS_156 H28 AJ13 VSS_256 VSS_353 U25 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
T41 VSS_58 VSS_157 F28 AE13 VSS_257 VSS_354 U29 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
M41 VSS_59 VSS_158 C28 N13 VSS_258 VSS_355 AJ6 AE21 VCC_AXG_15
G41 VSS_60 VSS_159 BF26 L13 VSS_259 AC21 VCC_AXG_16
B41 VSS_61 VSS_160 AH26 G13 VSS_260 VSS_NCTF_1 AF32 AA21 VCC_AXG_17
BG40 VSS_62 VSS_161 AF26 E13 VSS_261 VSS_NCTF_2 AB32 Y21 VCC_AXG_18
BB40 VSS_63 VSS_162 AB26 BF12 VSS_262 VSS_NCTF_3 V32 AH20 VCC_AXG_19
AV40 VSS_64 VSS_163 AA26 AV12 VSS_263 VSS_NCTF_4 AJ30 AF20 VCC_AXG_20
AN40 VSS_65 VSS_164 C26 AT12 VSS_264 VSS_NCTF_5 AM29 AE20 VCC_AXG_21
1
H40 B26 AM12 AF29 C503 AC20
VSS_66 VSS_165 VSS_265 VSS_NCTF_6 cost down 080510 hads VCC_AXG_22
E40 BH25 AA12 AB29 + ns AB20
1
VSS NCTF
VSS_67 VSS_166 VSS_266 VSS_NCTF_7 VCC_AXG_23

AT39 VSS_68 VSS_167 BD25 J12 VSS_267 VSS_NCTF_8 U26 AA20 VCC_AXG_24
AM39 BB25 A12 U23 CT7343_19 T17
2
VSS_69 VSS_168 VSS_268 VSS_NCTF_9 VCC_AXG_25
AJ39 VSS_70 VSS_169 AV25 BD11 VSS_269 VSS_NCTF_10 AL20 T16 VCC_AXG_26
AE39 AR25 BB11 V20 220UF/2.5V,POSCAP AM15
VSS_71 VSS_170 VSS_270 VSS_NCTF_11 VerB:change the type of C503 at the demand of ME VCC_AXG_27
B
N39 VSS_72 VSS_171 AJ25 AY11 VSS_271 VSS_NCTF_12 AC19 AL15 VCC_AXG_28 B
L39 VSS_73 VSS_172 AC25 AN11 VSS_272 VSS_NCTF_13 AL17 AE15 VCC_AXG_29
B39 VSS_74 VSS_173 Y25 AH11 VSS_273 VSS_NCTF_14 AJ17 AJ15 VCC_AXG_30
BH38 VSS_75 VSS_174 N25 VSS_NCTF_15 AA17 AH15 VCC_AXG_31
BC38 VSS_76 VSS_175 L25 Y11 VSS_275 VSS_NCTF_16 U17 AG15 VCC_AXG_32
BA38 VSS_77 VSS_176 J25 N11 VSS_276 AF15 VCC_AXG_33
AU38 VSS_78 VSS_177 G25 G11 VSS_277 VSS_SCB_1 BH48 AB15 VCC_AXG_34
AH38 E25 C11 BH1 AA15
VSS SCB
VSS_79 VSS_178 VSS_278 VSS_SCB_2 VCC_AXG_35
VCC GFX
AD38 VSS_80 VSS_179 BF24 BG10 VSS_279 VSS_SCB_3 A48 Y15 VCC_AXG_36
AA38 VSS_81 VSS_180 AD12 AV10 VSS_280 VSS_SCB_4 C1 V15 VCC_AXG_37
Y38 VSS_82 VSS_181 AY24 AT10 VSS_281 U15 VCC_AXG_38
U38 VSS_83 VSS_182 AT24 AJ10 VSS_282 VSS_SCB_6 A3 AN14 VCC_AXG_39
T38 VSS_84 VSS_183 AJ24 AE10 VSS_283 AM14 VCC_AXG_40
J38 AH24 AA10 E1 U14 AV44 VCCSM_LF1
VSS_85 VSS_184 VSS_284 NC_26 VCC_AXG_41 VCC_SM_LF1
VCC SM LF
F38 AF24 M10 D2 +V1.05S T14 BA37 VCCSM_LF2
VSS_86 VSS_185 VSS_285 NC_27 VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
C38 VSS_87 VSS_186 AB24 BF9 VSS_286 NC_28 C3 VCC_SM_LF3 AM40
BF37 R24 BC9 B4 AV21 VCCSM_LF4
VSS_88 VSS_187 VSS_287 NC_29 VCC_SM_LF4 VCCSM_LF5
BB37 VSS_89 VSS_188 L24 AN9 VSS_288 NC_30 A5 VCC_SM_LF5 AY5
AW37 K24 AM9 A6 R153 AM10 VCCSM_LF6
VSS_90 VSS_189 VSS_289 NC_31 1K VCC_SM_LF6 VCCSM_LF7
AT37 VSS_91 VSS_190 J24 AD9 VSS_290 NC_32 A43 VCC_SM_LF7 BB13
AN37 G24 G9 A44 ns
VSS_92 VSS_191 VSS_291 NC_33
AJ37 F24 B9 B45
NC
VSS_93 VSS_192 VSS_292 NC_34

H37 VSS_94 VSS_193 E24 BH8 VSS_293 NC_35 C46 AJ14 VCC_AXG_SENSE
C37 BH23 BB8 D47 AH14 C111 C95 C107 C103 C93 C110 C108
VSS_95 VSS_194 VSS_294 NC_36 VSS_AXG_SENSE
BG36 VSS_96 VSS_195 AG23 AV8 VSS_295 NC_37 B47
BD36 Y23 AT8 A46 C0402 C0402 C0603 C0603 C0603 C0603 C0603
VSS_97 VSS_196 VSS_296 NC_38 R141 0.1UF/10V,X7R 0.47UF/25V,Y5V
AK15 VSS_98 VSS_197 B23 NC_39 F48
AU36 A23 E48 1K 0.22UF/10V,X7R 1uF/10V,X7R
VSS_99 VSS_198 NC_40 ns 0.1UF/10V,X7R 0.22UF/10V,X7R 1uF/10V,X7R
NC_41 C48
NC_42 B48
CANTIGA_1p2 A47
NC_43
CANTIGA_1p2 VerA:Reserve PU&PD resistor though it's CANTIGA_1p2
suggested that this two pin could be NC
A A
TOPSTAR TECHNOLOGY
bent
Page Name CANTIGA(VSS&NCTF)
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3S {6,7,10,12,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
+VCC_PEG {10}
+V1.8 {12,13,15,16,37,40,42}
+V1.5S {8,22,24,26,27,28,30,38,40,42}
CHANGED +V1.05S {6,7,8,9,12,13,22,24,31,38,40,41,42,44}
+V3.3S
+V1.05S
R648 R0603 0 +3.3S_A_CRT_DAC

C505 +V1.05S
C504 U13H
0.1UF/10V,X7R 0.01uF/16V,X7R 852mA
C0402 U13
VTT_1
D 73mA VTT_2 T13
C83
C91
C0402
C75
C0805
C78
C0805 C87 D
B27 VCCA_CRT_DAC_1 VTT_3 U12 C77
A26 T12 10UF/6.3V,X5R C0805
VCCA_CRT_DAC_2 VTT_4 C0805 0.1UF/10V,X7R ns 10uF/6.3V,X5R 2.2uF/10V,X7R 10UF/6.3V,X5R U13F
VTT_5 U11
R649
R0603
414uA +3.3S_A_CRT_DAC_BG A25 VTT_6 T11 10uF/6.3V,X5R C0805
U10
CRT
VCCA_DAC_BG VTT_7
0
C507
C506
0.01uF/16V,X7R
B25 VSSA_DAC_BG VTT_8 T10 2898mA
VTT_9 U9 AG34 VCC_1
0.1UF/10V,X7R
C0402 64.8mA VTT_10
VTT_11
T9
U8 VerV:Ns C75 Hads 080510
AC34
AB34
VCC_2
VCC_3
+V1.05S +V1.05S_DPLLA F47 T8 AA34
VCCA_DPLLA VTT_12 VCC_4
64.8mA U7 Y34
VTT
VTT_13 VCC_5
50mA +V1.05S_DPLLB L48 VCCA_DPLLB VTT_14 T7 V34 VCC_6
FB23 1 2 FB0805
300ohm@100MHz,1.5A
+V1.05S_PEGPLL
24mAAD1
+V1.05S_HPLL VTT_15 U6
T6
U34
AM33
VCC_7
PLL
C322 C321 VCCA_HPLL VTT_16 C80 VCC_8
VTT_17 U5 AK33 VCC_9
R398 R0603 +V1.8 +V1.05S_MPLL AE1 T5 C0805 AJ33
1 C0402 C0402 VCCA_MPLL VTT_18 10UF/6.3V,X5R VCC_10
VTT_19 V3 AG33 VCC_11
C316
10UF/6.3V,X5R
0.1UF/10V,X7R
+V3.3S
0.1UF/10V,X7R
13.2mA VTT_20 U3 AF33 VCC_12
J48 VCCA_LVDS VTT_21 V2
C0805 C508 U2 AE33
A LVDS
VTT_22 VCC_13
VCC CORE
R139 10UF/6.3V,X5R J47 T2 AC33
0 C0805 VSSA_LVDS VTT_23 VCC_14
VTT_24 V1 AA33 VCC_15
+V1.5S R0603 U1 +V1.05S Y33
VTT_25 C487 VCC_16
ns 414uA W33 VCC_17
R140 R0603 0 AD48 V33
C81 VCCA_PEG_BG VCC_18
U33 VCC_19
CHANGED 0.1UF/10V,X7R AH28
0.1uF/10V,X5R VCC_20
place close to (G)MCH C0402
50mA AF28
A PEG
C0402 VCC_21
C488 AC28 VCC_22
+V1.05S_PEGPLLAA48 AA28
+V1.05S VCCA_PEG_PLL VCC_23
AJ26 VCC_24
480mA~720mA AG26 VCC_25
R149 0 R0805 AR20 AE26
C98 C89 C97 C99 VCCA_SM_1 0.1uF/10V,X5R VCC_26
AP20 VCCA_SM_2 AC26 VCC_27
C0805 C0805 C0603 C0402 AN20 C0402 AH25
4.7uF/6.3V,X5R 0.1UF/10V,X7R
AR17
AP17
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
POWER AG25
AF25
VCC_28
VCC_29
VCC_30
+V1.05S
C 10UF/6.3V,X5R 1uF/10V,X7R AN17 AG24 C

VCCA_SM_6 VCC_31
AT16 VCCA_SM_7 AJ23 VCC_32
AR16 AH23
A SM
VCCA_SM_8 VCC_33
POWER
AP16 VCCA_SM_9 AF23 VCC_34
VCC_NCTF_1 AM32
R1360 T32 AL32
R0402 VCC_35 VCC_NCTF_2
VCC_NCTF_3 AK32
VCC_NCTF_4 AJ32
+V1.05S C76 AH32
VCC_NCTF_5
24mA~26mA +V1.05S C0805
VCC_NCTF_6 AG32
R157 R0603 0
C104 C102 C100 C96
AP28
AN28
VCCA_SM_CK_1
B22
321.35mA C59 C58 R105R0603 0
10UF/6.3V,X5R
VCC_NCTF_7 AE32
AC32
C0805C0603 C0603 C0402 VCCA_SM_CK_2 VCC_AXF_1 C0402 C0805 VCC_NCTF_8
AP25 B21 AA32
AXF
ns ns VCCA_SM_CK_3 VCC_AXF_2 VCC_NCTF_9
AN25 VCCA_SM_CK_4 VCC_AXF_3 A21 VCC_NCTF_10 Y32
1uF/10V,X7R 0.1UF/10V,X7R AN24 0.1UF/10V,X7R10UF/6.3V,X5R W32
10UF/6.3V,X5R 1uF/10V,X7R VCCA_SM_CK_5 VCC_NCTF_11
AM28 VCCA_SM_CK_NCTF_1 VCC_NCTF_12 U32
+V1.05S +V3.3S AM26 +V1.8 AM30
A CK
VCCA_SM_CK_NCTF_2 VCC_NCTF_13
AM25 VCCA_SM_CK_NCTF_3 119.85mA~124mA VCC_NCTF_14 AL30
D7 AL25 BF21 FB28 1 2 FB0805 AK30
R87 10 VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 C357 VCC_NCTF_15
1 2 AM24 BH20 AH30
SM CK
R0402 VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 C0402 C361 R420 R0603 300ohm@100MHz,1.5A VCC_NCTF_16

AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20 VCC_NCTF_17 AG30
1N4148WS AM23 BF20 10UF/6.3V,X5R
1 C363 AF30
SOD323 VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 0.1UF/10V,X7R C0805 10UF/6.3V,X5R +V1.8 VCC_NCTF_18
AL23 VCCA_SM_CK_NCTF_8 VCC_NCTF_19 AE30
C0805 AC30
+V3.3S C509 VCC_NCTF_20
VCC_NCTF_21 AB30
0.022uF/16V,X7R 79mA VCC_TX_LVDS K47 +V_TXLVDS R650 0 R0603
VCC_NCTF_22 AA30
FB34 R0603 0 C0402 B24
A24
VCCA_TV_DAC_1 105.3mA
C35
+V3.3S
C510 VCC_NCTF_23 Y30
W30
VCCA_TV_DAC_2 VCC_HV_1 VCC_NCTF_24
TV
VCC NCTF
B35 10UF/6.3V,X5R V30
VCC_HV_2 C55 C0805 VCC_NCTF_25
A35 U30
HV
VCC_HV_3 C0402 +VCC_PEG +V1.05S VCC_NCTF_26

VCC_NCTF_27 AL29
+V1.5S R365 0 R0402 VCC_HDA A32 0.1UF/10V,X7R AK29
VCC_HDA VCC_NCTF_28
35mA 1782mA
HDA
VCC_PEG_1 V48 +VCC_PEG R379 0 R0805

VCC_NCTF_29 AJ29
FB9 R0603 0 No HDMI OPTION U48 AH29
C56 C57 C53 changed VCC_PEG_2 C312 C314 C302 VCC_NCTF_30
V47 AG29
PEG
C0402 C0402 C0603 0805089 hads VCC_PEG_3 C0603 10UF/6.3V,X5R C0805 VCC_NCTF_31
VCC_PEG_4 U47 VCC_NCTF_32 AE29
D TV/CRT
M25 U46 1uF/10V,X7R C0805 10uF/6.3V,X5R +V1.05S AC29

0.1UF/10V,X7R VCCD_TVDAC VCC_PEG_5 VCC_NCTF_33
B VCC_NCTF_34 AA29 B
0.022uF/16V,X7R 1uF/10V,X7R +V1.05S +V1.5S_QDACL28
VCCD_QDAC
AH48
456mA(Only in 1.25V) R399 0 R0805 VCC_NCTF_35 Y29
W29
157.2mA AF1
VCC_DMI_1
AF48 C327 C334 VCC_NCTF_36
V29
VCCD_HPLL VCC_DMI_2 VCC_NCTF_37
1
+V1.5S C73
50mA AH47 C0603 CT7343_19 AL28
DMI
+V1.05S_PEGPLL VCC_DMI_3 VCC_NCTF_38

C0402 AA47 AG47 + CT4 AK28
1
VCCD_PEG_PLL VCC_DMI_4 VCC_NCTF_39
R651 50mA 500uA 0.1UF/10V,X7R
1uF/10V,X7R ns C0805
220UF/2.5V,POSCAP 10uF/6.3V,X5R VCC_NCTF_40 AL26
AK26
2
+V1.5S_QDAC VCC_NCTF_41
M38 VCCD_LVDS_1 VCC_NCTF_42 AK25
LVDS
L37 VCCD_LVDS_2 VTTLF1 A8 VCC_NCTF_43 AK24

R0402 VCC_HDA FB35 L1 AK23
VTTLF2 VCC_NCTF_44
60.31mA
VTTLF
C483 C484 R0603 AB2

0 HDMI 0 C511 VTTLF3
0.1UF/10V,X7R 0.01uF/16V,Y5V 1uF/10V,X7R C313 C310 C287
C0402 C0402 C0603
ns CANTIGA_1p2 C0603 0.47UF/25V,Y5V C0603
+V1.8 0.47UF/25V,Y5V C0603 0.47UF/25V,Y5V
CANTIGA_1p2
+V1.05S
FB22 R0603 0
24mA+V1.05S_HPLL DG:The usage of Ferrite bead is under
C319 investigation. A stuffing option should be +V1.05S
L3 L1008 provided in case
1
the investigation results suggests the need of
82nH ns a Ferrite bead. The CRB schematics currently
C318 0.1UF/10V,X7R
10UF/6.3V,X5R uses a Zero-Ohm resistor in place of the FB36 R0603 0
24mA+V1.05S_DPLLA
C0805 Ferrite bead.
C513
139.2mA C512
10UF/6.3V,X5R
0.1UF/10V,X7R
A FB24 1 2 FB0603 +V1.05S_MPLL C0805 A

120ohm@100MHz,500mA C328
CHANGED
R400 R0603 0
0.1UF/10V,X7R
139.2mA
FB37 0 R0603 +V1.05S_DPLLB TOPSTAR TECHNOLOGY
C325
10UF/6.3V,X5R C514 bent
C0805 R652 R0603 0 0.1UF/10V,X7R Page Name CANTIGA(POWER)
C515 C M46G
10UF/6.3V,X5R B
C0805 Date: Thursday, August 27, 2009 Sheet 14 of 51
5 4 3 2 1
5 4 3 2 1
+V3.3S
+V1.8
{6,7,10,12,14,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
{12,13,14,16,37,40,42}
DIM1
+V1.8 DDR2_SODIMM200
DDR200RVS_5D2
SO-DIMM 0
112
111
117
118
103
104
187
178
190
155
132
144
156
168
149
161
138
150
162
96
95
81
82
87
88
21
33
34
15
27
39
28
40
9
2
3
D D
{11,17} MA_A_A[13:0]
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
MA_DATA[63:0] {11}
MA_A_A0 102 5 MA_DATA0
MA_A_A1 A0 D0 MA_DATA1
101 A1 D1 7
99 A3 D3 19
97 A5 D5 6
92 A7 D7 16
MA_A_A8 93 23 MA_DATA8 +V1.8
91 A9 D9 25
MA_A_A11 A10/AP D10 MA_DATA11
90 A11 D11 37
1
MA_A_A12 89 20 MA_DATA12 C179
116 22 + ns C160 C168 C173 C174 C156 C162 C158
1
MA_A_A14 A13 D13 MA_DATA14 ns ns ns
{11,17} MA_A_A14 86 A14 D14 36
84 38 MA_DATA15 CT7343_19 C0402 C0805 C0805 C0402 C0805 C0402 C0805
2
A15 D15 MA_DATA16 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R 2.2UF/10V,X7R
{11,17} MA_A_BS#2 85 A16_BA2 D16 43
45 MA_DATA17 220UF/2.5V,POSCAP 2.2UF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V
D17 MA_DATA18
{11,17} MA_A_BS#0 107 BA0 D18 55
106 57 MA_DATA19
{11,17} MA_A_BS#1 BA1 D19 1, A minimum of 9 high frequency
44 MA_DATA20
D20 MA_DATA21 capacitors are recommended to be
{12,17} M_CS#0 110 CS0 D21 46
115 56 MA_DATA22 placed near each SO-DIMM of DDR2.
{12,17} M_CS#1 CS1 D22 MA_DATA23 +V1.8 2, 2.2μF*5 per DIMM,0.1μF*4 per
D23 58
MA_DM0 10 61 MA_DATA24 DIMM,330μF*1 per DIMM
MA_DM1 DQM0 D24 MA_DATA25
26 DQM1 D25 63
MA_DM2 52 73 MA_DATA26
MA_DM3 DQM2 D26 MA_DATA27
67 DQM3 D27 75
MA_DM4 130 62 MA_DATA28
MA_DM5 DQM4 D28 MA_DATA29 C157 C172 C164 C163 C159 C161
147 DQM5 D29 64
MA_DM6 170 74 MA_DATA30 ns
{11} MA_DM[7:0] MA_DM7 DQM6 D30 MA_DATA31 C0805 C0402 C0805 C0402 C0805 C0402
185 DQM7 D31 76
DDRII
123 MA_DATA32 2.2UF/10V,X7R 2.2UF/10V,X7R 2.2UF/10V,X7R
D32 MA_DATA33 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
{11,17} MA_A_WE# 109 WE D33 125
C 113 135 MA_DATA34 C
{11,17} MA_A_CAS# CAS D34
108 137 MA_DATA35
{11,17} MA_A_RAS# RAS D35
124 MA_DATA36
D36 MA_DATA37
79 126
{12,17} M_CKE0
{12,17} M_CKE1 80
CKE0
CKE1
D37
D38 134 MA_DATA38 Layout note:电容靠近DDR slot VDD PIN
136 MA_DATA39
D39 MA_DATA40
{12} M_CLK_DDR0 30 CK0 D40 141
32 143 MA_DATA41
{12} M_CLK_DDR#0 CK0 D41 MA_DATA42
{12} M_CLK_DDR1 164 CK1 D42 151
166 153 MA_DATA43
{12} M_CLK_DDR#1 CK1 D43 MA_DATA44
D44 140
114 142 MA_DATA45
{12,17} M_ODT0 ODT0 D45
119 152 MA_DATA46
{12,17} M_ODT1 ODT1 D46
154 MA_DATA47
MA_DQS0 D47 MA_DATA48
13 DQS0 D48 157
MA_DQS1 31 159 MA_DATA49
MA_DQS2 DQS1 D49 MA_DATA50
51 DQS2 D50 173
131 DQS4 D52 158
{11} MA_DQS[7:0] 169 DQS6 D54 174
DQS7 D55 MA_DATA56
D56 179
181 MA_DATA57
D57 MA_DATA58
{6,16,23,26,27,28} SMB_DATA_S 195 SDA D58 189
197 191 MA_DATA59
{6,16,23,26,27,28} SMB_CLK_S SCL D59 MA_DATA60
D60 180
R232 10K R0402 198 182 MA_DATA61
Note: R233 10K R0402 SA0 D61 MA_DATA62
+V3.3S SO-DIMM0 SPD Address is 0xA0
200 SA1 1010 000x D62 192
MA_DATA63
D63 194
SO-DIMM0 TS Address is 0x30
199 11 MA_DQS#0
VDDSPD DQS#0 MA_DQS#1
DQS#1 29
R226 0 1 49 MA_DQS#2
{12,16,37} SM_VREF_L VREF1 DQS#2
0.1UF/25V,Y5V C154 68 MA_DQS#3
C152 DQS#3 MA_DQS#4
DQS#4 129
C169 83 146 MA_DQS#5
C0402 2.2UF/10V,X7R C166 2.2UF/10V,X7R NC1 DQS#5 MA_DQS#6
B
120 NC2 DQS#6 167 B
C0805 0.1UF/25V,Y5V 50 186 MA_DQS#7
C0402 C0805 NC3 DQS#7
69 MA_DQS#[7:0] {11}
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC4
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
163 NCTEST
close to DDR pin
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
201
202
{12} DIM_EXTTS#0
A A
TOPSTAR TECHNOLOGY
bent
Page Name DDR2 SODIMM0
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3S
+V1.8
{6,7,10,12,14,15,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
{12,13,14,15,37,40,42}
DIM2
+V1.8 DDR2_SODIMM200,H9.2
DDR200RVS_9D2
112
111
117
118
103
104
187
178
190
155
132
144
156
168
149
161
138
150
162
96
95
81
82
87
88
21
33
34
15
27
39
28
40
9
2
3
{11,17} MB_B_A[13:0] SO-DIMM 1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
MB_DATA[63:0] {11}
D D
MB_B_A0 102 5 MB_DATA0
MB_B_A1 A0 D0 MB_DATA1
101 A1 D1 7
99 A3 D3 19
97 A5 D5 6
92 A7 D7 16
91 A9 D9 25
MB_B_A11 A10/AP D10 MB_DATA11 +V1.8
90 A11 D11 37
116 A13 D13 22
{11,17} MB_B_A14 MB_B_A14 86 36 MB_DATA14
A14 D14 MB_DATA15 C123 C211 C213 C218 C201 C203 C206 C215 C202
84 A15 D15 38
85 43 MB_DATA16 ns ns
{11,17} MB_B_BS#2 A16_BA2 D16
45 MB_DATA17 C0805 C0805 C0402 C0805 C0805 C0402 C0805 C0805 C0402
D17 MB_DATA18 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R
{11,17} MB_B_BS#0 107 BA0 D18 55
106 57 MB_DATA19 10UF/6.3V,X5R 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V
{11,17} MB_B_BS#1 BA1 D19
44 MB_DATA20
D20 MB_DATA21 +V1.8
{12,17} M_CS#2 110 CS0 D21 46
115 56 MB_DATA22
{12,17} M_CS#3 CS1 D22 MB_DATA23
D23 58
MB_DM0 10 61 MB_DATA24 C195 C194
MB_DM1 DQM0 D24 MB_DATA25 10uF/6.3V,X5R 10uF/6.3V,X5R
26 DQM1 D25 63
MB_DM2 52 73 MB_DATA26 C0805 C0805
MB_DM3 DQM2 D26 MB_DATA27 +V1.8
67 DQM3 D27 75
MB_DM4 130 62 MB_DATA28
MB_DM5 DQM4 D28 MB_DATA29
147 DQM5 D29 64
MB_DM6 170 74 MB_DATA30
{11} MB_DM[7:0] MB_DM7 DQM6 D30 MB_DATA31 C171 C205 C214 C204 C207 C199 C216 C212
185 DQM7 D31 76
DDRII
123 MB_DATA32 ns ns ns
D32 MB_DATA33 C0402 C0805 C0402 C0805 C0805 C0402 C0805 C0805
{11,17} MB_B_WE# 109 WE D33 125
113 135 MB_DATA34 0.1UF/25V,Y5V2.2UF/10V,X7R 2.2UF/10V,X7R 0.1UF/25V,Y5V 2.2UF/10V,X7R
{11,17} MB_B_CAS# CAS D34
108 137 MB_DATA35 0.1UF/25V,Y5V 2.2UF/10V,X7R 2.2UF/10V,X7R
{11,17} MB_B_RAS# RAS D35
124 MB_DATA36
D36 MB_DATA37 ns
C
{12,17} M_CKE2 79 CKE0 D37 126 C
80 134 MB_DATA38
{12,17} M_CKE3 CKE1 D38 MB_DATA39
136
{12} M_CLK_DDR2 30 CK0
D39
D40 141 MB_DATA40 Layout note:电容靠近DDR slot VDD PIN
32 143 MB_DATA41
{12} M_CLK_DDR#2 CK0 D41 MB_DATA42
{12} M_CLK_DDR3 164 CK1 D42 151
166 153 MB_DATA43
{12} M_CLK_DDR#3 CK1 D43 MB_DATA44
D44 140
114 142 MB_DATA45
{12,17} M_ODT2 ODT0 D45
119 152 MB_DATA46
{12,17} M_ODT3 ODT1 D46
154 MB_DATA47
MB_DQS0 D47 MB_DATA48
13 DQS0 D48 157
MB_DQS1 31 159 MB_DATA49
MB_DQS2 DQS1 D49 MB_DATA50
51 DQS2 D50 173
131 DQS4 D52 158
{11} MB_DQS[7:0] 169 DQS6 D54 174
DQS7 D55 MB_DATA56
D56 179
181 MB_DATA57
D57 MB_DATA58
{6,15,23,26,27,28} SMB_DATA_S 195 SDA D58 189
197 191 MB_DATA59
{6,15,23,26,27,28} SMB_CLK_S SCL D59 MB_DATA60
D60 180
R517 10K R0402 198 182 MB_DATA61
Note: R514 10K R0402 SA0 D61 MB_DATA62
+V3.3S SO-DIMM1 SPD Address is 0xA4
200 SA1 1010 010x D62 192
MB_DATA63
D63 194
SO-DIMM1 TS Address is 0x34
199 11 MB_DQS#0
VDDSPD DQS#0 MB_DQS#1
DQS#1 29
R241 0 1 49 MB_DQS#2
{12,15,37} SM_VREF_L VREF1 DQS#2
68 MB_DQS#3
C193 DQS#3 MB_DQS#4
DQS#4 129
C200 C191 83 146 MB_DQS#5
0.1UF/25V,Y5V C197 NC1 DQS#5 MB_DQS#6
120 NC2 DQS#6 167
C0402 2.2UF/10V,X7R 0.1UF/25V,Y5V 50 186 MB_DQS#7
C0805 C0402 2.2UF/10V,X7R NC3 DQS#7
69 MB_DQS#[7:0] {11}
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC4
GND0
GND1
C0805
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
B
163 NCTEST B
close to DDR pin1
close to DDR
pin199
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
201
202
{12} DIM_EXTTS#1
A A
TOPSTAR TECHNOLOGY
bent
Page Name DDR2 SODIMM1
C M46G
B
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +V0.9S {18,37,42}
D D
+V0.9S
+V0.9S
RN15 56x4 RA0402_8
1 2 MB_B_A9 RN23 56x4 RA0402_8
3 4 MB_B_BS#2 {11,16} 1 2 MB_B_RAS# {11,16}
5 6 MB_B_A12 3 4 MB_B_BS#1 {11,16}
7 8 5 6 MB_B_A0
M_CKE2 {12,16}
7 8 MB_B_A2
RN20 56x4 RA0402_8

1 2 MA_A_A10
3 4 MA_A_BS#0 {11,15}
5 6 MA_A_WE# {11,15}
7 8 MA_A_CAS# {11,15}
RN24 56x4 RA0402_8
1 2 MB_B_A4
3 4 MB_B_A6 RN14 56x4 RA0402_8
5 6 MB_B_A7 1 2 MA_A_A2
7 8 MB_B_A11 3 4 MA_A_A0
5 6 MA_A_BS#1 {11,15}
7 8 MA_A_RAS# {11,15}
RN18 56x4 RA0402_8
C C
1 2 MB_B_A8
3 4 MB_B_A5 RN13 56x4 RA0402_8
5 6 MB_B_A1 1 2 MA_A_A11
7 8 MB_B_A3 3 4 MA_A_A7
5 6 MA_A_A6
RN19 56x4 RA0402_8 7 8 MA_A_A4
1 2 MA_A_A8
3 4 MA_A_A5
5 6 MA_A_A3
7 8 MA_A_A1 R519 56 R0402 MB_B_A13
R238 56 R0402 MA_A_A13
R291 56 R0402
M_CKE3 {12,16}
RN21 56x4 RA0402_8
1 2 R450 56 R0402
M_CKE0 {12,15}
3 4 R237 56 R0402
MA_A_BS#2 {11,15} M_CKE1 {12,15}
5 6 MA_A_A12
7 8 MA_A_A9 RN22 1 2 56 M_CS#1 {12,15}
3 4 RA0402_4 M_ODT1 {12,15}
RN17 56x4 RA0402_8
1 2 MB_B_A10 RN25 1 2 56 M_ODT2 {12,16}
3 4 MB_B_BS#0 {11,16} 3 4 RA0402_4 M_CS#2 {12,16}
5 6 MB_B_WE# {11,16}
7 8 RN16 1 2 56
MB_B_CAS# {11,16} M_CS#3 {12,16}
B 3 4 RA0402_4 M_ODT3 {12,16} B
RN12 1 2 56 M_CS#0 {12,15}

3 4 RA0402_4 M_ODT0 {12,15}
+V0.9S
R236 56 R0402 MA_A_A14

{11,15} MA_A_A[13:0] MA_A_A14 {11,15}
R292 56 R0402 MB_B_A14
MB_B_A14 {11,16}
{11,16} MB_B_A[13:0]
TOPSTAR TECHNOLOGY
A bent A
Page Name DDR2 Series Termination
B M46G
B
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +V0.9S {17,37,42}
D D
Layout note:Place one cap close toevery 2 pullup resistors terminatedto +V0.9S
每4个电阻两个0.1UF电容
+V0.9S
C233 C386 C231 C184 C385 C183

0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V C387
C0402 C0402 C0402 C0402 C0402 C0402 0.1UF/25V,Y5V
C0402
C186 C187 C188 C185 C232 C391 C455

C 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V C
C0402 C0402 C0402 C0402 C0402 C0402 C0402
C454 C457 C388 C459 C456 C229 C230

0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0402 C0402 C0402 C0402 C0402 C0402 C0402
C389 C390 C227 C228 C458

0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0402 C0402 C0402 C0402 C0402
B B
TOPSTAR TECHNOLOGY
A bent A
Page Name DDR2 Decoupling
B M46G
B
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +VDC {28,32,34,36,37,38,41,42,44}
+V5AL {24,29,32,36,37,39,40,42}
+V3.3AL {12,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
+V3.3S {6,7,10,12,14,15,16,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
500mA
LCDCON
+V5S {20,21,23,24,25,30,31,32,33,38,41,42}
LCDCON2X20
CNS40_LCDB
41 41
LCDVDD 1 2
D 1 2 D
3 3 4 4
{10} LVDS_YAM0 5 5 6 6 LVDS_YAM1 {10}
{10} LVDS_YAP0 7 7 8 8 LVDS_YAP1 {10}
9 9 10 10
{10} LVDS_YAM2 11 11 12 12 LVDS_CLKAP {10}
{10} LVDS_YAP2 13 13 14 14 LVDS_CLKAM {10}
15 15 16 16
{10} LVDS_YBM0 17 18 LVDS_YBM1 {10}
PANEL INTERFACE
17 18
{10} LVDS_YBP0 19 19 20 20 LVDS_YBP1 {10}
21 21 22 22
{10} LVDS_YBM2 23 23 24 24 LVDS_CLKBP {10}
{10} LVDS_YBP2 25 25 26 26 LVDS_CLKBM {10}
EDID_CLK 27 28
EDID_DATA 27 28 EDID_PWR
29 29 30 30
+5VAL_Camera 31 32 LVDS_CAM_USB_PN4
BKLT_PWM 31 32 LVDS_CAM_USB_PP4
33 33 34 34
35 36 BKLT_ON
35 36
37 37 38 38
+VDC FB18 0 INVT_VDD
+V3.3S High : Enable R0805
39 39 40 40
42
42
Low : Disable
C245
R3371.5A T-Fuse
CLOSE TO INTCON ns R0603 0.1UF/25V,Y5V
R332
1K M46G VerB:change the LCDCON the same as VerA,down-lead two channels of LVDS signal from the GMCH
R329 0 D23 2 1 1N4148WS
{10} LVDS_BKLTEN
SOD323
R330 100K VerC:change the LCDCON the same as S46P--xiezx
D46 2 1 1N4148WS BKLT_ON
{32,33} LIDR# SOD323
D25 2 1 1N4148WS C241

{33} HW_OFF_BKLT# SOD323
1000pF/50V,X7R
D24 2 1 1N4148WS
{23,33} PM_SUS_STAT# SOD323 ns
C C
+V3.3S
Add AND Gate
BY bent 080218
R624
D44 2 1 1N4148WS 1K
{12,23,26,27,28,31,33,51} BUF_PLT_RST# SOD323 R11 R0402 0
D45 2 1 1N4148WS LCDVDD_ON R14 R0402 0

{10} LVDS_VDDEN
SOD323
CHK1
C485
1 2 LVDS_CAM_USB_PN4
R625 1000pF/50V,X7R {23} CAM_USB_PN7 LVDS_CAM_USB_PP4
{23} CAM_USB_PP7 4 3
100K
L4_0805 90ohm@100MHz,0.5A
D1 D2
1
R0402
ns EGA10603V05A1-B EGA10603V05A1-B
ESDPAD_R0603 ESDPAD_R0603
ns ns
2
R626 0 R0402 ns
+V5S
4
5
6
S
Q13
AO6409 VerA:Q45由6401改为6409 071027
D
G
R726
3
2
1
0
+V3.3AL +V3.3S
LCDVDD R0805
R3 0 R0603 ns
Q35 1.5A T-Fuse ns F1
FB1 0 R0805 500mA +V5AL AO3415 R0603
B B
SOT23
LCDVDD_EN#
R10 R5 C5 C3 C2 2 3 +5VAL_Camera
10K 100K 0.047uF/16V,X7R 10UF/6.3V,X5R R2 +VDC FB17
C6
ns ns 0.1UF/25V,Y5V C0805 100 R1 300ohm@100MHz,1.5A
0.01uF/16V,X7R R0603 2.2K FB0805 R569
C486
ns R570 C243 C244 10K
1
R6 10K 0.01uF/25V,X7R R0402
100K R0402 C0402 470pF/50V,X7R 10UF/6.3V,X5R
3
LCDVDD 的参数取值待定. PQ2 PQ1 R8 R571 1K ns C0402 C0805

3
Q14 2N7002 2N7002 100K R0402 ns
3
2N7002E-T1 SOT23 SOT23 ns
LCDVDD_ON R331 0 1 SOT23 ns Q36
LCDVDD_ON 2N7002
100pF/50V,NPO
1 1
{33} Camera_ON 1 SOT23
2
R333 C4 R7
SPWG Require LCDVDD rising time
2
100K 100K
2
R572
is 0.5-10ms,1-10ms is better 100K Using EC to enable camera Power
ns
R0402 By Johan 071224
ns
R335 0
{33} EC_BKLT_PWM +V3.3S +V3.3AL
BKLT_PWM
R336 0 ns R334 C242 R12 0 R0603 ns R681 0 EDID_CLK

{10} LVDS_BKLTCTL {10} L_DDC_CLK
A 10K R682 0 EDID_DATA A
100pF/50V,NPO {10} L_DDC_DATA
R13 0 R0603 EDID_PWR
C7 R683 0 ns
{23} PANEL_ID0
R684 0 ns TOPSTAR TECHNOLOGY
0.1UF/10V,X7R {23} PANEL_ID1
bent
Page Name
LVDS&Inverter CONN
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3S {6,7,10,12,14,15,16,19,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
+V5S {19,21,23,24,25,30,31,32,33,38,41,42}
CRT INTERFACE
try to delete these components
for cost down(need enhanced test)
Cross moat place
D Place close to VGA port
VerC: ns
+V5S Cross moat place
D
VGA CONNECTOR
+V5_VGA
IFB1
47ohm/100MHz,500mA ID1 IFB2
{10} MCH_RED 1FB0603 2 ROUT 1 2 1 2
GND_VGA
3
IC2 1N5819 120ohm/100MHz,500mA
IR1 ID2 SOD123 FB0603 IR2 CONNECTOR
150,1% 5.6pF/50V,NPO BAV99 IC3 100K TOP VIEW
150ohm电阻前走线阻抗50ohm IC1
SOT23 0.1UF/25V,Y5V VGA1
17
(From GPU to CONN) 5.6pF/50V,NPO VGADMF
2
GND_VGA GND_VGA 6 GND
IFB3 GND_VGA NV suggest:2pf 1 R NC
11
47ohm/100MHz,500mA GND_VGA+V5_VGA 7 GND
NV suggest:22pf 1FB0603 2 GOUT 2 G SDA
12 5VDDCDA
{10} MCH_GREEN
3
8 GND
3 B HSYNC 13 HSYNC
IR3 IC4 IC5 ID3 9 NC
150,1% BAV99 4 NC VSYNC 14 VSYNC
5.6pF/50V,NPO 5.6pF/50V,NPO SOT23 10 GND
GND CLK 5VDDCCK
5 15
2
shell
shell
GND_VGA GND_VGA+V5_VGA IC6 IC7 IC8 IC9
16
C10518-11505-L 15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO 15PF/50V,NPO
{10} MCH_BLUE 1 2 IFB4 FB0603 BOUT
47ohm/100MHz,500mA ns ns
3
IR4
IC11 ESD:
IC10
150,1% 5.6pF/50V,NPO ID4 NV suggest use +3.3V
5.6pF/50V,NPO BAV99 GND_VGA
Layout note:
C SOT23
1. +3.3V and GND Route >15mils trace width
S46/修改成跟M21一致的VGA Conn。LJ081223 GND_VGA
C
2
GND_VGA 2. No more than 75mils
GND_VGA+V5_VGA 3. ESD diode should no more than 10pf cap.
VerB:stuff ID2,ID3,ID4
+V5_VGA +V5_VGA
IC12 IC13
0.1UF/25V,Y5V 0.1UF/25V,Y5V
GND_VGA
GND_VGA GND_VGA +V5_VGA
+V3.3S
reserved ciucuit possibility to Cost down 1G125 follow design guide--0929 IR5 IR6
+V5_VGA +V5_VGA R724 Q37 2.2K 2.2K +V5_VGA
VerC: Del VR7 ID6
8.2K BSS138
2 R0402 SOT23 2
VSYNC 3 IC16 2 3 5VDDCDA 3

{10} CRT_DDC_DATA VerC: Change to bat54s
IC14 IC15 0.1UF/25V,Y5V
IU1 1 1
B 74AHCT1G125
SOT23_5
0.1UF/25V,Y5V 0.1UF/25V,Y5V ID5
+V3.3S
B
1
BAT54SPT GND_VGA +V3.3S BAT54SPT
1 OE# VCC 5
SOT23 SOT23 GND_VGA
{10} CRT_HSYNC 2 VerB:BAV99由DIODES改为PHILIPS的
A VerC: Change to bat54s for cost down
3 4 CRT_H_SYNC Near U5/U6 ASAP +V5_VGA071016
GND Y +V5_VGA R725 Q38
ID7 ID8
8.2K BSS138
IU2 IR7 39 HSYNC 2 R0402 SOT23 2
74AHCT1G125 IC17
SOT23_5 IR8 39 VSYNC HSYNC 3 0.1UF/25V,Y5V 2 3 5VDDCCK 3
{10} CRT_DDC_CLK
1 OE# VCC 5
1 1
{10} CRT_VSYNC 2 A +V3.3S
1
CRT_V_SYNC BAT54SPT GND_VGA BAT54SPT GND_VGA
3 GND Y 4
SOT23 SOT23
Demo has no voltage lever shifter
IH1 H18
IM1 IM3
HOLE HOLE
1 1 1 1
1
TH_315_118_P TH_315_118_P
A ns ns FMARKS
ns
FMARKS
ns A
TOPSTAR TECHNOLOGY
bent
IO_CASE_GND
Page Name CRT Interface
Custom M46G
A
5 4 3 2 1
5 4 3 2 1
+V5S +V5_HDMI
Cross moat place
D31 FB25
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
1 2 1 2120ohm@100MHz,500mA +V3.3S {6,7,10,12,14,15,16,19,20,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
+V3.3S +V3.3S +V3.3S +V5S {19,20,23,24,25,30,31,32,33,38,41,42}
1N5819HW-F FB0603
SOD123 HDMI C94 R152
HDMI 0.1UF/25V,Y5V 100K
R655 R656 C0402 R0402
4.7K ns 4.7K HDMI HDMI
R653 R654
4.7K 4.7K DDC_EN HDMI TMS_EN
ns
R657 R658
D Add for EMC issue D
0 0 GND_HDMI GND_HDMI
DDCBUF_EN
ns By Johan 071227
HDMI
CFG
GND GND R580HDMI R581 HDMI
HDMI 0 R0603 0 R0603
+V3.3S R582 R583
0 HDMI
R0603 0 R0603
HDMI
HDMI_CON
C516 C517 CHK7 GU10 AZ1045 ns
0.01uF/25V,X7R 0.01uF/25V,X7R OUT_D2+_ESD4 3 IFPC_TXD6P 1 10 IFPC_TXD6P 1
OUT_D2-_ESD1 IFPC_TXD6N LINE_1 NC4 D2+
2 CHK8 2 LINE_2 NC3 9 2 D2 SHTELD
ns GND_HDMI GC97 ns 3 8 IFPC_TXD6N 3
OUT_D1+_ESD IFPC_TXD5P VDD GND IFPC_TXD5P 4 D2-
100M0.33A 4 3 4 LINE_3 NC2 7 D1+
HDMI HDMI OUT_D1-_ESD 1 2 IFPC_TXD5N
0.1UF/25V,Y5V 5 6 5
GND l4_0805 ns LINE_4 NC1 IFPC_TXD5N 6 D1 SHTELD
CHK9 D1-
5VDDCDA_HDMI
5VDDCCK_HDMI
100M0.33A GU11 AZ1045 ns IFPC_TXD4P 7 20
OUT_D0+_ESD IFPC_TXD4P D0+ GND1
4 3 1 10 8 21
DDCBUF_EN
OUT_D0-_ESD l4_0805 IFPC_TXD4N LINE_1 NC4 IFPC_TXD4N 9 D0 SHTELD GND2

HDMIHP_C
1 2 CHK10 2 LINE_2 NC3 9 D0-

+V3.3S ns IFPC_TXC 10
GND_HDMI GC104 ns
DDC_EN
TMS_EN
3 VDD GND 8 CK+
CLK_D4+_ESD 100M0.33A 4 3 IFPC_TXC 4 7 11 22
LINE_3 NC2 CK SHTELD GND3
CFG
CLK_D4-_ESD 1 2 IFPC_TXC#
0.1UF/25V,Y5V 5 6 IFPC_TXC# 12 23
l4_0805 ns LINE_4 NC1 CK- GND4
13 CEC
C518 C519 100M0.33A 14
0.01uF/25V,X7R
0.01uF/25V,X7R 5VDDCCK_HDMI RESERVED
15
R585 l4_0805 SCL
G7
G6
G5
G4
HDMI R584 GND_HDMI 5VDDCDA_HDMI

36
35
34
33
32
31
30
29
28
27
26
25
16 SDA
colay common choke and res 0 R0603 0 R0603 17 GND_HDMI
U20 R586 R587 DCC/CEC_GND
18
HPD_SINK
SDA_SINK
SCL_SINK
g7
g6
GND7
FUNCTION4
FUNCTION3
VCC3V5
GND6
GND5
VCC3V4
DDC_EN
TMDS_EN
g5
g4
GND HDMI HDMI +V5_HDMI +5V

HDMI 0 R0603 0 R0603 HDMIHP_C 19
GND HP_DET
g1 G1 HDMI HDMI
gnd10 49
37 24 HDMI HDMI_D_1A
GND8 GND4 OUT_D2+_ESD C520 C521 620401900007
{10} IN_D2+ 38 IN_D1- OUT_D1- 23
39 22 OUT_D2-_ESD 0.01uF/25V,X7R 0.01uF/25V,X7R
{10} IN_D2- IN_D1+ OUT_D1+
40 21 GND_HDMI
VCC3V6 VCC3V3 OUT_D1+_ESD
{10} IN_D1+ 41 IN_D2- OUT_D2- 20
C 42 19 OUT_D1-_ESD C
{10} IN_D1- IN_D2+ OUT_D2+
43 18 HDMI HDMI
GND9 GND3 OUT_D0+_ESD
{10} IN_D0+ 44 IN_D3- OUT_D3- 17
45 16 OUT_D0-_ESD
{10} IN_D0- IN_D3+ OUT_D3+
ANALOG1(REXT)
46 VCC3V7 VCC3V2 15
HPD_SOURCE
CLK_D4+_ESD
SDA_SOURCE
SCL_SOURCE
{10} MCH_CLK_D4+ 47 IN_D4- OUT_D4- 14

CLK_D4-_ESD
FUNCTION1
FUNCTION2
{10} MCH_CLK_D4- 48 IN_D4+ OUT_D4+ 13

+V3.3S
ANALOG2
g2 G2
VCC3V1
G3
VCC3V
g3
GND1
GND2
gnd18
GND
1
2
3
4
5
6
7
8
9
10
11
12
G8
CH7318
GND
HDMI_DDC_DATA
HDMI_DDC_CLK
PC0
PC1
GND +V5_HDMI
+V5_HDMI
C522
HDMI 0.01uF/25V,X7R
+V3.3S GND R661
R660 2.2K
intel demo 499 and chro demo 1.2k by homy 1029 2.2K
HDMI
+V3.3S 5VDDCCK_HDMI
R659 5VDDCDA_HDMI
R890 HDMI
1.2K 499,1% HDMI
{10}
MCH_HDMI_HPD#
CH7318 PS8101
GND
GND
Colay 8101 and 7318 by xiezx
B B
+V3.3S +V3.3S
R662 R663
4.7K 4.7K R664 R665
ns PS8101 2.2K 2.2K
HDMI HDMI
+V5_HDMI
PC0
PC1
HDMI_DDC_DATA {12}
R666
HDMI_DDC_CLK {12} GC164
R0402 R0402
0.1UF/25V,Y5V
Colay 8101 and 7318 by xiezx C0402
HDMI 0
change 4.7k to 2.2k 080508 hads
HDMI
GND_HDMI
R896 GND
4.7K
CH7318
VerC:PC1 PD to GND for CH7318;PU for PS8101--XIEZX
GND_HDMI
A A
TOPSTAR TECHNOLOGY
GND_HDMI
bent
Page Name HDMI
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3S {6,7,10,12,14,15,16,19,20,21,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
ICH_EC_RTC {24}
EC_RTC {36}
+V1.05S {6,7,8,9,12,13,14,24,31,38,40,41,42,44}
+V1.5S_PCIE_ICH {23,24}
+V3.3AL {12,19,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
Note:The new SRTCRST# signal is used to reset the RTC registers used for the Intel +V1.5S {8,14,24,26,27,28,30,38,40,42}
Management Engine when the on-board battery is changed. The external capacitor and
the external resistor between SRTCRST# and VccRTC were selected to create an RC
time delay, such that RTCRST# will go high some time after the battery voltage is ICH_EC_RTC
valid. 332K 1% PULL
The RC time delay should be in the range of 18 ms to 25 ms. There must not be a HIGH TO
jumper for SRTCRST# pin. The SRTCRST# does not impact the implementation of CMOS C742
VBAT_RTC FOR
clearing. 32XCLK0 C0402 ICH8M INTRNAL
R269 VR ENABLE(PULL
Y7 15pF/50V,NPO 332K,1% LOW DISABLE)
R0402
1
D 32.768KHz D
Voltage Swing on RTCX1 pin
xd3_2X6
3
should not exceed 1.0V. ASSY ICH_INTVRMEN
EC_RTC
2
C743
ICH_EC_RTC 32XCLK1 C0402 R293
D22
15pF/50V,NPO 0
1 ns
VerB:chang the clk of 32.768 to dip R0402
3
2 C235 Y4
1uF/10V,X7R
C0603
BAT54C R523
CMOS Settings J1
Clear CMOS Short 2 1 10M
R309 R261 R0402
Keep CMOS Open 3 4
20K
1K
32XCLK0
32.768KHz
R0402
1
R268R0402 XS4_8038 +V3.3S
RTCBAT1 20K J9
CONN2_R C430 C223 JOPEN ns R891 0
U6A
3
CNS2_R R262 R0402 1uF/10V,X7R 1uF/10V,X7R

RESISTOR_1
C0603 C0603 ns R0402 32XCLK1
1 1 C23 K5
3
LPC_AD0 {28,31,33}
2
1M RTCX1 FWH0/LAD0 R239 R242
2 2 R0402 C24 RTCX2 FWH1/LAD1 K4 LPC_AD1 {28,31,33}
4
L6 10K 10K
FWH2/LAD2 LPC_AD2 {28,31,33}
RTC_RST# A25 K2 R0402 R0402 +V1.05S
LPC_AD3 {28,31,33}
4
RTCRST# FWH3/LAD3
RTC
LPC
SRTC_RST# F20 ns ns
SM_INTRUDER# SRTCRST#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# {28,31,33}
Delete RTCBat socket for ICH_INTVRMEN B22 J3
mechanical conflict INTVRMEN LDRQ0# R213 R454 R214
A22 LAN100_SLP LDRQ1#/GPIO23 J1
56 56 56
E25 N7 ns ns
If LAN interface is GLAN_CLK A20GATE H_A20GATE {33}
AJ27 R0402 R0402 R0402
not used, this signal A20M# H_A20M# {7}
SPONGE_RTC1 R282 0 R0402 ns C13
RTCBAT GLUE can be left as No LAN_RSTSYNC R0402
C
DPRSTP# AJ25 R208 0 H_DPRSTP# {7,12,41} C
Connect. F14 AE23 R444 0 R0402
LAN / GLAN
LAN_RXD0 DPSLP# H_DPSLP# {7}
+V1.5S_PCIE_ICH G13 LAN_RXD1 R207 56
D14 LAN_RXD2 FERR# AJ26 H_FERR# {7}
RTC_BAT1 R0402
+ C373
ns
5.6pF/50V,NPO C0402 R487
24.9,1%
D13
D12
LAN_TXD0 CPUPWRGD AD22 H_PWRGD {7}
Checklist:the series termination RES of
- {30} AZALIA_CODEC_BITCLK
R438 33 R0402 R0402 E13
LAN_TXD1
LAN_TXD2 IGNNE# AF25 H_IGNNE# {7} FERR#/IERR#/THERMTRIP are 56/56/55ohm。
CPU
RTCBAT with Cable
GPIO56 B10 AE22
GPIO56 INIT# H_INIT# {7}
根据机构 R200 33 R0402 B28
INTR AG25
L3
H_INTR {7}
+V1.05S
H_RCIN# {33}
定Cable尺寸 {30} AZALIA_CODEC_SYNC
B27
GLAN_COMPI
GLAN_COMPO
RCIN#
R215 R177 NEEDS BE PLACE
NMI AF23 H_NMI {7}
bitclk AF6 AF24 R435 0 R0402 56 WITHIN 2" OF ICH9, R173
HDA_BIT_CLK SMI# H_SMI# {7}
ACSYNC_D AH4 R0402 NEEDS BE PLACED WITHIN
HDA_SYNC
AH27 H_STPCLK# {7} 2" OF R177 WITHOUT STUB
R442 33 R0402 RST# STPCLK#
{30} AZALIA_CODEC_RST# AE7 HDA_RST#
AG26 R216 54.9,1%
THRMTRIP# PM_THRMTRIP# {7,12,31}
+V3.3AL AF4
{30} AZALIA_SDATAIN0 HDA_SDIN0
ns ICTP T137 AG4 AG27 T67 ICTP ns R0402
HDA_SDIN1 TP12
IHDA
{12} AZALIA_SDATAIN2 AH3 HDA_SDIN2
R275 ns ICTP T135 AE5 HDA_SDIN3
10K
SATA4RXN AH11 SATA4_RXN R192 1K R0402 ns
R0402 R189 33 R0402 AC_SDOUT AG5 AJ11 SATA4_RXP
{30} AZALIA_CODEC_SDOUT HDA_SDOUT SATA4RXP R191 1K R0402 ns
SATA4TXN AG12
HDA_DOCK_EN# AG7 AF12
HDA_DOCK_EN#/GPIO33 SATA4TXP
AE8 HDA_DOCK_RST#/GPIO34
GPIO56 ns ICTP T136 AH9 SATA5_RXN R194 1K R0402 ns No stuff for SATA function
SATA5RXN
{50} IDE_LED# AG8 SATALED# SATA5RXP AJ9 SATA5_RXP
AE10 R193 1K R0402 ns
+V1.5S +V3.3S SATA5TXN
{25} SATA_RXN0 AJ16 SATA0RXN SATA5TXP AF10
SATA HDD AH16
{25} SATA_RXP0
SATA
C0402 C369 SATA0RXP
{25} SATA_TXN0 AF17 SATA0TXN SATA_CLKN AH18 CLK_ICH_SATA# {6}
C0402 C370 AG17 AJ18
{25} SATA_TXP0 SATA0TXP SATA_CLKP CLK_ICH_SATA {6}
R685 R686 0.01uF/25V,X7R 0.01uF/25V,X7R
8.2K 8.2K del ns hads 080514 AH13 AJ7 R0402 24.9,1% R427
SATA ODD {25} SATA_RXN1 SATA1RXN SATARBIAS#
R0402 R0402 AJ13 AH7
B {25} SATA_RXP1 SATA1RXP SATARBIAS B
ns C0402 C134 AG14 within 500 mils of
{25} SATA_TXN1 SATA1TXN
C0402 C135 AF14 the ICH9-M
{25} SATA_TXP1 0.01uF/25V,X7R 0.01uF/25V,X7R SATA1TXP
HDA_DOCK_EN# ICH9M REV 1.0
1
Same distance to the ICH

HDCP Close the ICH as possible
JOPEN
R687 RESISTOR_1
1K ns
2
R0402
后盖打开就能看到。
ns +V1.05S +V1.05S
+V3.3S
+V3.3S
C731 C732
0.01uF/25V,X7R 0.01uF/25V,X7R
C0402 C0402
C526 C737
C523 5.6pF/50V,NPO 0.01uF/25V,X7R 0.01uF/25V,X7R
C0402 ns C0402 C0402
HDMIR0402
R667 33
bitclk
{12} AZALIA_HDMI_BITCLK
R668 R0402
HDMI ACSYNC_D
{12} AZALIA_HDMI_SYNC
R669
33
R0402
缝合电容 BIT_CLK
HDMI 33 RST#
{12} AZALIA_HDMI_RST#
R670<Designator>
A HDMI AC_SDOUT A
{12} AZALIA_HDMI_SDOUT
33 R0402
TOPSTAR TECHNOLOGY
bent
Page Name Title
C M46G
B
5 4 3 2 1
5 4 3 2 1
Close ICH9 as possible
+V3.3AL {12,19,22,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
+V1.5S_PCIE_ICH {22,24}
+V5S {19,20,21,24,25,30,31,32,33,38,41,42}
+V3.3S
U6D
U6B AC_SPKR R474 1K ns N29 V27
{51} PCIE_RXN1_ICH PERN1 DMI0RXN DMI_RXN0 {12}
D11 F1 PCI_REQ#0 PCI_FRAME# R265 8.2K N28 V26
AD0 REQ0# {51} PCIE_RXP1_ICH PERP1 DMI0RXP DMI_RXP0 {12}
PCI
Direct Media Interface

C8 G4 PCI_GNT#0 PCI_IRDY# R248 8.2K LAN IC C176 0.1UF/10V,X7R P27 U29
AD1 GNT0# {51} PCIE_TXN1_ICH PETN1 DMI0TXN DMI_TXN0 {12}
D9 B6 PCI_REQ#1 PCI_TRDY# R501 8.2K C178 0.1UF/10V,X7R P26 U28
AD2 REQ1#/GPIO50 {51} PCIE_TXP1_ICH PETP1 DMI0TXP DMI_TXP0 {12}
E12 A7 PCI_GNT#1 PCI_STOP# R256 8.2K
AD3 GNT1#/GPIO51 PCI_REQ#2 PCI_SERR# R485 8.2K
E9 AD4 REQ2#/GPIO52 F13 {28} PCIE_RXN2_ICH L29 PERN2 DMI1RXN Y27 DMI_RXN1 {12}
C9 F12 PCI_GNT#2 T145 ICTPns PCI_DEVSEL# R254 8.2K L28 Y26
AD5 GNT2#/GPIO53 Robson {28} PCIE_RXP2_ICH PERP2 DMI1RXP DMI_RXP1 {12}
E10 E6 PCI_REQ#3 PCI_PERR# R252 8.2K C175 0.1UF/10V,X7R 3G M27 W29
AD6 REQ3#/GPIO54 {28} PCIE_TXN2_ICH PETN2 DMI1TXN DMI_TXN1 {12}
B7 F6 PCI_GNT#3 T144 ICTPns PCI_LOCK# R251 8.2K C170 0.1UF/10V,X7R 3G M26 W28
AD7 GNT3#/GPIO55 {28} PCIE_TXP2_ICH PETP2 DMI1TXP DMI_TXP1 {12}
C7 PCI_REQ#0 R246 8.2K
D AD8 PCI_REQ#1 R257 8.2K D
C5 AD9 C/BE0# D8 {26} PCIE_RXN3_ICH J29 PERN3 DMI2RXN AB27 DMI_RXN2 {12}
G11 B4 PCI_REQ#2 R494 8.2K J28 AB26
AD10 C/BE1# {26} PCIE_RXP3_ICH PERP3 DMI_RXP2 {12}
PCI-Express
PCI_REQ#3 R267 8.2K EXPRESS Card C181 0.1UF/10V,X7R DMI2RXP
F8 AD11 C/BE2# D6 {26} PCIE_TXN3_ICH K27 PETN3 DMI2TXN AA29 DMI_TXN2 {12}
F11 A5 PCI_GNT#1 R266 8.2K ns +V3.3AL +V3.3S C182 0.1UF/10V,X7R K26 AA28
AD12 C/BE3# {26} PCIE_TXP3_ICH PETP3 DMI2TXP DMI_TXP2 {12}
E7 GPIO1 R184 10K
AD13 PCI_IRDY# INT_PIRQA# R498 8.2K
A3 AD14 IRDY# D3 {27} PCIE_RXN4_ICH G29 PERN4 DMI3RXN AD27 DMI_RXN3 {12}
D2 E3 T74 ICTPns INT_PIRQB# R247 8.2K Echo Peak G28 AD26
AD15 PAR {27} PCIE_RXP4_ICH PERP4 DMI3RXP DMI_RXP3 {12}
F10 R1 PCI_RST# INT_PIRQC# R486 8.2K R554 R553 C189 0.1UF/10V,X7R MiniCard H27 AC29
AD16 PCIRST# {27} PCIE_TXN4_ICH PETN4 DMI3TXN DMI_TXN3 {12}
D5 C6 PCI_DEVSEL# INT_PIRQD# R253 8.2K 0 C192 0.1UF/10V,X7R MiniCard H26 AC28
AD17 DEVSEL# {27} PCIE_TXP4_ICH PETP4 DMI3TXP DMI_TXP3 {12}
D10 E4 PCI_PERR# INT_PIRQE# R493 8.2K ns 0
AD18 PERR# PCI_LOCK# INT_PIRQF# R481 8.2K
B3 AD19 PLOCK# C2 R551 E29 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# {6}
F7 J4 PCI_SERR# INT_PIRQG# R245 8.2K ns E28 T25 +V1.5S_PCIE_ICH
AD20 SERR# PERP5 DMI_CLKP CLK_PCIE_ICH {6}
C3 A4 PCI_STOP# INT_PIRQH# R243 8.2K F27
AD21 STOP# PCI_TRDY# PM_CLKRUN# R479 8.2K 10K R0402 U16 PETN5 Place within 500
F3 AD22 TRDY# F5 F26 PETP5 DMI_ZCOMP AF29
F4 D7 PCI_FRAME# PCI_RST# R230 10K ns VDD 8 5 SI R529 15 AF28 DMI_IRCOMP_R R218 24.9,1% R0402 mils of ICH
AD23 FRAME# VDD SI SO R531 15 DMI_IRCOMP
C1 AD24 SO 2 C29 PERN6/GLAN_RXN
G7 C14 PLT_RST# GPIO6 R201 10K R530 3.3K WP# 3 1 CE# R552 15 C28 AC5
AD25 PLTRST# WP# CE# PERP6/GLAN_RXP USBP0N EXPCARD_USB_PN0 {26} EXPRESS Card
H7 D4 SV_SET_UP R429 10K 6 SCK R526 15 D27 AC4
AD26 PCICLK CLK_ICHPCI {6} SCK PETN6/GLAN_TXN USBP0P EXPCARD_USB_PP0 {26}
D1 R2 PCI_PME# R555 3.3K HOLD# 7 D26 AD3
AD27 PME# HOLD# PETP6/GLAN_TXP USBP1N T164 ns
G5 GPIO7 R183 10K 4 VSS AD2
AD28 VSS USBP1P T165 ns
H6 AD29 D23 SPI_CLK USBP2N AC1 USB_PN2 {32}
G1 PCI_GNT#0 R497 1K W25X40 ns D24 AC2 USB0 PORT
AD30 SPI_CS0# USBP2P USB_PP2 {32}
H3 SO8_50_150 ns T79
nsT79 F23 AA5
AD31 SPI_CS1#/GPIO58/CLGPIO6 USBP3N MINICARD_USB_PN3 {28} Robson
USBP3P AA4 MINICARD_USB_PP3 {28}
Interrupt I/F ns change to stuff
for boot from ICH
+V3.3AL D25 SPI_MOSI USBP4N AB2 MINICARD_USB_PN4 {27} Echo Peak
SPI
INT_PIRQA# J5 H4 INT_PIRQE# E23 AB3
PIRQA# PIRQE#/GPIO2 By Johan 071224 Co-lay with U28 U17 SPI_MISO USBP4P MINICARD_USB_PP4 {27}
INT_PIRQB# E1 K6 INT_PIRQF# +V3.3AL AA1
PIRQB# PIRQF#/GPIO3 USBP5N BT_USB_PN5 {31} BLUETOOTH
INT_PIRQC# J6 F2 INT_PIRQG# VDD 8 VCC 1 CE# R459 10K N4 AA2
PIRQC# PIRQG#/GPIO4 CS# OC0#/GPIO59 USBP5P BT_USB_PP5 {31}
INT_PIRQD# C4 G2 INT_PIRQH# PCI_PME# R231 10K HOLD# 7 HOLD# 2 SO N5 W5
PIRQD# PIRQH#/GPIO5 Q OC1#/GPIO40 USBP6N USB_PN6 {32}
ICH9M REV 1.0
SCK
SI
6 CLK
5 D
W# 3
4
WP#
VSS
{32} USB_OC#2 N6
P6
OC2#/GPIO41 USB
USBP6P W4
Y3
USB_PP6 {32}
USB1 PORT
PM_RI# R304 10K VSS Change OC connecttion OC3#/GPIO42 USBP7N CAM_USB_PN7 {19} CAMERA
M1 OC4#/GPIO43 USBP7P Y2 CAM_USB_PP7 {19}
S25FL008A By Johan071108 N2 W1
SMB_ALERT# R289 10K SOIC8_50_208 OC5#/GPIO29 USBP8N USB_CR_PN8 {29}
{32} USB_OC#6 M4 OC6#/GPIO30 USBP8P W2 USB_CR_PP8 {29}
M3 OC7#/GPIO31 USBP9N V2 USB_PN9 {32}
CL_RST#1 R303 10K ns +V3.3AL N3 V3 USB2 PORT
OC8#/GPIO44 USBP9P USB_PP9 {32}
N1 OC9#/GPIO45 USBP10N U5 T162 ns
C +V3.3S +V3.3AL SMLINK0 R272 10K R463 10K P5 U4 VerA:change the port sequence for the C
OC10#/GPIO46 USBP10P T163 ns convenience of layout
R460 10K P3 U1
OC11#/GPIO47 USBP11N T70 ns
SMLINK1 R271 10K U2
USBP11P T71 ns
ns AG2
GPIO13 R294 10K R211 300 R0603 USB_RBIAS_PN USBRBIAS
AG1 USBRBIAS#
R324 R326 Place within 500
0 0 LINKALERT# R305 10K mils of ICH ICH9M REV 1.0
ns R892 18.7,1% R0402
PM_SLP_S3# R273 10K
VerB:预留一个并联支路以调节偏置电阻大小,同时将R211改为20ohm，以改善眼图
PM_BATLOW# R505 8.2K
GNT0# SPI_CS1# Boot BIOS
C239 0 1 SPI +V3.3S
0.1UF/25V,Y5V 1 0 PCI Add for option(SATA interlock switch)
PM_SYSRST# R306 10K
1 1 LPC
5
R203R430R433R447
VCC 1 PLT_RST# SMB_CLK R307 2.2K 10K 10K 10K 10K
{12,19,26,27,28,31,33,51} BUF_PLT_RST# 4
2 SMB_DATA R515 2.2K ns ns ns ns
GND
U9 R279 PCIE_WAKE#_R R302 1K U6C
3
R328 74AHCT1G08GV 10K SMB_CLK G16 SMBCLK AH23 R205 10K

SOT23_5 GPIO26 R276 10K SMB_DATA SATA0GP/GPIO21 R431 10K
100K A13 SMBDATA SATA1GP/GPIO19 AF19
LINKALERT# E17 LINKALERT#/GPIO60/CLGPIO4 AE21 R434 10K
SATA
GPIO
SATA4GP/GPIO36
SMB
R507 10K ns PANEL_ID1 R512 10K SMLINK0 C17 SMLINK0 AD20 R452 10K
SMLINK1 SATA5GP/GPIO37
B18 SMLINK1
R278 10K ns PANEL_ID0 R277 10K H1
CLK14 CLK_ICH14 {6}
+V3.3S PM_RI# F19 AF3
Clocks
RI# CLK48 CLK_USB48 {6}
SLP_M# R290 10K
R4 P1 T72 ns
{19,33} PM_SUS_STAT# SUS_STAT#/LPCPD# SUSCLK
PM_SYSRST#
The Bus switch prevents GPIO12 R513 10K
G19 SYS_RESET#
C16
SLP_S3# PM_SLP_S3# {26,33,40}
Leakage of the SMBus into GPIO10 10K R510
{12} PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# {26,33,42}
R522 R310 GPIO14 10K R274 G17 T143 ns
devices powered on the 2.2K 2.2K SMB_ALERT# A17
SLP_S5#
EC_RUNTIME_SCI# R511 10K SMBALERT#/GPIO11 GPIO26
switched rail. Q29
EXTSMI# R270 10K R281 0 S4_STATE#/GPIO26 C10
{6} PM_STPPCI# A14 STP_PCI#
ns ns R489 0 PM_ICH_PWROK
SYS GPIO
B 2N7002E-T1 {6} PM_STPCPU# E19 STP_CPU# PWROK G20 PM_ICH_PWROK {12} B
SMB_DATA 3 2 SMB_DATA_S L4 M2 R234 100 PM_DPRSLPVR
SMB_DATA_S {6,15,16,26,27,28} {31} PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR {12,41}
+V3.3S
R316 0 PCIE_WAKE#_RE20 B13 PM_BATLOW#
Power MGT
{26,27,28,33,51} PCIE_WAKE# WAKE# BATLOW#
SMB_CLK SMB_CLK_S R432 10K MFG_MODE INT_SERIRQ M5
SMB_CLK_S {6,15,16,26,27,28} {31,33} INT_SERIRQ SERIRQ
Q12 R480 10K INT_SERIRQ PM_THRM# AJ23 R3 PM_PWRBTN# {33}
1
R204 8.2K PM_THRM# THRM# PWRBTN#

+V5S R199 10K
2N7002E-T1 BIOS_REC_R VR_PWRGD_CK410_INV D21 D20 R325 0 ns PLT_RST#
VRMPWRGD LAN_RST#
2
R327 0
3 2 J8 ns T75 ns A20 D22 R520 100
TP11 RSMRST# PM_RSMRST# {33,39,40}
JOPEN
R355 10K PM_RSMRST# RESISTOR_1 GPIO1 AG19 R5 R465 0
GPIO1 CK_PWRGD CLK_PWRGD {6}
+V5S GPIO6 AH21 C460
1
GPIO7 GPIO6 1000pF/25V,X7R

AG21 R6 PM_ICH_PWROK {12}
1
R235 100K ns PM_DPRSLPVR GPIO7 CLPWROK

{33} EXTSMI# A21 GPIO8
GPIO12 C12 B16 SLP_M# +V3.3S +V3.3S
GPIO13 GPIO12 SLP_M#
C21 GPIO13
SV_SET_UP AE18 F24
GPIO17 CL_CLK0 CL_CLK0 {12}
T73 ns ICH_GPIO18 K1 B19
GPIO18 CL_CLK1 CL_CLK1 {27}
+V3.3S +V3.3S T134 ns ICH_GPIO20 AF8 R284 R287
BIOS_REC_R GPIO20
AJ22 SCLOCK/GPIO22 CL_DATA0 F22 CL_DATA0 {12}
R280 10K ns PM_STPPCI# +V3.3AL PANEL_ID0 A9 C19
Controller Link
{19} PANEL_ID0 CL_DATA1 {27}
GPIO
PANEL_ID1 GPIO27 CL_DATA1 3.24K,1% 3.24K,1%
{19} PANEL_ID1 D19 GPIO28
R488 10K ns PM_STPCPU# L1 C25
{6} SATA_CLKREQ# SATACLKREQ#/GPIO35 CL_VREF0
C240 +V3.3AL R263 R441 10K AE19 A19
R202 10K SLOAD/GPIO38 CL_VREF1
10K AG22 SDATAOUT0/GPIO39
0.1UF/25V,Y5V Note:1.GPIO57 Can be used as TPM Physical ns MFG_MODE AF21 F21
U8 SDATAOUT1/GPIO48 CL_RST0# CL_RST#0 {12}
Presence pin for iTPM 2.The AH24 D18 CL_RST#1 C217 R258 R288
GPIO49 CL_RST1# CL_RST#1 {27}
5
74AHCT1G08GV PM_RSMRST# iTPM function of chipset is disabled A8 0.1UF/10V,X7R 453,1% C221 453,1%
VCC default GPIO57/CLGPIO5 0.1UF/10V,X7R
{33,40} Main_PWROK 1 SOT23_5 MEM_LED/GPIO24 A16 ICH_EXP_RST# {26}
3
4 PM_ICH_PWROK M7 C18 GPIO10

{30} AC_SPKR SPKR GPIO10/SUS_PWR_ACK
2 R366 100K 1 Q19 R264 AJ24 C11 GPIO14
{33,41} IMVP_PWRGD GND {12} MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
2N2222 100K T78 ns B21 C20
TP3 WOL_EN/GPIO9 EC_RUNTIME_SCI# {33}
SOT23 T63 ns
MISC
ns AH20
3
R312 ns +V3.3S T65 ns TP8

EC_PWROFF# {33} AJ20 TP9
10K T64 ns AJ21
R0402 R317 0 TP10
A ICH9M REV 1.0 A
+V3.3AL The signal is required to
be low for desktop
R322 0
R323 C236ns applications and high for
ns 20K mobile app.It has a weak TOPSTAR TECHNOLOGY
0.1UF/10V,X7R internal pull-up(20K)
5
R315 bent
10K 1 VCC Page Name Title
4 VR_PWRGD_CK410_INV
3
ns 2 Size Project Name Rev

Q11 GND C M46G
R321 C237 U7 B
3
1K 2N7002E-T1 74AHCT1G08GV Date: Tuesday, September 01, 2009 Sheet 23 of 51

{41} CK505_CLK_EN# 1
0.1UF/10V,X7R SOT23_5 PROPERTY NOTE: this document contains information confidential and property to
ns TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
2
5 4 3 2 1
5 4 3 2 1
+V5S {19,20,21,23,25,30,31,32,33,38,41,42}
+V5AL {19,29,32,36,37,39,40,42}
+V3.3AL {12,19,22,23,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
VerB nS CT8 C410 080510 hads +V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
ICH_EC_RTC
+V1.5S_PCIE_ICH {22,23}
Layout note:Distribute near +V1.05S
ICH_EC_RTC {22}
+V5S +V3.3S pin ICH9 Package edge 1634mA +V1.5S {8,14,22,26,27,28,30,38,40,42}
+V1.05S {6,7,8,9,12,13,14,22,31,38,40,41,42,44}
C224 C226 C424 C423 CT8 C410 C421 C414 C427
+V1.5AL {39}
1
C0603 CT11 ns C0805 C0805 C0805 C0805 C0805
R285 D21 Layout note: + CT7343_19
1
10 0.1uF needs be placed 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 10UF/6.3V,X5R10UF/6.3V,X5R 10UF/6.3V,X5R
1N4148WS
R0402
SOD323 within 100mils of 2mA U6F 1uF/10V,X7R 220UF/2.5V,POSCAP 10UF/6.3V,X5R 10UF/6.3V,X5R
2
A23 A15 U6E
ICH8M PIN A16
2
VCCRTC VCC1_05[1]
VCC1_05[2] B15 AA26 VSS[1] VSS[107] H5
+V3.3AL
2mA A6 V5REF VCC1_05[3] C15
D15 R223
+V1.5S AA27
AA3
VSS[2] VSS[108] J23
J26
+V5AL VCC1_05[4] FB16 1 VSS[3] VSS[109]
D C222 AE1 V5REF_SUS VCC1_05[5] E15 2 FB0603 R0603 1 AA6 VSS[4] VSS[110] J27 D
C219
VCC1_05[6] F15 23mA 120ohm@100MHz,500mA AB1 VSS[5] VSS[111] AC22
1
1uF/10V,X7R 0.1UF/10V,X7R AA24 L11 C167 Place within 100 AA23 K28
C0603 D17 VCC1_5_B[1] VCC1_05[7] C165 mils on the VSS[6] VSS[112]
AA25 VCC1_5_B[2] VCC1_05[8] L12 AB28 VSS[7] VSS[113] K29
ns R224 AB24 L14 C0805 bottom or 140 mil AB29 L13
10 1N4148WS VCC1_5_B[3] VCC1_05[9] 0.01uF/16V,X7R on the top of ICH VSS[8] VSS[114]
SOD323 AB25 VCC1_5_B[4] VCC1_05[10] L16 AB4 VSS[9] VSS[115] L15
R0402 AC24 L17 +V1.05S AB5 L2
2
VCC1_5_B[5] VCC1_05[11] 10UF/6.3V,X5R VSS[10] VSS[116]
AC25 VCC1_5_B[6] VCC1_05[12] L18 AC17 VSS[11] VSS[117] L26
Layout note:
AD24
AD25
VCC1_5_B[7] VCC1_05[13] M11
M18
48mA The voltage of VCC_DMI
AC26
AC27
VSS[12] VSS[118] L27
L5
VCC1_5_B[8] VCC1_05[14] C405 CT7 change from 1.25V to VSS[13] VSS[119]
0.1uF needs be placed C149 AE25 VCC1_5_B[9] VCC1_05[15] P11 AC3 VSS[14] VSS[120] L7
C147 AE26 P18 C0805 1.05V AD1 M12
within 100mils of pin 1uF/10V,X7R VCC1_5_B[10] VCC1_05[16] VSS[15] VSS[121]
0.1UF/10V,X7R AE27 T11 AD10 M13
G4 of ICH8M C0603 VCC1_5_B[11] VCC1_05[17] VSS[16] VSS[122]
AE28 T18 10UF/6.3V,X5R AD12 M14
ns VCC1_5_B[12] VCC1_05[18] 0.01uF/16V,X7R VSS[17] VSS[123]
AE29 U11 AD13 M15
CORE
+V1.5S VCC1_5_B[13] VCC1_05[19] +V1.05S VSS[18] VSS[124]
F25 VCC1_5_B[14] VCC1_05[20] U18 AD14 VSS[19] VSS[125] M16
300 OHM@100MHz BEAD

G25
H24
VCC1_5_B[15] VCC1_05[21] V11
V12
2mA R4570 R0603
AD17
AD18
VSS[20] VSS[126] M17
M23
IN INTEL DEMO CIRCUIT +V1.5S_PCIE_ICH VCC1_5_B[16] VCC1_05[22] C402 C395 C408 VSS[21] VSS[127]
H25 VCC1_5_B[17] VCC1_05[23] V14 AD21 VSS[22] VSS[128] M28
FB31 0 R0805
646mA J24
J25
VCC1_5_B[18] VCC1_05[24] V16
V17
C0805 AD28
AD29
VSS[23] VSS[129] M29
N11
VCC1_5_B[19] VCC1_05[25] 0.1UF/10V,X7R 4.7UF/10V,Y5V VSS[24] VSS[130]
K24 VCC1_5_B[20] VCC1_05[26] V18 AD4 VSS[25] VSS[131] N12
C429 C376 CT9 CT10 C379 C416 C428 C426 K25 0.1UF/10V,X7R AD5 N13
C0805 C0805 C0805 C0805 C0603 VCC1_5_B[21] VSS[26] VSS[132]
L23 VCC1_5_B[22] VCCDMIPLL R29 AD6 VSS[27] VSS[133] N14
Place above cap L24 AD7 N15
10UF/6.3V,X5R 10UF/6.3V,X5R 0.22UF/10V,X7R 0.1UF/10V,X7R VCC1_5_B[23] VSS[28] VSS[134]
with 100milof ICH L25 W23 AD9 N16
10UF/6.3V,X5R 10UF/6.3V,X5R 0.1UF/10V,X7R 0.1UF/10V,X7R VCC1_5_B[24] VCC_DMI[1] VSS[29] VSS[135]
on the bottom or M24 Y23 AE12 N17
VCC1_5_B[25] VCC_DMI[2] VSS[30] VSS[136]
140 mil on the top M25 AE13 N18
VCC1_5_B[26] VSS[31] VSS[137]
near D28 T28 N23 VCC1_5_B[27] V_CPU_IO[1] AB23 AE14 VSS[32] VSS[138] N26
AD28 N24
N25
VCC1_5_B[28] V_CPU_IO[2] AC23 308mA +V3.3S
+V3.3S_1.5S_HDA
+V1.5S AE16
AE17
VSS[33] VSS[139] N27
P12
VCC1_5_B[29] Close to AF29 Close to AD2 R4430 R0603 VSS[34] VSS[140]
P24 VCC1_5_B[30] VCC3_3[1] AG29 AE2 VSS[35] VSS[141] P13
P25 VCC1_5_B[31] AE20 VSS[36] VSS[142] P14
VCCA3GP
R24 AJ6 C380 C374 C377 AE24 P15
VCC1_5_B[32] VCC3_3[2] VSS[37] VSS[143]
R25 VCC1_5_B[33] AE3 VSS[38] VSS[144] P16
R26 VCC1_5_B[34] VCC3_3[7] AC10 AE4 VSS[39] VSS[145] P17
R27 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R AE6 P2
Place within 100 VCC1_5_B[35] VSS[40] VSS[146]
T24 VCC1_5_B[36] VCC3_3[3] AD19 AE9 VSS[41] VSS[147] P23
C +V1.5S FB131 2 FB0603 mils on the T27 AF20 Place within 100 AF13 P28 C
VCCP_CORE
VCC1_5_B[37] VCC3_3[4] mils on the R672 0 VSS[42] VSS[148]
bottom or 140 mil T28 AG24 AF16 P29
VCC1_5_B[38] VCC3_3[5] bottom or 140 mil VSS[43] VSS[149]
120ohm@100MHz,500mA on the top of ICH 47mA T29
U24
VCC1_5_B[39] VCC3_3[6] AC20
on the top of ICH
AF18
AF22
VSS[44] VSS[150] P4
P7
1 VCC1_5_B[40] VSS[45] VSS[151]
L1 0.68uH/150mA ns U25 B9 R508 0 R0603 AH26 R11
VCC1_5_B[41] VCC3_3[8] VSS[46] VSS[152]
1
C384 C131 C132 C133 V24 F9 C438 C450 C435 AF26 R12
VCC1_5_B[42] VCC3_3[9] VSS[47] VSS[153]
+ CT7343_19 C0805 C0603 V25 G3 +V3.3S_1.5S_HDA AF27 R13
1
220UF/2.5V,POSCAP VCC1_5_B[43] VCC3_3[10] VSS[48] VSS[154]

U23 VCC1_5_B[44] VCC3_3[11] G6 AF5 VSS[49] VSS[155] R14
ns 10UF/6.3V,X5R 1uF/10V,X7R 0.1UF/10V,X7R W24 J2 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R +V3.3A_1.5A_HDA +V1.5AL AF7 R15
2
VCC1_5_B[45] VCC3_3[12] VSS[50] VSS[156]
PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AF9 VSS[51] VSS[157] R16
K23 VCC1_5_B[47] VCC3_3[14] K7 AG13 VSS[52] VSS[158] R17
Y24
Y25
VCC1_5_B[48]
AJ4
11mA +V3.3A_1.5A_HDA
C136 AG16
AG18
VSS[53] VSS[159] R18
R28
+V1.5S VCC1_5_B[49] VCCHDA 0.1UF/10V,X7R VSS[54] VSS[160]
AG20 VSS[55] VSS[161] T12
AJ19 VCCSATAPLL VCCSUSHDA AJ3 11mA AG23 VSS[56] VSS[162] T13
R436 0 R0805
1342mA AC16 AC8 TP_VCCSUS1_05_ICH1 T138 ns C145
AG3
AG6
VSS[57] VSS[163] T14
T15
C372 C378 VCC1_5_A[1] VCCSUS1_05[1] TP_VCCSUS1_05_ICH2 T142 ns VSS[58] VSS[164]
AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 AG9 VSS[59] VSS[165] T16
C0603 C0603 AD16 0.1UF/10V,X7R R671 0 AH12 T17
VCC1_5_A[3] VSS[60] VSS[166]
ARX
AE15 VCC1_5_A[4] VCCSUS1_5[1] AD8 AH14 VSS[61] VSS[167] T23

1uF/10V,X7R 1uF/10V,X7R AF15 AH17 B26
VCC1_5_A[5] TP_VCCSUS1_5_ICH +V3.3AL VSS[62] VSS[168]
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AH19 VSS[63] VSS[169] U12
AH15 VCC1_5_A[7] AH2 VSS[64] VSS[170] U13
AJ15 VCC1_5_A[8]
A18
212mA R4990 R0603
AH22
AH25
VSS[65] VSS[171] U14
U15
VCCPSUS
VCCSUS3_3[1] C436 C439 VSS[66] VSS[172]

AC11 VCC1_5_A[9] VCCSUS3_3[2] D16 AH28 VSS[67] VSS[173] U16
AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 AH5 VSS[68] VSS[174] U17
AE11 VCC1_5_A[11] VCCSUS3_3[4] E22 AH8 VSS[69] VSS[175] AD23
ATX
AF11 0.1UF/10V,X7R AJ12 U26

VCC1_5_A[12] 0.1UF/10V,X7R VSS[70] VSS[176]
AG10 VCC1_5_A[13] AJ14 VSS[71] VSS[177] U27
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 AJ17 VSS[72] VSS[178] U3
AH10 VCC1_5_A[15] AJ8 VSS[73] VSS[179] V1
+V1.5S AJ10 T1 R4580 R0603 B11 V13
VCC1_5_A[16] VCCSUS3_3[6] C407 C413 C415 VSS[74] VSS[180]
VCCSUS3_3[7] T2 B14 VSS[75] VSS[181] V15
AC9 T3 C0805 B17 V23
C398 C396 C365 C397 VCC1_5_A[17] VCCSUS3_3[8] VSS[76] VSS[182]
VCCSUS3_3[9] T4 B2 VSS[77] VSS[183] V28
C0603 C0603 AC18 T5 4.7UF/10V,Y5V 0.1UF/10V,X7R B20 V29
0.1UF/10V,X7R VCC1_5_A[18] VCCSUS3_3[10] VSS[78] VSS[184]
B
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 B23 VSS[79] VSS[185] V4 B
0.1UF/10V,X7R U6 0.1UF/10V,X7R B5 V5
VCCPUSB
1uF/10V,X7R 1uF/10V,X7R VCCSUS3_3[12] VSS[80] VSS[186]

AC21 VCC1_5_A[20] VCCSUS3_3[13] U7 B8 VSS[81] VSS[187] W26
VCCSUS3_3[14] V6 C26 VSS[82] VSS[188] W27
G10 V7 TP_VCCSUS1_5_ICH R688 0 +V3.3A_1.5A_HDA C27 W3
VCC1_5_A[21] VCCSUS3_3[15] VSS[83] VSS[189]
G9 VCC1_5_A[22] VCCSUS3_3[16] W6 E11 VSS[84] VSS[190] Y1
VCCSUS3_3[17] W7 ns E14 VSS[85] VSS[191] Y28
AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 E18 VSS[86] VSS[192] Y29
+V1.5S AC13 Y7 E2 Y4
VCC1_5_A[24] VCCSUS3_3[19] VSS[87] VSS[193]
AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 E21 VSS[88] VSS[194] Y5
R451 0 R0603
10mA(VccUSBPLL) AJ5 G22 TP_VCCCL1_05_ICH
E24
E5
VSS[89] VSS[195] AG28
AH6
C394 C393 VCCUSBPLL VCCCL1_05 VSS[90] VSS[196]
E8 VSS[91] VSS[197] AF2
AA7 VCC1_5_A[26] VCCCL1_5 G23 VCCCL1_5_INT_ICH F16 VSS[92] VSS[198] B25
USB CORE
AB6 +V3.3S C433 C432 C431 F28

0.1UF/10V,X7R VCC1_5_A[27] R509 0 R0603 C0603 C0603 VSS[93]
AB7 VCC1_5_A[28] VCCCL3_3[1] A24 F29 VSS[94] VSS_NCTF[1] A1
0.1UF/10V,X7R AC6 B24 G12 A2
VCC1_5_A[29] VCCCL3_3[2] C451 0.1UF/10V,X7R 1uF/10V,X7R 1uF/10V,X7R VSS[95] VSS_NCTF[2]
AC7 VCC1_5_A[30] G14 VSS[96] VSS_NCTF[3] A28
0.1UF/10V,X7R ns ns ns G18 A29
ns T76 TP_VCCLAN1.05_ICH_1 A10 ns VSS[97] VSS_NCTF[4]
VCCLAN1_05[1] G21 VSS[98] VSS_NCTF[5] AH1
+V3.3S ns T77 TP_VCCLAN1.05_ICH_2 A11 G24 AH29
VCCLAN1_05[2] VSS[99] VSS_NCTF[6]
R301 0 R0603
19mA A12
G26
G27
VSS[100] VSS_NCTF[7] AJ1
AJ2
C220 +V1.5S VCCLAN3_3[1] VSS[101] VSS_NCTF[8]
B12 VCCLAN3_3[2] G8 VSS[102] VSS_NCTF[9] AJ28
R249 0 R0603
23mA A27
H2
H23
VSS[103] VSS_NCTF[10] AJ29
B1
0.1UF/10V,X7R C210 VCCGLANPLL VSS[104] VSS_NCTF[11]
H28 VSS[105] VSS_NCTF[12] B29
GLAN POWER
D28 VCCGLAN1_5[1] H29 VSS[106]

+V1.5S D29 VCCGLAN1_5[2] ICH9M REV 1.0
E26 VCCGLAN1_5[3]
R250 0 R0603
80mA 0.1UF/10V,X7R E27 VCCGLAN1_5[4]
A26 VCCGLAN3_3
C198
ICH9M REV 1.0
+V3.3S 1uF/10V,X7R
C0603
A R283 0 R0603
ns 1mA A
TOPSTAR TECHNOLOGY
bent
Page Name ICH9M(3 of 3)
C M46G
B
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +V5S {19,20,21,23,24,30,31,32,33,38,41,42}
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,26,27,28,29,30,31,33,38,40,41,42,50,51}
D D
SATAHDD_B1 SATAHDD_B2
+V3.3S
FB20 0 R0805
V3.3_SATA
ns
CT2 4.7uF/10V,Y5V C250 C249
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V Screw 2*5mm Screw 2*5mm
ns ns ns
ASSY ASSY
+V5S
Average 1A,Peak 1.5A
FB19 0 R0805
V_HDD Close to connector as possible SATA_HDD1
the same distance to connector
{22} SATA_TXP0 2 TX
CT1 4.7uF/10V,Y5V C247 C246 0.01uF/25V,X7R 3 1
{22} SATA_TXN0 TX# GND0
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V C263 C0402 5 4
{22} SATA_RXN0 RX# GND1
V3.3_SATA C264 C0402 6 7
{22} SATA_RXP0 RX GND2
0.01uF/25V,X7R
8 VCC3_0 GND3 11
9 VCC3_1 GND4 12
V_HDD 10 13
VCC3_2 GND5
14 VCC5_0 GND6 17
15 VCC5_1
+V5S 16 19
VCC5_2 GND7
FB32 0 R0805 Average 1A,Peak 1.5A 18 REEVE
23
V_ODD GND23
20 VCC12_0 GND24 24
21 VCC12_1
CT12 4.7uF/10V,Y5V C452 C453 22
C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V VCC12_2
SATA_HDD CONN
SATA_D_50B
C C
SATA_CON1
S1 GND1
{22} SATA_TXP1 S2 A+
{22} SATA_TXN1 S3 A- GND6 14
S4 GND2
C467 0.01uF/25V,X7R S5
{22} SATA_RXN1 B-
C464 0.01uF/25V,X7R S6
{22} SATA_RXP1 B+
S7 GND3
V_ODD
VerB:del the screws of SATA_CON1
P1 DP
P2 +5V_1
P3 +5V_2
P4 MD GND7 15
B
P5 GND4 B
P6 GND5
SATA_ODD CONN
SATA_S_50G
VerB:change the footprint the same as S46P
A A
TOPSTAR TECHNOLOGY
bent
Page Name SATA HDD&ODD
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3S +V1.5S http://shop61976717.taobao.com

+V3.3S
+V1.5S
+V3.3AL
{6,7,10,12,14,15,16,19,20,21,22,23,24,25,27,28,29,30,31,33,38,40,41,42,50,51}
{8,14,22,24,27,28,30,38,40,42}
{12,19,22,23,24,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
EP_MYLAR1
U15
C434 C420 R5538
0.1uF/10V,X5R QFNS20_0D5_0D85G
0.1uF/10V,X5R 12
14
1.5Vin1 3.3Vout1 3
5
EXP_3.3V
PVC Change mylar type follow ME advised
1.5Vin2 3.3Vout2 By Johan 071228
2 15 EXP_AUX_3.3V ASSY
+V3.3AL 3.3Vin1 3.3Vauxout
D 4 3.3Vin2 D
11 EXP_1.5V
1.5Vout1
17 3.3Vauxin 1.5Vout2 13
EP_CON1
C425 PM_SLP_S3# 1 8 EXP_RST# Shield
STBY# PERST# ASSY
0.1uF/10V,X5RPM_SLP_S4# 20 10 EXP_CPPE# 621000000002
SHDN# CPPE#
SYS_RST# 6 9 CP_USB#
SYSRST# CPUSB#
16 NC GND2 G1
RCLKEN 18 G2
RCLKEN GND3
19 OC# GND1 7
R476 0 SYS_RST#
{12,19,23,27,28,31,33,51} BUF_PLT_RST#
add power sw
R484 0 ns
{23} ICH_EXP_RST#
EP_B1 EP_B2
PM_SLP_S3#
{23,33,40} PM_SLP_S3#
PM_SLP_S4# ASSY ASSY
{23,33,42} PM_SLP_S4#
Screw 2*5mm Screw 2*5mm
C C
+V3.3AL
R483
100K +V3.3AL
2
PM_SLP_S4# ns 1 D34 R482 0 ns

BAT54S +V3.3S1300mA MAX R255 R0805 ns 0 EXP_3.3V
SOT23 Q27 +V3.3AL 275mA MAX R244 R0805 ns 0 EXP_AUX_3.3V
J7 ns 2N7002E-T1-E3
3
SOT23 +V1.5S 650mA MAX R240 R0805 ns 0 EXP_1.5V

25 16 EXP_CARD_CLKREQ# 2 3
{23} PCIE_TXP3_ICH PETp0 CLKREQ# EXPCARD_CLKREQ# {6}
{23} PCIE_TXN3_ICH 24 PETn0

RESV1 6 ns change to power sw
{23} PCIE_RXP3_ICH 22
1
PERp0 EXP_3.3V RCLKEN
RESV2 5
{23} PCIE_RXN3_ICH 21 PERn0
B B
+3.3VS_2 15
19 C208
{6} CLK_PCIE_EXPCARD REFCLK+
14 C209 10UF/10V,Y5V
+3.3VS_1 C1206
{6} CLK_PCIE_EXPCARD# 18 REFCLK- 0.1uF/10V,X5R ns
EXP_CPPE# 17 26
CPPE# GND0 EXP_AUX_3.3V +V3.3AL
EXP_RST# 13 PERST#
+3.3VAUX 12
11 C190 C196
{23,27,28,33,51} PCIE_WAKE# WAKE# 10UF/10V,Y5V
8 0.1uF/10V,X5R C1206
{6,15,16,23,27,28} SMB_DATA_S SMB_DATA
23 ns
GND1 EXP_1.5V R471 R466 R470
{6,15,16,23,27,28} SMB_CLK_S 7 SMB_CLK 100K 100K 100K
R229 0 R0402 CP_USB# 4 10
L4_0805 CPUSB# +1.5V_1 ns
+1.5V_2 9
CHK3 2 1 3
{23} EXPCARD_USB_PP0 USB_D+
{23} EXPCARD_USB_PN0 3 4 GND2 20 C180
ns 2 CP_USB#
USB_D-
1
90ohm@100MHz,0.5A D19 D20 1 0.1uF/10V,X5R C177

R228 0 GND3 10UF/10V,Y5V EXP_CPPE#
R0402 27 C1206
GND4 ns EXP_CARD_CLKREQ#
28
2
EGA1-0603-V05 EGA1-0603-V05 GND5

G1
G2
ESDPAD_R0603 ESDPAD_R0603 Chang the CAP type from X7R to X5R

ns ns PECA00-000LBS4Z4N0
G1
G2
NEW_CARD3
A A
TOPSTAR TECHNOLOGY
bent
Page Name EXPRESS CARD
A3 M46G
B
5 4 3 2 1
5 4 3 2 1
H12
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,28,29,30,31,33,38,40,41,42,50,51}
+DATA3 2*6mm
+V1.5S {8,14,22,24,26,28,30,38,40,42}
+V3.3AL {12,19,22,23,24,26,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
-DATA3
+VDC {19,28,32,34,36,37,38,41,42,44}
MiniCard
1
D30 D29
ESDPAD_R0603 ESDPAD_R0603 +V3.3S +V3.3AL +V3.3AL
EGA1-0603-V05 EGA1-0603-V05
D D
2
ns ns +V3.3S +V3.3AL
R392 R393 R394 +V1.5S
0 0 0
R0603 R0603 R0603
ns MiniCard MiniCard
3V3PCIE1 R390 R397
10K 10K
ns ns
Keep USB2.0 Signal stub short 与mini PCI不同，此处为低有效
52
24
48
28
2
6
minicard_CLKREQ#
注意修改LED等处的电路
+3.3V0
+3.3V1
+3.3VAUX
+1.5V0
+1.5V1
+1.5V2
minicard_Wake#
R386 0 R0402 MiniCard

R387 0 R0402 MiniCard
CHK5 ns
3 4 -DATA3 36 46
{23} MINICARD_USB_PN4 USB_D- LED_WPAN# T88 ns
2 1 +DATA3 38 44
{23} MINICARD_USB_PP4 USB_D+ LED_WLAN# Wireless_LED# {50}
LED_WWAN# 42 T89 ns
L4_0805
C C
90ohm@100MHz,0.5A
PCIE mini Card

{6} CLK_PCIE_MINICARD# 11 REFCLK- PERST# 22 BUF_PLT_RST# {12,19,23,26,28,31,33,51}
13 1 minicard_Wake# R396 0 ns
{6} CLK_PCIE_MINICARD REFCLK+ WAKE# PCIE_WAKE# {23,26,28,33,51}
CLKREQ# 7 minicard_CLKREQ# Don't use minipcie clock
31
request function.
{23} PCIE_TXN4_ICH Delete in series 0ohm RES PETN0
33 32 R389 0 ns
{23} PCIE_TXP4_ICH By Johan 0711081231 PETP0 SMB_DATA SMB_DATA_S {6,15,16,23,26,28}
30 R388 0 ns
SMB_CLK SMB_CLK_S {6,15,16,23,26,28}
23 确定此处smbus的作用?
{23} PCIE_RXN4_ICH PERN0
{23} PCIE_RXP4_ICH 25 PERP0
5 R541 0 ns
CHANNEL_CLK CH_CLK {28,31}
3 R542 0 ns
CHANNEL_DATA CH_DATA {28,31}
ns T100
nsT100 17 RESERVED0
19 RESERVED1
+V3.3AL ns T99
nsT99
20 R395 0 MiniCard
RESERVED_DISABLE HW_RATIO_OFF# {33}
R403 0 MiniCard37
R404 0 RESERVED_PCIE0
39 RESERVED_PCIE1
MiniCard 41 16 ns
RESERVED_PCIE2 RESERVED_SIM0 T91
43 14 ns R383 R490
RESERVED_PCIE3 RESERVED_SIM1 T93
R405 0 ns 45 12 ns 10K 10K
{23} CL_CLK1 RESERVED_PCIE4 RESERVED_SIM2 T92
R406 0 ns 47 10 ns ns MINICARD
{23} CL_DATA1 RESERVED_PCIE5 RESERVED_SIM3 T94
B R407 0 ns 49 8 ns B
{23} CL_RST#1 RESERVED_PCIE6 RESERVED_SIM4 T90
51 RESERVED_PCIE7
+V3.3S +V3.3AL +V3.3AL
3V3PCIE1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
C528 C529 C298 C308 C301 C296

0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V
9
15
21
27
29
35
4
18
26
34
40
50
53
54
55
56
57
58
59
60
61
C0402 C0402 C0805 C0402 C0805 C0402

MPCIE1
MINIPCIE_L6
PCIE CARD MiniCard MiniCard MiniCard MiniCard MiniCard MiniCard
MiniCard
VerC: change the footprint of wifi,add some GND hole to the position hole--xiezx
+V1.5S
TOPSTAR TECHNOLOGY
A bent A
Page Name
PCIE MINI SLOT 1
C303 C304 C307 C306 C309 Size Project Name Rev
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V B M46G
C0805 B
MiniCard MiniCard MiniCard MiniCard MiniCard Date: Thursday, August 27, 2009 Sheet 27 of 51
5 4 3 2 1
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,29,30,31,33,38,40,41,42,50,51}
+V1.5S {8,14,22,24,26,27,30,38,40,42}
+V3.3AL {12,19,22,23,24,26,27,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
+VDC {19,32,34,36,37,38,41,42,44}
H17
3G
Hole+Dowel
+DATA8
注意3G卡功耗比较大 PCIE_NUT3
-DATA8 +V3.3S
+V3.3AL +V3.3AL
1 1
D36 D35 R500 Hole+Dowel
EGA10603V05A1-B EGA10603V05A1-B 0 R506 R504
ESDPAD_R0603 ESDPAD_R0603 R0603 0 0 TH_200_132_118
ns ns ns R0603 R0603 +V1.5S
1
2 2 3G 3G
ns
3V3PCIE
MPCIE2
MINIPCIE_DEBUG_R +V3.3S +V3.3AL
Keep USB2.0 Signal stub short
52
24
48
28
2
6
VerC: add a hole for position stud of 3G connector--xiezx
+3.3VAUX
+3.3V0
+3.3V1
+1.5V0
+1.5V1
+1.5V2
R495 0 3G
R496 0 3G
R540 R539
10K 10K
CHK6 ns ns
90ohm@100MHz,0.5A
L4_0805
3 4 -DATA8 36 46 T148 ns
{23} MINICARD_USB_PN3 USB_D- LED_WPAN# VerB:the SW1 controll the 3G_LED
2 1 +DATA8 38 44 T166 ns MiniPCIE_REQ#
{23} MINICARD_USB_PP3 USB_D+ LED_WLAN#
LED_WWAN# 42
ns T147 ns
{6} CLK_PCIE_3G# 11 REFCLK- PERST# 22 BUF_PLT_RST# {12,19,23,26,27,31,33,51}

13 1 WAKE# R538 0 ns WAKE#
PCIE mini Card

{6} CLK_PCIE_3G REFCLK+ WAKE# PCIE_WAKE# {23,26,27,33,51}
7 MiniPCIE_REQ#
CLKREQ#
{23} PCIE_TXN2_ICH 31 PETN0

33 32 R382 0 ns
{23} PCIE_TXP2_ICH PETP0 SMB_DATA SMB_DATA_S {6,15,16,23,26,27}
30 R381 0 ns
SMB_CLK SMB_CLK_S {6,15,16,23,26,27}
{23} PCIE_RXN2_ICH 23 PERN0

{23} PCIE_RXP2_ICH 25 PERP0
5 R537 0 ns
CHANNEL_CLK CH_CLK {27,31}
3 R543 0 ns
T150 CHANNEL_DATA CH_DATA {27,31}
ns ICTP 17
ns ICTP T146 RESERVED0
19 RESERVED1
+V3.3AL
20 R503 0 3G
RESERVED_DISABLE HW_RATIO_OFF_3G# {33}
R532 0 3G 37
R533 0 3G R0603 RESERVED_PCIE0
39 RESERVED_PCIE1
41 16 R693 3G 0 SIM_VPP
RESERVED_PCIE2 RESERVED_SIM0 SIM_REST R491 R492
R0603 43 RESERVED_PCIE3 RESERVED_SIM1 14
45 12 SIM_CLK 10K 10K
RESERVED_PCIE4 RESERVED_SIM2 SIM_DATA ns
47 RESERVED_PCIE5 RESERVED_SIM3 10
+VDC +V3.3S +V3.3AL 49 8 SIM_PWR 3G
RESERVED_PCIE6 RESERVED_SIM4
51 RESERVED_PCIE7
+V3.3S +V3.3AL
A1 +V3.3AL REFRESH_EN# A15 EC_DEBG_Enable {33}
A2 +V3.3S
A17 +VDC PWR_SW_VCC A18 PWR_SW_VCC2 {32,33,36}
PWRSW# A19
C271 SIM_PWR R694 8.2K SIM_DATA
0.1UF/25V,Y5V A3 A13 R0402
{12,19,23,26,27,31,33,51} BUF_PLT_RST# PCIRST# DEBG_URXD EC_DEBG_URXD {33}
1
3G A9 A14 D47 C535
{6} CLK_DEBUGPCI PCICLK DEBG_UTXD EC_DEBG_UTXD {33}
A12 ESDPAD_R0603 C533 C534 100pF/50V,NPO
{22,31,33} LPC_FRAME# LFRAME#
1
A20 EGA1-0603-V05 0.1UF/25V,Y5V 1uF/10V,X7R C0402
NC ns C0402 C0603 D48
{22,31,33} LPC_AD0 A5
2
LAD0 ns
{22,31,33} LPC_AD1 A6 LAD1 GND14 A4
{22,31,33} LPC_AD2 A8 A7
2
LAD2 GND15
A10 A11
GND10
GND11
GND12
GND13
{22,31,33} LPC_AD3 LAD3 GND16

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
A16
Hole
GND17
3G
9
15
21
27
29
35
4
18
26
34
40
50
53
54
55
PCIE
3V3PCIE SIMCARD
SIM_PWR C1
SIM_REST VCC1
C2 RESET HOLE0 G1
C437 C468 C530 C531 SIM_CLK C3 G2
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V CLK HOLE1
1
C0805 C0402 C0402 C0402 D49 C536 C5
0.1UF/25V,Y5V SIM_VPP GND
C6 VPP
1
C0402 C537 SIM_DATA C7
ns 3G 3G 3G ns D50 47pF/50V,NPO IO
1
+V3.3AL ns C0402 CD
ns D51 CD
2
ns SIMCARD
SIMCARD_3
2
R867 VerB:the SW1 controll the 3G_LED +V3.3AL R695 PCIE2
10K 56
R0402 R0402 Add SIM card
{33} 3G_OFF# Swain 081111
3G ns
3GVDD_ON R869 0 3G C445 C443

10UF/6.3V,X5R
C0805
0.1UF/25V,Y5V
C0402 VerC:change the SIMCARD the same as XO1--xiezx
ns SIM card periphery current
许沐锌 081222
4
3G 3G
4
3G_SW1
1 LSS-12M-V-B
1 1
3 SW_W_S7A
3
2 2 2
3
+V1.5S
6
Assy
6
VerC: connect the 3G_OFF# to EC to control the 3G_LED and the HW_RATIO_OFF for 3G--xiezx
C441 C447 C446 C442 C440
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0805 C0402 C0402 C0402 C0402
3G 3G 3G 3G 3G
TOPSTAR TECHNOLOGY
bent
Page Name Robson
C M46G
B
5 4 3 2 1
All of by-pass capacitors must be closed to IC

+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,30,31,33,38,40,41,42,50,51}
REG18V
+V3.3AL {12,19,22,23,24,26,27,28,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
D3.3V
D3.3V
+V5AL {19,24,32,36,37,39,40,42}
REG18V VDD18
REG3.3V D3.3V
REG3.3V
R733 R734 0 R0402 ns
IT1337E-48 PIN MUX
REG3.3V
D C588 30K R735 0 R0402 D
REG18V
DGND
DGND
0.1UF/25V,Y5V C589
C0402
R0402
C590 2.2uF/10V,X7R C591 PINs SM/xD SD/MMC MS
RST 4.7uF/10V,X5R C0805 0.1UF/25V,Y5V 05 SM_WPSW SD_CMD MS_BS
U30 C592 C0805 C0402
4.7uF/10V,X5R 06 SM_RD MS_INS
36
35
34
33
32
31
30
29
28
27
26
25
C0805
07 SM_RNB SD_CD
REG18Vout
REG33Vout
SM/SD/MS D7
SM/SD/MS D6
SM/SD/MS D5
VSS
REG33Vin
GPIO6
GPIO5
TC
GPIO1
GPIO4
REG3.3V R197 R0603 0 R196 R0603 0 +V3.3AL 08 SM_D0 SD_D0 MS_D0
R195 R0603 0 +V5AL 09 SM_D1 SD_D1 MS_D1
ns
M46G VerB:Change this power rail to +V3.3AL 11 SM_D2 SD_D2 MS_D2
followed latest IT1337E Demo,PWR_SW2
Reserve +V5AL
power rail 090703
37 GPIO7 REG5Vin 24 C593 18 SM_D3 SD_D3 MS_D3
Clk12M-out 38 23 2.2uF/10V,X7R C594
Clk12M_out GPIO0/LED
SM_CE 39 SM_CE/SD_WP SM/SD/MS D4 22 C0805 0.1UF/25V,Y5V PWR_SW2 22 SM_D4 SD_D4 MS_D4
SM_WP 40 21 RST C0402
SM_WP/SD_CLK/MS_CLK RST
DGND 41 VSS GPIO3 20 29 SM_D5 SD_D5 MS_D5
EE_SDA
42
43
SM_WR IT1337E-48 ClkSel 19
18
ClkSel
SM_D3
C595
1uF/10V,X7R 32 SM_D6 SD_D6 MS_D6
EE_SDA SM/SD/MS D3 PWR_SW2
EE_SCL 44 EE_CLK SD/MS/xD
SM_WP_SW/SD_CMD/MS_BS
SM_CD 17 C0603
D3.3V
D3.3V 45 AVDD33 SM_ALE 16 34 SM_D7 SD_D7 MS_D7
{23} USB_CR_PP8 46 DP PWR_SW 15
C {23} USB_CR_PN8 47 DM VDD33 14 D3.3V 39 SM_CE SD_WP C
DGND 48 13 DGND
AVSS VSS C596 40 SM_WP SD_CLK MS_CLK
0.1UF/25V,Y5V
SM_RNB/SD_CD
SM_RD/MS_INS
C0402 SM_WP R736 0 R0402 SD_CLK

SM/SD/MS D0
SM/SD/MS D1
SM/SD/MS D2
SM_CLE
Clk48M
XTALO
xD_CD
VDD18
XTALI
+V3.3S
IT1337E-48
1
2
3
4
5
6
7
8
9
10
11
12
QFPS48_0D5_1D6
CLK_CR_48M
SM_WPSW
SM_RNB
3IN1 CONN
SM_RD
SM_D0
SM_D1
SM_D2
VDD18
C733
XTALI
VDD18 0.01uF/25V,X7R
C0402
use 48Mhz crystal　 J13A PWR_SW2

SM_D2 2
ClkSel R737 0 SM_D3 DAT2_SD CARD_3V3
3 DAT3_SD VDD_SD 6
R0402 SM_WPSW 4 CMD_SD C598
SD_CLK 7 CLK_SD SD+MMC C597
0.1uF/10V,X7R
1uF/10V,X7R
C0603
B B
CLK_CR_48M {6} SM_D0 9 8
SM_D1 DAT0_SD VSS_SD2
10 DAT1_SD
SM_RNB 1 5
SM_CE CD_SD# VSS_SD1
11 WP_SD#
use 12Mhz crystal　
D3.3V 3IN1
PWR_SW2
R738 0 Clk12M-out Int-12MHz J13B
R0402 SD_CLK 14 13 CARD_3V3
CLK_MS VCC_MS
EEprom Setting C599
0.1UF/25V,Y5V XTALI SM_D3 15
U31 C0402 SM_RD 16
DAT3_MS MS
ns SM_D2 INS_MS C601
1 A0 VCC 8 17 DTA2_MS VSS_MS1 12
2 7 SM_D0 18 21 C600 1uF/10V,X7R
A1 WP EE_SCL VerB:cancel the obligating of 12Mhz crystal by xie SM_D1 DTA0_MS VSS_MS2 0.1uF/10V,X7RC0603
3 A2 SCL 6 19 DTA1_MS GND1 22
4 5 EE_SDA SM_WPSW 20 23
VSS SDA BS_MS GND2
S-24CS02AFJ-TB-G R740 R741 3IN1
SO8_50_150 0 0
ns R0402 R0402
ns
S0=P12=EEP_SDA
S1=P13=EEP_SCK
TOPSTAR TECHNOLOGY
A A
Robin
Page Name Cardreader(ITE1337)
Custom S46
A
5 4 3 2 1
5 4 3 2 1
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,31,33,38,40,41,42,50,51}
+V1.5S +V3.3S
+V5S {19,20,21,23,24,25,31,32,33,38,41,42}
VCC5CDC +V5S
FB30 +V1.5S {8,14,22,24,26,27,28,38,40,42} GND_AUD GND_AUD
600ohm@100MHz,1.5A GND_AUD GND_AUD
1 2FB0805
Change to cap for esd Solve audio curve cut issue
R426 C150 C381 By Johan 071228 By Johan 071224
C151 C146 C141 C382 C383
1
0 10UF/6.3V,X5R 10UF/6.3V,X5R D40 D41
R0402 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 0.1UF/25V,Y5V R0402 R0402 ESDPAD_R0603 ESDPAD_R0603
100pF/50V,NPO100pF/50V,NPO EGA1-0603-V05 EGA1-0603-V05
R190 R174 ns ns
2
U5 Cross moat place
25
38
1
9
LINE_OUT1
GND_AUD
VerA:Reserve +1.5S power rail for GM C371 4.7uF/10V,X5R SURR_OUT_L FB14
1 2300ohm@100MHz,1.5A 1 L
VDD1
VDD2
AVDD1
AVDD2
T69 C0805 FB0805 4
ICTP ns A_GPIO0 2 35 CT6 ns R424 75 R0402 SURR_OUT_L SURR_OUT_R FB10
1 2300ohm@100MHz,1.5A 2
GPIO0 FRONT-OUT-L R
+
T68 ct6032 100uF/10V FB0805 5
ICTP ns A_GPIO1 3 36 CT5 ns R421 75 R0402 SURR_OUT_R HP_DET 6
GPIO1 FRONT-OUT-R
+
ct6032 100uF/10V 3
1
D D
37 C366 4.7uF/10V,X5R D9 C116 C137 C120 7
LINE1-VREFO-R C0805 ESDPAD_R0603 0.1uF/10V,X7R 100pF/50V,NPO100pF/50V,NPO 8
C142 0.1UF/25V,Y5V EGA1-0603-V05 C0402 C0402
27 ns ns ns AZALIAJACK
2
VREF C144 C0805 change to ns for esd AUDIO8B
GND_AUD By Johan 071228
11 28 VREFOUT 10UF/6.3V,X5R
{22} AZALIA_CODEC_RST# REST# MIC1-VREFO-L R206 4.7K R0402 INT_MIC_L_R GND_AUD GND_AUD GND_AUD GND_AUD
{22} AZALIA_CODEC_BITCLK 6 BITCLK GND_AUD
{22} AZALIA_CODEC_SYNC 10 SYNC

LINE1-VREFO-L 29
Headphone Jack
5
MIC2-VREFO 30 MIC2_REF
INPUT:HEADPHONE/LINE-OUT
{22} AZALIA_CODEC_SDOUT SDOUT
LINE2-VREFO 31 OUTPUT:FRONT L/R
{22} AZALIA_SDATAIN0
R210 22 8 SDIN
32 R209 4.7K R0402 INT_MIC_L_R used for enhancing Audio
MIC1-VREFO-R
R222 51K R0402 C138 1uF/10V,X7R 12 33 R217 10K ns
ns
D16
1N4148WS
quality and ESD ability.
{33} BTL_BEEP PC-BEEP DCVOL VCC5CDC
C0603 MIC2_REF 1 2
JACK_DET_A 13 34 JACK_DET_B SOD323
JD1 JD2 D12
1N4148WS
{23} AC_SPKR
R219 75K R0402 C140 1uF/10V,X7R C143 14 LINE2-L
ALC662 CEN-OUT 43 1 2
C0603 SOD323 GND_AUD GND_AUD
100pF/50V,NPO 15 44
LINE2-R LFE-OUT Solve audio curve cut issue
R221 R220 MIC2_L R416 75 R0402 C367 4.7uF/10V,X5R C0805 16 45 By Johan 071224
MIC2-L SIDESURR-OUT-L
1
4.7K 4.7K R182 R212 D42 D43
MIC2_R R415 75 R0402 C364 4.7uF/10V,X5R C0805 17 46 4.7K 4.7K ESDPAD_R0603 ESDPAD_R0603
MIC2-R SIDESURR-OUT-R
All of JD resistors should be R0402 R0402 EGA1-0603-V05 EGA1-0603-V05
placed as close as possible to ICTPT131 ns 18 47 EAPD R453 0 R0402 SHUTDOWN# ns ns
2
CD-L SPDIFI/EAPD ns
the sense pin of codec. ICTPT132 ns 20 48
MIC_IN1
CD-R SPDIFO MIC2_L FB15
1 2300ohm@100MHz,1.5A 1 L
INT_MIC_L C129 1uF/10V,Y5V C0603 21 FB0805 4
MIC1-L AMP_OUT_L MIC2_R FB12
39 1 2300ohm@100MHz,1.5A 2
C128 1uF/10V,Y5V C0603 22
SURR-OUT-L FB0805 5 R
JACK_DET_B R440 5.11K,1% R0402 ns MIC1-R R445 20K,1% MIC1_JD
JDREF 40 GND_AUD 6
23 LINE1-L 3
C JACK_DET_A R188 5.11K,1% R0402 HP_DET 41 AMP_OUT_R 7 C
SURR-OUT-R
1
CD-GND
VerA:follow the DEMO design in MIC1&MIC2 071108 24 D14 C139 8
AGND1
AGND2
LINE1-R C148 C130
GND1
GND2
R187 20K,1% ns MIC1_JD ESDPAD_R0603
EGA1-0603-V05 100pF/50V,NPO
0.1uF/10V,X7R 100pF/50V,NPO AZALIAJACK
JACK_DET_B R573 20K,1% ns C0402 C0402 AUDIO8B
2
QFPS48_0D5_1D6 ALC662 ns ns
4
7
19
26
42
GND_AUD GND_AUD GND_AUD GND_AUD GND_AUD
connecr mic1_jd to senseB change to ns for esd
and reserved route to senseA
By Johan 071224
Stereo Microphone Jack By Johan 071228
INPUT:STEREO MIC-IN
T133GND_AUD
OUTPUT:CENT/LFE
ICTP MIC2_L
ns
MIC2_R
add cap for esd
By Johan 071228
INT_MIC_L_R C492 C493

100pF/50V,NPO 100pF/50V,NPO
C0402 C0402
INT_MIC_L R186
FB11 FB0805
+
1K 1 2 1
300ohm@100MHz,1.5A 2 GND_AUD GND_AUD
1
D13 C127
ESDPAD_R0603 MIC1
EGA1-0603-V05 100pF/50V,NPO Microphone
ns C0402 BZ_D6027
2
VCC5CDC VCC5CDC SURR_OUT_L SURR_OUT_R
ASSY GND_AUD GND_AUD
PQ38 PQ35
GAIN0 GAIN1 Av(inv) PQ36 PQ37
3
2N7002 2N7002 2N7002 2N7002
0 0 6dB R473 R477
SOT23 SOT23 SOT23 SOT23
B 10K 10K AMP_SHDW1 AMP_SHDW1 B
0 1 10dB GND_AUD 1 1
ns
1 0 15.6dB ns
INPUT:STEREO MIC-IN
2
GAIN0
GAIN1
1 1 21.6dB OUTPUT:CENT/LFE
R468 R478 onboard stereo
10K 10K
VerB:chang the gain to 10dB--090716
microphone VCC5CDC
GND_AUD GND_AUD U14 R475

VerB:chang the gain to 6dBand change r464,r462 to 10k--090729 TPA6017A2
sop20_0d65_4d4g
10K
AMP_OUT_R C0603 R464 10K 17 18 +INTSPR

C419 0.22uF/10V,X7R RIN- ROUT+ SHUTDOWN#
7 14 -INTSPR
RIN+ ROUT-
3
FB29 1 2FB0805 ns C406
300ohm@100MHz,1.5A 0.47uF/25V,Y5V R455 10K 9 4 +INTSPL Q25
GND_AUD LIN+ LOUT+ 2N7002
C0603
C401 0.22uF/10V,X7R 10 8 -INTSPL VCC5CDC 1
BYPASS LOUT- {33} AMP_SHDW
C375 0.1UF/25V,Y5V C0603 R469
ns AMP_OUT_L C0603 R462 10K 5 16 100K
2
C422 0.22uF/10V,X7R LIN- VDD R446
12 NC PVDD1 6
15 C418 10K
SHUTDOWN# PVDD2 0.1UF/10V,X7R SOT23
19 SHDWN# GND1 1
GND_AUD 11 C409 4.7uF/10V,Y5V
GAIN0 GND2 C417 C0805
2 GAIN0 GND3 13
20 0.1UF/10V,X7R
GAIN1 GND4 GND
3 GAIN1 GND5 21 GND_AUD
GND_AUD
IO_INTSPK1
A GND_AUD GND CNS4_V A
5 1 +INTSPR
5 1 -INTSPR
2 2
3 +INTSPL
3 -INTSPL
6 6 4 4
TOPSTAR TECHNOLOGY
bent
Page Name AZALIA(ALC883)
C M46G
B
GND_AUD PROPERTY NOTE: this document contains information confidential and property to
5 4 3 2 1
5 4 3 2 1
FAN Controller Circuit

R893ns
BT
+V5S +V3.3S 0
+V1.05S {6,7,8,9,12,13,14,22,24,38,40,41,42,44}
Q10
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,33,38,40,41,42,50,51}
AO3415 +V5S {19,20,21,23,24,25,30,32,33,38,41,42}
+V3.3AL {12,19,22,23,24,26,27,28,29,32,33,34,35,36,37,38,39,40,41,42,50,51}
R318 BT 0 R0805 2 3 R320 0
BT
+V1.5S {8,14,22,24,26,27,28,30,38,40,42}
R319 ns 0 R0805 BT
C225 BT C238 R297 BT 0 R0402
+V1.5AL {24,39}
1000pF/50V,X7R TPCON_USB R298 BT 0 R0402
1
BT CNS10_0D8_R 0.1UF/10V,X7R H16
R296 H13
100K 1
BT 1 CHK4 90ohm@100MHz,0.5A L4_0805
2 2
D
11 11 3 3 2 1 BT_USB_PP5 {23} D
4 4 3 4 BT_USB_PN5 {23}
12 5 ns Hole+Dowel
R286 0 ns BT_ON# R295 BT 1K 12 5
6 6
7 R314 0 ns Hole+Dowel TH_200_132_118
7 CH_CLK {27,28}
8 R313 0 ns TH_230_132_118_6 +V5S +V3.3AL +V3.3S
CH_DATA {27,28}
1
8 R300 0 ns
9 CH_CLK {27,28}
1
2
3
4
5
6
7
9
10 10
3
Q9 R299 ns 0 BT_ON# R107 R357

2N7002E-T1-E3 BT_CON Billiton和CCOM的要求不一样 R359 10K 10K
R260 BT 1K 1 SOT23 M46 VERB:CHANGE BT_CON THE SAME AS X01--XIEZX R894 BT_PWRON VerB:H14闲置不用，删除 xie 10K ns
{33} BT_PWRON
BT C234 100K
ns
FAN_BACK {33}
2
R259 0.22uF/10V,X7R
BT
100K +V3.3S For FAN&Heatsink use
3
BT
R351 1K FAN_TACH_ON 1 Q17
R308 ns 10K CH_CLK R897 2N2222 R352
ns C284 ns SOT23
BT_ON {33}
2
R311 ns 10K CH_DATA 0 ns 0
+V5S 1000pF/50V,X7R
ns
Q5
BCP69-16 Vfan
CPUFAN1
SOT223 4
3 2 1 1 4 4
2 2
1
C276 3 5
R35 D26 C275 3 5
1
1K R24 0.1UF/25V,Y5V 10uF/10V,Y5V CONN3_V
2
1N4148WS
1
TCM 10
R0402 R346 SOD323
C1206 CNS3_V
FAN_FB
1
+V3.3S VCC_358 5.11K,1%
1
C30
2
+V3.3S U36 R36 U1A
C 1K 0.1UF/25V,Y5V LM358 C
8
22 10 R885 0 so8_50_150 Shut-Down
{22,28,33} LPC_FRAME# LFRAME# VDD1
16 19 R0805 TCM 3 +V3.3S
{12,19,23,26,27,28,33,51} BUF_PLT_RST# +
2
LRESET# VDD2
{6} CLK_TCMPCI 21 LCLK VDD3 24 1
1
26 C738 C739 C740 2 Throttling/
{22,28,33} LPC_AD0 LAD0 -
23 4 0.1UF/25V,Y5V 0.1UF/25V,Y5V R349 Un-throttling
{22,28,33} LPC_AD1 LAD1 GND1
R886 R887 20 11 10uF/6.3V,X5R TCM TCM R22
{22,28,33} LPC_AD2
4
10K 10K LAD2 GND2 TCM C26 10K,1%
{22,28,33} LPC_AD3 17 LAD3 GND3 18 4.7K
ns TCM 27 25 R0402
{23,33} INT_SERIRQ
2
SERIRQ GND4 0.1UF/25V,Y5V
{23} PM_CLKRUN# 15 CLKRUN#
LPCPD# 28 1 R26 R25
LPCPD# NC High-5V
LPCPD# 2 1 100K 2
NC1 FAN1_V {33}
5 200K R0402
LPCPP NC2
9 BA0 NC3 6 Middle-4V
3 BA1 NC4 8
NC5 12
LPCPP 7 13 Low-3V
PP NC6
C28
R888 R889 C32
10K 10K
14 NC-P FAN1_V=3.30V,Vfan=5V 4.7UF/10V,Y5V 0.1uF/25V,Y5V
TCM TCM C0805 C0402
TCM
FAN1_V=2.65V,Vfan=4V 50 55 60 65 70 75 80 85 90 95 100
C741
1uF/10V,X7R
SOP28_0D65_6D1
VerB：add the TCM function FAN1_V=1.98V,Vfan=3V
C0603
TCM
+V3.3S
+V1.05S
R547
B B
10K R548
4.7K
VerA:Add RC circuit 071106 R0402
ns
SHDN_LOCK#
3
R550
R560 10K 5 2 R546 100
{7} OVT_SHUTDOWN#
Q32 VerB:Add R618,LJ070712 4.7K R0402
C479 MMDT3904 ns ns SHDN_LOCK#
SHDN_LOCK# {40}
4
R559 1000pF/50V,X7R SC70_6

100K
3
R549ns
{7,12,22} PM_THRMTRIP# 5 2 R556 1K
3
Q30 R0402
Q31 MMDT3904 C471
4
470 R545 C470 SC70_6

2N7002E-T1 100K ns 2.2uF/10V,X7R
{33} ALT_ON 1
ns 0.1UF/25V,Y5V C0805
Use for temperature alarm driver. ns ns
2
R561
100K
ns
OVP CIRCUIT
ns hads 080514
A VerA:Delete GMCH_TEMP signal and components 071026 A
Shut Down PCB1 PCBA1

VIN
CPU R20 MB R20 PCBA
8VCC_358
TOPSTAR TECHNOLOGY
Throttling on
THRMTRIP# SHDN#
PCB PCBA U1B bent
AND LM358 Page Name
CPU Temperature MDC&BT/FAN/OTP
THERM_ALERT# so8_50_150
Throttling Off 5 Size
+ Project Name Rev
VDC 0 85 90 95 100 7 C M46G
Thermal (Degree) B
6 -
sensor Date: Tuesday, September 01, 2009 Sheet 31 of 51
4

5 4 3 2 1
5 4 3 2 1
USB Board CONN http://shop61976717.taobao.com
+V3.3S
+V5S
+V3.3AL
+V5AL
{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
{19,20,21,23,24,25,30,31,33,38,41,42}
{12,19,22,23,24,26,27,28,29,31,33,34,35,36,37,38,39,40,41,42,50,51}
{19,24,29,36,37,39,40,42}
+VDC {19,28,34,36,37,38,41,42,44}
AD+ {34}
24pin 0.5mm bot FFC
D 24
+VDC +VDC
D
24
23 23
22 22
21 21
20 20
{23} USB_OC#6 19 19
18 C734 C735
{23} USB_OC#2 18
17 17 0.01uF/25V,X7R 0.01uF/25V,X7R
{23} USB_PN9 16 16 C0402 C0402
{23} USB_PP9 15 15
14 14
{23} USB_PN6 13 13 26 26
{23} USB_PP6 12 12 25 25
11 11
{23} USB_PN2 10 10
{23} USB_PP2 9 9
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
+V5AL USB_CONN
C C
+V3.3AL +V5S +V3.3AL +V5S
R728 R729
1
1
Q39 10K Q40 10K
2N7002E-T1 R0402 2N7002E-T1 R0402
TPCLK 2 3 TP_TPCLK_R TPDAT 2 3 TP_TPDAT_R

{33} TPCLK {33} TPDAT
TR1 0 R0402
ns
TR2 0 R0402
ns
power button Conn
PWRCONN1
21 21
AD+ 1 1 2 2 AD+
3 3 4 4
5 5 6 6
7 8
B R730 LEFT 9
7
9
8
10 10 B
1K 11 12
R0402 11 12
3 4 13 13 14 14
{34,43} Isense_SYSP 15 15 16 16 LIDR# {19,33}
3
C586 17 18 +V3.3AL
{28,33,36} PWR_SW_VCC2 17 18
D52 19 20
100pF/50V,NPO 19 20
22 22
1 2
TLSW1 BAT54SPT 88242_2001
TMG-534-V
1
1 +V5S BUTTON4_S CNS2x10_1_R

1 TP_TPDAT_R 620902010002
2 2
7 3 TP_TPCLK_R +V5S
7 3
4 4
8 5 LEFT
8 5 RIGHT
6 6
CNS6_1_R1
Conn 6Pin R0402 R731 RIGHT
TP_CON1 1K
+V3.3AL
VerB:converse the connection of TP_CON1 3 4
3
+V5S C587 D53
100pF/50V,NPO 1 2 BAT54SPT
TRSW1
A C311 C315 R99 R401 TMG-534-V TOPSTAR TECHNOLOGY A
1
47K 47K C300 BUTTON4_S

0.1UF/25V,Y5V C0603 R0402 R0402 C0402 bent
C0402 1UF/10V,Y5V 0.1UF/25V,Y5V +V5S Page Name USB2.0&&LED CONN&Qkey CONN
Add pull res
TPDAT A3 M46G
B
TPCLK Date: Tuesday, September 01, 2009 Sheet 32 of 51
5 4 3 2 1
+V3.3S +V5S +V3.3AL +V3.3S

+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,38,40,41,42,50,51}
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,34,35,36,37,38,39,40,41,42,50,51}
+V5S {19,20,21,23,24,25,30,31,32,38,41,42}
C66 C0402
+VDC {19,28,32,34,36,37,38,41,42,44}
R380 Q23
8.2K 2N7002E-T1 0.1UF/16V,Y5V EC_V3.3AL
1
C47
R0402 C64 C0402 10UF/6.3V,X5R C60 C61 C50 C48 C51
R75 C0805
2 3 A20GATE 0.1UF/16V,Y5V 0 +V3.3AL 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
{22} H_A20GATE
ns FB21 R0805
EC Output Signal! 120ohm/100MHz,500mA
1 2FB0603 EC_V3.3AL 1 2 V18R
D28 1 1N4148WS
Should have a 0.1uF capacitor close to every GND-VCC pair + one
SOD323 C575 larger cap on the supply.
C273 C277 0.1UF/25V,Y5V C576
+V3.3S +V5S C0402 1uF/10V,X7R
0.1UF/25V,Y5V
0.1UF/25V,Y5V C0603
Q21 Vin>=1.5V turn on the cup FAN. HDD_ZOUT R33 10K
V18R
2N7002E-T1 HDD_YOUT R42 10K
1
D R375 HDD_XOUT R32 10K D

10K ns
124
111
125
RCIN#
67
96
33
22
{22} H_RCIN# 2 3
9
U29
EC Output Signal!
V18R
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
D27 1 1N4148WS
SOD323 63 SYS_I_Sense
AD0/GPI38 SYS_I_Sense {43}
ADC
64 HDD_ZOUT +V3.3AL
A20GATE AD1/GPI39 HDD_YOUT CHG_ON R94 10K
1 GA20/GPIO00 AD2/GPI3A 65
RCIN# 2 66 HDD_XOUT ALW_PWROK need move to other
KBRST#/GPIO01 AD3/GPI3B place.pin110&111 follow the
MSIC
20 SCI#/GPIO0E
{23} EC_RUNTIME_SCI# EC_RESET#37 sequence of R18EC
ECRST#
EC Input Signal! C494 change to DG
SYS_I_Sense By Johan 071224
R59 0 EC_BUF_PLT_RST# 12 21
{12,19,23,26,27,28,31,51} BUF_PLT_RST# {6} CLK_591PCI PCICLK PWM0/GPIO0F BTL_BEEP {30}
PWM
3 23 SPI_CS# R574 10K
{23,31} INT_SERIRQ SERIRQ PWM1/GPIO10 POWERLED# {50} 3300pF/50V,X7R
R0402 4 25 SPI_MOSI R575 10K
{22,28,31} LPC_FRAME# LFRAME# PWM2/GPIO11 SET_I {43} swap for DG C0402
10 34 SPI_MISO R577ns 10K
{22,28,31} LPC_AD0 LAD0 PWM3/GPIO19 EC_BKLT_PWM {19} By Johan 071224
KBCON1 8 SPI_SCK R576ns 10K
{22,28,31} LPC_AD1 LAD1
ACES 85201-2602 +V3.3AL 7
LPC
{22,28,31} LPC_AD2 LAD2 ns
CNS26_1_R_1D7 5 I2C_CLK R119ns 4.7K
{22,28,31} LPC_AD3 LAD3
EC_PCI_RST# 13 28 EC_FAN_BACK 1 D8
PCIRST#/GPIO05 FANFB0/GPIO14 FAN_BACK {31}
FAN
26 R717 CLKREQ 38 29 1N4148WS I2C_DATA R120 4.7K
26 CLKRUN#/GPIO1D FANFB1/GPIO15 BT_ON {31}
25 4.7K R0402 CLKREQ 26 SOD323
25 FANPWM0/GPIO12 FAN1_V {31}
24 SCANOUT15 27 R579 1K R104 SM_BAT_SDA2 R118 5.6K
24 FANPWM1/GPIO13 Camera_ON {19}
23 SCANOUT10 R0402 100K
23 SCANOUT11 +V3.3AL SCANIN7 SM_BAT_SCL2 R110 5.6K
22 22 62 KSI7/GPIO37
21 SCANOUT14 SCANIN6 61
21 SCANOUT13 RN1 4.7K SCANIN5 KSI6/GPIO36 LIDR# R71 10K
20 20 60 KSI5/GPIO35
19 SCANOUT12 1 2 SCANIN0 SCANIN4 59
19 SCANOUT3 SCANIN1 SCANIN3 KSI4/GPIO34
18 18 3 4 58 KSI3/GPIO33
17 SCANOUT6 5 6 SCANIN2 SCANIN2 57 83
17 KSI2/GPIO32 PSCLK1/GPIO4A/P80CLK TPCLK {32}
16 SCANOUT8 7 8 SCANIN3 SCANIN1 56 84 EC_DEBG_Enable_R R108 10K
16 KSI1/GPIO31 PSDAT1/GPIO4B/P80DAT TPDAT {32}
15 SCANOUT7 ns SCANIN0 55 85
15 KSI0/GPIO30/E51_TXD(ISP) PSCLK2/GPIO4C BT_PWRON {31}
14 SCANOUT4 RN28 4.7K 86 EC_PWROFF# R103 10K ns
14 PSDAT2/GPIO4D HW_RATIO_OFF# {27}
PS2
13 SCANOUT2 1 2 SCANIN4 82 87 PCIE_WAKE#_EC R68 10K
13 KSO17/GPIO49 PSCLK3/GPIO4E OV_BAT_ALART {35}
12 SCANIN7 3 4 SCANIN5 81 88 VOLUME- R73 10K
12 KSO16/GPIO48 PSDAT3/GPIO4F EXTSMI# {23}
KB3926
11 SCANOUT1 5 6 SCANIN6 SCANOUT15 54 VOLUME+ R76 10K
11 SCANOUT5 SCANIN7 SCANOUT14 KSO15/GPIO2F/E51_RXD(ISP) ns R100 Media R88 10K
10 10 7 8 53 KSO14/GPIO2E
9 SCANIN4 SCANOUT13 52 0 Mute R83 10K
9 KSO13/GPIO2D
KB
8 SCANIN5 ns SCANOUT12 51 ALT_ON R48 10K ns
8 SCANOUT0 SCANOUT11 KSO12/GPIO2C
7 7 50 KSO11/GPIO2B
C 28 6 SCANIN2 SCANOUT10 49 +V3.3AL C
28 6 SCANIN3 SCANOUT9 KSO10/GPIO2A
27 27 5 5 48 KSO9/GPIO29
4 SCANOUT9 SCANOUT8 47
4 KSO8/GPIO28
SMBUS
3 SCANIN1 SCANOUT7 46 80 GPXIOA00 R732 10K
3 KSO7/GPIO27 SDA1/GPIO47 I2C_DATA {7}
2 SCANIN0 SCANOUT6 45 79
2 KSO6/GPIO26 SCL1//GPIO46 I2C_CLK {7}
1 SCANIN6 SCANOUT5 44 78 R93 R90 R85
1 KSO5/GPIO25 SDA0/GPIO45 SM_BAT_SDA2 {35}
SCANOUT4 43 KSO4/GPIO24 SCL0/GPIO44 77 SM_BAT_SCL2 {35}
10K 10K 10K Fuction P.M2 P.M1 P.M0
SCANOUT3 42 ns
SCANOUT2 KSO3/GPIO23/TP_ISP
41 KSO2/GPIO22/TP_ANA_TEST VerA 0 0 0
+V3.3AL Double confirmed SCANOUT1 40 PCB_Mark0
不用的pin上拉到+V3.3AL. By Johan 0711081231 KSO1/GPIO21/TP_PLL
SCANOUT0 39 KSO0/GPIO20/TP_TEST GPXIOA00/SDICS# 97 GPXIOA00 PCB_Mark1 VerB 0 0 1
98 ns PCB_Mark2
GPXIOA01/SDICLK CHG_LED# {50}
R47 10K ns EC_IMVP_ON
GPXIOA02/SDIMOSI 99 BTL_LED# {50} Verc 0 1 1
GPXIOA
R106 10K EC_IR_IN EC_PMSUSStat# 6 GPIO04 100
GPXIOA03 PM_PWRBTN# {23}
0 R69ns PCIE_WAKE#_EC
14 GPIO07/i_clk_8051 101 R92 R89 R84
{23,26,27,28,51} PCIE_WAKE# GPXIOA04 AMP_SHDW {30}
15 GPIO08/i_clk_peri 102 10K 10K 10K
{34} AC_IN GPXIOA05 MCH_TSATN# {12}
16 GPIO0A/CIR_RX2 103 ns
{23,39,40} PM_RSMRST# GPXIOA06 CHG_ON {43}
R72 1K 17 GPIO0B/ESB_CLK 104
{19,32} LIDR# GPXIOA07 HW_RATIO_OFF_3G# {28} change vera to verb hads
+V3.3AL PWRSW# R67 1K 18 GPIO0C/ESB_DAT_O/ESB_DAT_I 105
GPXIOA08 EC_PWROFF# {23}
19 GPIO0D 106 HW_OFF_BKLT# R895
{23,26,40} PM_SLP_S3# GPXIOA09 HW_OFF_BKLT# {19} 3G_LED# {50} BIU configuration should match flash speed used
32 GPIO18 107 0
{23,26,42} PM_SLP_S4# GPXIOA10 AC_OFF {34}
R121 10K ns BT_PWRON 36 GPIO1A/NUMLED# 108 3G
{38} V1_5S_ON GPXIOA11 BAT_OV_REV {35}
EC_IR_IN 73
R46 1K EC_IMVP_ON 74 GPIO40/CIR_RX LABEL1
GPIO
{41} IMVP_ON GPIO41/CIR_RLC_TX U2

{31} ALT_ON 89 GPIO50 Topstar Soft
127 GPIO59/TEST_CLKSPICLKI 109 SPI_CS# 1 8 VCC_SPI R23 0 EC_V3.3AL BIOS Ver: X.XX
{38} V1_05S_ON GPXIOD0/SDIMISO 3G_OFF# {28} CS# VCC
0 R56EC_PMSUSStat# 110 ALW_PWROK {36,39} SPI_MISO 2 7 HOLD#1 R0603 4.7K EC_V3.3AL EC Ver: X.XX
{19,23} PM_SUS_STAT# GPXIOD1 Q HOLD#
GPXIOD
68 112 PCB_Mark0 EC_V3.3AL 4.7K WP#1 3 6 SPI_SCK R0402 R763
{36} ALWAYS_ON GPO3C GPXIOD2 W# CLK XXXX年XX月XX日
R55 70 GPO3D 114 PCB_Mark1 R762 R0402 VSS 4 5 SPI_MOSI
{42} MAIN_ON GPXIOD3 VSS D
1K 71 GPO3E 115 PCB_Mark2 EC/BIOS Label
{37} V1_8_ON GPXIOD4
{37} V0_9S_ON 72 GPO3F GPXIOD5 116 W25X80A ASSY
+V3.3AL 117 EC_DEBG_Enable_R R578 0 ns BATT_IN# {35}
GPXIOD6 EC_BUF_PLT_RST# R0402 ns SOIC8_50_208
{23,41} IMVP_PWRGD 76 GPI43 GPXIOD7 118
+V3.3AL 75
{23,40} MAIN_PWROK GPI42 EC_DEBG_Enable {28}
R101 SPI_MISO U35
MISO 119
SPI
PROCHOT# 90 120 SPI_MOSI VCC_SPI 8 5 SPI_MOSI

10K E51CS#/GPIO52 MOSI SPI_SCK VDD SI SPI_MISO
30 E51TXD/GPIO16 SPICLK/GPIO58 126 SO 2
ns AMP_SHDW {28} EC_DEBG_UTXD 31 128 SPI_CS# WP#1 3 1 SPI_CS#
{28} EC_DEBG_URXD VOLUME- E51RXD/GPIO17/E51CLK change to DG SPICS# WP# CE# SPI_SCK
92 E51TMR0/GPIO54/WDT_LED# SCK 6
VOLUME+ 93 By Johan 071224 HOLD#1 7
Media E51INT0/GPIO55/SCROLED# HOLD# VSS
8051
91 E51TMR1/GPIO53/CAPSLED# VSS 4
+V3.3AL Mute 95 121
E51INT1/GPIO56 XCLK32K/GPIO57
CLK
122 32XCLK1 W25X40

XCLKI 32XCLK0 SO8_50_150
XCLKO 123
B EC_V3.3AL B
AGND
R66
GND
GND
GND
GND
GND
10K
R0402 R378
KB3926 10K
VerB: Colay tow roms,stuff U35
69
113
94
35
24
11
PWRSW# C288 R0402

4.7UF/10V,Y5V
C0805 EC_RESET#
3
Q7 C45
R593
3
{28,32,36} PWR_SW_VCC2 1 C292
2N7002E-T1C0402 The 0ohm RES will across the isolate 1 Q22 R588
R70 1000pF/50V,X7R island of anolog GND and digital GND +V3.3S MMBT3904-F 0.01uF/16V,Y5V 0
2
R344 R0603 C0402 R0402
2
1M 0 +V3.3AL 100
R0402 R0402 ns
PM_SLP_S4# R111 4.7K R0402 R373
ns 10K
PM_SLP_S3# +V3.3AL R0402
R115 4.7K R0402
ns C37
+V5S R58 4.7K R0402 EC_BUF_PLT_RST# 0 R116 EC_PCI_RST#
C44 C46
R0402 32XCLK0 R30 121K,1% C0402
100pF/50V,NPO 100pF/50V,NPO Q8 ns
1
2N7002E-T1 R63
EC Input Signal! Y2 15pF/50V,NPO
10K
1
R0402 32.768KHz
2 3 PROCHOT# ns R27 xd3_2X6
3
{7} EC_PROCHOT#
10M ASSY
R0402
2
R91 0 ns
C29
32XCLK1 C0402
15pF/50V,NPO
A A
R718 0 R0603
TOPSTAR TECHNOLOGY
bent
Page Name KBC(PC87541L)
Custom M46G
B
5 4 3 2 1
BATT+ {35,43}
+VDC {19,28,32,36,37,38,41,42,44}
AD+
+V3.3AL
{32}
{12,19,22,23,24,26,27,28,29,31,32,33,35,36,37,38,39,40,41,42,50,51}
PR39 PR44
3.3K 15K
R0402 R0402
PR45 10
R0402
ALW_EN {36}
PC35 SO8_50_150
0.1uF/25V,X7R PD2 SSM34PT SI4435BDY
AD+ C0603 1 SMA ns PQ4
4
Change from 0.020ohm to 0.025ohm 071026
G
SBM54PT
PD35 PR15 D
5A 1 8 1
SMB
5A 7A 3
S 5
6
7A
BATT+
2 7 2 7
3 6 0.025,1% 1 8
S 5 1 PD36 R2512
PR94 D SBM54PT SMB
PC102 100K G 1
0.01uF/25V,X7R R0402 PQ10 PD3 SSM34PT
4
C0402 SI4435BDY 1 SMA ns PD1
PR96
SO8_50_150
7A PC105
0.1uF/25V,Y5V
SSM34PT
SMA
51K C0402
{32,43} Isense_SYSP
R0402
{40,43} Isense_SYSN
PR98
51K colay sbm54pt 080514 7A 1
2
8
7
7A
+VDC
R0402 3 6
PR112 S 5
51K D
R0402 G
PQ6
4
SI4435BDY
PR19 SO8_50_150
510K
R0402
PR101 PR97
510K 100K
R0402 R0402
3
PQ27
3
PQ28 2N7002 PQ25
2N7002 SOT23 2N7002
SOT23 1 SOT23
{40} SHDN#
{33} AC_OFF 1 1 BAT_OV# {35}
2
PC103
2
C0402
PR113 PR100 1000pF/50V,X7R
51K 510K
R0402 PC113 R0402
C0402
1000pF/50V,X7R
AD+ +V3.3AL
PR95
3
100K
R0402 PQ26
2N7002
1 SOT23
AC_IN {33}
2
PR109
51K PR102
R0402 1K
PR99 R0402
PC104 20K
1000pF/50V,X7R R0402
C0402
TOPSTAR TECHNOLOGY
bent
Page Name ADAPTER IN
A3 M46G
B
PFB4
http://shop61976717.taobao.com GND_BAT
BATT+
AD+
+V3.3AL
{34,43}
{32,34}
{12,19,22,23,24,26,27,28,29,31,32,33,34,36,37,38,39,40,41,42,50,51}
100ohm@100MHz,3A PC198
1 2 PF1 0.1uF/25V,Y5V add 0.1u for EMI hads 080514
8A C0402
FB0805 FUSE1206 ns
PFB3 100ohm@100MHz,3A 1 2
1 2
PF2 BATCON1
FB0805 8A
7A PFB2 100ohm@100MHz,3A
1 2
FUSE1206
1 2
7A 7 BATT+ BAT_B1 BAT_B2
BATT+
PC7 FB0805
1000pF/50V,X7R KEY PR1 0 R0402 ns
SM_BAT_SDA2 PR8 100 SM_BAT_SDA 6 SDAT

{33} SM_BAT_SDA2
R0402 PR7 0 R0402 ns
SM_BAT_SCL2 100 SM_BAT_SCL 5 SCLK
{33} SM_BAT_SCL2
PR3 R0402 Screw 2*8mm Screw 2*8mm
4 TEMP PR9 0 R0402 ns
711000000013 711000000013
3 BAT_IN#
change to 2*11mm
2 GND By Johan 071224
GND_BAT
1 GND
SK-C103A3-100A
9
+V3.3AL +V3.3AL
+V3.3AL
GND_BAT PZD2 PZD1

PR2 2 2
SM_BAT_SDA2 300K
R0402 3 SM_BAT_SDA 3 SM_BAT_SCL
SM_BAT_SCL2 PC1 PC3
0.1uF/25V,Y5V 1 0.1uF/25V,Y5V 1
change to 5.6pF,070428 C0402 C0402
PR6
PC6 PC2 BAT54S BAT54S
BATT_IN# {33}
5.6pF/50V,NPO 5.6pF/50V,NPO SOT23 SOT23
C0402 C0402 R0402 1K
GND_BAT
GND_BAT
GND_BAT GND_BAT
{33} BAT_OV_REV
{34} BAT_OV#
1 PD16 +V3.3AL
1N4148WS
SOD323
2
1 PQ31
2N2907 PR122 PR47
SOT23 1K 51K
3
R0402 R0402
3
PQ32 1
2N2222
SOT23
2
PR125
OV_BAT_ALART {33}
2K PC121
R0402 0.1UF/25V,X7R
C0603
Delete reserve
TOPSTAR TECHNOLOGY
bent
Page Name BATTERY IN
A3 M46G
B
5 4 3 2 1
+V3.3AL
+VDC
AD+
+V5AL
{12,19,22,23,24,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,50,51
{19,28,32,34,37,38,41,42,44}
{32,34}
{19,24,29,32,37,39,40,42}
EC_RTC {22}
1.输入电容要靠近MOSFET漏极
2.MOS管尽量靠近IC芯片
3.芯片的Thermal
GND_ISL62382 GND_ISL62382 GND用至少5个过孔连到信号地,用来散热
D D
PC229 PC230
1uF/10V,X7R 1uF/10V,X7R
C0603 C0603
C0402 PC228
0.01uF/25V,X7R PR273 4.信号地和电源地在输出电容的负极连到一起
10 ns LDO5
GND_ISL62382 R0402 PC231 C0402
R0402 PR274 PR276 GND_ISL62382 0.01uF/25V,X7R +VDC
20K,1% 10
+VDC +V3.3AL R0402 GND_ISL62382
VDC1
TestP 2A PR275
R0402
100K PR278
0
PR277
20K,1% R0402 2A
{33,39} ALW_PWROK
TPC60 R0402
ns PR279 ns PR280
GND_ISL62382 R0402 10K,1% ALW_PWROK 3.01K,1% R0402 GND_ISL62382
PC232 PC233 PC234 PC235 PC236 PC237 PC238
1
10uF/ 25V 0.1uF/25V,X7R 1000pF/50V,X7R PC239 PC240 1000pF/50V,X7R 0.1uF/25V,X7R ns 10uF/ 25V,X7R 4.7uF/25V,X7R
C1210 C0603 C0402 PR281 1000pF/50V,X7R 1000pF/50V,X7R PR282 C0402 C0603 C1210 C1206
FCCM
PGOOD1
FSET1
VCC1
VCC2
FSET2
PGOOD2
LDO3EN
R0402 680 C0402 C0402 680 R0402
090803:PC237与PC238colay,ns PC237--xiezx
9 32 VERC:去掉COLAY--XIEZX
R0402 PR283 FB1 FB2 PR284 R0402
45.3K,1% 22.1K,1%
10 VOUT1 VOUT2 31
PR285 11 30
C ISEN1 ISEN2 PR286 C
15K 20K R0402
R0402 12 29
OCSET1 OCSET2
+V3.3AL 3A +V5AL 6A
PC241 PU11 PC242
0.047uF/50V,X7R ISL62382HRTZ 0.047uF/50V,X7R
8
7
6
5
5
6
7
8
C0603 EN_V3AL 13 28 EN_V5AL PQ78 C0603
EN1 EN2
D
V3.3AL1 AO4468 V5AL1
D
TestP SO8_50_150 PR288 TestP

TPC60 PR287 4 14 27 4 20K TPC60
PHASE1 PHASE2
G
ns ns
G
15K R0402
S
PQ79 PR290 PR291
S
R0402
AO4468 PR289 15 26
1
2
3
3
2
1
PC246 SO8_50_150 10K UGATE1 UGATE2 PC248
4.7uF/25V,X7R R0402 0 R0402 0 R0402 PR292 4.7uF/25V,X7R
C1206 1
ns 16 25 10K LL2 1
C1206
BOOT1 BOOT2
LDO3FB
LGATE1
LGATE2
PL14 PC243 R0402 PL15
LDO3IN
PGND
LDO3
LDO5
PZ12 3.3uH/4.8A 0.22uF/16V,X7R PC244 ns PR301 5.2uH/5.5A
0.22uF/16V,X7R
2
VIN
BZT52C3V6S-F/3.6 LS2_8836 C0603 ns LS2_1040
G3
G4
G5
G2
G1
SOD323 + C0603 2.2
1
8
7
6
5
5
6
7
8
2
R0805
G3
G4
G5
17
18
19
20
21
LDO5 22
23
24
G2
G1
D
ns PR302 + ns
D
1
GND_ISL62382 GND_ISL62382
2
ns PD37 PR294 PR296 ns

1
PC247 2.2 4 +VDC 4 PC254 PZ13
2
G
220UF/6.3V,OSCON R0805 1N5819 PR295 0.01uF/25V,X7R BZT52C5V6S-F/5.6
1
1
G
1
S
CAP6_6x7_3 SOD123 0 R0402 PR293 0 R0402 PQ81 PD38 C0402 SOD323
S
5.11K,1%
PC245 ns PQ80 R0402 0 AO4468 1N5819
1
2
3
3
2
1
1000pF/50V,X7R PC255 AO4468 R0402 SO8_50_150 SOD123
C0402 0.01uF/25V,X7R SO8_50_150 PC249
B
C0402
3A PC250 1000pF/50V,X7R
B
M46G VerB:add the RC circuit to PC251 6A 220UF/6.3V,OSCON
CAP6_6x7_3
C0402
improve the power quality--xiezx M46G VerB:add the RC circuit to
PR297 4.7uF/10V,X5R
improve the power quality--xiezx
3.01K,1% C0805
R0402
PD39 EC_RTC
1N4148WS
SOD323
PC252
1 4.7uF/10V,X5R
{28,32,33} PWR_SW_VCC2
C0805
PR298
2 R0402
{33} ALWAYS_ON
10
3 EN_V5AL EN_V3AL
{34} ALW_EN 1
PC253
PD40 PR299 1000pF/50V,X7R
BAT54C 100K C0402
SOT23 R0402 PR300
0 R0402
A
GND_ISL62382 GND_ISL62382 TOPSTAR TECHNOLOGY A
GND_ISL62382
Hads
Page Name +V3.3AL/+V5AL/+V1.5AL
A3 M42G
B
5 4 3 2 1
+V0.9S {17,18,42}
+V5AL {19,24,29,32,36,39,40,42}
+V3.3AL
+VDC
+V1.8
{12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,38,39,40,41,42,50,51}
{19,28,32,34,36,38,41,42,44}
{12,13,14,15,16,40,42}
DDR2用电源
+V1.8 2.5A 1.5A
+VDC
PC144 PC137
1000pF/50V,X7R 4.7uF/25V,X7R
PU8 C0402 C1206
PC147 PC150 TPS51116 PQ49 PC142 PC138
5
6
7
8
0.1UF/10V,X7R 4.7UF/6.3V,X5R SOP20_0D65_4D4G PC141 AO4468 0.1uF/25V,X7R 10uF/25V,X5R
D
C0402 C0805 0.1uF/25V,X7R PR243 SO8_50_150 C0603 C1210
C0603 R0603 ns CO_Lay
1 20 0 4
VLDOIN VBST
S
PL10
9 19
500mA PR150 5.2uH/5.5A V1_8
12,15,16} SM_VREF_L
3
2
1
VDDQSNS DRVH 10K LS2_1040 TestP
PC152 6 18
500mA 4A 1
+V1.8
TPC60
ns
MODE LL +V1.8
0.1uF/10V,X7R PR244 PQ50 PQ56
5
6
7
8
5
6
7
8
C0402 R0603
500mA
AO4468 AO4468 PD20 PR303 PC135
4A
D
DDR_GND 7 17 0 SO8_50_150 SO8_50_150 SSM34PT ns PL13 ns PC136 C0402
VTTREF DRVL
2
SMA 2.2 1
220UF/6.3V,OSCON 0.1uF/10V,X7R
1
TPS51116 DRVL TPS51116 DRVL R0805 + CAP6_6x7_3
1
4 4
1
2.2uH/9A
D-CAP
G
PR165 10K R0402 11 8 + PZ4
1
{33} V0_9S_ON S3 COMP LS2_6530
S
PC140 ns BZT52C2V0S-F/2.0V
2
PR163 200K R0402 1000pF/50V,X7R PC256 PC200 SOD323
3
2
1
3
2
1
1
PR168 10K R0402 12 10 C0402 0.01uF/25V,X7R 220uF/2.5V,POSCAP ns
{33} V1_8_ON S5 VDDQSET colay pl13
C0402 CT7343_19
PR167 200K R0402 ns
4 15 F_5VAL 10
DDR_GND VTTSNS CS PR162 PR160
2.5A 2 14
R0402
20K
R0402
VTT V5IN +V5AL M46G VerB:add the RC circuit to
+V0.9S PR166
improve the power quality--xiezx
PC151 PC159 100K
10uF/6.3V,X5R10uF/6.3V,X5R 3 13 R0402 ns
VTTGND PGOOD +V3.3AL
V0_9S1 C0805 C0805 PC143
TestP ns 4.7UF/6.3V,X5R F_5VAL
TGND
ns 5 16 C0805
TPC60 GND PGND
PC145
21
Change from 22uf to 10uf 1108 Steven

400KHz 1uF/10V,X7R
C0603
DDR_PWG ns
DDR_PWG {40}
R0402
PR172
0 DDR_GND
V1_8_ON
1
PJ4
JOPEN DDR_GND
RESISTOR_1
ns
2
+V3.3AL
+V3.3AL
+V5AL
PR267
20K
R0402
+V0.9S PR266
51K DDR_PWG
R0402
3
PQ75
1
PR268 2N7002E-T1-E3
1K 1 SOT23 J12
R0402 JOPEN
RESISTOR_1
2
ns
2
3
PQ76
1 MMBT2222A
SOT23
2
PR269
20K
R0402
TOPSTAR TECHNOLOGY
bent
Page Name +V1.8/+V0.9S DDR
A3 M46G
B
http://shop61976717.taobao.com +V1.05S
+VDC
{6,7,8,9,12,13,14,22,24,31,40,41,42,44}
{19,28,32,34,36,37,41,42,44}
+V5S {19,20,21,23,24,25,30,31,32,33,41,42}
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,40,41,42,50,51}
+V1.5S {8,14,22,24,26,27,28,30,40,42}
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,39,40,41,42,50,51}
2A
+VDC
PC48 PC64
4.7uF/25V,X7R 4.7uF/25V,X7R
C1206 C1206
PC52 PC47 PC53 PC65
0.1uF/25V,X7R 10uF/25V,X5R 1000pF/50V,X7R 10uF/25V,X5R
PR49 R0402 10K C0603 C1210 C0402 C1210
{33} V1_05S_ON
ns ns
PR52 R0402 CO_Lay
200K AO4468 CO_Lay
5
6
7
8
PQ15
D
PR245
GND_51124 R0603
PR51 R0402 0 500mA HDR2 4
G
20K CHIPPWROK
+V3.3S
S
ns PR48
10K PC130
3
2
1
+V1.05S 500mA PL7 220UF/6.3V,OSCON
lx2 lx2 1
CAP6_6x7_3 +V1.05S
1.0uH/11A
PR57 PC56 PD19
12A
5
6
7
8
5
6
7
8
2K,1% 470pF/25V,X7R PC55 SSM34PT
1
500mA
D
R0402 C0402 0.22uF/16V,X7R PR246 SMA
2
ns C0603 R0603 + + PC188
1
0 TPS51124_LDR2 4 TPS51124_LDR2 4 1uF/10V,X7R V1_05S1
TestP
G
PC132 C0603
1
GND_51124
2
S
S
220UF/6.3V,OSCON ns PZ2 TPC60
PR55 PQ77 PQ14 CAP6_6x7_3 BZT52C2V0S-F/2.0V ns
3
2
1
3
2
1
1
4.99K,1% AO4706 AO4706
12A SOD323
G2
R0402 SO8_50_150 SO8_50_150 ns
10
11
12
7
9
PU2 ns
tps51124
PG2
EN2
VBST2
DRVH2
LL2
DRVL2
GND2
PC57 1000pF/50V,X7R
6 VO2 PGND2 13 GND_51124
GND_51124 C0402 ns
5 14 PR53 GND_51124
PR56 1K R0402 ns VFB2 TRIP2
FILT124 Change from 23.7k to 9.31k 1108 Steven
9.31K,1%
4 TONSEL V5FILT 15 FILT124 +V5S
TPS51124 PR58 R0402 2.2
PC59 0.01uF/16V,X7R
C0402 ns 3 QFNS24_0D5_1G 16 FILT124
GND_51124 GND V5IN
PC60 PC58
2 17 1uF/10V,X7R C0603
VFB1 TRIP1 C0603
PR61 1uF/10V,X7R
GND_51124 1 18 15K
VO1 PGND1 R0402
DRVH1
DRVL1
VBST1
GND1
PC62 GND_51124
PG1
EN1
LL1
1000pF/50V,X7R
C0402
PR59 ns
24
23
22
21
20
19
G1
4.99K,1%
R0402 GND_51124 GND_51124
GND_51124
PR60 PC61
4.99K,1% 470pF/25V,X7R PC63
3
2
1
R0402 C0402 0.22uF/16V,X7R PR247
1
ns C0603 R0603
S
2
500mA 0 PD7 PC189
1
G
4
+V1.5S 1N5819 1uF/10V,X7R + PC133 Delete PC70
1
SOD123 ns 220UF/6.3V,OSCON PZ3
SO8_50_150 BZT52C2V0S-F/2.0V
D
CAP6_6x7_3
2
CHIPPWROK AO4468 C0603 SOD323
{40} CHIPPWROK
5
6
7
8
PQ17
PR62
500mA
lx1 1
4A +V1.5S
ns
R0402 +V1.5S
{33} V1_5S_ON
10K PR54 PL9
4A
3
2
1
PR248 10K 3.3uH/4.8A V1_5S1

R0603 LS2_8836 TestP
S
PR63 500mA 0 ns
G
4
200K TPC60
R0402 SO8_50_150
D
AO4468
5
6
7
8
PQ16
GND_51124
V1_5S_ON V1_05S_ON PC50

4.7uF/25V,X7R TOPSTAR TECHNOLOGY
PR50 0 R0402 C1206
1
PC51 PC54 bent

PJ3 PJ2 0.1uF/25V,X7R PC49 1000pF/50V,X7R Page Name +V1.5S/+V1.05S CHIPSET
JOPEN JOPEN C0603 10uF/25V,X5R C0402
RESISTOR_1 RESISTOR_1 CO_Lay C1210
1A Size Project Name Rev
ns ns ns +VDC A3 M46G
2
+V3.3AL +V3.3AL B
GND_51124
http://shop61976717.taobao.com +V1.5AL {24}
+V5AL {19,24,29,32,36,37,40,42}
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,40,41,42,50,51}
PD34 1N4148WS
SOD323
1 ns
0.5A 0.5A
ADJ/GND
+V3.3AL 3 VIN VOUT 2 +V1.5AL
Vo 4
PU10 PR270
1
KIA1117 301,1%
SOT223
PC196 PC197
10uF/6.3V,X5R 10uF/6.3V,X5R
C0805 C0805 PR271
1K
PR272 R0402
60.4,1%
Add 0ohm
By Johan 071224 PR136 +V5AL
0 +V3.3AL
R0402
PR212
{33,36} ALW_PWROK
0 PC69
R0402 ns ns 0.1uF/10V,X7R
C0402
PC73 ns PR161
0.22uF/10V,X7R 1K
C0603 R0402 R518 0
ns PU3B ns
8
LM358 ns Q28
5 SO8_50_150
+
7 PD8 1 RSMRST# 2 HMBT3906
3 PM_RSMRST# {23,33,40}
6 ns 1N5819 SOD123
-
ns ns
+V3.3AL PR70 +V3.3AL
1
10K PC139 R516 10K
R0402 PR69 0.22uF/10V,Y5V
ns 10K C0402 PR164 ns R521
R0402 ns 510K D37 10K
1
ns R0402 1N4148WS ns
ns ns
PR66
D38
1
0 1N4148WS
ns
R0402
ns
D39
1
1N4148WS
ns
R525
5.11K,1%
+V5AL ns
PU3A
8 LM358
3 SO8_50_150 ns
+
1
2 -
TOPSTAR TECHNOLOGY
4
bent
Page Name +PEX_VDD/+V1.8GDDR
A3 M46G
B
+V3.3S
+V3.3S
+V5AL
+V3.3AL
{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,41,42,50,51}
{19,24,29,32,36,37,39,42}
{12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,41,42,50,51}
+V1.05S {6,7,8,9,12,13,14,22,24,31,38,41,42,44}
+V1.5S {8,14,22,24,26,27,28,30,38,42}
+VCC_CORE {8,41}
Power Good Logic CIRCUIT +V1.8
AD+
{12,13,14,15,16,37,42}
{32,34}
PR171
10K
R0402
Delete NVVDD_PWROK
Delete IO_PWRGD 1108 Steven
MAIN_PWROK {23,33}
PR170 1K
R0402
{38} CHIPPWROK
PD30 1 1N4148WS
{37} DDR_PWG
SOD323
{23,33,39} PM_RSMRST#
PD24 1 1N4148WS OVP CIRCUIT
SOD323
R544 1K
PD28 1 1N4148WS
{23,26,33} PM_SLP_S3#
R0402
SOD323 PQ58
C469 DTB114EK
0.1uF/10V,X7R SOT23
C0402 2 3
{34,43} Isense_SYSN SHDN# {34}
PR196
20K
PR201
1
PC170 100K
0.1uF/25V,Y5V R0402
C0402 PR181
20K
R0402
2
PR199 0 PR198 PQ61
3
R0402 20K 1 DTB114EK
{31} SHDN_LOCK#
R0402 SOT23 PC162 PQ57
0.01uF/25V,X7R 2N7002
3
PQ53 C0402 1
6
PZ8 SOD323 SOT23
2
2 1 5 2
+V5AL
BZT52C5V6S-F/5.6 MMDT3904 SC70_6
1
PR180
PZ6
ns SOD323 20K
2 1 PR194 PR185 R0402
+V3.3AL PC168 100 PC166 20K
BZT52C3V6S-F/3.6 1uF/10V,X7R R0402 1000pF/50V,X7R R0402
C0603 C0402
PZ5
2 1
+V1.8
ns BZT52C2V0S-F/2.0V
SOD323
PZ7
2 1
+V1.5S ns
BZT52C2V0S-F/2.0V
SOD323
PZ9
2 1
+V1.05S ns
BZT52C2V0S-F/2.0V
SOD323
PZ11
+VCC_CORE 2 1
ns
BZT52C2V0S-F/2.0V
SOD323
TOPSTAR TECHNOLOGY
bent
Page Name
Power Good Logic/OVP
A3 M46G
B
5 4 3 2 1
+V5S
{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,42,50,51}
{19,20,21,23,24,25,30,31,32,33,38,42}
+VDC {19,28,32,34,36,37,38,42,44}
+VCC_CORE {8,40}
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,42,50,51}
+V1.05S {6,7,8,9,12,13,14,22,24,31,38,40,42,44}
H_VID6 {8}
D +VDC D
H_VID5 {8}
3A
{33} IMVP_ON H_VID4 {8}
PR14 470 R0402
{12,23} PM_DPRSLPVR H_VID3 {8}
5
6
7
8
9
PC82 PC80 PC81 PC84 PC83
{7,12,22} H_DPRSTP# H_VID2 {8} VCC_IMVP1
D
1uF/25V,Y5V 10uF/25V,X7R 10uF/25V,X7R 0.1uF/25V,X7R 1000pF/50V,X7R
PQ23 C0805 C1210 C1210 C0603 C0402 TestP
{23} CK505_CLK_EN# H_VID1 {8}
500mA 4 AOL1426
ns TPC60
G
PC34 1uF/10V,X7R ns
CPU_GND H_VID0 {8}
S
C0603 PR74 SO8_50_150_PPAK ns PL1
1 0.68uH/28A
PR18 10K PC39
+V3.3S
3
2
1
2K R0402 220UF/2.5V,POSCAP
22A
48
47
46
45
44
43
42
41
40
39
38
37
PU1 CT7343_19
1
PR21 100K PC8 PL20.36uH/30A
3V3
CLK_EN#
DPRSTP#
IVD6
VID5
VID4
VID3
VID2
VID1
VIO0
DPRSLPVR
VR_ON
+V1.05S +VCC_CORE
3
R0402 0.22uF/16V,X7R LS2_1040
1
ns
1 36
C0603
PR235 0
PQ3
AOD448
PR75
2.2PR81 PR83 PR84 PC194 + +
44A
1
{23,33} IMVP_PWRGD PGOOD BOOT1
PMON1 TestP R0603 1 5.11K,1%
R0805 10K 10 1uF/10V,X7R
TPC60 ns
{7} PM_PSI#
PR22 0 2 35 500mA PD10 ns R0402 R0402 R0402 C0603
2
R0402 PR23 PSI# UGATE1 SBM54PT ns PC38
1
2
PC95
CPU_GND
PC30 0 3 PMON PHASE1 34 500mA SMB PC85 220UF/2.5V,POSCAP
C0402 1000pF/50V,X7R R0402 500mA 0.01uF/25V,X7R CT7343_19
PR24 500mA C0402
ISEN1
CPU_GND 4 RBIAS PGND1 33
147K,1% ns 0.22uF/16V,X7R
PR31 R0402 5 32 PR236 0 R0603 C0603
4.02K,1% {7} VR_PROCHOT# VR_TT# LAGTE1
CPU_GND
R0402 PR30 NTC 6 NTC PVCC 31 +V5S
VSUM VCC_OUT
C 470K,1% PC22 PR238 PC86 C
C0402 PC18 R0603 C0402 0 4.7uF/10V,X5R
ISEN2
7 SOFT LGATE2 30
1000pF/50V,X7R R0603
CPU_GND
0.022uF/16V,X7R 8 OCSET PGND2 29 500mA PC97 PC96
0.01uF/25V,X7R C0603
PC21 1000pF/50V,X7R 9 VW PHASE2 28 500mA C0402
C0402 ns 0.22uF/16V,X7R
2
PR29 10 COMP UGATE2 27 500mA PR85
2
1
PC20 10K PR25 R0402 1 5.11K,1% PR86 PR87
1000pF/50V,X7R R0402 6.98K,1% 11 FB BOOT2 26 500mA PD13 R0402 10K 10 PC195 + + PC37
1
C0402 AOD448 SBM54PT PR88 R0402 R0402 1uF/10V,X7R 220UF/2.5V,POSCAP
12 25 PC9 PQ11 SMB 2.2 0.36uH/30A C0603 CT7343_19
1
FB2 NC
DROOP
0.22uF/16V,X7R R0805 LS2_1040 ns
3
VDIFF
VSUM
ISEN2
ISEN1
VSEN
PC31 C0603 PL4
GND
VCC_OUT
VDD
RTN
DFB
ns
VIN
3300pF/50V,X7R PC36
22A
VO
PC19 C0402 PR237 PR40 220UF/2.5V,POSCAP
3
2
1
100pF/50V,NPO PR20 0 10K PL51 CT7343_19
13
14
15
16
17
18
19
20
21
22
23
24
C0402 R0603 CPU_GND SO8_50_150_PPAK
S
R0603
PR28 6.04K,1% 0.68uH/28A
G
4 AOL1426
ns ns
VSUM
ISEN2
ISEN1
75K
VCC_OUT
ISL6262A_0 PQ29
R0402
D
PR10 PC32 PC26 PC25 PC24 PC27
5
6
7
8
9
PR26 10 PC23 1000pF/50V,X7R R0402 1000pF/50V,X7R 0.1uF/25V,X7R 10uF/25V,X7R 10uF/25V,X7R 1uF/25V,Y5V
+V5S
R0402 C0402 10 C0402 C0603 C1210 C1210 C0805
PR27 2K PC11 ns
R0402 1uF/10V,X7R
{8} VCCSENSE
PR17
10 PC17
C0603 CPU_GND 3A +VDC
B R0402 1000pF/50V,X7R PC12 B
PC16 C0402 0.1uF/25V,X7R
1uF/10V,X7R PC15 C0603
C0603 0.1UF/10V,X7R PR11 10 IMVP_PWRGD# IMVP_PWRGD
+VDC
ns C0402 R0402
CPU_GND
{33} IMVP_ON +V3.3AL
PR13 4.02K,1%
PR16 PC93 1000pF/50V,X7R PR78
{8} VSSSENSE
0 C0402 R0402
R0402 3.57K,1%
PC14 PC13 PR12 PR80 10K,1% PR32 PQ8 PR43
1000pF/50V,X7R C0402 1K,1% R0402
IMVP_VI Test Debug 1K 2N7002 PQ9 10K
3
C0402 330pF/50V,X7R R0402 R0402 SOT23 2N7002 ns
PR79 1K,1% +V1.05S ns ns SOT23 R0402
CPU_GND R0402 ns
1 1 IMVP_PWRGD#
PR82
PR77 CPU_GND
PC94 4.53K,1% PR33 56 R0402 ns
2
0.1UF/10V,X7R R0402 {8} H_VID0 PR36 56 R0402 ns PR38 PR42
C0402 PC90 {8} H_VID1 PR37 56 R0402 ns 100K 510K
0 0.22uF/16V,X7R CHANGE from Y5V to X7R {8} H_VID2 PR34 56 R0402 ns R0402 ns
R0402 C0603 {8} H_VID3 PR35 56 R0402 ns ns R0402
PC91 {8} H_VID4 PR41 56 R0402 ns
CPU_GND 0.047uF/50V,X7R {8} H_VID5
{8} H_VID6
1
C0603 J2
J1 J6 J4 JOPEN
JOPEN JOPEN JOPEN RESISTOR_1
RESISTOR_1 RESISTOR_1 RESISTOR_1 ns
ns ns ns ns ns
A A
2
2
J3 J5 TOPSTAR TECHNOLOGY
JOPEN JOPEN
RESISTOR_1 RESISTOR_1 bent
Page Name +VCC_CORE
A3 M46G
B
5 4 3 2 1
5 4 3 2 1
http://shop61976717.taobao.com +VDC
+V5S
{19,28,32,34,36,37,38,41,44}
{19,20,21,23,24,25,30,31,32,33,38,41}
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,50,51}
+V5AL {19,24,29,32,36,37,39,40}
PR187
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,50,51}
100mA 1K 9--19V 50mA +V0.9S {17,18,37}
2 3 R0402
+VDC +V1.05S {6,7,8,9,12,13,14,22,24,31,38,40,41,44}
+V1.5S {8,14,22,24,26,27,28,30,38,40}
PQ55
+V1.8 {12,13,14,15,16,37,40}
DTB114EK
PR178 SOT23
1
D 100K PC161 D
R0402 0.01uF/25V,X7R +V3.3AL
C0402 +V5AL
50mA
PR183
PR182 33K 5A PD31 +V3.3S
1K R0402 PQ52 PC257 1N4148WS PQ59
5
6
7
8
5
6
7
8
R0402 SI4800BDY 4.7uF/10V,Y5V SOD323 AO4468
D
SO8_50_150 C0805 1 SO8_50_150 V3_3S1
MAIN_PWR_DN# ns TestP
4 4 TPC60
G
+V5S ns
S
PQ62 PR195 PR188
2N7002 51K 5A 75K
3
2
1
3
2
1
{33} MAIN_ON 1 R0402 R0402 4A
EC PR206 SOT23 V5S1 PC165
2
1K PR205 PC172 TestP 0.1uF/25V,Y5V

R0402 510K 0.1uF/25V,Y5V PC146 TPC60 C0402 PC171
R0402 C0402 4.7uF/10V,Y5V ns 4.7uF/10V,Y5V
C0805 C0805
M46G VerB:改用AO4468的2S SI4800,在第一版用AO4468时上电不正常--xie
C C
+V1.5S +V5S +V3.3S +V1.05S +V0.9S +VDC
30mA 100mA 70mA 21mA 18mA

2
2
PR147
100 PR148 PR145 PR146 PR154 PR159 PR158 PR143 PR144 PR141
R0402 100 100 100 PR152 100 100 100 100 100 510K
R0402 R0402 R0402 100 R0402 R0402 R0402 R0402 R0402 R0402
ns ns R0402 ns ns
1
1
DISCHG
3
PQ42 PQ43
3
3
PQ39 2N7002 PQ41 2N7002 PQ46 PQ40
2N7002 SOT23 2N7002 SOT23 2N7002 2N7002
SOT23 SOT23 1 SOT23 SOT23
B MAIN_PWR_DN# ns1 ns DISCHG B
1 1 1 1
2
2
2
PR142
200K
R0402
+V1.8 +VDC
36mA
PR151
100
2
R0402
PR149
100
R0402 PR140
V1_8DISCHG 510K
1
R0402
PQ44
3
PQ48 2N7002
2N7002 SOT23
SOT23
PR155 10K 1 1 V1_8DISCHG
A {23,26,33} PM_SLP_S4# A
R0402 TOPSTAR TECHNOLOGY
2
PR153 bent
200K Page Name SYSTEM/DISCHARGE
R0402 Size Project Name Rev
A3 M46G
B
5 4 3 2 1
BATT+ {34,35}
+V5AL {19,24,29,32,36,37,39,40,42}
+V3.3AL {12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
+V3.3S {6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50,51}
CHG_GND
PU4
PC98 PR107 0
1.5A
1uF/10V,X7R VDDP 15 2 R0402 Isense_SYSN {34,40}
C0603 VDDP ACSET
PR108
4.7 5V_internal_LDO PC106
R0402 1 0.1uF/50V,Y5V PC33 PC10 PC29 PC28
PC110 VDD C0603 PD14 SOD323 1000pF/50V,X7R 0.1uF/25V,X7R 10uF/ 25V 4.7uF/25V,X7R
CHG_GND
1uF/10V,X7R 24 1N4148WS/75V/150mA C0402 C0603 C1210 C1206
C0603 DCIN 1
ns ns
{32,34} Isense_SYSP 19 CSIP
PC100 PR93 0
PR89 0.1uF/50V,Y5V R0402 070906VA：Co-lay。
C0603 20 17 PR91 Add cap for emi
{34,40} Isense_SYSN CSIN UGATE By Johan 071228
R0402 0
5
6
7
8
10 R0402
PD11
D
PC108 PC109 PQ5
1000pF/25V,X7R 5600pF/50V,Y5V 5 16 VDDP AO4468
C0603 ICOMP ISL6251HAZ BOOT 1
SO8_50_150
C0402 4
G
PC101 1N4148WS/75V/150mA PR90 PR76
S
SSOP24_25_150 SOD323 10K 0.05,1% PC89 BATT+
PC111 PC107 0.01uF/25V,X7R 6 0.1uF/50V,Y5V R0402 PL3 R2512 2A 0.1uF/25V,X7R 12.63V
3
2
1
C0402 VCOMP C0603 phase C0603
1
R0402 10K 18 phase 15uH/3.6A
PHASE
5
6
7
8
LS2_1040
3.3V
D
CHG_GND 11 PR213 PC87
VADJ PR214
PD12 2.2 PC182 PC92
14 4 1N5819 4.7uF/25V 10uF/ 25V 1uF/25V,Y5V
LGATE R0805
G
C1210 C0805
1
{33} CHG_ON 3 EN SOD123 ns C1206
S
0 R0402 PQ24 ns
Change from 10k to 6.98k 13 AO4468 PC181
3
2
1
PR104 PGND SO8_50_150 0.01uF/25V,X7R
10K 9 C0402
{33} SET_I CHLIM
R0402 21 PR92
CSOP ns
PC99 2.2 R0402

PC227 2.39V_Vref 8 VREF 1uF/10V,X7R
SET_I 充电电流 0.1uF/10V,X7R
C0402 CSON 22
C0603
PR110 10 ACLIM
0V 0A 10.5K,1%
R0402
CELLS 4 CHG_GND
0.33V 200mA 0.643Vref
23 ACPRN PR103
设置适配器限流值为
3.3V 2A 82mV/25m ohm=3.28A. ICM 7 SYS_I_Sense {33}
PR106 100 R0402 PC112
20K,1%
R0402 GND 12
3300pF/50V,X7R Layout note:
C0402
Far away from critical signal trace
SYS_I_Sense SYS_CURRENT PR111 0
BOM:change to 0402
400mV 1A CHG_GND
R0402
1.67V 4.2A change to signal gnd CHG_GND

By Johan 071224
1.87V 4.7A CHG_GND
Change solution from OZ8602 to ISL6251
SYS_CURRENT SYS_I_Sense SYS_I_Trip

>3.6A >1.8V High
<3A <1.5V Low
TOPSTAR TECHNOLOGY
bent
Page Name CHARGER
A3 M46G
B
5 4 3 2 1
H19
H2 H5 H3 H1 http://shop61976717.taobao.com
H7 H4 H8
FD7 FD8 FD1 FD4 FD6 FD5 FD3 FD2
+V3.3AL
+VDC
+V1.05S
{12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50,51}
{19,28,32,34,36,37,38,41,42}
{6,7,8,9,12,13,14,22,24,31,38,40,41,42}
1 1 1 1 1 1 1 1 1 1 1 1
HOLE FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS
1
ns ns ns ns ns ns ns ns
TH_197_118 HOLE HOLE HOLE HOLE HOLE HOLE HOLE
1
FD9 FD10 FD11 FD12 FD13 FD14 FD15 FD16
ns TH_315_118_P TH_315_118_P TH_315_118_P TH_315_118_P TH_315_118_P TH_315_118_P TH_315_118_P
ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GND E8
1
GND GND GND GND GND GND GND FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS EMI
ns ns ns ns ns ns ns ns ns
1
D VerB:change footprint to TH_197_88 XIE M46G VerB:change the footprint of H4 D
H9 VerB:cancel E2 by xie
H6
GND_AUD
HOLE
1
TH_315_118_P HOLE
1
TH_315_118_P
ns
ns
GND GND
V37 V4 V32 V19 V18 V16 V44 V36 E4 E7 E1 E5 E6 E9 E10
1
1
1
EMI EMI EMI EMI EMI EMI EMI
1
VIA VIA VIA VIA VIA VIA VIA VIA ns ns ns ns ns ns ns
1
1
Add for EMI
By Johan 071228
GND GND
V23 V24 V43 V40 V17 V20 V27 V22 V25 V3 GND
1
1
C C
VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA
1
1
ns ns ns ns ns ns ns ns ns ns
GND
V10 V9 V5 V2 V6 V7 V8 V28
1
VIA VIA VIA VIA VIA VIA VIA VIA

1
GND GND +V1.05S

V42 V34 V41 V29 V31 V30 V33 V39 V38 V11 +VDC
1
VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA C482
1
ns ns ns ns ns ns ns ns ns ns Add 2 via for stitch plane C532

By Johan 071227 0.1UF/25V,Y5V
C0402 0.1UF/25V,Y5V
C0402
GND
GND
V35 V12 V13 V26 V15 V14 V1 V21 V45 V46 GND
1
VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA
1
ns ns ns ns ns ns ns ns ns ns
GND GND
B B
A A
TOPSTAR TECHNOLOGY
bent
Page Name
THROUGH HOLE/EMI
C M46G
B
5 4 3 2 1
5 4 3 2 1
C0 to C3 to C0 Timings http://shop61976717.taobao.com
C0 to C2 to C0 Timings
CPU I/F CPU I/F Unlatched Latched Unlatched
Unlatched Latched Unlatched Signals
Signals T28
T28
STPCLK# STPCLK#
(ICH Output) (ICH
T26 Output) T26
T33 T27
D D
Bus Master Break
Active Idle Event
CPUSLP# T29
(ICH Output)
DPSLP# T30a T32b
(ICH Output)
T31 T32a
S0 to S3 to S0 Timings
STP_CPU# T30b
(ICH Output)
S0 S0 S3 S3 S3 S0 S0
CPU Clocks Running Stopped Running

STPCLK#
T34a
T37
T36b
DMI Message
Break Event
STP_CPU# CPUSLP# DPSLP#
DPRSTP# (ICH Output)
C0 to C4 to C0 Timings T25
C C
DPRSLPVR(ICH Output)
CPU I/F Unlatched Latched Unlatched T15
Signals SUS_STAT#(ICH OUTPUT)
T28
STPCLK#
(ICH
Output) T26 T33 STP_PCI#
Active T18
Bus Master PLTRST#
T29 PCIRST#
CPUSLP#
(ICH T21
Output) T32b SLP_S3# (input to EC)
T30a
DPSLP# T19 T51
(ICH
Output) T32a IMVP_ON (EC OUTPUT)
T30b
STP_CPU#
(ICH T22
Output) IMVP_PWROK (ISL6260 Output)
T34a
CPU Clocks Running Stopped Running T22a
MAIN_ON T07
DPRSTP# T35 V0_9S_ON
T36b
(ICH +V3.3S,+V5S,+V1.5S,+V1.05S,
B
Output) T34b T36a B
+V0.9S,+V1.2PCIE
DPRSLPVR T49
(ICH Output) MAIN_PWROK
CPU Vcc
Break PM_ICH_PWROK(ICH Input)

Event
Break Event
TOPSTAR TECHNOLOGY
A bent A
Page Name
ACPI Mode Switch Timings
B M46G
B
5 4 3 2 1
5 4 3 2 1
CLOCK Distribution:
Merom
Pin53 166/200/266MHz
CPU_0# CLK_CPU_BCLK#
D CPU_0 Pin54 166/200/266MHz CLK_CPU_BCLK D
Pin50 166/200/266MHz
CPU_1# CLK_NB_BCLK# ADAPTER MODE
CPU_1 Pin51 166/200/266MHz CLK_NB_BCLK no Check RTC
SUSCLK
Pin31 100MHz CLK_MCH_3GPLL# Xtal&Battery
SRC9#
SRC9 Pin30 100MHz CLK_MCH_3GPLL yes
CANTIGA
EC_RTC,+V5_STB, no
+V3.3AL,+V5AL Check ISL6232
Pin14
SRC0# 96MHZ DREFCLK#
SRC0 Pin13
96MHZ DREFCLK
yes
Check no
Pin18 no EC XTAL
SRC1# 100MHz DREFSSCLK# BIOS FLASH ROM Check EC Xtal
SRC1 Pin17 EC&BIOS 32.768K
100MHz DREFSSCLK
ROM yes
yes
Pin47 100MHz Press

C SRC8# CLK_PCIE_ICH# no LPC PWRSW C
SRC8 Pin46 100MHz CLK_PCIE_ICH Check ICH9M Frame# yes

100MHz
SATA# Pin22 CLK_ICH_SATA# 32.768KHz
Pin21 100MHz yes SLP_S4# no
SATA CLK_ICH_SATA
14.318MHz
SLP_S3# Check EC output PWRBTN#
14.318MHz
REF0 CLK_ICH14ICH9M no SLP_S1#
133MHz Audio Codec Check ICH9M PCI
24MHz yes
48MHz ALC662 Frame#
CLK_USB48
USB_48 no
33MHz Sytem Main
PCIF5 yes Check PWM & MOS Switch
CLK_ICHPCI Power Plane
100MHz no yes
Pin35 CPUBUS
SRC10# PCIE Check CPU no
SRC10 Pin34 100MHz ADS#
NEWCARD MAIN_PWROK Check Power Good logic
yes
100MHz
SRC4# Pin28 yes
100MHz MPCIE
SRC4 Pin27 CARD no no
Check H_CPURST#
33MHz All Clock Check Clock chip
PCI4 (G)MCH
yes yes
SRC7# Pin43
B MPCIE B
SRC7 Pin44 no yes no
Check ICH9M H_CPUPWRGD Check IMVP6 for Yonah
PM_ICH_PWROK
100MHz PLT_RST# CPU
Pin25 CLK_PCIE_GLAN#
SRC3#
Pin24 100MHz CLK_PCIE_GLAN
SRC3
33MHz
PCI3
W83L951ADG 32.768KHz
Card Reader 24.576MHz

(UB6232 USB)
CY28548_TSSOP-56P
A A
TOPSTAR TECHNOLOGY
bent
Page Name
Clock Distribution
C M46G
B
5 4 3 2 1
5 4 3 2 1
1B 2A 2B
BATT+ EC_RTC
PQ4 ALW_PWROK
PD35
PD36 4A 5B
1A +VDC
AD+
Always_On 4B +V3.3AL 4B +V1.5AL
D
PQ10 D
Power +V5AL
3A 3A
2A ISL62382HRTZ
ALW_EN
PWRSWVCC2
V1_8_PWROK 11
3B ALWAYS_ON 6B DDR_PWROK 11
System Power 11 +V3.3S
5A +V_S +V5S
PWRSWVCC2 PWRSW# DDR Power 10 +V1.8
Isense_SYSN
7B 6B TPS51116 +V0.9S
24
ALW_PWROK
10 10 MAIN_ON
10 10
MAIN_ON
CLK_PWRGD
V1_8_ON
V0_9S_ON
PM_SLP_S4# 9 13 4A 4B
V1_05S_ON,V1_5S_ON ALW_PWROK
PM_SLP_S3# 9
DDR_PWROK 11
PM_RSMRST# 4A 3A 20 V1_5S_PWROK 15
MAIN_PWROK
C
EC_KBC V1_05S_PWROK 15
C
8 PM_PWRBTN# SET_I
ICH9
CHG_ON
25 B6 ALWAYS_ON MAIN_PWROK
IMVP_ON
to IMVP_ON SYS_I_Sense
PM_ICH_PWROK
Delay 100mS
VR_PWRGD_CK410_INV
13 SYS_I_Sense AC_IN
V1_05S_ON,V1_5S_ON 21
+VDC Charge BATT+
Chipset PWR 14 +V1.5S ISL6251
PLT_RST#
26 TPS51124 +V1.05S
23 SET_I
MAIN_PWROK
IMVP_PWRGD
H_PWRGD
CHG_ON
26 V1_5S_PWROK 15
V1_05S_PWROK 15
B
20 24 21 IMVP_ON
B
24 IMVP_PWRGD CK410_CLK_EN#
Cantiga VCC_CORE Clock
GMCH ISL6262A 22 CK505M Note:
22
*A:For adapter in
+VCC_CORE *B:For battery only
24
H_CPURST# 27 23 VR_PWRGD_CK410_INV * :For all
CLK_PWRGD
H_PWRGD Penry
Merom
CPU
A A
TOPSTAR TECHNOLOGY
bent
Page Name
THROUGH HOLE/EMI
A3 M46G
B
5 4 3 2 1
5 4 3 2 1
Power On Sequence(Battery mode)

http://shop61976717.taobao.com Power On Sequence(Adapter mode)
G3 G3 S5 S3/S4/S5 S0 S0 G3 G3 S5 S3/S4/S5 S0 S0
With Main Battery
With Main Battery Without AC T26 1ms
T230 T26 1ms
Without AC adapter T230
adapter
H_CPURST# T25
H_CPURST# T25
PLTRST# min 33ms
PLTRST# T27
T27 min 33ms
SUS_STAT#
SUS_STAT#
D D
(CPU PWRGD) T24
(CPU PWRGD) T24
H_PWRGD
H_PWRGD
PM_ICH_PWROK (Input to ICH)
PM_ICH_PWROK (Input to ICH)
T23
T23
IMVP_PWRGD IMVP_PWRGD
CLK_PWRGD(ICH output)
T22
CLK_PWRGD(ICH output) T22 VR_PWRGD_CK410_INV(ICH Input)
VR_PWRGD_CK410_INV(ICH Input)
T20
+VCC_CORE 130ms
+VCC_CORE
130ms
IMVP_ON(EC Output)
IMVP_ON(EC Output) T20
T19
MAIN_PWROK(Input to EC) MAIN_PWROK(Input to EC)

T19 +V3.3S,+V5S,+V1.5S,+V1.05S,+V1.8,
+V0.9S
+V3.3S,+V5S,+V1.5S,+V1.05S,+V1.8, V1_05_ON(EC Output) T18
+V0.9S T18
V1_5S_ON(EC Output) V1_5S_ON(EC Output) T12
T04
V1_05S_ON(EC Output) T12 V1_8_PWROK
T11 T11
V1_8_PWROK V0_9S_ON,V1_8_ON(EC Output)
V0_9S_ON,V1_8_ON(EC Output) MAIN_ON(EC Output)
MAIN_ON(EC Output) ALWAYS_ON(EC Output)
T10 T10
SLP_S3#(Input to EC) SLP_S3#(Input to EC)
T8+T9 SLP_S4#(Input to EC) T8+T9
SLP_S4#(Input to EC)
T6 T6
PM_PWRBTN# PM_PWRBTN#
C C
ALWAYS_ON(EC Output) PWRSW#(Input to EC)
T7 Press Power Button
T4 Keep up (PRESS POWER
RSMRST#(EC Output)
+V3.3AL BUTTON) PWRSWVCC2 T7
ALW_PWROK(Input to EC)
EC_Reset T5 RSMRST#(EC Output)
ALW_PWROK(Input to EC) T5
T3 +V3.3AL,+V5AL,+V1.5AL
EC_Reset
PWRSW#(Input to EC) T2+T30
Press Power Button +V3.3AL,+V5AL,+V1.5AL
T3
V5FILT,EC_RTC
(PRESS POWER BUTTON)
+VDC
V5FILT,EC_RTC
AD+
+VDC
T1 AC_IN
RTCRST#
RTCRST#
VCCRTC T1
PLUG
Main VCCRTC
Battery PLUG
Adapter
Power Off Sequence(Battery Mode) Power Off Sequence(Adapter Mode)

S0 S0 S5 S5 G3
S0 S0 S5 S5 G3
STPCLK#
STPCLK#
T285
SUS_STAT# T285
SUS_STAT#
STP_PCI#
STP_PCI#
PCIRST#
PLTRST# PCIRST#
SLP_S3#(Input to EC) T286 T31
PLTRST# T288
SLP_S3#(Input to EC) T31
B B
IMVP_ON(EC Output)
IMVP_ON(EC Output)
IMVP_PWROK(ISL6262A Output)
IMVP_PWROK(ISL6260 Output)
MAIN_PWROK
T34 MAIN_PWROK
PM_ICH_PWROK(ICH Input) T34
PM_ICH_PWROK(ICH Input)
V1_05_ON(EC Output) V0_9S_ON(EC Output)
V1_5S_ON(EC Output)
V1_8_ON(EC Output)
V0_9S_ON(EC Output)
T33 V1_5S_ON(EC Output) T33
V1_8_ON(EC Output)
MAIN_ON(EC Output) V1_05_ON(EC Output)
+V3.3S,+V5S,+V1.5S,+V1.05S,+V1.8, MAIN_ON(EC Output)
+V0.9S +V3.3S,+V5S,+V1.5S,+V1.05S,+V1.8,
+V0.9S
ALWAYS_ON(EC Output)
ALWAYS_ON(EC Output)
+V3.3AL,+V5AL,+V1.5AL
RSMRST#(EC Output)
ALW_PWROK to EC
RSMRST#(EC output) +V3.3AL,+V5AL,+V1.5AL
Isense_SYSN +VDC
Pull out
Main Pull out
Battery AC_ADPTER
T3 V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V
A A
TOPSTAR TECHNOLOGY
bent
Page Name
Power On/Off Sequence
A2 M46G
B
5 4 3 2 1
5 4 3 2 1
POWER Distribution
D D
CPU(Socket-M) R0.92
0V-1.4625V VCC 0V-1.4625V VCC
1.05V FSB VCCP
CPU Core Regulator
INVP-6 Compliant 1.5V VCCA
USB
DDR2 SO-DIMM V5A&V3.3A
Battery 0.9V SM VTT
VCCP,GMCH_CORE,
ICH_CORE 1.8V VDD/VDDQ
1.05V SATA
V3.3S&V5S
AC Cantiga GMCH
1.8V DDR I/O
DDR VCC Regulator 3.3V TVDAC
V1.8 BLUETOOTH
1.05V FSB VTT
C V3.3S C
1.05V Core(Int)
System
VREG 1.05V VCC_PEG
9-19V 1.8V LVDS
DDR VTT Regulator SPI
V0.9S 1.05V DMI
V3.3S
1.05V HSIO
+V1.5 HDA
+V1.5 VCCD_QDAC
LVDS
System VREG(9-12.6V)
+V3.3S
CK505-M
ICH9-M V3.3S
1.05V VCC_CPU
1.5V Interface Regulator 1.05V Core
V1.5S 1.05V DMI SMC/KBC
1.5V PCI Express V3.3A
1.5V SATA
1.5V LAN
B B
5.0V Interface Regulator +V5S 1.5V USB Azalia
V5A 1.5V AZALIA V5,V3.3S,+V1.5S
RTC 5VRef
5VrefSus
+V3.3S 3.3VBG
3.3V Interface Regulator RTC
V3.3A Mini-PCI Express
3.3V IDE/PCI V1.5S +1.5V
3.3V VccSus V3.3A +3.3Vaux
1.5VSUS(IntVR) V3.3S +3.3V-3.0A
+V1.5AL 1.05VSUS(Int/ExtVR)
A A
TOPSTAR TECHNOLOGY
bent
Page Name
POWER Distribution
C M46G
B
5 4 3 2 1
5 4 3 2 1
+V3.3AL
{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,51}
{12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,51}
+V3.3S
Blue color
D D
3G IDE_LED# ESD1 1 2 EGA1-0603-V05
3G 3G_LED ns ESDPAD_R0603
2 1 3G+ R881 330
{33} 3G_LED#
LED2_0805 BL-HGB35A-TRB R0402 WIRELESS_LED# ESD2 1 2 EGA1-0603-V05
ns ESDPAD_R0603
HDD1
2 1 IDE+ R882 150 CHARGE_LED ESD3 1 2 EGA1-0603-V05
{22} IDE_LED#
LED2_0805 BL-HGB35A-TRB R0402 ns ESDPAD_R0603
BAT_STATE_LED ESD4 1 2 EGA1-0603-V05

{27} WIRELESS_LED# 2 1WIRELS1 WIRE- R719 220 ns ESDPAD_R0603
BL-HGB35A-TRB R0402
LED2_0805 PWR_LED ESD5 1 2 EGA1-0603-V05
VerC:change R881 to 330 and R719C579
to 220 to change the brightness --xiezx ns ESDPAD_R0603
C578 1000pF/50V,X7R
1000pF/50V,X7R C0402
C0402
C730
1000pF/50V,X7R
C C0402 C
+V3.3AL
BAT_STATE_LED C580 1000pF/50V,X7R C0402
CHARGE1 CHARGE_LED C582 1000pF/50V,X7R C0402
R721 220 R0402 CHARGE_LED 2

G Blue Color C581
PWR_LED C584 1000pF/50V,X7R C0402
{33} CHG_LED# 1
R 0.1UF/10V,X7R
R883 220 R0402 BAT_STATE_LED 4 3 C0402
{33} BTL_LED#
Red color
B B
HA1GE33B AMB/GREEN
LED4_1210A
POWER1
{33} POWERLED# R722 220 R0402 PWR_LED 2 1
BL-HGB35A-TRB
LED2_0805
M46G VerB:Achange all the LED to

the same with M12 090713
TOPSTAR TECHNOLOGY
bent
Page Name LED&Touch PAD&QuickButton
A A
A4 M46G A
5 4 3 2 1
5 4 3 2 1
VDD3D3_LAN
Layout Note:
Place close to VDD33_LAN PINS.
(PIN16,PIN37,PIN46 and PIN53)
+V3.3AL
+V3.3S
+V3.3AL
{12,19,22,23,24,26,27,28,29,31,32,33,34,35,36,37,38,39,40,41,42,50}
{6,7,10,12,14,15,16,19,20,21,22,23,24,25,26,27,28,29,30,31,33,38,40,41,42,50}
VDD3D3_LAN
R743 3.6K R0402
VDD3D3_LAN
VDD3D3_LAN
100M Lan(RTL8101E/8102E)
FB38
120ohm/100MHz,500mA 2FB0603
Power domain chart 1
R744 10K R0402 10K is used only
when 93C56 is
ns used.
RTL8101E RTL8102E
VerD:LAN Delete Caps and change VDD3D3_LAN AVDD33 DVDD15
EECS
C604 C605 C606 C607 1 8
C0402 C0402 C0402 C0402 some options followed demo AVDD33 3.3V 3.3V EESK 2 CS VCC
7
SK NC1
0.1UF/25V,Y5V
0.1UF/25V,Y5V
0.1UF/25V,Y5V
0.1UF/25V,Y5V
board and colay 8102E EEDO
EEDI/AUX 3
DI NC2 6
4 5
By K' 080522 AVDD18 1.8V 1.2V
DO GND C608
D D
U32 C0402
AT93C46-10SU-2.7 0.1UF/10V,X7R
AVDD33 EVDD18 1.8V 1.2V SO8_50_150
U33
53
46
37
16
59
58
33
52
49
43
41
38
32
21
15
48
47
45
44
2
Layout Note:
C609 DVDD15 1.5V 1.2V
Place close to AVDD33 PINS.
EESK
EEDI
EECS
EEDO
VDD33_04
VDD33_03
VDD33_02
VDD33_01
AVDD33_02
AVDD33_01
VDD15_10
VDD15_09
VDD15_08
VDD15_07
VDD15_06
VDD15_05
VDD15_04
VDD15_03
VDD15_02
VDD15_01
0.1UF/25V,Y5V
VerC:Delete Caps followed C0402 (PIN2)
demo board by Robin 080418 Layout Note:
Place close to AVDD18 PINS. {6} CLK_PCIE_GLAN 26 28 EVDD18
REFCLK_P EVDD18_02
FB12
(PIN5,PIN8) {6} CLK_PCIE_GLAN# 27 REFCLK_N EVDD18_01 22
CTRL18 AVDD18 23 14
{23} PCIE_TXP1_ICH HSIP AVDD18_04 AVDD18
{23} PCIE_TXN1_ICH 24 HSIN AVDD18_03 11
RTL8111B/RTL8101E时为1.8V C610 C0402 29 8 Layout note:
RTL8111C是1.2V {23} PCIE_RXP1_ICH HSOP AVDD18_02
C611 C0402 0.1UF/10V,X7R 30 5 FB12
FB39 0 R0805
{23} PCIE_RXN1_ICH
0.1UF/10V,X7R HSON AVDD18_01 0.01uf caps need to be
{12,19,23,26,27,28,31,33} BUF_PLT_RST# 20 PERSTB VCTRL15 63 CTRL15
CTRL18
C612
C0402
placed close to PIN5
VCTRL18 1
C613 C614 C615 C616 19 0.01uF/25V,X7R
{23,26,27,28,33} PCIE_WAKE# LANWAKEB
C0805 C0402 C0402 C0402 3 LAN_TX0+
0.1UF/25V,Y5V 0.1UF/25V,Y5V +V3.3S R745 1K R0402 MDIP0 LAN_TX0-
36 ISOLATEB MDIN0 4
10UF/6.3V,X5R 0.1UF/25V,Y5V 6 LAN_TX1+
MDIP1 LAN_TX1-
R746 54 LED3 MDIN1 7
8101E 8101E 8101E 15K R0402 55 LED2 MDIP2 9 VerC:Add 0.01uF followed demo
56 10
R747 2.49K,1% R0402 57
LED1 MDIN2
12 for better EMI performance
LED0 MDIP3
8102E
MDIN3 13 by Robin 080417
R748 0 R0805 EVDD18 Layout Note: R749 2K,1% R0402 RSET 64 RSET LAN_XTALOUT
8101E 8101E 61
C617 C618 C619 Place close to CKTAL2
60 LAN_XTALIN
CKTAL1
C0402
0.1UF/25V,Y5V
C0402
0.1UF/25V,Y5V
C0805
1uF/25V,Y5V
EVDD18 PINS. 62 GVDD
Y6 25MHz
1 2
EGND1
EGND2
(PIN22,PIN28)
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
XS2
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
8101E 8102E C620 C621 C622 C623
C0603 C0402 C0402 C0402
C 1uF/10V,Y5V 0.1UF/25V,Y5V 27pF/50V,NPO 27pF/50V,NPO C
25
31
G1
G2
G3
G4
G5
G6
G7
G8
G9
51
50
42
40
39
35
34
18
17
8101E 8101E RTL8101E-GR
CTRL15 DVDD15
TP3 TP4
Layout Note:
ICTP
ICTP
C624 C625 C626 C627 C628 C629 place close to transformer
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V Layout Note:
C0805 C0402 C0402 C0402 C0402 C0402 place close to IC ns ns
8101E
LAN_TX1+
LAN_TX1-
Layout Note:
LAN_TX0+
LAN_TX0-
Place close to DVDD15 PINS
(PIN15,PIN21,PIN43,PIN49 and PIN58) C630 330PF/50V,X7R
DVDD15 C0603 R752 R753
R750 R751 C631 4.7uF/10V,Y5V 49.9,1% 49.9,1%
49.9,1% 49.9,1% C0805 R0402 R0402
R0402 R0402 C632 330PF/50V,X7R 8101E 8101E
8101E 8101E C0603
C634 C633 330PF/50V,X7R
0.1UF/25V,Y5V C0603 C636
C0402 C635 0.01UF/25V,Y5V
C0402 C0402
0.01UF/25V,Y5V IO_CASE_GND 8101E
8101E
RN27
AVDD18 VDAC 0x4
RA0603_8 IO_CASE_GND
B B
R754 0 R0402 U34 1 2
8101E 3 4 RJ1
TRAN16_50_272 5 6 RJ45
9
7 8 RJ45_S
GND 13 5 RJ45
IO_GND N4 N2
12 N3 N1 4
RJ45_TX0+ 1 TX0+
VDAC LAN_TX0- 9 8 TX0- CHK11 RJ45_TX0- 2 TX0- TX0+
TD- TX- TX1- RJ45_TX1- RJ45_TX1+ TX1+ TX0-
4 L2+ 5L3+ 3
11 6 MCT5 TX1+ 3 6 RJ45_TX1+ RJ45_TX2+ 4 TX2+ TX1+
TDC CMT L2- L3- TX2+
TX0- 2 7 RJ45_TX0- RJ45_TX2- 5 TX2- TX2-
LAN_TX0+ TX0+ TX0+ L1+ L4+ RJ45_TX0+ RJ45_TX1-
10 TD+
1CT:1CT TX+ 7 1 L1- 8L4- 6 TX1- TX1-
ns RJ45_TX3+ 7 TX3+ TX3+
LAN_TX1- 15 2 TX1- 90ohm@100MHz RJ45_TX3- 8 TX3- TX3-
RD- RX- CMC8
14 3 MCT6
RDC RXC
LAN_TX1+ 16 1 TX1+
10
C637 C638 RD+
1CT:1CT RX+
C0402 C0402 Layout Note:
0.01UF/25V,Y5V 0.01UF/25V,Y5V Colay CHOCK AND RN
IO_CASE_GND
MCT5
RJ45_TX0+ RJ45_TX1- MCT6
RJ45_TX2+
RJ45_TX2-
D54 RJ45_TX3+
AZC099-04S RJ45_TX3-
6
SOT23_6
R755 R756 R757 R758 R759 R760

75 75 75 75 75 75
A R0402 R0402 R0402 R0402 R0402 R0402 A
1
Topstardigital
C639
RJ45_TX0- RJ45_TX1+ C1206 K'
1000pF/2000V Page Name PWR/Lan/USB/RJ45 Board
M46G VerB:change the TVS to be near the RJ45 and stuff--xiezx C M21
IO_CASE_GND IO_CASE_GND D
Date: Friday, August 28, 2009 Sheet 51 of 51
to others or used for any purpose other than that for which it was obtained with the
expressed written consent of TOPSTAR
5 4 3 2 1

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5 4 3 2 1

Board name: MotherBoard Schematic 02. System block & Index

56. Power on & off Sequence

Power drawing by: Power check by:

Manager Sign by:

PCI-Express X16 1329 FCBGA DDR2 SODIMM1 23 ICH9_M(2 of 3)

DAUGHTER BOARD DAUGHTER BOARD

ISL6251 44A VR_TT#

DPRSTP# PSI# PROCHOT#

Always_On ICH-M CPU_PWRGD CPU-M

Chipset PWR ISL62382 Page 42

BATT+ +V5AL +V3.3AL +V1.8 +V1.5S +V1.05S +VCC_CORE

+V3.3AL 3.3V always on power rail KB3926

C Board stack up description C

IN2 Trace Impedence:55ohm +/-15%(Default) Power States/AC mode

IN3 S0(Full On) HIGH HIGH HIGH ON ON ON ON

GND S3(STM) LOW HIGH HIGH ON ON OFF OFF

Bottom S4(STD) LOW LOW HIGH ON OFF OFF OFF

0 Express Card Wake up Events

2 USB Port(on Main Board) LID switch from EC

4 Mini PCIE Card(WLAN & ROBSON)

5 Bluetooth ns: Component marked "ns" is not stuff

Schematic modify Item and history:

1.HDMI Level shifter CH7318的第四pin由PU改为PD--PG21

FB271 2 FB0805 +V3.3S_CK_VDD

D FB0805 C351 C347 C0805 +V3.3S_CK_VDD D

CLK_BSEL0 R166 2.2K 27 RN4 3 4 0

CLK_ICH14 C118 10PF/50V,NPO ns

R409 +V1.05S CLK_ICHPCI C117 10PF/50V,NPO ns

http://shop61976717.taobao.com +V1.05S {6,8,9,12,13,14,22,24,31,38,40,41,42,44}

H_A#20 W6 AD3 H_BPM#1 ICTP ns H_D#19 R23 AB22 H_D#51

Y5 A[22]# BPM[3]# AC4 T2 M24 D[21]# D[53]# AC26

A5 C7 D25 AA1 COMP_CPU2 R17 27.4,1% R0402

ns ICTP T13 TP_CPU_RSVD06 RSVD[05] NC R589 routing is reference

PROCESSOR HOT H_THERMDA

EC SMBUS ADD:1001 100X

delete for DFX

Demo:22uF*32 3mOhm 0.6nH U10D

HCPU1 HCPU2 HCPU3 HCPU4

CPU_HOLE CPU_HOLE CPU_HOLE CPU_HOLE

E28 J42 C499 0.1UF/10V,X7R

MA_DATA36 SA_DQ_35 SA_DQS#_7 SB_DQ_35 SB_DQS#_6

AV5 BG26 MB_DATA48 AV2 BB16 MB_B_A10

+V3.3S ns ICTP T32 RSVD1 M36

DDR CLK/ CONTROL/COMPENSATION

C23 CFG_9 DMI_TXP_0 AD35 DMI_RXP0 {23}

ns ICTP T38 P29 CFG_18

R0402 0 R158 AT40 C34 PCIE_CLKREQ# 1K,1%

ns ICTP TP_CN3 BD48 AH34 MCH_CLVREF R353 R0402

ns ICTP TP_CN10 BG45 E36 +V1.05S 1 Q16 C0402 R0402

T108 NC_23 HDA_SYNC AZALIA_HDMI_SYNC {22}

VCC GFX NCTF

VSS_67 VSS_166 VSS_266 VSS_NCTF_7 VCC_AXG_23

VSS_79 VSS_178 VSS_278 VSS_SCB_2 VCC_AXG_35

VSS_93 VSS_192 VSS_292 NC_34

R648 R0603 0 +3.3S_A_CRT_DAC

C 10UF/6.3V,X5R 1uF/10V,X7R AN17 AG24 C

R0402 VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 C0402 C361 R420 R0603 300ohm@100MHz,1.5A VCC_NCTF_16

VCC_HV_3 C0402 +VCC_PEG +V1.05S VCC_NCTF_26

VCC_PEG_1 V48 +VCC_PEG R379 0 R0805

M25 U46 1uF/10V,X7R C0805 10uF/6.3V,X5R +V1.05S AC29

+V1.05S_PEGPLL VCC_DMI_3 VCC_NCTF_38

L37 VCCD_LVDS_2 VTTLF1 A8 VCC_NCTF_43 AK24

use 48Mhz crystal　 J13A PWR_SW2