百胜mylab30英文维修手册 unlocked PDF

ESAOTE S.p.A.
November 2005
Rev.C
7300
SERVICE MANUAL
8310057000
Introduction
This manual describes for the Service technicians the 7300 system functions
and the block diagram of the boards that implements these functions.
The service manual is available in English only.
The manual is addressed to all the Service centres directly authorised by

ESAOTE. All the operations described in this manual are not critical from a
safety point of view.
Do not attempt to service 7300 unless this service manual has been consulted
and understood.
The enter and context menu keys are respectively indicated as ENTER and
UNDO keys in this manual.
ii
Sections Overview
This Service Manual is composed of the following sections:
• Section 1: 7300 Service Characteristics

• Section 2: Disassembling/Assembling
• Section 3: 7300 Block Diagram
• Section 4: Parts Lists
• Section 5: Configurations and Calibrations
• Section 6: Maintenance Procedures
• Section 7: Troubleshooting
• Section 8: Check Lists
• Section 9: Boards Electric Diagrams
In this manual a WARNING pertains to possible injury to the operator. A

CAUTION describes the precautions which are necessary to protect the
equipment. Be sure that you understand and observe each of the
cautions and warnings.
iii
iv
Table of Contents
Section 1
1- Service Characteristics.............................................................................................................1
Identifying the boards ......................................................................................................................1
Configuration Screen .......................................................................................................................1
General .........................................................................................................................................2
Boards ..........................................................................................................................................2
Firmware ......................................................................................................................................3
Demo Licenses.............................................................................................................................4
Machine Self-test .............................................................................................................................4
Configuration Conflicts....................................................................................................................5
Updating the device .........................................................................................................................5
2- Equipment ................................................................................................................................7
Disassembling equipment ................................................................................................................7
Etafoam support ...............................................................................................................................7
Service procedures ...........................................................................................................................8
USB Pen Drive and Re-writable CD................................................................................................8
3- Precautions ...............................................................................................................................9
Section 2
1- How to remove the 7300 covers and gain access to the trackball, the loudspeakers, the fan..1
Trackball ..........................................................................................................................................1
Lower Cover ....................................................................................................................................1
Tools ............................................................................................................................................1
Removal procedure ......................................................................................................................1
Assembly procedure.....................................................................................................................2
Spare code ....................................................................................................................................2
Loudspeakers ...................................................................................................................................2
Tools ............................................................................................................................................2
Fan....................................................................................................................................................3
Tools ............................................................................................................................................3
Trackball ..........................................................................................................................................3
Tools ............................................................................................................................................3
LCD Covers .....................................................................................................................................4
Tools ............................................................................................................................................4
Spare code ....................................................................................................................................4
Right Cover ......................................................................................................................................5
Tools ............................................................................................................................................5
v
Rear Cover .......................................................................................................................................5
Tools ............................................................................................................................................5
Spare code ....................................................................................................................................5
Left Cover ........................................................................................................................................5
Tools ............................................................................................................................................5
2- How to remove/reassemble the 7300 internal parts .................................................................7
Boards position ................................................................................................................................7
Input Board ......................................................................................................................................7
Tools ............................................................................................................................................7
TRX1/TRX2, Control and Doppler Boards .....................................................................................8
Video Board .....................................................................................................................................9
Tools ............................................................................................................................................9
Processor Board ...............................................................................................................................9
Tools ............................................................................................................................................9
Removal procedure ....................................................................................................................10
Assembly procedure...................................................................................................................10
Programmed Hard Disk .................................................................................................................10
Tools ..........................................................................................................................................10
Power Supply Board ......................................................................................................................10
Tools ..........................................................................................................................................10
LCD Display ..................................................................................................................................11
Tools ..........................................................................................................................................11
Spare code ..................................................................................................................................12
Boards Chassis ...............................................................................................................................12
Tools ..........................................................................................................................................12
CD Burner ......................................................................................................................................13
Tools ..........................................................................................................................................13
LCD Cable .....................................................................................................................................14
Spare code ..................................................................................................................................15
vi
Keyboard Assembly.......................................................................................................................15
Tools ..........................................................................................................................................15
Encoder Knobs...............................................................................................................................16
Tools ..........................................................................................................................................16
Spare code ..................................................................................................................................17
TGC Keyboard...............................................................................................................................18
Tools ..........................................................................................................................................18
PC Keyboard ..................................................................................................................................18
Tools ..........................................................................................................................................18
Spare code ..................................................................................................................................19
Upper Cover...................................................................................................................................20
Spare code ..................................................................................................................................20
Appendix A - Parts Accessing Times ...........................................................................................21
Parts with direct access ..................................................................................................................21
Parts with indirect access ...............................................................................................................21
Section 3
1- 7300 Block Diagram ................................................................................................................1

TRX1 and TRX2 boards ..................................................................................................................7
Control board ...................................................................................................................................9
Doppler board ................................................................................................................................11
Processor board ..............................................................................................................................13
Video board....................................................................................................................................15
Power Supply board .......................................................................................................................17
Keyboard and TGC boards ............................................................................................................18
Section 4
1- Traceability ..............................................................................................................................1
2- Parts List ..................................................................................................................................3
7300 Code 9707300000 100-230V 50/60 Hz ..............................................................................3
7300 Covers .....................................................................................................................................4
Spare Parts List ................................................................................................................................5
3- Hard Disk replacement.............................................................................................................7
Procedure .........................................................................................................................................7
4- Main Power Cables ..................................................................................................................9
Section 5
1- Service Menu ...........................................................................................................................1
vii
Settings Option.................................................................................................................................1
Language Settings Folder.............................................................................................................3
Licenses Folder ............................................................................................................................3
Save and Load Configuration ..........................................................................................................4
Upgrading the 7300..........................................................................................................................4
Firmware Upgrade .......................................................................................................................5
Windows Upgrade........................................................................................................................5
Processors Re-synchronization ....................................................................................................6
2- Hard Disk Menu.......................................................................................................................7
Properties .........................................................................................................................................7
Network Configuration ....................................................................................................................7
IP Address Configuration.................................................................................................................9
Export log files to USB..................................................................................................................10
Recover Archive ............................................................................................................................10
Exams Not Archived......................................................................................................................10
Hard Disk Menu in Archive Review..............................................................................................10
3- PC Printer Configuration Menu and PC Printer Installation..................................................13
Operations ......................................................................................................................................13
Configuration .................................................................................................................................14
Print to PC printer now ..................................................................................................................14
PC Printer Installation....................................................................................................................14
Installation of a PC Printer with pre-installed driver .................................................................15
Installation of a PC Printer.........................................................................................................16
Installation of a Network PC Printer..........................................................................................18
4- Mitsubishi CP750E - Print size settings.................................................................................21
Procedure .......................................................................................................................................21
5- Sony UP-21 MD - Print size settings .....................................................................................25
Procedure .......................................................................................................................................25
6- Mitsubishi CP900E - Print size settings.................................................................................27
Procedure .......................................................................................................................................27
7- AG MD835 - VTR settings....................................................................................................29
Procedure .......................................................................................................................................29
Play Back Quality and Frame Position ..........................................................................................30
VTR Soft Keys...........................................................................................................................30
8- MD3000 - VTR settings.........................................................................................................33
Procedure .......................................................................................................................................33
Play Back Quality and Frame Position ..........................................................................................35
VTR Soft Keys...........................................................................................................................35
9- Report and Measure Configuration........................................................................................37
Report Configuration .....................................................................................................................37
Measure Configuration ..................................................................................................................38
Appendix A - Cables Assembly....................................................................................................39
Section 6
1- Maintenance Procedures ..........................................................................................................1

Trackball ..........................................................................................................................................1
Tools ............................................................................................................................................1
Processor battery cell .......................................................................................................................1
Procedure .....................................................................................................................................2
viii
Tools ............................................................................................................................................2
Procedure .....................................................................................................................................2
2- Safety Test................................................................................................................................5
Definitions....................................................................................................................................5
7300 safety test - Operating Procedures ..........................................................................................6
Tools ............................................................................................................................................6
Measurement of the Impedance of Protective Earth connection .................................................7
Measurement of Earth leakage current ........................................................................................8
Measurement the Enclosure Leakage Current .............................................................................8
Measurement the Patient Leakage Current (ECG cable) .............................................................8
Measurement the Patient Auxiliary Current ................................................................................9
Cart Mod.7310 safety tests.............................................................................................................10
Probe safety tests............................................................................................................................10
Section 7
1- Error messages .........................................................................................................................1

Communication error with the CONTROL BOARD (TGC) and Communication error with the
CONTROL BOARD........................................................................................................................1
Suggestion....................................................................................................................................1
2- Hardware error messages .........................................................................................................3
3- Archiving troubleshooting .......................................................................................................5
Hard Disk Crossed Icon ...................................................................................................................5
Suggestion....................................................................................................................................5
Hard Disk Grey Icon ........................................................................................................................5
Suggestion....................................................................................................................................5
CD Burner and USB Pen Drive Crossed Icons................................................................................6
Suggestion....................................................................................................................................6
4- Shut Down Log File.................................................................................................................7
Procedure .........................................................................................................................................7
Section 8
1- Check List ................................................................................................................................1

Technical Check List .......................................................................................................................1
Maintenance Check List...................................................................................................................2
Stand alone equipment .................................................................................................................2
Full configured equipment ...........................................................................................................2
Section 9
1- Schematic Diagrams ................................................................................................................1

Section 1...........................................................................................................................................v
ix
x
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Service
Characteristics
The aim of this introductory chapter is to illustrate some of the characteristics of
the 7300 of fundamental importance to the technical staff, in particular, where to
find the equipment status and how to keep it up to date.
Identifying the boards

Most boards of the 7300 are identified:
• by its Reference (950..), which is always indicated on the external side

of one pull tab, and its description, which is indicated on the internal
side of the pull tab.
• by the Serial Number (SN), indicated on the external side of the other
pull tab.
• by the Configuration Index (CI), indicated by two decimal figures on
the internal side of the pull tab. The Configuration Index represents
the HW level of the board. The Configuration Index is loaded in
specific components mounted on each board.
• when applicable, by its Firmware (FW) level, displayed in the System
Configuration screen, Firmware Option (see below).
The Input, Keyboard and TGC boards are not equipped with pull tabs thus this
information is on labels affixed on the printed circuit.
Configuration Screen
From the keyboard you can display the Configuration Screen. To do this, press the
key and select SYSTEM CONFIGURATION option. The unit will show:
SECTION 1 1
7 3 0 0 – S E R V I C E M A N U A L
The system configuration screen is organized in four folders:
• General
• Boards
• Firmware
• Demo licenses
To select a folder, useg the trackball to position the cursor over the correct tab and
press ENTER.
General
The screen displays:
Serial number It is the unit serial number
System Software The displayed data indicate:
• the release resident in the Processor board (RES).

• the Output Data System release (ODS).
• the installed SW release (STD)
Video standard It reports which video standard (PAL or NTSC) has been set.
System Licenses The active licences are listed in these fields.

and Licenses
Boards
The BOARDS option has two columns.
SECTION 1 2
7 3 0 0 – S E R V I C E M A N U A L
The “Board” column lists all the installed boards. The “CI” column lists the
Configuration Index (the [NN] figures) of the installed boards.
Firmware
The unit displays:
The Firmware option shows the installed boards equipped with Flash EPROM
(“Board” column) and their Firmware version.
Please note that the Flash EPROMs located on the boards are partitioned into
several sectors. Each sector of the Flash is independent and therefore each of them
can be separately programmed.
SECTION 1 3
7 3 0 0 – S E R V I C E M A N U A L
Demo Licenses
See further in this Service technician can activate the available Demo licenses.
manual to know how
to activate a Demo
license
A demo license lasts two hundreds (200) working hours. The “Demo licenses”
display allows to check the status of the activated demo licenses to be checked.
To exit from the System Configuration screen press OK.
The System Configuration screen can be saved on USB pen drive through
EXPORT option. The system creates a .txt file containing all Configuration Screen
information.
When units ship from Esaote, prints of the initial configuration are placed in a
pocket located on the bottom cover of the device. The technical staff will be
responsible for keeping these prints up to date when the configuration of the
device changes.
Machine Self-test
At power-on, the Processor board executes a self-test to check:
• the Configuration Index and the FW level of the boards

• which SW release is installed
The result of this self-test is displayed for a short time, before the Exam Start
window appears. However you can access to the Configuration Screen in Real
Time or in Freeze by pressing the key and selecting the SYSTEM
CONFIGURATION option.
The initial self-test has a dual function:
SECTION 1 4
7 3 0 0 – S E R V I C E M A N U A L
• “Self-configuration”
If new features have been added (e.g. a new license has been installed), the CPU
automatically reconfigures itself to manage the new devices. The Configuration
display indicates the changes made: with reference to the same example above, the
screen will show the new license name on the “Licenses” field.
• Control
The Processor board checks for internal conflicts and, if there are any, displays a
warning message.
Configuration Conflicts
If there are conflicts between the HW levels of boards or between HW and SW,
the system stops at the General Configuration screen and displays a warning
message detailing the reason of the conflict. For example, the unit displays the
following message:
System Configuration Error: Board(s) not available or not compatible
In the BOARDS option, all the fields that caused the conflict are displayed in red.
If the cause is a board having a configuration index incompatible with the HW
level of the device, the Configuration Index field of that board will be red. This
screen thus represents a useful diagnostic tool for technical staff. This screen may
be bypassed by pressing the CANCEL key and access gained to the Exam Start
window.
Updating the device

Each unit has a CD The 7300 is designed so as to minimize the number of update procedures that
Burner drive installed require changing or replacing hardware in the system. This is possible due to the
on the left-hand side
use of Flash EPROM which may be updated by means of a Compact Disk without
having to disassemble the device.
The SW used on the machine is installed physically on the Processor board: the
procedure for updating the SW release does not require any boards or CI’s to be
changed. As we have seen, the release installed appears on the Configuration
display.
The same philosophy is used for storing all the probe control tables. Whenever the
number of probes managed by the 7300 is changed, the new Acoustic Output
Data must be loaded from a CD.
The release installed in the Flash EPROM is controlled using the Firmware option
of the Configuration screen.
SECTION 1 5
7 3 0 0 – S E R V I C E M A N U A L
If there are conflicts caused by the firmware release installed, the characters of
these fields will be displayed in red.
SECTION 1 6
2
7 3 0 0 – S E R V I C E M A N U A L
Chapter
2 - Equipment
In this chapter are listed the tools you need in order to access the 7300s internal
parts, to activate the Service procedures and to perform a functional test of the
unit.
Disassembling equipment
In order to access the 7300, the following tools are needed:
The disassembling Tool Dimension
procedures are
Dynamometric Phillips electric screwdriver Medium and small tip
detailed in Section 2
Slotted screwdriver Small tip
Tweezers -
The use of an electric screwdriver allows the access time to be minimized. Low
torques are recommended.
In order not to damage the parts during the disassembling procedures, it is

CAUTION
recommended to use the torques values indicated in Section 2.
Etafoam support
Etafoam support If the lower cover is removed, the unit can be switched on only if laying on the
P/N 8107992000 support shown in the following picture.
The support allows the correct air flow to guarantee the unit will not overheat.
SECTION 1 7
7 3 0 0 – S E R V I C E M A N U A L
The unit is prone to overheating if switched on when not lying on the Etafoam
N O T E
support. Once the Power Supply reaches the protection temperature it cuts out
automatically.
Service procedures
Service key The service procedures that require an interaction with the unit, as for example the
P/N 8610264000 language setting, can be activated only through the service key. The service key is
provided with an USB connector and can be inserted in any of the two USB ports
placed on the rear panel.
The key must be inserted before switching on the unit, to be able to access to the
several service menus. If the procedure is not carried out properly, the system
doesn’t allow the access to the menu and, in some cases, the following message is
shown:
The symbol shown on the left is used in this manual to indicate all the procedures
that require the use of the key.
USB Pen Drive and Re-writable CD

To perform a complete check of the unit, it is suggested to always have an USB
pen drive and a re-writable CD. These tools allow the service technician to test the
functioning of the CD burner and of the USB ports.
SECTION 1 8
3
7 3 0 0 – S E R V I C E M A N U A L
Chapter
3 - Precautions
A series of precautions that must be observed each time you perform an operation
on the 7300 are emphasised below:
• the equipment must always be switched off before carrying out any
service operation. In the same way, all the probes and peripherals
(external monitor, printer, video-recorder...) must also be
disconnected.
• the boards may only be removed when the equipment is powered off.
• an electrostatic discharge occurring through the contact with the
operator, can irreparably damage the electronic components on 7300
boards, that are sensitive to electro-static discharges: we therefore
recommend that you take precautions to prevent these discharges each
time a board has to be removed/installed. In operational terms, this
means:
o the machine must rest on an electro-static mat connected to
earth.
o the service technician must also be connected to the same
earth each time he removes or installs the boards.
o the boards and components must always be moved in their
special electro-static containers.
o for the service on the field, use the specific kits including the
anti-static mat.
The chapter entitled “7300 Parts List” details the sub-assemblies that are to be
considered sensitive to electro-static discharges (ESD).
When the board is ESD sensitive, you can find on the PCB master this symbol.
SECTION 1 9
7 3 0 0 – S E R V I C E M A N U A L
SECTION 1 10
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - How to remove the

7300 covers and gain
access to the trackball,
the loudspeakers, the
fan
This chapter describes how to remove/assemble the covers of the 7300 and some
subassemblies. In order to carry out all the removal procedures, you must
disconnect all peripherals connected, disconnect the probes and power cable, close
the LCD screen and, when applicable, remove the system from the cart.
The procedure to gain access to the upper cover is described in the following
chapter, as it requires the removal of the chassis and of many other parts inside the
system.
Trackball
You can access the trackball sphere directly: apply light pressure while turning the
plastic locking ring in a counter-clockwise direction the lift and remove.
Lower Cover
Lower Cover Tools
P/N 9102809000 Tool Dimension
Phillips electric screw Medium tip
¼h
Removal procedure
• Turn the system upside down.
• Remove the seven (7) screws (from A to G) shown in Figure 1 and lift
the cover.
SECTION 2 1
7 3 0 0 – S E R V I C E M A N U A L
Fig. 1
Assembly procedure
Carry out the inverse of the removal procedure.
Recommandation Torque = 0,6 Nm
Spare code
The spare code includes the lower cover and the clear adhesive pocket, where the
system configuration printouts must be inserted.
Once the lower cover has been removed you get access to the trackball assembly,
to the fan and to the loudspeakers.
Loudspeakers
Loudspeaker Tools
Phillips electric Medium tip
screwdriver
¼h
Removal procedure
• Remove the lower cover.
• Disconnect the two (2) cables.
SECTION 2 2
7 3 0 0 – S E R V I C E M A N U A L
• Unscrew the two (2) screws fixing each loudspeaker to the upper
cover.
Assembly procedure
Fan
Fan Tools
screwdriver
¼h
Removal procedure
• Disconnect the power cables both of the fan and of the trackball.
• Unscrew the two (2) screws fixing the fan/trackball group to the upper
cover.
• Remove the fan/trackball group from the chassis.
• Unscrew the two (2) Phillips head screws to free the fan.
Assembly procedure
Trackball
Trackball Tools
screwdriver
¼h
Removal procedure
• Remove the fan/trackball group.
SECTION 2 3
7 3 0 0 – S E R V I C E M A N U A L
• Once access is gained to the fan/trackball group, remove the trackball

(it sits freely in the fan enclosure).
Assembly procedure
LCD Covers
LCD Covers Tools
Phillips screwdriver Small tip
¼h
Removal procedure
• Remove the two little rubber plugs located on the bottom left and
right corners of the LCD front cover.
• Unscrew the two (2) Phillips screws
• The LCD covers are held together by tongue and groove joints:
carefully insert a thin slotted screwdriver in the slit between the front
and rear covers to uncouple them.
• Start in the lower left hand corner and work your way around the LCD
cover loosening the tongue and groove joints.
• Disconnect the two (2) LCD cables connectors.
• Using a thin slotted screwdriver, carefully free the cable from the glue.
The LCD covers could be damaged during the disassembling. It is a good
CAUTION
idea to have spare LCD covers available.
Assembly procedure
The INVERTER pcb that is placed on the LCD front cover, can produce
WARNING!
voltage up to 1600 V, so the maximum care is recommended in connecting
the LCD voltage supply cable
Spare code
The spare code includes the stickers showing the logo (Esaote and Biosound).
Once the covers have been replaced, apply the proper sticker.
SECTION 2 4
7 3 0 0 – S E R V I C E M A N U A L
Right Cover
Right Cover Tools
screwdriver
¼h
Removal procedure
• Release the right cover, by applying a light pressure downwards and
towards the equipment.
Assembly procedure
Rear Cover
Rear Cover Tools
screwdriver
¼h
Removal procedure
Once the right cover has been removed, the rear cover is free (just take it out)
Assembly procedure

Spare code
The spare code includes the 7300 identification label, with the SN and Year of
production fields in blank.
The unit’s data must be copied on the label using an indelible pen, in order to
N O T E
preserve system traceability.
Left Cover
Left Cover Tools
screwdriver
SECTION 2 5
7 3 0 0 – S E R V I C E M A N U A L
¼h
Removal procedure
• Remove the lower, right and rear covers.
• Unscrew the four (4) lateral screws fixing the cover to the chassis.
• Remove the cover.
Assembly procedure
Once removed the lower, rear, left and right covers, you can get access to the
board’s chassis.
SECTION 2 6
2
7 3 0 0 – S E R V I C E M A N U A L
Chapter
2 - How to
remove/reassemble the
7300 internal parts
This chapter describes how to remove/re-assemble:
• the 7300 boards

• the programmed Hard Disk
• the LCD display
• the LCD cable
• the CD burner
• the Keyboard group and the PC keyboard
• the Encoder knobs
• the upper cover
Boards position
Most boards are placed inside the chassis. The Input board closes the chassis and
the Power Supply board is installed on the opposite side of the chassis itself.
The Mother board is affixed to the board’s chassis.
The Keyboard group and the TGC keyboard are fixed to the upper cover.
Input Board
Input Board Tools
P/N 9501075000 Tools Dimension
screwdriver
¼h
SECTION 2 7
7 3 0 0 – S E R V I C E M A N U A L
Removal procedure
• Remove the right cover.
• Unscrew the fourteen (14) screws fixing the Input board to the chassis
• To facilitate extraction, first move the board away from the chassis and
then pull outwards
Assembly procedure
Once the Input board is removed, you gain access to all the boards inside the
chassis as shown in Fig.1.
Fig. 1
TRX1/TRX2, Control and Doppler Boards
¼h
TRX1 Board Removal procedure

P/N 9501076000 • Remove the Input board.
TRX2 Board
P/N 9501077000 • Extract each board from the chassis, using the two black pull tabs (see
Control Board blue arrows in Fig.1).
P/N 9501078000
Assembly procedure
Doppler Board
P/N 9501079000
SECTION 2 8
7 3 0 0 – S E R V I C E M A N U A L
Video Board
Video Board Tools
screwdriver
¼h
Removal procedure
• Remove the right cover and the rear cover.
• Unscrew the two (2) screws (A and B in Fig. 2) fixing the Video board
to the chassis.
• Loosen the two (2) front chassis screws on the left and the two (2)
front screws on the right side of the chassis that attach to the top
cover. This allow the Video board to be removed over the lip of the
top cover of the system.
• Extract the board from the chassis, using the black pull tabs.
Be careful not to damage the copper grounding strip (refer to Section 4 for its
C A U T I O N
P/N).
Fig. 2
Assembly procedure
Processor Board Processor Board

P/N 9501080010
Tools
Tools Dimension
screwdriver
¼h
SECTION 2 9
7 3 0 0 – S E R V I C E M A N U A L
Removal procedure
• Unscrew the two (2) screws (C and D in Fig. 2) fixing the Processor
board to the chassis.
• Extract the board from the chassis, using the black pull tabs.
Be careful not to damage the copper grounding strip.
C A U T I O N
Assembly procedure
Programmed Hard Disk

Programmed Hard Tools
Disk Tools Dimension
P/N 9102650000 Phillips electric Medium tip
screwdriver
¼h
Removal procedure
• Remove the Processor board.
• Unscrew the four (4) screws fixing the Hard Disk to the board.
Assembly procedure

Carefully follow the instruction in Section 3 for replacing the programmed Hard
N O T E
Disk.
Power Supply Board

Power Supply Tools
Board Tools Dimension
screwdriver
¼h
Removal procedure
• Remove the left cover.
SECTION 2 10
7 3 0 0 – S E R V I C E M A N U A L
• Unscrew the eleven (11) screws fixing the board shield to the chassis.
• Remove the shield.
• Unscrew the three (3) screws fixing the board to the chassis.
• Extract the board using the pull tabs.
Assembly procedure
Carry out the inverse of the removal procedure
When inserting the Power Supply, be sure that the board and its internal shield are
N O T E
in good contact. To ease the board installation, keep their alignment and contact.
LCD Display
LCD Display Tools
¼h
Removal procedure
• Remove the LCD covers.
• Separate the strips paying attention to the LCD cable sheath.
Fig.3
• Only once the copper strip has been removed and the cable is
completely free, disconnect the cable from the plug placed on the rear
side of the LCD.
SECTION 2 11
7 3 0 0 – S E R V I C E M A N U A L
• Remove the six (6) screws (three on the left side and three on the right
side), fixing the LCD to the two metallic stirrups.
• Extract the LCD display.
Assembly procedure
When the LCD Display P/N 9102812000 has the C.I. 01 a specific configuration
procedure is required: refer to Section 5 for further details.
Recommandation Torque ≤ 0,198 Nm
The INVERTER pcb that is placed on the front cover, can produce voltage
WARNING
up to 1600 V, so the maximum care is recommended in connecting the
LCD voltage supply cable
Spare code
The LCD display spare part code includes the copper shielding pre-applied to the
back of the display. The adhesive backed copper strip (that is necessary to secure
the LCD cable to the rear side of the display) is also included in the LCD spare
part code as a separate item. The LCD covers P/N 9102810000 are included in the
LCD spare part number.
Boards Chassis
The board’s chassis is not supplied as spare part. The procedure to disassemble it is
described anyway, as it is necessary to gain access to the CD burner, to the LCD
cable, to the Keyboard group, to the PC keyboard, to the TGC keyboard and to
the Upper cover.
The Mother board is fixed to the boards chassis. The UP1 EPROM, that contains
N O T E
the unit SN and its presets, is installed on the Mother board. The 7300 must be
sent to ESAOTE whenever you have to replace the Mother board.
Tools
Tools Dimension
screwdriver
Tweezers -
½h
Removal procedure
• Remove the fan/trackball group.
• Remove the Input board and all the boards inside the chassis.
SECTION 2 12
7 3 0 0 – S E R V I C E M A N U A L
• Loosen the retaining screw “A” screw inside the chassis (rear side) to
remove the cable lock (Fig.4)
Fig.4
• Disconnect the LCD cable from the Mother board side using
tweezers.
• Unscrew the seven (7) screws that fix the chassis to the upper cover.
• Disconnect all the flat cables between the chassis and the keyboard
group.
Assembly procedure
Carry out the inverse of the removal procedure. When re-assembling the chassis,
loosly tighten the cable lock screw to facilitate positioning the LCD cable. This also
allows the lock to be correctly placed. Once correctly placed, complete tightening
the screw.
CD Burner
CD Burner Tools
Tweezers -
½h
Removal procedure
• Free the board’s chassis.
SECTION 2 13
7 3 0 0 – S E R V I C E M A N U A L
• Remove the CD burner by unscrewing the 3 slotted screws.

• Disconnect the flat cable, using the tweezers if necessary.
Assembly procedure
Recommandation Torque = 0,176 ÷ 0,235 Nm
Align the CD burner when re-assembling it. Wrong alignment may block the
N O T E
opening of the CD burner.
LCD Cable
½h
LCD Cable Removal procedure

P/N 9102813000 • Free the board’s chassis.
• Disconnect the LCD cable from the Mother board and let it pass
through the chassis hole (Fig. 5).
Fig. 5
• Remove the LCD covers.

• Disconnect the LCD cable from the LCD itself.
SECTION 2 14
7 3 0 0 – S E R V I C E M A N U A L
Fig.6
Assembly procedure
Spare code
The supplied cable includes its sheath. The adhesive back insulating copper strip is
included in the spare code as a separate item.
Keyboard Assembly
Keyboard Tools
Assembly Tools Dimension
screwdriver
Tweezers -
½h
Removal procedure
• Remove the Video and Processor boards
• Disconnect the LCD cable from the Mother board side
• Remove the boards chassis
• Remove the nineteen (19) screws fixing the keyboard assembly (A-U
in Fig. 7) and disconnect the flat cables.
SECTION 2 15
7 3 0 0 – S E R V I C E M A N U A L
Fig. 7
Assembly procedure
Carry out the inverse of the removal procedure .
Once the Keyboard group has been removed, you gain access to the Silver
keyboard cover (P/N 8107244000) and to the Encoder knobs (P/N 9102815000).
The silver cover is free.
Encoder Knobs
Encoder Knobs Tools
½h
Removal procedure
• The encoder knob is secured to the keyboard by a containment ring.
In order to remove it, pry gently against the ring using a small flat
blade slotted screwdriver as illustrated in Figure 8.
SECTION 2 16
7 3 0 0 – S E R V I C E M A N U A L
Fig.8
• Once the knob is removed, remove also the knob lock as shown in
Fig. 9.
Fig.9
Assembly procedure
When re-assembling the knob lock, align the tongues with the grooves as shown in
Fig. 10 and press to match them.
Fig.10
Spare code
The spare code includes two (2) encoder knobs and two (2) knob locks.
SECTION 2 17
7 3 0 0 – S E R V I C E M A N U A L
TGC Keyboard
TGC Keyboard Tools
screwdriver
Tweezers -
½h
Removal procedure
• Remove the slider caps.
• Remove the board’s chassis.
• Unscrew the five (5) screws fixing the TGC keyboard to the upper
cover.
• Disconnect the flat from the TGC keyboard, using the tweezers if
necessary.
Assembly procedure
PC Keyboard
PC Keyboard Tools
Slotted screwdriver Little tip
Tweezers -
½h
Removal procedure
• Disconnect the flat cable, using the tweezers if necessary.
• Using a thin slotted screwdriver, gently press the little metallic tongues
(shown in Fig. 11) inward that fix the PC keyboard to the chassis.
SECTION 2 18
7 3 0 0 – S E R V I C E M A N U A L
Fig.11
• Remove the three (3) the elastomer strips..

• Extract the PC keyboard.
Assembly procedure
Spare code
The PC keyboard spare code includes a adhesive backed elastomer strip. Once the
PC keyboard has been installed on the upper cover, the strip must be cut and
attached according to the locations and dimensions indicated by Number 013 in
Fig. 12.
Fig.12
SECTION 2 19
7 3 0 0 – S E R V I C E M A N U A L
Upper Cover
½h
Upper Cover Removal procedure

P/N 9102816000 • Remove the loudspeakers.
• Remove the LCD display.
• Remove the keyboard assembly, the TGC keyboard and the PC
keyboard.
Assembly procedure
Spare code
The upper cover spare code includes the two stirrups holding the LCD panel. It
also includes the product label, to be attached in the proper position, when the
assembly procedure is completed.
SECTION 2 20
A
7 3 0 0 – S E R V I C E M A N U A L
Appendix
Appendix A - Parts
Accessing Times
This evaluation refers to the 7300 only: the system is considered removed from the
cart and free from all the peripherals and probes.
Note: the accessing time has been qualified by multiples of 15 minutes
Accessing times have been get using electric screwdriver, straight screwdriver and
tweezers.
Parts with direct access

Part Parts to be removed Time
Trackball Trackball sphere ¼h
Lower cover n.7 screws ¼h
LCD covers n.2 screws ¼h
Parts with indirect access

Right cover Lower cover ¼h
Rear cover Right cover ¼h
Left cover Lower cover + n.4 screws ¼h

Loudspeaker Lower cover + n.2 screws ¼h
Fan Lower cover + n.2 screws ¼h
Trackball group Fan + n.2 screws ¼h
SECTION 2 21
7 3 0 0 – S E R V I C E M A N U A L

Input board Right cover + n.14 screws ¼h
Video board Input board + n.2 screws ¼h
Processor board Input board + n.2 screws ¼h
Power Supply board Left cover + n.14 screws ¼h
TRX1, TRX2, Control, Input board ¼h
Doppler boards
Programmed HD Input + Processor boards ¼h
LCD Display LCD covers + n.6 screws ¼h
Rack (Board chassis + Input board + All internal boards + ½h
Mother board) CD burner + n.7 screws
Keyboard group Input board + Video & Processor ½h
boards + Rack + n.19 screws
TGC Keyboard Input board + Video & Processor ½h
PC Keyboard Input board + Video & Processor ½h
boards + Rack
CD Burner Input board + Video & Processor ½h
LCD Cable Input board + Video & Processor ½h
boards + Rack + LCD Covers
Upper cover group LCD display + LCD cable + ½h
Keyboard group + TGC keyboard
SECTION 2 22
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - 7300 Block Diagram

This chapter contains the block diagram descriptions for each board. The general Block Diagram
shows the relationships of each board having a unique function within the overall unit.
SECTION 3 1
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 2
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 3
1 2 3 4 5 6 7 8 9 10 11
9501082000
MOTHER BOARD
F
9501083000
POWER SUPPLY
J1 P1
J2 P2
9501075000 2200000161 J5 J6 P1
9501085000 9730640009
INPUT
J3 P3 KEY BRIDGE KEYBOARD PC
E 9501076000
J5 P5
TRX1
J4 P4
Probe A
8830740000 P1
3400000048
N TRACKBALL
J?
L
9501077000
J6 P6
TRX2
J7 P7
9501112000
CDRW BRIDGE
Probe B
D J6 2200000155 J1
9102616000
9730650075 VENTILATORE
Le informazioni contenute nel presente disegno sono proprieta' di ESAOTE S.p.A. e sono riservate;
The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
CDRW
document may be reproduced, copied distributed or in any way exploited.All rights reserved.
Ne e' vietata la riproduzione e la diffusione in qualunque modo eseguita.Tutti i diritti riservati.
9501078000
CONTROL
Probe C
9501084000
KEYBOARD
J3 9102615000
LOUDSPEAKER R
9501079000 P2
DOPPLER J5 2200000155 J?
C 9102615000
P3
LOUDSPEAKER L
P1
J4 2200000156 J?
P4
9501080000 9501117000
PROCESSORS KEY BOARD TGC
J4 2200000161 J1
9501115000
B 9501081000 INVERTER LCD
VIDEO
P7 J1 J2 P2
J3 P1 3900000023
DISPLAY LCD
8830739000
A
837 0147 042 Rev.A
FORM:
SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION:

GENERALE 7300
A2 A.BERTINI G.DONNINI A.BERTINI 01/04/04
Document Revision: SHEET: OF:
by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 7300 000 SB A 1 1
DOCUMENTO FIRMATO ELETTRONICAMENTE - DOCUMENT ELECTRONICALLY SIGNED
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 4
7 3 0 0 – S E R V I C E M A N U A L
Input board
The probes are physically connected to the Input board: this board's main function is that of
connecting the active connector to the Front End.
Three (3) connectors are fitted to the board: two of them are 192 channels connectors for the
electronic probes (CONN. A, B), and the third is for the Doppler probe (CONNECTOR PEDOF).
The connectors of the electronic probes are connected to the 192 CH SWITCH block that sends
signals (192 CH bi-directional bus) coming from the active electronic probe (A/B) to the Front End.
The INPUT CONTROL block has two functions:
o to send the active probe identification code to the Control board.
o to have the board configuration which is displayed in the System Configuration screen.
SECTION 3 5
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 6
FORM:
837 0147 043 Rev.A The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
by EdP
SHEET
A3
B
A
C
D
1
2
B
A
PEDOF
CONNECTOR
CONNECTOR
CONNECTOR
192 CH
192 CH
3
ELT
ELR
TO TRX1
FROM TRX2
4
CODE
Nr. O.V.:
E.O.C. EVENT:
PREPARED BY:
A.BERTINI
5
CONTROLLED BY:
G.DONNINI
INPUT
192CH
SWITCH
CONTROL
APPROVED BY:
A.BERTINI
DATE:
6
06/03/04
Number:
PROBE A/B
Document
DESCRIPTION:
TO CONTROL
192 CH

7
INPUT BOARD
950 1075 000 SB
Revision:
A
8
TO/FROM TRX1-TRX2
SHEET:
1
OF:
1
7 3 0 0 – S E R V I C E M A N U A L
TRX1 and TRX2 boards

The TRX1 board, together with the TRX2 board, manages the Reception/Transmission from and to
the probes. The TRX 1 board manages 96 channels, as does the TRX2 board; therefore the 7300
manages electronic probes with 192 elements. Moreover both the TRX1 and TRX2 boards manage
the CW Doppler. The TRX2 transmits the CW Doppler signal; its reception is managed first by the
TRX1 board then by the TRX2 one.
The transmission pulses, generated by the TX TRXCELL (96 high voltage transmitters), are sent
directly to the electronic probe (CER signals). The signals coming from the probe are input to the
PRE TRXCELL blocks where they are pre-amplified. They then enter the MUX RX_CELL blocks
to be summed before being sent to the internal bus.
The internal bus is a 64 channels one: each TRX board will therefore allow to obtain 32 channels to
be obptained as output. The 96 ECH input signals (64 in case of PA probe), are summed with a
proper delay in order to reduce the channels number.
Once summed, the signals enter the VGA-AD DIG CELL blocks, a variable gain amplifier chain that
depends on the TGC curve set by the user. In the same blocks each signal is digitally converted.
The signals then enter the two receiving blocks RX1 and RX2 (two FPGA devices) that delay, sum
and filter the signals so that the output of the board is a 16 bit data, which represents the RF signal,
that are sent to the Control board.
The Control board loads all the information concerning the delays for the reception into RAM
blocks, delays that are depending on the active probe. The appropriate delays are then sent to the
specific FPGA. The CONTROL block is the interface between the RAM and the Control board.
The SWITCH MATRIX block in the TRX1 board is involved in the CW Doppler reception. It
receives the CWCH signals coming form the MUX RX_CELL and delays them for the focalization.
The NOTCH FILTER eliminates the Doppler frequency emitted in the event of CW. The signal is
then sent to the TRX 2 board (CW PROCESSOR block) where the Doppler signal is processed
before being de-modulated by the Doppler board.
SECTION 3 7
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 8
1 2 3 4 5 6 7 8 9 10 11
FDL,/ADD SC
49 32
FDA-C0 3 +1V5A,+1V5B,+1V8A,+1V8B,+2V5
ADCK0
TXH0 CER1 ECH1
F TX 1 PRE 1 ECH1 SCA-B0 2 ADCK0-15
RXCT
ECH65
POWER DISTRIBUTION
TXL0 TRXCELL(1/4) TRXCELL(1/4) BCH1
VGA+A/D 1 AD000-9 16 20
+2V2
MUX 1
/ADD TGC
CK40
ECH129
DIG-CELL(1/2) MUX
RX_CELL(1/2) CWCH1
TXH1 CER2 2 GSEL0-1
INTERFACE
ECH2
TX 2 PRE 2 XC2V100 10 RX
ADDATA 10X16 RXADD
TXL1
TRXCELL(2/4) TRXCELL(2/4) RAM 256Kx16 INTERFACE
160
CLOCK DISTRIBUTION
RXADB,RXOEB,RXWEB,RXCEB,RXADSCB
16 7
TRXCK0
RX2
TXH2 CER3
12
ECH3
TX 3 PRE 3
TXL2
TRXCELL(3/4) TRXCELL(3/4)
16
XTXRES,MOD,STB 3
E CONF
PREV0-15,RXSP
CK40
IDX1
6
CONF
6
ADCK16-32
CONFOE
16
CK40
10
RXADD
XC2V1000
RAM 256Kx16
ADDATA 10X16
160
RXADA,RXOEA,RXWEA,RXCEA,RXADSCA
16
FEXPRG,FEXCCLK,FEXDATA,FEWE,FECS0-3
RX1 12
XINIT,XDONE
D XC2S300E
32 CH MUX
96CH TRANSMITTER 16 XILINX BOOT
96CH PREAMP CONTROL FEXINIT,FEXDONE
RXCT
32CH VGA+A/D 20 11
CK40
IDX0
XTXSTB,RES,MOD
CK40
TXH RLB
C 96 TX 16
XC2S300
RAM 256Kx16
INTERFACE
TXADD,TXOE,TXWE,TXCE,TXADSC
16
TXL 22
TX
96
16
TXCT
DREADY0
10
CONTROL
FERW
INTERFACE
FEPRG
DTSB,DRES
B
TXSTB,TXRES,RXSTB,TXFRAME
CWCH
4
32
RAM 128Kx8
LQ
SWITCH MATRIX CW
P? 5
SIGA,B 8
INTERFACE
2
19
FES
RX
CW 3
PEDOF
8
SADD
20
SWITCH 3
SUMA,B
NF
A ECH32
FDA-C15 3
ADCK31
FILA;B
2
837 0147 042 Rev.A
CK40
SCA-B15 2 NOTCH FILTER
ECH96 BCH32
VGA+A/D 32
FORM:
2
AD310-9
SELPED
MUX 32
TXH95 CER160 ECH160 /ADD TGC
ECH160
TX 96 PRE 96
RX_CELL(2/2) CWCH32
DIG-CELL(2/2)
TXL95 2 GSEL0-1

TRX1
by EpD
Nr. O.V.:
1 2 3 4 5 6 7 8 9 10 11
FDL,/ADD SC
49 32
FDA-C0 3 +1V5A,+1V5B,+1V8A,+1V8B,+2V5
ADCK0
TXH0 CER1 ECH1
F TX 1 PRE 1 ECH1 SCA-B0 2 ADCK0-15
RXCT
ECH65
POWER DISTRIBUTION
TXL0 TRXCELL(1/4) TRXCELL(1/4) BCH1
VGA+A/D 1 AD000-9 16 20
+2V2
MUX 1
/ADD TGC
CK40
ECH129
DIG-CELL(1/2) MUX
RX_CELL(1/2) CWCH1
TXH1 CER2 2 GSEL0-1
INTERFACE
ECH2
TX 2 PRE 2 XC2V100 10 RX
ADDATA 10X16 RXADD
TXL1
TRXCELL(2/4) TRXCELL(2/4) RAM 256Kx16 INTERFACE
D40M
160
RXADB,RXOEB,RXWEB,RXCEB,RXADSCB
16 8 80MHZ E
RX2
TXH2 CER3
12 CLOCK DISTRIBUTION
ECH3
TX 3 PRE 3
TRXCK0
TXL2
16
XTXRES,MOD,STB 3
E CONF
PREV0-15,RXSP
CONF
CK40
IDX1
6
6
CONFOE
ADCK16-32 ICONF
16
CK40
6
INPUTCONFOE
10
RXADD
XC2V1000
RAM 256Kx16
ADDATA 10X16
160
RXADA,RXOEA,RXWEA,RXCEA,RXADSCA
16
FEXPRG,FEXCCLK,FEXDATA,FEWE,FECS0-3
RX1 12
XINIT,XDONE
D XC2S300E
32 CH MUX
96CH TRANSMITTER 16 XILINX BOOT
96CH PREAMP CONTROL FEXINIT,FEXDONE
RXCT
32CH VGA+A/D 20 11
CK40
IDX0
XTXSTB,RES,MOD
CK40
TXH RLB
C 96 TX 16
XC2S300
RAM 256Kx16
INTERFACE
TXADD,TXOE,TXWE,TXCE,TXADSC
16
TXL 22
TX
96
16
TXCT
DREADY0
10
CONTROL
FERW
INTERFACE
FEPRG
DEMODULATOR SIGNALS
B
TXSTB,TXRES,RXSTB,TXFRAME
CW DOPPLER PROCESSOR WALL FILTERS

LQ
CW
FILA,B
5
3
INTERFACE
2
FES
2
2
SADD
SUMA,B
20
PEDOF PULSER
A ECH32
FDA-C15 3
ADCK31
TX PEDOF TX PEF
837 0147 042 Rev.A
CK40
CK80
SCA-B15 2
ECH96 BCH32
VGA+A/D 32
FORM:
AD310-9
MUX 32
TXH95 CER160 ECH160 /ADD TGC
ECH160
TX 96 PRE 96
RX_CELL(2/2) CWCH32
DIG-CELL(2/2)
TXL95 2 GSEL0-1

TRX2
by EpD
Nr. O.V.:
7 3 0 0 – S E R V I C E M A N U A L
Control board
The Control board is a complex board that implements several functions:
1. it initialises the RX1 and RX2 blocks in the TRX1 andTRX2 boards. (FPGA
CONFIGURATION and TRX CONTROL INTERFACE blocks)
2. it programs all the RAMs on the Front End boards involved in the signal reception.
(FOCALIZATION DELAY block)
3. it manages the Front End boards (TRX1, TRX2) during the acquisition scanning
(SCANNER CONTROL block).
4. it processes the radio-frequency signal. (RF DATA PROCESSING, RF LINE MEMORY

and DYNAMIC FILTER blocks)
5. it detects the TGC gains so that the corresponding curve can be generated. (TGC & GAIN
block)
6. it manages a mechanical probe. (MOTOR INTERFACE block)
7. it detects the temperature sensor of the connected probe (TGC & GAIN block).
8. it sends the Clocks to the other digital boards. (CLK block)
9. it implements the scan conversion, generating the memory writing addresses (RHO,
THETA-X, Y CONVERSION, RHO-THETA INTERPOLATION blocks)
10. it applies post processing elaboration (persistence) process to BW, CFM and Contrast data
(PERSISTANCE MEMORY, PERSISTANCE & AVERAGE PROCESS blocks).
11. it manages the scanning generating the proper timings for the Doppler board (PRF TIMING
block).
12. it identifies the connected probes and the active one (PROBE AND READ SELECTION
block).
SECTION 3 9
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 10
1 2 3 4 5 6 7 8 9 10 11
Processor Bus
(LA 0-4, LD0-15
LRW, LSCNT, LSSCAN,
LSGW, LSGR)
Control DSP
F Control DSP Bus Processor Interface CK40E
(Tca 0-19, Processor Interface POS
Tcd 0-31) to PROCESSOR
Scanner
to TRX1, TRX2 SCSTOP
Control TRX Control SADD 0-19, RLB 0-15, LQ 0-2,
Micro
TCINT 0-3 FES 0-2, FEPRG, FERW, HF0-2, MOT0, MOT1, PROBE
& Interface TXSTB, TXRES, RXSTB, PI, TXFRAME DL, ML, IL, ACFM0-1
FEXDONE0-1, FEXINIT0-1, X-Y(0-8)
FEXCCLK0-1,FEXPROG0-1 TXS, TCLK, DPTCK
FPGA Scan Converter
to
SCAN_MODE(0-9) VIDEO
TCRESET,FLASH
Configuration TXS, DPTCK
Interface SCCTRL 0-13, SCCTRLRW, SCCTRLCS
(Rho,Theta) - (X,Y)
MCYCLE_START
& to on board FPGA Conversion MRESET_DONE from
E VIDEO
XDATA 0-7, RFXPROG, RFCSA-B
Focalization CK40B FPGA Configuration DDOT,DLINE from
RFXDONE, RFXINIT, RFXCCLK
CK40A Interface DP1D(0-7) DOPPLER
Delay SCXPROG, SCXCS0-1, SCXDONE,
QM1D(0-15)
Line Line
SCXINIT, SCXCCLK, Ping Pong Ping Pong
Memory Memory
1 2 DP2D(0-7)
BW1WE,BW1OE
BW1A(0-18) QM2D(0-15)
from/to CFM1A(0-18)
KEYBOARD TGC
Ping Pong Memory BW2WE,BW2OE
POT 0-6 BW2A(0-18)
TGC, DGAIN Control CFM2A(0-18)
POTREF to TRX1, TRX2
TGC & Gain
TEMP 1-2, TSENSE, PSENSE, POFFS
D
VREF CFMPWE,CFMPOE
CFMPA(0-18)
BWPWE,BWPOE
from/to
RF Line Board CNPWE,CNPOE
INPUT TCRESET,FLASH
Memory BWPA(0-18)
Boot
CK40D
TXS, DPTCK
from
TRX1
ADIG 0-15 RF Data
BWD0-7, CND0-7
from Processing Frame Frame
SCCLK0,SCCLK1
BDIG 0-15 DDOP 0-19 to DOPPLER
THETA_WEIGHT(0-3)
TRX2
Ping Pong Persistence Ping Pong
LINK(0-15)
RHO_WEIGHT(0-3)
C
Memory Memory
Memory
CONF 0-5 1 2
RFI 0-15 FIROUTCK Board to/from
REAL 0-15
IMG 0-15 Revision CONFOE 0-2 TRX1, TRX2
CFM1D(0-15) BW2D(0-7)
CK40 A-F
BW1D(0-7) BWPD(0-7) CFM2D(0-15)
Dynamic Filter CFMPD(0-23)
from D5M GSEL0-1 to TRX1, TRX2 CNPD(0-7)
TRX2 to POWER SUPPLY
CK40C TXS, TCLK, DPTCK to DOPPLER, VIDEO
D40M
CLK D40A
B to PROCESSOR CFMON, CFMOFF, MLN0-3, ACFM, DL
to DOPPLER
PRF Timing
D40B MOT0, MOT1, PROBE
to DOPPLER to PROCESSOR
DL, ML, IL, ACFM0-1
D40C
RHO - THETA
to VIDEO MOT0, MOT1, PROBE
Interpolation SCAN_MODE(0-9)
DL, ML, IL, ACFM0-1
Probe Read SELPED, SELA/B, PED, PBA/B TXS, TCLK, DPTCK
AVG_DATA(0-15)
to
& Selection to INPUT, TRX1, TRX2 VIDEO
MCYCLE_START
SCSTOP MRESET_DONE from
CK40F VIDEO
DSP Persistence
Tcint 0-3 Test DAC
&
Interrupt BWD0-7, CND0-7 CFMD(0-17)
A Average DPD(0-7)
837 0147 042 Rev.A
DDOT,DLINE from
process
FORM:
MPH 1-4 DOPPLER

MOTOR Interface to INPUT

SCHEMA A BLOCCHI CONTROL 7300
A2 MOGLIA DONNINI BERTINI 23/06/04
by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1078 000 SE A 1 1
7 3 0 0 – S E R V I C E M A N U A L
Doppler board
The Doppler board receives the radio frequency signal and extracts the Doppler (CW, PW and CFM)
information. The PW and CFM signals are digital data coming from Control board while the CW
signal CW coming from TRX2 board is analog.
The CFM SIGNAL DEMODULATION & LP FILTERING block filters the CFM data, de-
modulates it to extract the phase and quadrature components. The MTI FILTERING block extracts
the high frequency components of the signal that are associated with the moving targets. The
AUTOCORRELATION & CFM PARAMETERS ESTIMATION extracts information concerning
the speed, variance and power of the color signal.
The PW SIGNAL DEMODULATION & LP FILTERING + CW SIGNAL DIGITIZING block

de-modulates the Doppler signal and digitizes the CW Doppler signal. The DOPPLER
PROCESSING block receives the de-modulated Doppler signal, extracts its audio component and
calculates the Fourier transform.
SECTION 3 11
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 12
1 2 3 4 5 6 7 8 9 10 11
XIL1_40M XIL1_40M XIL2_40M , XIL3_40M
XIL1_TXS XIL1_TXS XIL2_TXS , XIL3_TXS
XIL1_DPTCLK XIL1_DPTCLK XIL2_DPTCLK , XIL3_DPTCLK

F
RFII MTI CORRELATOR
AUTOCORRELATION VEL
SIN I
to CONTROL BOARD
CFM SIGNAL
CSIN(15:0) CFI(15:0)
&
DEMODULATION MTI FILTERING
E
CFM IN CFM POW
DDIG(15:0)
& (DC REMOVAL)

COS Q PARAMETERS
LP FILTERING CCOS(15:0) CFQ(15:0) VAR
from CONTROL BOARD
ESTIMATION CFMD(15:0)
D
CPU INTERFACE DSP
PW IN PW SIGNAL DATA & COMMANDS

DDIG(15:0)
DOPPLER FFT DATA to CONTROL BOARD
PROCESSORS
DEMODULATION ED(31:0)
C DPD(7:0)
BOARD
CPU & ADDRESSES

from
PROCESSING
LATCHES LP FILTERING EA(23:0)
LCA(4:0) , LC(15:0)
LSDOP, LCRW
+
(AUDIO & FFT) AUDIO SIGNAL to VTR, LOUDSPEAKERS & ETX BOARD
CW SIGNAL ADVOUT , RECOUT
from SPKR1, SPKN1 , SPKR2 , SPKN2
TRX2 CW IN DIGITIZING LINEINADV , LINEINREC
BOARD DSIN , DCOS
XIL0_40M
B
XIL1_40M
XIL0_40M DSP_CLK GENERAL XIL2_40M
XIL0_TXS XIL3_40M
D40B
XIL0_DPTCLK from TIMING DSP_CLK
CONTROL TXS XIL0_TXS
BOARD & XIL1_TXS

DPTCLK
XIL2_TXS
EXTERNAL AUDIO SOURCES from XIL3_TXS
LSGW
BOARD
from VTR & ETX BOARD PROCESSORS XIL0_DPTCLK
LSGR
A
ADVIN , RECIN , LINEOUTADV, LINEOUTREC
BOARD XIL1_DPTCLK
CONFIGURATION XIL2_DPTCLK
837 0147 042 Rev.A
XIL3_DPTCLK
FORM:
BOARD CONFIGURATION
SCHEMA GENERALE LC(5:0)

SCHEMA A BLOCCHI DOPPLER BOARD
A2 GANDINI DONNINI BERTINI 23/06/04
by EpD
Nr. O.V.:
E.O.C. EVENT: Number: 950 1079 000 SE A 1 4
1 2 3 4 5 6 7 8 9 10 11
XIL1_40M
LC(15:0) , LA(4:0) , LCRW , LSDOP
XIL1_DPTCLK
E
TP9
CSIN(15:0) CFI(15:0)
DIGITAL
DEMODULATION
HIGH PASS FILTER
D
DDIG(15:0) &
&
LP FILTERING
CFM GAIN
CCOS(15:0) CFQ(15:0)
TP11
C
AD_MTI(10:0) , LN(3:0) 1J(15:0) , 2J(15:0) , 3J(15:0) , 4J(15:0)
TP6
B
TRACES
TESTSIN(15:8)
MEMORY
TESTCOS(15:8)
BANK
TP8
A
837 0147 042 Rev.A
FORM:
RFII & MTI

SHEET DESCRIPTION:
A2 Document Revision: SHEET: OF:
by EpD Number: 950 1079 000 SE A 2 4

1 2 3 4 5 6 7 8 9 10 11
AD(9:0) , ADA(15:10) , ADB(14:10) , ADP(17:10) , ADQ(14:10) , ADR(14:10)

F
XIL2_40M XIL3_40M
LC(15:0) , LA(4:0) , LCRW , LSDOP LC(15:0) , LA(4:0) , LCRW , LSDOP
XIL2_DPTCLK XIL3_DPTCLK
OCI(15:0)
E OCQ(15:0) M1O(15:0)
MEMORY MEMORY
M1X(23:0) M2O(15:0)
POWER
M2X(23:0) DPO(15:0)
AUTOCORRELATION BANK
CFI(15:0)
BANK CFI(15:0)
ESTIMATION
DPX(23:0) Q(15:0)
AVERAGING DPY(23:0) &

D TP12
CFM POWER
&
CFQ(15:0) CFQ(15:0) PARAMETERS CFMD(15:12) , CFMD(7)
PERSISTANCE
CFMD(11:8) , CFMD(1:0)
EXTRACTION
CFMD(6:2)
VELOCITY
C
TP14
TX(8:0) TY(8:0) VE(7:0) VA(7:0) T0(8:1)
VELOCITY
&
VARIANCE
TABLES
A
837 0147 042 Rev.A
FORM:
CORRELATOR
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE A 3 4

1 2 3 4 5 6 7 8 9 10 11
XIL0_40M DSP_CLK
LC(15:0) , LA(4:0) , LCRW , LSDOP
XIL0_DPTCLK
CPU
DDIG(15:0)
DOPPLER
INTERFACE
EA(23:0)
SIGNAL
&
D
DOPPLER PROCESSING
ED(31:0)
SIGNAL (AUDIO & FFT)
DPD(7:0)
SININ , COSIN
PREPROCESSING
DSIN , DCOS A/D
C
ACLKX0 , ADX0 , ADLL , ADLR
B
AUDIO DAC
&
ADVIN , RECIN , LINEOUTADV , LINEINADV ADVOUT , RECOUT , LINEINADV , LINEINREC , SPKR1 , SPKN1, SPKR2 , SPKN2
AUDIO ANALOG
PROCESSING
A
837 0147 042 Rev.A
FORM:
DOPPLER SIGNAL PROCESSING

SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE A 4 4

7 3 0 0 – S E R V I C E M A N U A L
Processor board
The Processor board contains two CPUs: the central processor (68340 block) and the ETX board.
The two CPUs are interfaced through the block PCI/68K DUAL PORT COMMUNICATION
MEMORY.
The central processor manages the system, contains the resident program and the AOD probe
management tables. Management of graphic memory, physically located on the board itself
(GRAPHIC MEMORY), takes place through the GRAPHIC MEMORY MANAGER and
DRAWING ENGINE blocks thus making it possible to superimpose the graphics on the echo
image.
The central processor also manages the interface with keyboard, trackball and encoders
(PERIPHERALS MANAGER and KEYBOARD ENCODERS TRACKBALL blocks), the VTR
serial interface and the footswitch. The EEPROM block, residing on the Mother board, contains all
the general machine information (configuration, set ups).
On the board is mounted the ETX board that manages digital filing and contains the LAN and USB
connectors. The ETX board has access to the Image and ECG memories on Video board through
the DSP/IMAGE MEMORY DUAL PORT COMMUNICATION MEMORY and ECG IMAGE
MEMORY MANAGER blocks.
The two DSP blocks at start up program the two FPGA 0 and 1. In the DSP1 block the JPEG
compression takes place.
SECTION 3 13
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 14
1 2 3 4 5 6 7 8 9 10 11
FPGA #0
ECG Memory
Internal Connections Only
F
TXD1, RXD1, -RTS1, -CTS1
-DTR1, -DSR1, -DCD1, -RI1
VMD(15..0), VMA(29..0), VMMODE, VMRW, -WMACK

COM1
-VMDS, -VMAS, -VMBH, -VMBL
ECG Image Memory
DSP/ Image Memory
TXD2, RXD2, -RTS2, -CTS2
ED(31..0), EA(21..2) Manager
-DTR2, -DSR2, -DCD2, -RI2 Image Memory
-AWE, -FPGA_WR
Dual Port FIFO
DSP #0
COM2
-WDATA, -WGATE, -STEP
Communication Memory
-DIR, MOT, -RDATA
-HDSEL, -TRK0, -INDEX
Floppy
Disk
+/-USB0
-LSVID, -LSECG, -LSPS, -LSSCAN
USB SDRAM
glue logic -LSDOP, -LSGR, -LSGW, -LSCNT, LC(15..0)
(16MB)
Latches
+/-USB1
E USB
PCI / 68k
+/-LAN_TXD
+/-LAN_RXD
FLASH Dual Port
LAN
(2MB)
SRAM
Communication Memory
(1MB)
CPU_D(15..0), CPU_A(23..0), -CPU_AS, -CPU_DS

PCI_AD(31..0), -PCI_CBE(3..0), -PCI_REQ0, -PCI_GNT0
-PCI_DEVSEL, -PCI_FRAME, -PCI_RST CPU_RW, CPU_SIZE1, CPU_SIZE0, CPU_FC(3..0)
FLASH
-PCI_INTA, -PCI_INTB, -PCI_INTC
-PCI_IRDY, -PCI_STOP, -PCI_TRDY (4MB)
-DSP_SAFE, DSP1T1
R, G, B, HSYNC, VSYNC, DDCK, DDDA
D KB_CLK, KBDAT, MS_CLK, MS_DAT, -EXTDEV

FPGA #1
CLKX0R1, FSX0R1, DX0R1

CLKX1R0, FSX1R0, DX1R0
-TXD, RTS, DTR
-RXD, CTS, DSR, DCD
Debug I/O
68k Bus
68340
glue logic
-TXD1, RTS1, DTR1
ETX PCI Bus
-RXD1, CTS1, DSR1, DCD1
VTR Output
Board
Drawing Engine
XED(15..0), XEA(21..2)
C -XAWE, -XFPGA_WR
DSP #1
Graphics Memory
Manager DM_A(12..0), DM_DQ(15..0)

DM_DQML, DM_DQMH
Grphics
PIDE_D(15..0), PIDE_A(2..0) -DM_RAS, -DM_CAS, -DM_WE
SDRAM
-PIDE_IOWR, -PIDE_IORD DM_BA1, DM_BA0, -DM_CS
-PIDE_DRQ, -PIDE_AK (16MB)
-IOCS16, -PIDE_CS3, -PIDE_CS1
PIDE_INT, PIDE_RDY, -HDRST
Memory
HD FLASH
(2MB)
B
Pheripherals Manager
KB_CLK, KBDAT, MS_CLK, MS_DAT, -EXTDEV
Serialize/Deserializer
Compact
FLASH
SIDE_D(15..0), SIDE_A(2..0), -SIDE_IOWR, -SIDE_IOR

-SIDE_DRQ, -SIDE_AK, -IOCS16, CDOUTR, CDOUTL
-SIDE_CS3, -SIDE_CS1, SIDE_INT, SIDE_RDY, -HDRST
ROW(15..0), COL(15..0)
ENCLA, ENCLB, ENCRA, ENCRB
MM_SO, MM_SI, -MM_HOLD
TRKXA, TRKXB, TRKYA, TRKYB
CDR-W -MM_CS, -MM_WP, -MM_SCK
GRA(15..0), VID_HSYNC, VID_VSYNC -ECG, -POS, -ESCAN, -TBASE, -MOT0, -MOT1, -TIMING, _PROBE
Keyboard, Encoders,
A Video Board
837 0147 042 Rev.A
Trackball, Interrups
EEPROM
FORM:
Elemento non presente sulla scheda

PROCESSORS
A2 MAGHERINI DONNINI BERTINI 28/06/04
by EpD
Nr. O.V.:
7 3 0 0 – S E R V I C E M A N U A L
Video board
The Video board can be divided into three sections:
1. The Video section generating the output signals for external monitors and peripherals. The
image data from Memory section, the ECG trace and the Graphic data enter the RGB
LOOK UP TABLES that supply the digital Video signal to be converted to standard RGB.
For the standard television presentation, the data is sent to VIDEO DAC that convert in the
RGB analogue output signals. The data are sent to VIDEO ENCODER blocks for the color
printer and the VTR. The VHS or S-VHS signals can arrive as input to the Video board from
a VTR. The signal from VTR enters the VIDEO DECODER whose outputs are sent to the
Memory section.
2. The ECG section where physiological signals (the ECG) is processed for presentation on the
board. The ECG signal is sent to the ECG & PHYSIO ELABORATION block via the
ECG & PHYSIO CONTROL INTERFACE. The block filters the notch, extracts the ECG
sync timing and sends the ECG signal to the Processor board (for possible synchronizing
with the ECG being acquired). The ECG data are written into MEMORY ECG TRACE
block. This block sends the data to the Video section for screen presentation.
3. The Image Memory section is where the acquired echo information is physically stored
(SDRAM MODULE block). The section inputs are the acquired echo signal coming from
Control board (acquired echo data), from Processor board (archived data) and from Video
board itself (VTR). The SDRAM block is controlled through SDRAM CONTROLLER, that
provides the Memory addresses and controls.
The TFT BRIGHTNESS CONTROL block manages the LCD brightness that can be adjusted
through the keyboard.
SECTION 3 15
7 3 0 0 – S E R V I C E M A N U A L
SECTION 3 16
1 2 3 4 5 6 7 8 9 10 11
from from
F Control DSP Connector Processor
Processor
Control DSP Bus Bus
MEMORY ECG
(LA 0-4, LD0-15
(Emifa 0-19, Emifd 0-31)
TRACE LSGW, LSGR)
ECG & PHYSIO ( Tmsclk,Emifclk2,
Elaboration Emifce (0-3),Tmsint(0-3)
eawe,eaoe,eare) ECG PHYSIO
&
CIRCUIT CIRCUIT
FPGA MDAT(0-15),MADD(0-11)
RESET,FLASH
Configuration MBADD(0,1)
&
E TFT Brightness
CLK40A Control Ecgsclk,Ecgconv,Ecgdata
Phsclk,Phconv,Phdata
ECG to Processor
ECG & PHYSIO
Control Interface Trace(0-1)

to on board Video Fpga
D Vid_Hsync,Vid_Vsync
FLASH BOOT from on board Video Fpga
Processor
Interface VMA(0-29),VMD(0-15)
to/from Processor
FLASH PROGR
C
FPGA
VXDATA 0-7, VXPROG, VXCS(0-1)
Configuration to on board FPGA
VXDONE(0-1), VXINIT(0-1), VXCCLK
RAM Interface
ECG SAMPLES
BRD(0-7), BRCS, BRWR
PHYSIO SAMPLES to on board D/A
TFT Brightness Lcdsleep

B to TFT
Control Interface
PanPos from TFT
CLK40B
D40C CLK CLK40 A-C

from Control
A
837 0147 042 Rev.A
FORM:
ECG SECTION

SCHEMA A BLOCCHI VIDEO 7300
A2 FERORELLI DONNINI BERTINI 01/04/04
by EpD
Nr. O.V.:
1 2 3 4 5 6 7 8 9 10 11
TIMEBASE
(CONTROL)
F SDRAM MODULE
CLOCK
& CONTROLS TCLK
IMAGE SCAN
U17
(CONTROL)
SCAN SDRAM
AVG_DATA VTR
DATA
VIDEO
CONVERTER
XY_ADD CONTROLLER PATH
E PATH DECODER
SCAN_MODE
VTR IN/OUT
ARCHIVE DATA
& CONTROLS
(PROCESSOR)
U27, U28, U33, U34 U21

DIGITAL
IMAGE
VMA, VMD PROCESSOR WRITEBACK
VISUALIZATION
VIDEO
PATH PATH PATH
FRAME ENCODER
D MEMORY
XILINX U23
U30
PRINTER OUT
ECG
SECTION VIDEO
ENCODER
XILINX U31
ECG TRACE TV OUT

C GENERATOR
BUFFER
U35
RGB
CRT OUT
LOOK UP VIDEO DAC
TABLES
(PROCESSOR)
INTERFACE
GRAPHIC
DATA
GRA GRAPHIC U20

BUFFER
VIDEO SCALER
B
(PROCESSOR)
PULSES
VIDEO
SYNC
VID_HSYNC VIDEO SYNC LVDS
(MOTHER BOARD)
U41
VID_VSYNC GENERATOR RECEIVER
LCD OUT
LVDS
TRANSMITTER
PC DISPLAY IN
(PROCESSOR)
A VGA_LVP
837 0147 042 Rev.A
VGA_LVN
FORM:
MEMORY & VIDEO SECTIONS

SHEET DESCRIPTION:
SCHEMA A BLOCHI VIDEO 7300
by EpD Number: 950 1081 000 SB A 2 2

7 3 0 0 – S E R V I C E M A N U A L
Power Supply board

The Power Supply board is an Alpha Bridge, universal switching board (100-240 V) with PFC
control. The layout has an EMI/RFI filter with the straightened and isolation transfer in cascade. The
secondary contains the DC converters that supply the 5, 3.3 and 2.2 and power supply and the high
voltage for the pulsars and the CW Doppler.
SECTION 3 17
1 2 3 4 5 6 7 8
BUCK
12V VCC
SYNC.
D
3V3
BUCK
LC
3V3A
FILTER
SYNC.
HALF
365V
VAC INPUT FILTER
PFC
2V2
BRIDGE
BUCK LC
2V2A
FILTER
SYNC.
OVER
TEMP
BUCK
+6V
C SYNC.
VBATT
BUCK
-6V
SYNC.
BUCK
OVER +VT
SYNC.
TEMP
B
+AT
FLYBACK LINEAR
JTAG
HI
REGULATOR
-AT
BUS CONTROLLER
5M
FLYBACK LINEAR
LOW
REGULATOR
FAN
CONTROLLER
A
837 0147 043 Rev.A
TEMP
+12V
FORM:

POWER SUPPLY 7300
A3 PATERNO DONNINI BERTINI 02/04/04
by EdP
Nr. O.V.:
7 3 0 0 – S E R V I C E M A N U A L
Keyboard and TGC boards
Under the control of the Processor board, the Keyboard is the interface board so that it manages
the alphanumeric keys, the trackball and the gain encoders.
The TGC board mounts seven (7) potentiometers and the three (3) keyboard leds.
SECTION 3 18
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Traceability
The traceability of a 7300 part can be based on:
• its Serial Number (S/N)

• its Lot Number
The Serial Number of a 7300 part is composed of two (2) or more figures. It is
reported in a label affixed to:
• board: on the pull tabs or on the printed circuit

• unit: on the rear panel
The Lot Number of a 7300 part is always composed of ten (10) numbers: the first
four numbers correspond to the manufacturing year of the part, the remaining six
are progressive figures. It is located on a label affixed to the part chassis.
The following 7300 Part Lists identify all parts that are traceable and their
corresponding traceability key.
SECTION 4 1
7 3 0 0 – S E R V I C E M A N U A L
SECTION 4 2
2
7 3 0 0 – S E R V I C E M A N U A L
Chapter
2 - Parts List
7300 Code 9707300000 100-230V 50/60 Hz
CODE DESCRIPTION QTY TRACEABILITY ESD
9501075000 INPUT 1 S/N Y

9501076000 TRX 1 1 S/N Y
9501077000 TRX 2 1 S/N Y
9501078000 CONTROL 1 S/N Y
9501079000 DOPPLER 1 S/N Y
9501080010 PROCESSORS ASSEMBLY 1 S/N Y
9501081000 VIDEO 1 S/N Y
9501083000 POWER SUPPLY 1 S/N Y
9102814000 KEYBOARD ASSEMBLY 1 - Y
9501117000 TGC KEYBOARD 1 - Y
ESD: Electrostatic Discharge
Read carefully the instructions in Section 2 for spare parts composition and
N O T E
assembling.
SECTION 4 3
7 3 0 0 – S E R V I C E M A N U A L
7300 Covers
No 7300 cover is considered a traceable part or to be sent in advance.
CODE DESCRIPTION QTY
8107248000 RIGHT COVER 1

8107249000 LEFT COVER 1
9102811000 REAR COVER 1
9102809000 LOWER COVER 1
9102810000 LCD COVERS 1
9102816000 UPPER COVER 1
8107244000 SILVER KEYBOARD COVER 1
N O T E
assembling.
SECTION 4 4
7 3 0 0 – S E R V I C E M A N U A L
Spare Parts List

No Spare Part is considered a traceable part or to be sent in advance.
CODE DESCRIPTION QTY
9102812000 LCD DISPLAY 1

9102615000 AUDIOSPEAKER 2
9102615000 FAN 1
3400000048 TRACKBALL 1
8830740000 TRACKBALL CABLE 1
9730650075 CD BURNER 1
9102817000 PC KEYBOARD 1
9102650000 PROGRAMMED HDD 1
9102813000 LCD CABLE 1
8107619000 TGC SLIDER CAP 7
7900000319 COPPER GROUNDING STRING 2
9102815000 ENCODER 2
3400000049 TGC SLIDER POT 7
8830740000 TRACKBALL CABLE 1
2200000155 50 CNT CD BURNER FLAT CABLE 1
2200000155 50 CNT KEYBOARD FLAT CABLE 1
2200000156 30 CNT KEYBOARD FLAT CABLE 1
2200000161 PC KEYBOARD FLAT CABLE 1
2200000161 TGC KEYBOARD FLAT CABLE 1
26222100085 2A 250V T FUSES 2
8107992000 ETAFOAM SUPPORT 1
N O T E
assembling.
SECTION 4 5
7 3 0 0 – S E R V I C E M A N U A L
SECTION 4 6
3
7 3 0 0 – S E R V I C E M A N U A L
Chapter
3 - Hard Disk
replacement
Whenever the programmed Hard Disk has to be replaced, please carefully follow
the detailed procedure below.
Note
The programmed Hard Disk is always delivered by Esaote with the

last software release installed. Please remind to install the last software
release in the unit if not already done.
Procedure
Once the Hard Disk has been replaced and the Processor board has been
reinstalled, set the following parameter:
• Press key and select GENERAL PRESET.

• Set the Data/Time.
• Press OK to confirm.
• Wait till the message appears, press OK and then turn the unit off by
pressing the Shut Down key. Turn the unit on.
• If necessary, re-configure the network (Hard Disk Configuration
menu).
• If necessary, set the DICOM Server and Printer configuration.
See Section 5 for PC • If necessary, install the PC printer and set the printing preferences of
printer installation
procedure
the PC printer (PC Printer Configuration menu).
If the presets (such as User Presets, Probe Presets, Application Measurements
presets) have been previously saved through the option “Save & Load Presets” of
the key, they can be loaded to be restored only when the “Save & Load
Preset” operations are done with the same software release.
SECTION 4 7
7 3 0 0 – S E R V I C E M A N U A L
SECTION 4 8
4
7 3 0 0 – S E R V I C E M A N U A L
Chapter
4 - Main Power Cables

The 7300 unit is equipped with power cord cables having the following
characteristics:
Device Plug Conductors Section Length

Socket #
CEE plug Type 510 IEC Type VII 3 1 mm2 2,5 m
320/C13 CEE(7) VII;
10A-250V 10A-250V
(European)
CEI plug Type 510 IEC Type I/3 CEI 3 1 mm2 2,5 m
320/C13 23-16; 10A-
10A-250V 250V
(Italian)
NEMA plug Type 510 IEC NEMA 5-15; 3 AWG 3m
320/C13 13A-125V 16
13A-125V (Medical
grade)
According to the IEC 60601-1 standard these cables are marked by a competent
body (TUV, UL, IMQ,..).
If these cables can’t be used in your country because of the plug, they can be only
replaced by other power cord cable having the same characteristics including the
Safety mark.
SECTION 4 9
7 3 0 0 – S E R V I C E M A N U A L
SECTION 4 10
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Service Menu
The key provides access to the Service menu. The key can be pressed both in
real-time and in freeze state. The system displays this window:
The Service key is
required
Select the SERVICE option with the trackball and press ENTER to continue. The
system displays the following Service menu:
To access the different folders, position the trackball on the required folder tab and
press ENTER.
Settings Option
This options is internally organized in folders This procedure makes it possible:
SECTION 5 1
7 3 0 0 – S E R V I C E M A N U A L
• To chose the default language and logo

• To set the ECG notch filter
• To set the LCD Display
• To activate Demo licenses
Once entered the SETTINGS option, the system displays:
The menu is organized in three folders.
Parameter Setting • Position the trackball on the field to be changed and press ENTER to
confirm.
• Use the alphanumeric keyboard to type in the characters.
• In the drop down menus, select the required option and press ENTER
to confirm.
The Tab ' key is used to jump over quickly from field to field; the keys Pgup c
and Pgdn d open the drop down menus and scroll among the relevant options.
After the modifications have been confirmed, the system displays the following
message:
SECTION 5 2
7 3 0 0 – S E R V I C E M A N U A L
Language Settings Folder

This procedure is used for choosing the default language, notch filter and logo.
Languages One of the following languages can be set as default one:
• English
• Italian
• French
• German
• Spanish
With the exception of Italian, German, Spanish and French language countries, all
N O T E
7300 units delivered by Esaote have English as the default language.
Logo The logo is used in the screen as the sector orientation icon. Either Esaote (E) or
Biosound (B) logo can be set. No logo can be selected too.
ECG AC Filter According to the mains frequency used in the country, the Notch filter for the
ECG signal must be selected. This is the filter that removes the mains frequency
interference from the ECG signal.
7300 is already set according with the Mains frequency of the country where it will
N O T E
be delivered.
LCD The LCD can be set either as Module 1 or as Module 2. The different settings
depend on LCD Display Configuration Index, as indicated in the below table
Module C.I.
Module 1 00
Module 2 01
N O T E
Software Release ≥ STD 3.21 for MyLab30CV and STD ≥ 1.21 for MyLab25 are
required whenever a LCD display with C.I. 01 is installed.
Licenses Folder
This procedure enables activations of the available Demo licenses and, when
necessary, to disable licenses. Demo licenses last two hundreds (200) working
hours before expiring; once expired, it can not be re-activated. If a demo license is
installed, it is possible to check its expiring date.
To activate a demo license position the trackball on the desired field and press
ENTER to confirm. Use the same procedure to disable licenses.
SECTION 5 3
7 3 0 0 – S E R V I C E M A N U A L
In this example, the

CnTI demo license
can be activated
Save and Load Configuration

This procedure allows to save and retrieve all the factory settings (both user and
service presets), the unit Serial Number and the unit licenses (demo licenses are not
saved!) in the internal E2PROM.
We strongly recommend to save the system configuration whenever the Service

technician modifies the settings and whenever the unit is upgraded.
Upgrading the 7300

Usually the procedure to upgrade a 7300 with a new software release has three
steps:
• Firmware upgrade
• Windows upgrade
• Internal processor re-synchronization
Typically the support used to upgrade the unit is a CD containing all necessary
files.
The upgrading procedure will remove the drivers of all PC printers added by the
N O T E
service. The PC printer driver CDs are necessary to install again the printers.
The upgrading procedure will cancel the network settings. Before starting the
upgrade, copy all the settings so that the network can be configured again.
The upgrading could remove the Dicom settings. Before proceeding with the
upgrade, copy the Dicom configuration (both server and printer) so that Dicom
can be configured again should it be necessary.
SECTION 5 4
7 3 0 0 – S E R V I C E M A N U A L
Firmware Upgrade
The firmware upgrade is performed through the Service menu.
Firmware 1. Turn on the unit with the Service key inserted.

upgrading
2. Enter Real-Time.
procedure
3. Press and verify if there are archived exams. If so, open the first
and last exams and annotate which images are archived and if the
report exists (the same check will be asked at the end of the
upgrading).
4. Access to the Service menu.
5. Select the option “Firmware upgrades” using the trackball and the
ENTER key to confirm.
6. The system displays the window (left)

allowing the selection of the upgrade source
drive. Choose the drive and press OK to
confirm.
7. The system shows a list of the files to be

installed. All the files marked with a cross will
be loaded. Press OK to start the programming
procedure
8. The upgrade procedure is automatically
executed: once reprogramming has been
started, a series of screens indicating the
progress of the upgrade procedure appears on
the display.
9. At the end of the upgrade procedure, the
system displays the Start Exam window.
If the upgrade procedure has not been carried out correctly, an error message will
be displayed to indicate which file has not been reprogrammed correctly. In this
case, the procedure must be repeated.
Windows Upgrade
Upgrading 10. Leaving the upgrading CD inserted, switch the unit off, remove the
procedure service key and then switch the unit on again.
The service key must be removed in order to be sure that the upgrading procedure
N O T E
ends successfully.
11. At start up the HD programming from CD is automatically started.

The upgrade progress can be controlled by pressing the keys Ctrl + Alt
+ from Real-Time: the upgrade status bar is displayed on unit
screen. The upgrade is finished when the following string appears on
the screen:
a:\ghost>
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7 3 0 0 – S E R V I C E M A N U A L
12. Extract the CD and swicth the unit off and on again.
Processors Re-synchronization
Upgrading 13. Wait for the Start End window. During this step (that could last some
procedure minutes) the HD icon stays grey since the system is re-programming
its devices.
14. Press the key.
15. Select “General preset” option.
16. Once you have accessed to the preset menu, press OK to confirm.
17. Wait till the hourglass disappears and then switch the system off by
pressing the STARTEND key (shut down key) for 3 seconds.
18. Turn the unit on and enter Real-Time.
19. Press FREEZE and then POINTER. Verify that there is no purple shadow
around the displayed mouse cursor. If so, insert the upgrading CD and
repeat the procedure starting from point 10.
20. Press and verify the correspondence of the first and last exams.
Should any inconsistency be noted, run the “Recover archive”
procedure (Hard Disk menu).
At the end of the upgrading procedure, insert again the service key to configure, if
necessary, the PC printer, the network and the Dicom server. Remind to save the
new configuration (“Save & Load Configuration” option of the Service menu) and
to print out the new System configuration screen.
Note
If the upgrading procedure is interrupted before its completion,

remember to start it again from the beginning.
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Chapter
2 - Hard Disk Menu

This procedure can be activated only if the Service key is inserted before switching
on the unit.
The Service key is
required To activate the HD Configuration menu the trackball has to be switched to pointer
mode: press FREEZE and then the key to activate it.
Place the pointer on the Hard Disk icon and press UNDO key. The system displays
the following Hard Disk configuration menu:
Hard Disk icon
Place the pointer on the desired option and press ENTER to confirm the selection.
Properties
See the Operator The system displays the free disk space, the name and the IP address of the unit
manuals for further and its AE Title. This option is always available (i.e. it does not require the Service
details
key to be shown).
Network Configuration
This option allows the network to be configured. It is necessary to have a working
knowledge of networking environments. Prior to starting the configuration
procedure, determine characteristics of the network like the addressing mode (fixed
or DHCP), the default gateway IP address, if a DNS server is present and so on.
Thus it is suggested to contact the network administrator before proceeding with
the configuration.
The Network board inside 7300 works at 100 Mbit per second.
N O T E
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Once activated, the equipment displays the Windows® XP Network configuration

menu.
Configuration • Double click on Local Area Connection Network icon.

procedure
• The system displays the following screen:
• Place the cursor on the “Internet Protocol (TCP/IP) option” and

highlight it by pressing ENTER.
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• Place the cursor on “Properties” button and activate it by pressing

ENTER.
• The system displays the following TCP/IP configuration menu:
This menu allows selecting either a fixed IP address or a DHCP (Dynamic

Host Configuration Protocol) address and to set the DNS addresses, when
necessary.
• Set the desired parameters and press OK to confirm.

The network settings will be operative at next start up.
IP Address Configuration
This option allows the user to set the network or to modify some parameters. In
this window the user can define a dynamic or static addressing. In this latter case
the user can set or modify the IP address, the subnet mask and the gateway
address.
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Export log files to USB

This option allows the user to save onto a USB key the log files. To save the log
files, insert a USB dongle into one of the two connectors on the rear panel and
activate the procedure.
Whenever a problem occurs in the field it is strongly recommended to provide

N O T E
Esaote Service with the unit log file.
Recover Archive
The system has been designed to preserve as much data integrity as possible . This
procedure allows rebuilding of the archive, if the hard disk is corrupted.
Do not switch the unit off while this procedure is running. The Hard Disk
W A R N I N G
could be damaged.
Exams Not Archived

See the Operator This option shows the list of exams which have been performed and not archived
manuals for further into the local database. From this window you can select the exams to be saved
details
onto the local hard disk.
Hard Disk Menu in Archive Review

When in Archive Review the Hard Disk configuration menu is different:
The Service key is

required
The last two options of the menu allows to back up and to restore the whole
internal archive or part of it (the exams are in the native format).
Back Up The internal archive can be stored either in an USB pen drive or in a remote disk
Procedure (shared directory in a PC).
• Press ARCHIVE REVIEW key.

• If necessary, select the exams to be backed up.
• Place the pointer on the HD icon and press UNDO.
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• Select the “BACKUP ARCHIVE” option.

• The system displays the following shot:
• Press the DESTINATION button to select the back up folder.
Note
The backup folder has to be empty! The DESTINATION button allows

to create a new folder.
• Once selected press START to copy the internal archive.

During the back up procedure the STOP button interrupts the copy of the internal
archive.
Restore Procedure • Press ARCHIVE REVIEW key.

• If necessary, select the exams to be backed up.
• Place the pointer on the HD icon and press UNDO.
• Select the “RESTORE ARCHIVE” option.
• The system displays the following shot:
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7 3 0 0 – S E R V I C E M A N U A L
• Press the SOURCE button to select the back up folder.

• Once selected press START to copy the internal archive.
During the restore procedure the STOP button completes the copy of the exam
under process and then stops the restore of the internal archive.
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7 3 0 0 – S E R V I C E M A N U A L
Chapter
3 - PC Printer
Configuration Menu and
PC Printer Installation
This procedure can be activated only if the Service key is inserted before switching
on the unit.
The Service key is
required 7300 manages both USB and Inkjet printers. Please refer to web site for the list of
the printers directly managed by 7300.
Once one of this printers is connected, the system automatically recognizes it and
shows the PC Printer Icon on screen.
PC Printer icon
To activate the PC Printer Configuration menu the trackball has to be switched to
pointer mode: press FREEZE and then the key to activate it.
Place the pointer on the printer icon and press UNDO key. The system displays the
following menu:
Place the pointer on the desired option and press ENTER to confirm the selection.
Operations
See the “Operator The operator can control the print queue and set print preferences .
manuals” for further
details
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7 3 0 0 – S E R V I C E M A N U A L
This option is always available (i.e. it does not require the Service key to be shown).
Configuration
This option allows the default printer to be set if more printers have been
configured.
Place the cursor on the PC printer icon and press UNDO key to open the menu.
Select “Set as default printer” to activate it.
Print to PC printer now

See the “Operator This option allows immediate printing without waiting to complete the set printer
manuals” for further format. This option is always available (i.e. it does not require the Service key to be
details
shown).
PC Printer Installation
7300 supports both Laser and Inkjet USB PC printers. Some printers drivers are
already installed on the unit:
Printer Model
Laser B/W HP 1150
Laser CFM Tally 8008
Inkjet Epson C86, HP 1100
These printers can be directly connected to the system.
Refer to the protected Anyway it is possible to connect to the unit any other PC printer, once the printer
web site for further driver is installed on the unit itself.
instructions on PC
printers installation
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Installation of a PC Printer with pre-installed driver

Procedure
• Connect the PC printer to one of the unit USB connector.
• Turn both the printer and the system on.
• Enter real-time.
• Press MENU key.
• Select “Peripherals” option (For MyLab25 software release < STD
1.21 and for MyLab30CV software release < STD 3.21, the
“Peripherals” option is one of the tab of the “General Preset” option).
• The system displays the following menu:
• REC/PRINT fields 1 and 2 are used to select the required peripheral

to be remotely controlled by the keys 1 and 2. Select “Windows
printer” in the desired field to activate the PC printer.
• Once the printer has been set, select the print format on the second
drop-down menu. The available formats are listed below together with
their pertaining icon.
1x1 format 2x2 format
2x1 format 3x2 format
• Wait for the message asking to restart the unit and then switch the unit
off.
• At next start up the unit will display on the right side of the header bar
the PC printer icon alongside with the icon of the selected format.
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7 3 0 0 – S E R V I C E M A N U A L
PC Printer
icon
Installation of a PC Printer
Before starting the installation procedure be sure to have the printer installation
driver CD with you. The procedure runs like a printer installation in Windows.
Procedure
• Connect the PC printer to one of the unit USB connectors.
• Turn both the printer and the system (with the service key inserted)
on.
• Enter real time and press ARCHIVE REV key.
• Press Ctrl + Esc keys to display Windows bar menu.
• Select “Settings” and the “Printers and Faxes” option, as shown in the
below screenshot.
• The system displays the following Windows Printer and Faxes menu:
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• Select option “Add a printer”. The systems displays the Windows new
hardware wizard for printers.
• Select “Install from a list or specific location” as shown in the screenshot and
then press “Next”
• Insert the printer driver CD in the unit.
• Please note that only the printer driver has to be installed! Any other
printer program which might be listed or proposed during this
installation phase has to be disactivated.
• Select “Include this location in the search” and browse selecting only the
Windows-XP printer drivers in the installation CD and then press
“Next”.
• The system starts copying files. When the operation is completed press
“Finish”. The installed printer is displayed in the “Printer and Faxes”
window.
• Print a test page to make sure the printer is functioning properly.
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7 3 0 0 – S E R V I C E M A N U A L
• Proceed with the printer configuration through the MENU key, as

already explained for the printer with already installed drivers.
Installation of a Network PC Printer

It is necessary to have a working knowledge of networking environments: it is
suggested to contact the network administrator before proceeding with the
configuration.
The described procedure refers only to “Point to Point ad hoc” connection: this
connection has to be a stand alone one. During the installation the printer IP
address is required: read the printer instructions to know how to get and set it.
Note
The software release STD ≥ 4.01 is required.
Procedure • Insert the Service Key into the unit and switch it on.
• Enter Real-Time, press ARCHIVE REVIEW and wait until the archive is
displayed.
• Switch the printer on.
• After the printer startup is done, connect the printer with the cross
cable to the unit.
• Press Ctrl + Esc keys to display Windows bar menu.
• Select “Settings” and then “Network connection” to set the unit IP address.
The unit IP address must be different from the Printer one (in the
following pages and shots the printer IP address is supposed to be
192.168.0.246 with subnet mask 255.255.255.0, the unit IP address is
supposed to be 192.168.0.245 with the same subnet mask).
• Double click on “Local Area Network”, highlight the TCP/IP protocol
and then press “Properties”.
• Set the unit IP and subnet mask addresses.
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7 3 0 0 – S E R V I C E M A N U A L
• Press “OK” to confirm and close the window.

• Press Ctrl + Esc keys again to display Window.
• Open the window “Printer and Faxes”” from “Settings” submenu.
• Press “Add a Printer”.
• Press “Next” and insert the printer installation driver CD.
• Select “Local printer” and verify that the box “Automatically detect and
install my Plug & Play printer” is not checked, then press “Next”.
• Select the “Create a New Port” option, set “Standard TCP/IP Port” and
press “Next”.
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7 3 0 0 – S E R V I C E M A N U A L
• Insert the IP address of the Printer (192.168.0.246) in the Add

Standard TCP/IP Printer Port Wizard and a brief description of this
port.
• After the port is configured, a report dialog is presented. Press “Finish”

to close the wizard.
• Press “Have disk” in the Add Printer Wizard to select the proper driver
to be installed and proceed with the installation. Please note that only
the printer driver has to be installed! Any other printer program which
might be listed or proposed during this installation phase has to be
disactivated.
• Press Ctrl + Esc keys again to display Windows bar menu.
• Select “Settings” and then “Printer and Faxes”.
• Right-click on the printer icon and then choose “Properties” from the
menu to set the printing characteristics.
• Set the printer as the default one.
• Print a test page to make sure the printer is functioning properly.
• Proceed with the printer configuration through the MENU key, as
already explained for the printer with already installed drivers.
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Chapter
4 - Mitsubishi CP750E -
Print size settings
Enclosed you will find the instructions to optimise the settings of the Mitsubishi
RGB printer. All the printers delivered by Esaote with the 7300 are already set
according with the Video standard of the country where they will be delivered.
Procedure
1. Connect the RGB printer to the 7300 via the RGB printer cable
8830429000 (do not connect the remote control connector).
RGB printer icon
2. Verify that the printer input switch, placed in the rear panel, are correctly
set:
Switch Set
RGB 75 Ohm
SYNC High
3. Connect the printer outputs to an RGB monitor via RGB cable.
4. Switch the 7300, the printer and the monitor on.
5. Enter Real-Time and press the key.
6. Select GENERAL PRESET, select the Video tab, set the Video standard and
wait for the re-start message.
7. Press the key again and select PERIPHERALS.
8. Set “Mitsubishi Thermal color printer” in one of the fields REC/PRINT 1

or 2.
9. Press OK to confirm and wait for the re-start message.
10. Switch the unit off by pressing the STARTEND key.
11. Switch the unit on.
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7 3 0 0 – S E R V I C E M A N U A L
12. Connect the Printer Remote Control to the RGB printer (REMOTE input
on the printer front panel).
13. Press the printer [DISPLAY] button: it will display the unit screen on the
monitor.
14. Press the [MENU] button to display the Printer Main Menu.
15. With the [∨] and [∧] buttons select the SIGNAL option and enter it by
pressing the [>] button.
16. With the [∨] and [∧] buttons highlight the INPUT option.
17. Scroll the INPUT menu with the [<] and [>] operations buttons and select
the same standard video standard set in the 7300.
18. With the [<] and [>] operations buttons select the CUSTOM option and
enter it by pressing the [>] button.
19. Set the following values (use the [>] and [<]operation buttons to change
each field, use the [∨] and [∧]operation buttons to scroll the menu):
Field PAL NTSC

H width 894 762
H dots 673 643
V dots 512 484
H posi 160 95
V posi 73 30
20. Verify the settings since the values are correlated.
21. Press the [SET] button four (4) times to store these values and go back to
the main Menu.
22. If the image is unstable, adjust V BP (SIGNAL option) and then press the
[SET] button two (2) times. Go back to the main Menu.
23. Select the [COLOR] option and set the following parameters:
Parameter PAL NTSC

Brt 6 5
Cont -7 -7
24. If necessary, adjust the parameter RSUB and BSUB to obtain a good grey
scale. Press the [SET] button two (2) times to save the settings and go back
to the main Menu.
25. Press the [SET] button two (2) times to cancel the printer menu from the
external monitor.
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7 3 0 0 – S E R V I C E M A N U A L
26. Press the [DISPLAY] button to deactivate the printer display.
27. Verify that the unit remote controls the printer by pressing the 1 or 2 key
(depending on the settings).
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SECTION 5 24
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7 3 0 0 – S E R V I C E M A N U A L
Chapter
5 - Sony UP-21 MD -
Print size settings
Enclosed you will find the instructions to optimise the settings of the Sony RGB
printer. All the printers delivered by Esaote with the 7300 are already set according
with the Video standard of the country where they will be delivered.
Procedure
1. Install the RGB printer on the cart and connect it to the 7300 via the RGB
printer cable cod.8830429000, leaving the printer remote control
RGB printer icon connector disconnected.
2. Before turning on the printer, select the required video standard on the
printer rear panel.
3. Connect the printer outputs to an RGB monitor via RGB cable. Anyway,
the printer settings can be directly controlled using the LCD display of the
printer itself.
4. Switch both the printer, the monitor and the 7300 on.
6. Select GENERAL PRESET, select the Video tab, set the video standard and
wait for the re-start message.
8. Set “Sony Thermal color printer” in one of the fields REC/PRINT 1 or 2.
11. Switch the unit on.

The following 12. Press the printer [MENU] button: it will activate the printer settings menu.
instruction refer to the You can scroll through it by pressing the [<] and [>]buttons and, once an
printer keys
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7 3 0 0 – S E R V I C E M A N U A L
option is selected, you can scroll its menu by pressing the [∧] and [∨]
buttons.
13. Once the value to be changed is selected, you have to press the [<] and
[>]buttons to modify it.
14. For the COLOR ADJUST and LAYOUT SETUP, WINDOW sub
menu, any modification has to be confirmed by pressing [SAVE] and then
[EXEC].
15. The table shows which value has to be set for the mentioned parameters:
Menu Option Parameter PAL NTSC

COLOR ADJUST CYN-RED 0 0
MAG-GRN 0 0
YEL-BLU 0 0
DARK 0 0
LIGHT 0 0
SHARPNESS 15 15
INTERPOL OFF OFF
LAYOUT SETUP MEMORY FRAME FRAME
WINDOW HSTART 12 0
VSTART 8 0
HWIDTH 936 936
VWIDTH 556 472
PRINTER SET UP GAMMA NORMAL NORMAL
INPUT SETUP INPUT SEL RGB RGB
GAIN -2 -2
OFFSET 1 1
AGC OFF OFF
16. Press [MENU] to exit from the configuration procedure.
17. Connect the printer remote control connector and check the settings by
making a demo print.
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Chapter
6 - Mitsubishi CP900E -
Print size settings
Enclosed you will find the instructions to optimise the settings of the Mitsubishi
RGB printer. All the printers delivered by Esaote with the 7300 are already set
according with the Video standard of the country where they will be delivered.
The Mitsubishi Model CP900E is a PAL video standard thermal printer.

N O T E
Procedure
1. Install the RGB printer on the cart and connect it to the 7300 via the RGB
printer cable cod.8830429000 (do not connect the remote control
RGB printer icon connector).
2. Verify that the printer input switch, placed in the rear panel, are correctly
set:
Switch Set
RGB 75 Ohm/High
SYNC High
3. Connect the printer outputs to an RGB monitor via RGB cable.
4. Switch both the printer, the monitor and the 7300 on.
6. Select GENERAL PRESET, select the Video tab and verify that PAL video
standard is set. If necessary, set it and wait for the re-start message.
8. Set “Mitsubishi Thermal color printer” in one of the fields REC/PRINT 1

or 2..
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7 3 0 0 – S E R V I C E M A N U A L
11. Connect the remote control to the printer(input on the printer front
panel).
The following 12. Press the printer [DISPLAY] button: it will display the system screen on
instruction refer to the the monitor.
printer keys on the
remote control
13. Press the [FIELD/FRAME] since the message FRAME is displayed on
the lower side of the screen.
14. Press the [MENU] key to display the printer menu on the monitor.
15. Select the INPUT option by pressing the [∧] and [∨] buttons.
16. Select the RGB option by pressing the [>] and [<] buttons.
17. Press the [SET] key two (2) times to save the configuration.
18. Press the keys [MENU] and then [CLEAR] + [STOP] to display the
service menu.
19. Select the GAMMA ADJ option by pressing the [∧] and [∨] buttons. Press
the [>] key to access to its configuration menu
20. The table shows which value has to be set for the mentioned parameters:
Parameter Value
COLOR ALL
HI -16
MID 0
LOW 15
POINT 32 128 223
21. Press the [SET] key two (2) times to save the configuration. Wait for
GAMMA SETTING message to stop flashing before proceeding with the
settings.
22. Press again the [DISPLAY] button to de-activate the printer menu.
23. Verify that the unit remote controls the printer by pressing the 1 or 2 key
(depending on the settings).
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Chapter
7 - AG MD835 - VTR
settings
The AG-MD835 VTR can be remotely controlled by the 7300. The VTR must be
provided with its RS232C serial interface board. In order to avoid the flickering
when in play-back, the VTR must be properly set.
All the VTRs delivered by Esaote with the 7300 are already set according with this
procedure.
Procedure
1. Connect the VTR to the 7300 through the S-VHS cable REF 8830427000.
VTR icon 2. Switch both the VTR and the 7300 on.
4. With the trackball select PERIPHERALS.
5. Cancel any settings in the fields REC/PRINT 1 and 2. Wait for the re-start
message.
6. Press again the key, select the GENERAL PRESET option, then the
VIDEO tab and set the desired Video standard and the input signal to S-
VHS.
9. Turn the unit on and enter Real-Time.
10. Press the key in the 7300 keyboard and then the P L A Y soft key.
11. Switch the switch [MENU] (located under the door on front panel) to
SET and the switch [MODE LOCK] to OFF: the VTR Menu options will
be displayed.
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7 3 0 0 – S E R V I C E M A N U A L
12. Select the Serial Interface board setting page (press the VTR [REC] and
[PLAY] operation buttons to scroll the menu pages).
13. Use the [FF] key to select each setting field (highlighted by a flashing bar).
14. Set the following values (use the operation button [STOP] or [REW] to
change the default settings):
Field Value
BIT LENGTH 7
STOP BIT STOP-1
PARITY ODD
BAUD RATE 9600
15. Go back to the VTR menu and select the VISS option.
16. Verify that VISS is set to OFF. If necessary, set it.
17. Switch the switch [MENU] to OFF.
18. Press again the key and with the trackball select PERIPHERALS.
19. Set MD835 either in the REC/PRINT 1 or 2 fields.
21. Turn the unit off by pressing the STARTEND key.
22. Verify that the VTR remote control works correctly.
Play Back Quality and Frame Position

The key activates the VTR Soft key menu. The displayed menu is:
The Service key is FORWAR
required D NEXT
PLAY PAUSE REWIND PREV STOP EJECT
By pressing the soft key N E X T / P R E V you gain access to the service menu:
SATUR↑ CONTRAST↑ BRIGHTN↑ OFFSET Y → OFFSET Y ↑ NEXT

PLAY PAUSE SATUR↓ CONTRAST↓ BRIGHTN↓ OFFSET X ← OFFSET Y ↓ PREV STOP EJECT
VTR Soft Keys

The soft key are used for adjusting the contrast, the brightness and saturation of
the Play-Back colors and for setting the video recorder position. To carry out the
procedure, a Video recorder with a pre-recorded video cassette must be connected
to the 7300.
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7 3 0 0 – S E R V I C E M A N U A L
Press P L A Y to see the recorded images on the display. As soon as one service soft
key is pressed, the system displays the set numeric values of the parameters on the
right sight of the screen. You have direct control over the procedure as the changes
in the settings are displayed immediately.
We recommend using the 7300 Real Time screen as a recorded image.
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7 3 0 0 – S E R V I C E M A N U A L
Chapter
8 - MD3000 - VTR
settings
The MD3000 VTR can be remotely controlled by the 7300. The VTR must be
provided with its RS232C serial interface board. In order to avoid the flickering
when in play-back, the VTR must be properly set.
All the VTRs delivered by Esaote with the 7300 are already set according with this
procedure.
Note
7300 requires software release ≥ STD 3.01!
Procedure
1. Remove the RS232 board from the VTR.
VTR icon 2. Set the switches SW5001 and SW5002 as shown in the below figure.
3. Install the RS232 board in the VTR.
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7 3 0 0 – S E R V I C E M A N U A L
4. Connect the VTR to the 7300 through the S-VHS cable.
5. Switch on both the VTR and the 7300.
7. With the trackball select PERIPHERALS.
8. Cancel any settings in the fields REC/PRINT 1 and 2. Wait for the re-start
message.
9. Press again the key, select the GENERAL PRESET option, then the
VIDEO tab and set the desired Video standard and the Input signal to S-
VHS.
12. Press the key in the 7300 keyboard and then the P L A Y soft key.
13. Press the VTR [MENU] key till its menu will be displayed on the screen.
14. Press [MENU] key several times till the Serial Interface board setting page
is displayed.
15. The key [FREAME/FIELD] toggles through settings parameters while

the key [REV-FWD] modifies the parameter value. Set the following
values:
Field Value
TRANSIMISSION RATE 9600
DATA BIT LENGTH 7 BIT
STOP BIT LENGTH 1 BIT
PARITY CHECK ODD
16. Go back to main menu. Select VISS option.
17. Verify that VISS is set to OFF; if necessary, set it.
18. Press the key [MENU] several times till the VTR menu disappears.
19. Press the key , select PERIPHERALS and set MD3000 either in the
REC/PRINT 1 or 2 fields.
20. Wait for the re-start message and turn the unit off by pressing the
STARTEND key.
21. Verify that the VTR remote control works correctly.
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7 3 0 0 – S E R V I C E M A N U A L
Play Back Quality and Frame Position

The key activates the VTR Soft key menu. The displayed menu is:
The Service key is FORWAR
required D NEXT
PLAY PAUSE REWIND PREV STOP EJECT
By pressing the soft key N E X T / P R E V you gain access to the service menu:
SATUR↑ CONTRAST↑ BRIGHTN↑ OFFSET Y → OFFSET Y ↑ NEXT

PLAY PAUSE SATUR↓ CONTRAST↓ BRIGHTN↓ OFFSET X ← OFFSET Y ↓ PREV STOP EJECT
VTR Soft Keys

The soft key are used for adjusting the contrast, the brightness and saturation of
the Play-Back colors and for setting the video recorder position. To carry out the
procedure, a Video recorder with a pre-recorded video cassette must be connected
to the 7300.
Press P L A Y to see the recorded images on the display. As soon as one service soft
key is pressed, the system displays the set numeric values of the parameters on the
right sight of the screen. You have direct control over the procedure as the changes
in the settings are displayed immediately.
We recommend using the 7300 Real Time screen as a recorded image.
SECTION 5 35
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 36
9
7 3 0 0 – S E R V I C E M A N U A L
Chapter
9 - Report and Measure

Configuration
Service personnel can customize the report, adding the centre logo, and can modify
measurement descriptions.
The Service key is
required
Report Configuration
Procedure • Press key.
• Select “Report Header” option.
• Select the desired application.
• The system displays the following menu
• Place the cursor on the field “Change” and press ENTER.

• The system open the browser shown in the figure. Select the driver
from which the logo has to be loaded and confirm.
SECTION 5 37
7 3 0 0 – S E R V I C E M A N U A L
Note
The logo has to be either PNG or BMP or JPG format.
Measure Configuration
The measurements descriptions, abbreviations and labels of both Cardiac and
Vascular applications can be modified by the Service personnel.
Procedure • Press key.

• Select “Application Measurement” option.
• Select the desired application.
• The system displays the application measurement menu. To modify
the description, place the cursor on the desired field and press ENTER.
• With the alphanumeric keyboard enter the new description.
It is possible to change only the descriptions but NOT the calculation combined to
C A U T I O N
the measure. Each measure is associated to a specific preset calculation (a velocity
measure can be freely named but it will always measure a velocity).
SECTION 5 38
A
7 3 0 0 – S E R V I C E M A N U A L
Appendix
Appendix A - Cables Assembly

The Appendix includes the assembly of:
• S-VHS VTR cable cod.8830427000

• Sony RGB Printer cable cod.8830915000
• B/W Printer cable cod.8830428000
• RGB Printer cable cod.8830429000
The scheme of the VHS VTR cable is also enclosed.
SECTION 5 39
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 40
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 41
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 42
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 43
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 44
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 45
7 3 0 0 – S E R V I C E M A N U A L
SECTION 5 46
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Maintenance
Procedures
The maintenance procedures are:
• Trackball
• Replacement of the Processor battery cell
• Replacement of the TGC potentiometer
Trackball
We recommend this maintenance procedure be carried out once a year
Tools
Tool Dimension
Paintbrush -
Removal procedure
• Applying light pressure, turn the plastic locking ring in a counter-
clockwise direction then lift and remove.
• Remove the ball and clean it.
• Clean the encoders with a paint brush (Do not use a cleaning spray!).
• Reassemble the trackball.
Processor battery cell

The Processor board contains a Lithium battery. We strongly recommend to
replace the battery cell every three (3) years. If the Processor board has to be
stored, it will be necessary to first remove the battery.
The Esaote supplier is 3V 210mA/h GP Model CR2032

Corroded cells Avoid contact with a leaking battery as the contents are harmful.
SECTION 6 1
7 3 0 0 – S E R V I C E M A N U A L
Irritation, including caustic burns and injury may occur following exposure
WARNING
to a leaking battery.
Do not expose the battery to high temperature. Dispose batteries according

to local regulation
Procedure
• Remove the lower, right and rear covers.
• Unscrew the fourteen (14) screws fixing the Input board to the chassis.
• Unscrew the two (2) screws fixing the Processor board to the chassis.
• Replace the battery cell paying attention to cell orientation. The cell
positive side of the cell (indicated with +) must be placed upwards.
Incorrect replacement of the battery can cause battery explosion.
WARNING
• Install the Processor and Input boards and close the unit.
• Power the unit and switch it on.
• Enter Real Time and press key.
• Select GENERAL PRESET.
• Set the data and time and press OK to confirm.
TGC Potentiometer Replacement

This procedure has to be followed whenever one or more TGC potentiometers are
damaged and they have to be replaced.
Tools
Tool Dimension
Soldering unit Medium tip
Philips electric screwdriver Medium tip
Tweezers -
Potentiometer -
Tin sucker -
Procedure
• Remove the slider caps.
• Unscrew the five (5) screws fixing the TGC keyboard to the upper
cover.
• Disconnect the flat from the TGC keyboard, using the tweezers if
necessary.
• Unsolder the broken slider from the underside
SECTION 6 2
7 3 0 0 – S E R V I C E M A N U A L
• Replace the broken lever.

• Re-solder the slider.
SECTION 6 3
7 3 0 0 – S E R V I C E M A N U A L
SECTION 6 4
2
7 3 0 0 – S E R V I C E M A N U A L
Chapter
2 - Safety Test
Every 7300 unit and cart Mod.7310 complies with EN60601-1 (IEC 60601-1)
standard. The 7300 is Class I Type B and BF (Ultrasound probe) and CF (ECG)
applied parts; the cart Mod.7310 is Class I.
We strongly recommend performing Safety Tests every time new peripherals are
powered through the cart or you had to replace any of the following parts:
• Power Supply board

• Video board (ECG connector)
Anyway we suggest repeating the safety tests every two years. If the system is used
in the Intensive or Coronary Care, we suggest repeating the safety tests once a year.
Whenever the measured values exceed the reference ones (see the following
WARNING
table) don’t use the unit and send it to ESAOTE
The parameters to be tested are the following:
• Impedance of Protective Earth Connection

• Earth Leakage Current
• Enclosure Leakage Current
• Patient Leakage Current
• Patient Auxiliary Current
This chapter defines safety Parameters and their range according to EN60601-1
standard and describes the safety tests to be carried out on the equipment.
Definitions
1) Impedance of Protective Earth Connection
The impedance between the Protective Earth (PE) terminal of the mains input
connector and any accessible metal part.
2) Earth Leakage Current
The current that flows from the mains terminals (P=Phase, N=Neutral) to the
Protective Earth (PE) through the insulation.
SECTION 6 5
7 3 0 0 – S E R V I C E M A N U A L
3) Enclosure Leakage Current
The current that flows between the enclosure and the Protective Earth (PE)
terminal.
4) Patient Leakage Current
The current that flows through the applied parts (ECG and US probe) towards the
Protective Earth (PE).
5) Patient Auxiliary Current
The current that flows between two different applied parts (for instance between
two ECG electrodes).
The table below provides the user with a list of the parameters to be checked, the
maximum values and references to the IEC 60601-1 standard (1988), II Edition.
Parameter Max Value N.C. Max Value EN 60601-1

S.F.C.
Impedance of protective earth connection (with 0.2 Ω - 18.f

Mains Power cable)
Earth leakage current 0.5 mA 1 mA 19.4.f
Enclosure leakage current 0.1 mA 0.5 mA 19.4.g
Patient leakage current CF 0.01 mA ac CF 0.05 mA ac 19.4.h
B/BF 0.1 mA ac B/BF 0.5 mA ac
Patient leakage current - CF 0.05 mA 19.4 h
(mains on applied part) BF 0.5 mA
Patient auxiliary current CF 0.01 mA CF 0.05mA 19.4.j
B/BF 0.1 mA B/BF 0.5 mA
N.C. Normal Condition
S.F.C. Single Fault Condition
The test must be carried out by skilled personnel using equipment compliant with
N O T E
the reference standard indicated. ESAOTE recommends the use of the automatic
BIO-TEK 601-PRO equipment manufactured by BIO-TEK Instruments INC. or
equivalent equipment.
7300 safety test - Operating Procedures

Tools
Tool Dimension
BIOTEK 601 Pro or -
equivalent
Metal foil maximum size 20 x 10 cm
SECTION 6 6
7 3 0 0 – S E R V I C E M A N U A L
Note
Before proceeding with the safety test, be sure of the equipment

calibration.
Procedure
• Power the automatic testing equipment through mains supply and the
equipment under test through the automatic equipment, as shown in
the Fig.1
Fig.1
• The ECG cable must be connected to the 7300 ECG connector and
the Applied parts terminals in the automatic equipment (see Fig.1).
• Set the automatic equipment according to its user manual in order to
perform a Class I, Type CF equipment test..
Measurement of the Impedance of Protective Earth connection
• Connect the test lead to 7300 equipotential node.
• Activate the procedure for measuring the Impedance of Protective
Earth on the automatic equipment.
• Check that the value indicated complies with the indications given in
the reference table for normal condition (NC).
If the measured value is higher than the value in the table, do not use the
equipment and send to ESAOTE.
SECTION 6 7
7 3 0 0 – S E R V I C E M A N U A L
Measurement of Earth leakage current

• Activate the procedure for measuring the earth leakage current on the
automatic equipment:
1.1 Check that the value indicated complies with the indications
given in the reference table for normal condition (NC).
1.2 Repeat the procedure simulating a break in a power conductor,

by means of the automatic equipment, and check that the value
indicated complies with the indications given in the reference table
for the single fault condition (SFC).
• Repeat the above measurement procedures inverting the polarity of

the power conductors, by means of the automatic equipment
If any measured value is higher than the value in the table, do not use the
equipment and replace the power cable. Repeat the procedure with the new cable
and if the values continue to be higher, send the equipment to ESAOTE.
Measurement the Enclosure Leakage Current

• Connect the test lead to the metal foil.
1.1 Place the metal foil in close contact with the unit and activate
the procedure for measuring the enclosure leakage current on the
automatic equipment; varying the foil position, check that the
value indicated complies with the indications given in the reference
table for the normal condition (NC)
1.2 Repeat the procedure simulating a break in the earth wire, by

means of the automatic equipment, and check that the value


the power conductors, by means of the automatic equipment.
If any of the measured values are higher than the value in the table, do not use the
equipment and send it to ESAOTE.
Measurement the Patient Leakage Current (ECG cable)

• Insert the ECG cable leads in the applied parts terminals in the
automatic equipment.
1.1 Activate the procedure for measuring the Patient leakage
current on the automatic equipment and check that the value
for the normal condition (NC).
SECTION 6 8
7 3 0 0 – S E R V I C E M A N U A L


1.4 Repeat the procedure simulating the application of the mains

voltage, by means of the automatic equipment, to the plugs on the
patient cable and check that the value indicated complies with the
indication given in the reference table for the single fault condition
(SFC).

• If any of the measured values are higher than the value in the table, do
not use the equipment and replace the ECG patient cable. Repeat the
procedure with the new cable and if the values continue to be higher,
send the equipment to ESAOTE.
Measurement the Patient Auxiliary Current
• Activate the procedure for measuring the patient auxiliary current on
the automatic equipment and check that the value indicated complies
with the indications given in the reference table for the normal
condition (NC).
• Repeat the procedure simulating a break in the earth wire, by means of
the automatic equipment, and check that the value indicated complies
with the indications given in the reference table for the single fault
condition (SFC).
• Repeat the procedure simulating a break in a power conductor, by
means of the automatic equipment, and check that the value indicated
complies with the indications given in the reference table for the single
fault condition (SFC).
equipment and replace the ECG patient cable. Repeat the procedure with the new
cable and if the values continue to be higher, send the equipment to ESAOTE.
The defective patient cable or power cable must not be used

WARNING
SECTION 6 9
7 3 0 0 – S E R V I C E M A N U A L
Cart Mod.7310 safety tests

The parameters to be tested are:
• Impedance of Protective Earth Connection

• Earth Leakage Current
• Enclosure Leakage Current
To test the cart, follow the instruction given above connecting the cart power cord
to the automatic test equipment as shown in Fig.1
Probe safety tests

For any probe in use with the unit, repeat the procedure for measuring the Patient
Leakage Current test (without application of mains voltage on applied part),
wrapping the probe enclosure with the metal foil and connecting the test lead to it.
The test must be performed in any Real Time mode application. The probe must
be connected to the unit
1.1 Activate the procedure for measuring the Patient leakage

current on the automatic equipment and check that the value
for the normal condition (NC).


Repeat the above measurement procedures inverting the polarity of the power
conductors, by means of the automatic equipment.
probe and send it to ESAOTE.
Any break in the probe case or in the probe cable can cause an electrical
WARNING
hazard. Do not use the probe and send it back to ESAOTE for repair.
SECTION 6 10
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Error messages
Communication error with the CONTROL

BOARD (TGC) and Communication error with
the CONTROL BOARD
When system displays one of the following messages:
Communication error with the CONTROL BOARD (TGC)

Please, contact the service department !
Press <PROBE> to continue
Communication error with the CONTROL BOARD

Please, contact the service department !
Press <PROBE> to continue
there is a communication problem between the Processor board and the Control
board.
Suggestion
• Replace the Control board and verify if the problem disappears.
• If not, re-install the Control board.
• Replace the Processor board and verify if the problem disappears.
• If not, contact Esaote central service.
SECTION 7 1
7 3 0 0 – S E R V I C E M A N U A L
SECTION 7 2
2
7 3 0 0 – S E R V I C E M A N U A L
Chapter
2 - Hardware error
messages
If an Hardware failure is present so that the Processor can’t access some of the
boards, the unit will display an error message in red on the right side of the screen.
In that situation power the unit on and off several times to verify that the message
persists (it could be caused by a board failing to initialise correctly).
If the message persists, the fault could be:
Message Fault Solution

03 ECG VIDEO board Replace the VIDEO board
04 POWER POWER SUPPLY board Replace the POWER SUPPLY board
05 DOPPLER DOPPLER board Replace the DOPPLER board.
07 CONTROL CONTROL board Replace the CONTROL boar
08 TGC CONTROL board Replace the CONTROL board
09 SCAN CONTROL board Replace the CONTROL board
12 E2PROM MOTHER/PROCESSOR Replace the PROCESSOR board. If
boards not solved, send the unit back to
Esaote
14 GRAPHIC PROCESSOR board Replace the PROCESSOR board
SECTION 7 3
7 3 0 0 – S E R V I C E M A N U A L
SECTION 7 4
3
7 3 0 0 – S E R V I C E M A N U A L
Chapter
3 - Archiving
troubleshooting
From the Real Time screen is possible to check if the Archiving services are
correctly functioning. The icons are shown over a blue background when they can
be activated. While data are being saved, the specific support icon is outlined by a
yellow flashing frame. The frame disappears when the operation ends.
Hard Disk Crossed Icon

The crossed out icon indicates that the communication between the ETX board
and the central processor on the Processor board has been interrupted sometime.
Suggestion
Torn the unit off an on and check if the Hard Disk icon is displayed with no cross.
If the problem persists, re-install the software release following the instruction
given in section 5.
If this does not work, replace the Hard Disk (see Section 4, Chapter 3 for Hard
Disk replacing instruction).
Hard Disk Grey Icon

When the Hard Disk icon stays grey, it means that there has never been
communication between the central processor and the ETX board on the on the
Processor board.
Suggestion
Torn the unit off and on and check if the Hard Disk icon is displayed on a blue
background. If the problem persists, re-install the software release following the
instruction given in section 5.
If this does not work, replace the Hard Disk (see Section 4, Chapter 3 for Hard
Disk replacing instruction).
SECTION 7 5
7 3 0 0 – S E R V I C E M A N U A L
CD Burner and USB Pen Drive Crossed Icons

The crossed out icon indicates management problems of the specific archival
support.
Suggestion
The interactive icon menu allows the operator to understand which operation has
failed, and, if necessary, to repeat (RETRY) or cancel the failed operation.
If the operation continuously fails, replace the support and repeat the operation. If
this does not work, replace the Processor board.
SECTION 7 6
4
7 3 0 0 – S E R V I C E M A N U A L
Chapter
4 - Shut Down Log File

The STARTEND key, when pressed for more than 3 seconds, activates the shut
down procedure. This procedure has to be followed before turning the unit off by
The Service key is pressing the main switch placed in the unit rear panel.
required
7300 is a PC based system; data loss or driver damage may occur if the system is
N O T E
turned off while working. The shut down procedure avoids these problems.
The Shut Down Log file allows the service to verify if the procedure is correctly
followed.
Procedure
1. Turn the unit on with the service key inserted.
2. Enter Real-Time and press .
3. Press the keys Ctrl + Esc to display the Windows menu.
4. Select Document/My Documents option.
5. Select in the drive D the Biolabwork directory and then the directory
Dam.
6. The file DamShutDown_0 is displayed by double-clicking it, as shown in

the below shot.
SECTION 7 7
7 3 0 0 – S E R V I C E M A N U A L
The line “Starting

dam” locates when
the unit has been
turned on; the line
“Fast shutdown
called by user” locates
when the unit has
been turned off by
pressing the
STARTEND key.
The Shut Down log file can be copied in an USB pen drive for any service need.
SECTION 7 8
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Check List
This chapter proposes two different check lists. The first one (Technical Check
List) suggests a set of inspection steps to be performed each time service personnel
modify the HW/SW composition (for example a board replacement or functional
upgrade); the other one (Maintenance Check List) suggests a check list intended for
a general equipment inspection like yearly maintenance.
Technical Check List

Once any HW/SW change, modification or upgrade is finished and the unit is
ready to be closed, perform the following:
The Service key is
required
• Make a note of any new boards or parts which have been replaced.
Part numbers can be found in the Traceable Part List section of the
manual.
• Close the unit.
• Switch the unit on with the service key inserted.
• Enter Real-Time, press the key and select SYSTEM
CONFIGURATION.
• Print the new System Configuration screen and place it in the bottom
pocket of the unit.
• When applicable, verify that the functional upgrade is working
properly.
• Press again the key and select the SERVICE option.
• Press ENTER and select SAVE CONFIGURATION.
• Save the configuration by pressing ENTER.
• Switch off the unit.
• Reinstall the unit.
• Verify the unit functioning using the Maintenance Check List as
reference
SECTION 8 1
7 3 0 0 – S E R V I C E M A N U A L
Maintenance Check List

Stand alone equipment
• Check the unit for any external damage.
• Check that the unit labels (Serial Number, Code and Certification) are
present.
• Check that the User Manual is enclosed and its revision is relevant to
the installed software release.
• Check the power cable status (no cut, plug condition).
• Check the connectors in the rear panel.
• If installed, check the ECG Cable status.
• Clean the trackball.
• Check that the fan works properly.
• Switch on the unit, enter Real-Time, press the key and select
SYSTEM CONFIGURATION.
• Compare the configuration prints located in the bottom pocket of the

unit with the configuration information shown on the System
Configuration screen.
• Check the keyboard functions.
For probes check • For all probes, check the external status (cable, housing and labelling).
refer also to
“Transducers and • Check that the unit is functioning properly, for each of the modalities
Consumables” listed below verify:
manual
• B Mode: General Gain (B/M Gain Encoder), TGC, TX
Focus, Power and all Soft keys controls.
• M Mode: General Gain (B/M Gain Encoder) and all Soft keys
controls.
• B + CFM: CFM Gain (C/D Gain Encoder), CFM ROI and
all Soft keys controls.
• CW/PW: Doppler Gain (C/D Gain Encoder), Audio and all
Soft keys controls.
• ECG ( ): ECG level and position.
• Insert a rewritable CD and save images. Then erase them (CD burner
menu).
• Insert a USB pen drive in one of the ports and save images.
• Repeat the operation in the other USB port.
SECTION 8 2
7 3 0 0 – S E R V I C E M A N U A L
Full configured equipment

• When applicable, check all above mentioned points.
• When equipped with a VTR, check:
• VTR cable and connection.
• When applicable, remote control setting and its functioning.
• Play back quality and Frame position (Service soft keys menu).
• Audio quality.
• When equipped with a printer:
• Printer cable and connection
• When applicable, remote control setting and its functioning.
• Print quality.
SECTION 8 3
7 3 0 0 – S E R V I C E M A N U A L
SECTION 8 4
1
7 3 0 0 – S E R V I C E M A N U A L
Chapter
1 - Schematic Diagrams
This chapter contains the Schematic Diagrams of the 7300 boards.
Note: the schematics of the TRX1, TRX2 and POWER SUPPLY boards are confidential so
they aren’t included in this manual.
SECTION 9 1
7 3 0 0 – S E R V I C E M A N U A L
SECTION 9 2
1 2 3 4 5 6 7 8 9 10 11
VCC
VCC
U5
74HC244 C1
R5 47N
1
4
3
2
1
4
3
2
1
1G PEDEN 180 3V3
2G 19
F U7 U8 RLB0 18 1Y1 1A1 2 COMP0

10K
10K U9 RLB1 16 1Y2 1A2 4 COMP1
74HC244 RLB2 14 6 COMP2 R2 R4 R1
1Y3 1A3
U1 CR5
1 RLB3 12 8 COMP3 12 10K
3K3 10K
5
6
7
8
5
6
7
8
1G 1Y4 1A4
19 RLB4 9 11 COMP4 LM339
2G 2Y1 2A1 V-
RLB5 7 13 COMP5 +
2 18 RLB0 2Y2 2A2 COMP3 11
CEA0 1A1 1Y1 13
RLB6 5 15 COMP6
4 16 RLB1 2Y3 2A3 -
10
CEA1 1A2 1Y2
6 14 RLB2
RLB7 3 2Y4 2A4 17 COMP7 V+
CR4 CR3 J3
CEA2 1A3 1Y3 C2 3 BAS21 7
1 ELT
8 12 RLB3 BAS21
CEA3 1A4 1Y4 100N DMSB 2
RLB4 6
11 9 U3
VCC
CEA4 2A1 2Y1 3
5 ELR
13 7 RLB5
CEA5 2A2 2Y2 10K 4
PLSB
15 5 RLB6
CEA6 2A3 2Y3 1 8 COMP0
U1 CR2 CR1
17 3 RLB7 12 BAS21 BAS21
CEA7 2A4 2Y4 4 5 COMP1
LM339
VCC 3 6 COMP2 V-
+
2 7 COMP3 COMP7 9
14
-
8
V+
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E COMP5
3
2 7
R3
RLB[0:9]
4 5 COMP6
4
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2
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VCC
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U12 U13 LM339
10K 74HC244 U4 V-
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5
6
7
8
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6
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6 14 RLB2
CEB2 1A3 1Y3 12
CEB3 8 1A4 1Y4 12 RLB3 LM339
V-
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CEB4 2A1 2Y1 7
COMP6
13 7 RLB5 1
CEB5 2A2 2Y2 -
15 5 RLB6 6
CEB6 2A3 2Y3 V+
17 3 RLB7 3
CEB7 2A4 2Y4
VCC R6
D 3K3
U2
12
LM339
V-
4
1
2
3
4
3
2
1
COMP1 +
U14 9
14 PROBEB
U15 10K -
8
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74HC244
1
5
8
7
6
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5
6
7
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U6
CEA8 2 1A1 1Y1 18 RLB8
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74AHCT02 R11
74AHCT02
CEA9 8 1A2 1Y2 12 RLB9 12 U2 4 2 274
6 14 LM339 6 1 LEDB
1A3 1Y3 V- VCC 3
+
4 1A4 1Y4 16 COMP5 11 C8
11 9 RLB8 13
CEB8 2A1 2Y1 -
10 100N
13 7 RLB9 V+
CEB9 2A2 2Y2
15 2A3 2Y3 5 3 R12
C 17 3 4K75
C7
2A4 2Y4 R7 U6
PBAEN U6 100N
3K3
8
74AHCT02 R9
PBBEN U2 SELA/B
10 11
74AHCT02
12 274
LM339 9 13 LEDA
V- 12
COMP0 +
7
1
RLB0 -
6
RLB1
V+ C3
3 10N R10
RLB2
4K75
RLB3
SELPED
RLB4
RLB5
VCC RLB6
RLB7 VCC
RLB8
RLB9 U2
12
LM339
V-
+
B COMP4 5
100
100
100
100
100
100
2
-
4
V+ C10 C15 C9 C11 C12 C6
3 C5 47N 47N 47N 47N 47N 47N
C4
R8 10N
100N
R24
R20
R26
R22
R30
R28
VCC
VCC
3K3
ICONF0
ICONF1
ICONF2 R15
ICONF3 4K75
ICONF4 U17
ICONF5 74ACT138
PBA/B 1 A Y0 15 PBBEN +6V
U10
VCC
100
100
100
100
100
100
PED 2 B Y1 14 PBAEN TPS72501

3 C Y2 13 PEDEN 2 IN OUT 4
R16 VCC 12
Y3 R17 680
4K75 Y4 11 1 EN FB 5
R23
A
R19
R25
R21
R29
R27
6 G1 Y5 10
GND
837 0147 042 Rev.A
4 G2A Y6 9 C13 C14

5 7 4U7
G2B Y7 4U7
FORM:
3 220
R18

"7300" INPUT BOARD
A2 GAMBACCIANI DONNINI BERTINI 14/06/05
by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500288 Number: 950 1075 000 SE D 1 5
DOCUMENT ELECTRONICALLY SIGNED DOCUMENTO FIRMATO ELETTRONICAMENTE
1 2 3 4 5 6 7 8 9 10 11
K21 K89 K90 K45 K50

K37 12V 2VIE
12V 2VIE 12V 2VIE 12V 2VIE 12V 2VIE
F 12V 2VIE 1 8
1
+
8
1 8 1 8 1 8
+ + + +
1 8
+
4 ELA169
5 ELA149 4 ELA189 4 ELA17 4 ELA25
CER137 3
5 ELA129 CER117 6 CER157 3 CER177 3 CER185 3
2 ELB169
CER97 6 7 ELB149 2 ELB189 2 ELB17 2 ELB25
7 ELB129 5 ELA170
4 ELA150 5 ELA190 5 5 ELA26
CER138 6 ELA18
7 ELB170
2 ELB130 K41 K97 K93 K46 K51
K80 12V 2VIE
12V 2VIE 1 8
1
+
8
1 8 1 8 1 8
+ + + +
1 8
+
5 ELA171
5 ELA151 4 ELA191 4 ELA19 4 ELA27
CER139 6
7 ELB171
2 ELB131 4 ELA172
4 ELA152 5 ELA192 5 ELA20 5 ELA28
CER140 3
2 ELB172
7 ELB132
K83 K101 K11 K47 K52
E K18
12V 2VIE 12V 2VIE 12V 2VIE 12V 2VIE 12V 2VIE
12V 2VIE 1 8
1
+
8 1
+
8
1 8 1 8
+ + +
1 8
+
4 ELA173 4 ELA1
4 ELA153 4 ELA21 4 ELA29
CER141 3 CER161 3
5 ELA133 CER121 3 CER181 3 CER189 3
2 ELB173 2 ELB1
CER101 6 2 ELB153 2 ELB21 2 ELB29
7 ELB133 5 ELA174 5 ELA2
5 ELA154 5 ELA22 5 ELA30
CER142 6 CER162 6
4 ELA134 CER122 6 CER182 6 CER190 6
ELB154 7 ELB174 7 ELB2
CER102 3 7 7 ELB22 7 ELB30
2 ELB134 K86 K96 K74 K75
K38 12V 2VIE K12
12V 2VIE 12V 2VIE 12V 2VIE
12V 2VIE 1 8
1
+
8 12V 2VIE 1 8 1 8
+ + +
1 8 1 8
+ +
4 ELA175
5 ELA155 4 ELA23 4 ELA31
CER143 3
5 ELA135 CER123 6 4 ELA3 CER183 3 CER191 3
2 ELB175
CER103 6 7 ELB155 CER163 3 2 ELB23 2 ELB31
7 ELB135 2 ELB3
5 ELA176
4 ELA156 5 ELA24 5 ELA32
CER144 6
4 ELA136 CER124 3 5 ELA4 CER184 6 CER192 6
7 ELB176
D CER104 3 2 ELB156 CER164 6 7 ELB24 7 ELB32
2 ELB136 7 ELB4
K85 K95
K19 K13
12V 2VIE 12V 2VIE K68
12V 2VIE
12V 2VIE 1 8
1
+
8
12V 2VIE
+ 1 8
1 8 +
+ 8 1
+
4 ELA177 L2
4 ELA157
CER145 3 4 ELA5
5 ELA137 CER125 3
2 ELB177 CER165 3 MPH1A 4 10U
CER105 6 2 ELB157 2 ELB5 3 MPH1
7 ELB137 1
5 ELA178 MPH1B 2 2
5 ELA158
4 ELA138 CER126 6 CER146 6 5 ELA6 C16
7 ELB178 CER166 6 MPH2A 5
CER106 3 7 ELB158 22N
7 ELB6 6
2 ELB138
MPH2B 7
K84 K92 K72
K81 12V 2VIE
12V 2VIE 12V 2VIE C18
12V 2VIE 1 8
1
+
8
1 8
1 8
+ + 22N L4
+
5 10U
4 ELA179 4
ELA159 6 ELA7 K60 MPH2
4 3 CER147 3 1
3
ELA139 CER127
2
7 ELB179
CER167
2
CR6 2
C CER107
2
ELB159 ELB7 BAS21 12V 2VIE
ELB139 4
VCC
VCC
5 ELA180 5 8 1
ELA160 3 ELA8 +
5 ELA140 6 CER148 6
6
CER128
7
2 ELB180
CER168
7
L3
CER108 ELB160 ELB8 10U
7 ELB140 K88 4
K61 K32 MPH3A
3 MPH3
K39 12V 2VIE 2 1
12V 2VIE 12V 2VIE MPH3B 2
12V 2VIE 1 8 C19
1 8 + 1 8 MPH4A 5
+ +
1 8 6 22N
+
MPH4B 7
5 ELA181
5 ELA161 4 ELA9
CER149 6
4 ELA141 CER129 6 CER169 3
7 ELB181
CER109 3 7 ELB161 2 ELB9 K98 C17
2 ELB141 4 ELA182 22N L5
4 ELA162 5 ELA10 12V 2VIE
CER150 3
5 ELA142 CER130 3 CER170 6
2 ELB182 8 1 10U
CER110 6 2 ELB162 7 ELB10 +
7 ELB142 MPH4
K71 K87 1 2
K20 K33 4
12V 2VIE 12V 2VIE TSENSEA
3
12V 2VIE 1 8 12V 2VIE 2
TSENSE
1 8 + TSENSEB
+ 1 8
1 8 +
+
PSENSEA 5
4 ELA183 6 PSENSE
B 5 ELA163
CER151 3 4 ELA11 PSENSEB 7
4 ELA143 CER131 6
2 ELB183 CER171 3
C24
C25
C22
C23
CER111 3 7 ELB163 2
10N
10N
10N
10N
2 ELB11 K99
ELB143 5
4 ELA184
ELA164 6 5
5 ELA144 CER132 3 CER152
7 6
ELA12 12V 2VIE
6 2 ELB184 CER172
CER112 ELB164 7 8 1
7 K91 ELB12 +
ELB144 K69 K34
K40 12V 2VIE
12V 2VIE 12V 2VIE POFFSA 4
12V 2VIE 1 8
1
+
8
1 8 3 POFFS
1 8
+ +
POFFSB 2
+
4 ELA185 VRCFA 5
5 ELA165 4 ELA13
CER153 3 6 VRCF
5 ELA145 CER133 6 CER173 3
2 ELB185 VRCFB 7
CER113 6 7 ELB165 2 ELB13
C28
C29
7 ELB145
C26
C27
5
10N
4 ELA186 5 K100
10N
10N
10N
ELA166 6 ELA14
4 3 CER154 6
ELA146 CER134 7 CER174
CER114 3 2 ELB166
ELB186 7 ELB14 12V 2VIE
2 ELB146
K70 K94 K73
8
+
1
K82 12V 2VIE
12V 2VIE 12V 2VIE 4
PROBEA
12V 2VIE 1 8
1
+
8
1 8
VAA
3
A 1 8
+ +
2
VA
+ VAB
837 0147 042 Rev.A
5
4 ELA187 4 5
R13
ELA167 3 ELA15 AUXA
4 6 CER155 3 6 100K
ELA147 CER135 CER175 AUX
FORM:
2 ELB187
CER115 3 7 ELB167 2 ELB15 AUXB 7
2 ELB147
C32
C33
C30
C31
5
10N
10N
4 ELA188 5 Q1
10N
10N
ELA168 6 ELA16
5 3 CER156 6
ELA148 CER136 7 CER176 IRF7103
6 2 ELB188 7 ELB16
CER116 ELB168
7 ELB148
SHEET DESCRIPTION:
"7300" INPUT BOARD
by EpD Number: 950 1075 000 SE D 2 5

1 2 3 4 5 6 7 8 9 10 11
K6 K67 K36 K22

K1
12V 2VIE 1 8 1 8 1 8
+ + + 1 8
1 8 +
+
F
4 ELB53 5 ELB73 4 ELB93 4 ELB113
4 ELB33 CER21 3 CER41 6 CER61 3
CER81 3
CER1 3 2 ELA53 7 ELA73 2 ELA93 2
2 ELA33 ELA113
5 ELB54 4 ELB74 5 ELB94 5 ELB114
5 ELB34 CER22 6 CER42 3 CER62 6
CER82 6
CER2 6 7 ELA54 2 ELA74 7 ELA94 7 ELA114
7 ELA34 K29 K66 K17 K42
K24
12V 2VIE 1 8 1 8 1 8
+ + + 1 8
1 8 +
+
4 ELB55 5 ELB75 4 ELB95 4 ELB115

4 ELB35 CER23 3 CER43 6 CER63 3
CER83 3
2 ELA35
5 ELB56 4 ELB76 5 ELB96 5 ELB116
5 ELB36 CER24 6 CER44 3 CER64 6
CER84 6
7 ELA36
K7 K65 K10 K23
K2
E 12V 2VIE 1 8 1 8 1 8
+ + + 1 8
1 8 +
+
4 ELB57 5 ELB77 5 ELB97 4 ELB117

4 ELB37 CER25 3 CER45 6 CER65 6
CER85 3
2 ELA37
5 ELB58 4 ELB78 4 ELB98 5 ELB118
5 ELB38 CER26 6 CER46 3 CER66 3
CER86 6
7 ELA38 K30 K77 K31 K43
K25
12V 2VIE 1 8 1 8 1 8
+ + + 1 8
1 8 +
+
4 ELB59 5 ELB79 5 ELB99 4 ELB119

4 ELB39 CER27 3 CER47 6 CER67 6
CER87 3
2 ELA39
5 ELB60 4 ELB80 4 ELB100 5 ELB120
5 ELB40 CER28 6 CER48 3 CER68 3
CER88 6
7 ELA40
D K8 K78 K44 K54
K3
12V 2VIE 1 8 1 8 1 8
1 8
+ + +
1 8 +
+
5 ELB61 4 ELB81 5 ELB101 4 ELB121

4 ELB41 CER29 6 CER49 3 CER69 6
CER89 3
2 ELA41
4 ELB62 5 ELB82 4 ELB102 5 ELB122
5 ELB42 CER30 3 CER50 6 CER70 3
CER90 6
7 ELA42
K9 K14 K49 K48
K26 12V 2VIE
12V 2VIE 1 8 1 8 1 8
1
+
8
+ + +
1 8
+
4 ELB123
5 ELB63 4 ELB83 5 ELB103
CER91 3
5 ELB43 CER31 6 CER51 3 CER71 6
2 ELA123
CER11 6 7 ELA63 2 ELA83 7 ELA103
7 ELA43 5 ELB124
4 ELB64 5 ELB84 4 ELB104
C 4 ELB44 CER32 3 CER52 6 CER72 3 CER92 6
7 ELA124
CER12 3 2 ELA64 7 ELA84 2 ELA104
2 ELA44 K57 K15 K55 K53
K4
12V 2VIE 1 8 1 8 1 8 1 8
+ + + +
1 8
+
5 ELB65 4 ELB85 5 ELB105 4 ELB125

4 ELB45 CER33 6 CER53 3 CER73 6 CER93 3
2 ELA45
4 ELB66 5 ELB86 4 ELB106 5 ELB126
5 ELB46 CER34 3 CER54 6 CER74 3 CER94 6
7 ELA46
K58 K35 K56 K62
CR7
K27 12V 2VIE BAS21
12V 2VIE
VCC
VCC
1 8
1 8 1 8 1 8 +
+ + +
1 8
+
4 ELB127
5 ELB67 4 ELB87 4 ELB107
CER95 3
4 ELB47 CER35 6 CER55 3 CER75 3
2 ELA127
B CER15 3 7 ELA67 2 ELA87 2 ELA107
2 ELA47 5 ELB128
4 ELB68 5 ELB88 5 ELB108
CER96 6
5 ELB48 CER36 3 CER56 6 CER76 6
7 ELA128
CER16 6 2 ELA68 7 ELA88 7 ELA108
7 ELA48 K59 K79 K63
K5 12V 2VIE
12V 2VIE 12V 2VIE
12V 2VIE 1 8
1
+
8
1 8
+ +
1
+
8 Q1
4 ELB89 IRF7103
5 ELB69 5 ELB109
CER57 3
5 ELB49 CER37 6 CER77 6
2 ELA89 PROBEB
CER17 6 7 ELA69 7 ELA109
7 ELA49 5 ELB90
4 ELB70 4 ELB110
CER58 6
4 ELB50 CER38 3
7 ELA90
CER78 3 R14
CER18 3 2 ELA70 2 ELA110
2 100K
ELA50
K76 K16 K64
K28
12V 2VIE 1 8 1 8 1 8
+ + +
1 8
+
A 4 4 4
ELB71 ELB91 ELB111
837 0147 042 Rev.A
5 ELB51 CER39 3 CER59 3 CER79 3

CER19 6 2 ELA71 2 ELA91 2 ELA111
7 ELA51
FORM:
5 ELB72 5 ELB92 5 ELB112

4 ELB52 CER40 6 CER60 6 CER80 6
CER20 3 7 ELA72 7 ELA92 7 ELA112
2 ELA52
SHEET DESCRIPTION:
"7300" INPUT BOARD
by EpD Number: 950 1075 000 SE D 3 5

1 2 3 4 5 6 7 8 9 10 11
J1 J1 J1 J1 J2 J2 J2 J2
A1 ELA1 H1 ELA57 R1 ELA113 Y1 ELA169 A1 ELB1 H1 ELB57 R1 ELB113 Y1 ELB169
A5 H5 R5 Y5 A5 H5 R5 Y5
F A6 H6 R6 Y6 A6 H6 R6 Y6
ELA5 ELA61 ELA117 ELA173 ELB5 ELB61 ELB117 ELB173
A0 TSENSEA H0 R0 Y0 MPH1A A0 TSENSEB H0 R0 Y0 MPH1B
J1 J1 J1 J1 J2 J2 J2 J2
B1 ELA9 J1 ELA65 S1 ELA121 Z1 ELA177 B1 ELB9 J1 ELB65 S1 ELB121 Z1 ELB177
B5 J5 S5 Z5 B5 J5 S5 Z5
E
B0 J0 VAA S0 Z0 MPH2A B0 J0 VAB S0 Z0 MPH2B
J1 J1 J2 J2
J1 J1 J2 J2
C1 ELA17 K1 ELA73 C1 ELB17 K1 ELB73
T1 ELA129 AA1 ELA185 T1 ELB129 AA1 ELB185
C5 K5 C5 K5
T5 AA5 T5 AA5
C0 AUXA K0 VRCFA C0 AUXB K0 VRCFB
T0 AA0 LEDA T0 AA0 LEDB
D
J1 J1 J1 J2 J2 J2
J1 J2
D1 L1 U1 D1 L1 U1
ELA25 ELA81 ELA137 CC1 ELB25 ELB81 ELB137 CC1

CEA0 CEB0
D2 ELA26 L2 ELA82 U2 ELA138 D2 ELB26 L2 ELB82 U2 ELB138

CC2 CEA1 CC2 CEB1
CC3 CEA2 CC3 CEB2
CC4 CEA3 CC4 CEB3
D5 L5 U5 D5 L5 U5
CC5 CEA4 CC5 CEB4
CC6 CEA5 CC6 CEB5
CC7 CEA6 CC7 CEB6
CC8 CEA7 CC8 CEB7
CC9 CEA8 CC9 CEB8
D0 L0 POFFSA U0 TEMP1 D0 L0 POFFSB U0 TEMP2
CC0 CEA9 CC0 CEB9
C21 10N C20 10N
J1 J2
J1 J1 J1 J2 J2 J2
BB1 BB1
E1 ELA33 M1 ELA89 V1 ELA145 E1 ELB33 M1 ELB89 V1 ELB145
C BB2 BB2
BB3 BB3
BB4 BB4
BB5 BB5
E5 M5 V5 E5 M5 V5
BB6 BB6
BB7 BB7
BB8 BB8
BB9 BB9
BB0 BB0
E0 M0 PSENSEA V0 E0 M0 PSENSEB V0
J1 J1 J2 J2
J1 J2
F1 ELA41 N1 ELA97 F1 ELB41 N1 ELB97
W1 ELA153 W1 ELB153
W2 ELA154 W2 ELB154
W3 ELA155 W3 ELB155
B W4 ELA156 W4 ELB156
F5 N5 F5 N5
W5 W5
W6 ELA157 W6 ELB157
W7 ELA158 W7 ELB158
W8 ELA159 W8 ELB159
W9 ELA160 W9 ELB160
F0 N0 F0 N0
W0 MPH3A W0 MPH3B
J1 J2
J1 J1 J2 J2
X1 ELA161 X1 ELB161
G1 ELA49 P1 ELA105 G1 ELB49 P1 ELB105
X2 ELA162 X2 ELB162
X3 ELA163 X3 ELB163
X4 ELA164 X4 ELB164
X5 X5
G5 P5 G5 P5
X6 ELA165 X6 ELB165
A G7 P7
X7 ELA166 G7 P7
X7 ELB166
ELA54 ELA110 ELB54 ELB110
837 0147 042 Rev.A
X8 ELA167 X8 ELB167
X9 ELA168 X9 ELB168
FORM:
X0 MPH4A X0 MPH4B
G0 P0 G0 P0
SHEET DESCRIPTION:
"7300" INPUT BOARD
by EpD Number: 950 1075 000 SE D 4 5

1 2 3 4 5 6 7 8 9 10 11
+6V
+6V
J7 J4
J5
J6
A1 B1
TEMP2 A1 B1 TEMP1
RLB9 A1 B1 RLB8
PED A2 B2 PBA/B
A1 B1 AUX A2 B2 VA
RLB7 A2 B2 RLB6
ICONF5 A3 B3 ICONF4
MPH4 A2 B2 MPH3 VRCF A3 B3 PSENSE
RLB5 A3 B3 RLB4
ICONF3 A4 B4 ICONF2
MPH2 A3 B3 MPH1 POFFS A4 B4 TSENSE
RLB3 A4 B4 RLB2
ICONF1 A5 B5 ICONF0
A4 B4 A5 B5
E SELPED A6 B6 SELA/B
RLB1 A5 B5 RLB0
A5 B5 A6 B6
A6 B6
A7 B7
A6 B6 A7 B7
A7 B7
A8 B8
VCC
A7 B7 A8 B8
A8 B8
A9 B9
A8 B8 A9 B9
A9 B9
A10 B10
A9 B9 A10 B10
A10 B10
A11 B11
A10 B10 A11 B11
A11 B11
A12 B12 ELT
A11 B11 A12 B12
A12 B12
CER48 A13 B13
A12 B12 ELR CER160 A13 B13
CER128 A13 B13
A14 B14 CER47
CER80 A13 B13 A14 B14 CER159 A14 B14 CER127
CER46 A15 B15
A14 B14 CER79 CER158 A15 B15
CER126 A15 B15
A16 B16 CER45
CER44 A17 B17
A16 B16 CER77 CER156 A17 B17
CER124 A17 B17
A18 B18 CER43
CER42 A19 B19
A18 B18 CER75 CER154 A19 B19
CER122 A19 B19
A20 B20 CER41
CER40 A21 B21
A20 B20 CER73 CER152 A21 B21
CER120 A21 B21
A22 B22 CER39
D A22 B22 CER71 CER150 A23 B23 CER38 A23 B23
CER118 A23 B23
A24 B24 CER37
CER36 A25 B25
A24 B24 CER69 CER148 A25 B25
A25 B25
A26 B26 CER116

A25 B25 A26 B26 CER35

CER68 CER147 A26 B26
A27 B27 CER115

A26 B26 A27 B27 CER34
A28 B28 CER114
A27 B27 A28 B28 CER33
A29 B29 CER113
A28 B28 A29 B29 CER192
A30 B30 CER112
A29 B29 A30 B30 CER191
A31 B31 CER111
A30 B30 A31 B31 CER190
A32 B32 CER110
A31 B31 A32 B32 CER189
A33 B33 CER109
A32 B32 A33 B33 CER188
A34 B34 CER108
A33 B33 A34 B34 CER187
A35 B35 CER107
A34 B34 A35 B35 CER186
A36 B36 CER106
A35 B35 A36 B36 CER185
A37 B37 CER105
A36 B36 A37 B37 CER184
A38 B38 CER104
A37 B37 A38 B38 CER183
A39 B39 CER103
A38 B38 A39 B39 CER182
A40 B40 CER102
C A39 B39 A40 B40 CER181
A41 B41 CER101
A40 B40 A41 B41 CER180
A42 B42 CER100
A41 B41 A42 B42 CER179
A43 B43 CER99
A42 B42 A43 B43 CER178
A44 B44 CER98
A43 B43 A44 B44 CER177
A45 B45 CER97
A44 B44 A45 B45 CER176
CER17 CER96 A45 B45
A46 B46 CER64
A45 B45 A46 B46 CER175
CER16 CER95 A46 B46
A47 B47 CER63
A46 B46 A47 B47 CER174
CER15 CER94 A47 B47
A48 B48 CER62
A47 B47 A48 B48 CER173
CER14 CER93 A48 B48
A49 B49 CER61
A48 B48 A49 B49 CER172
CER13 CER92 A49 B49
CER60
CER12 A49 B49
A50 B50 CER171
A50 B50 CER91 A50 B50 CER59
CER170 A51 B51
A50 B50 CER11 CER90 A51 B51
CER58 A51 B51
A52 B52 CER169
CER168 A53 B53
A52 B52 CER9 CER88 A53 B53
CER56 A53 B53
A54 B54 CER167
CER166 A55 B55
A54 B54 CER7 CER86 A55 B55
CER54 A55 B55
A56 B56 CER165
CER6 A55 B55 A56 B56 CER85
B CER164 A57 B57
A56 B56 CER53
A56 B56 CER5 CER84 A57 B57
CER52 A57 B57
A58 B58 CER163
CER162 A59 B59
A58 B58 CER3 CER82 A59 B59
CER50 A59 B59
A60 B60 CER161
A60 B60 CER1
NON MONTARE: ALIMENTAZIONI IMPLICITE (1075000C_2)

-----------------------
A R24 R20 R26 R22 R30 R28
NET: GND
837 0147 042 Rev.A
--------
U5.10 U6.7 U9.10 U13.10 U16.10 U17.8
FORM:
NET: VCC
--------
U5.20 U6.14 U9.20 U13.20 U16.20 U17.16
ALIMENTAZIONI MODIFICATE
------------------------
SHEET DESCRIPTION:
"7300" INPUT BOARD
by EpD Number: 950 1075 000 SE D 5 5

1 2 3 4 5 6 7 8 9 10 11
+3V3
U17
L8 TMS320VC5502 +3V3 UP1
330U 29F040-120
60 PVDD PSENSE 61
+3V3 U7 +3V3 R144 TCOE 24 OE
C238 C239 TCD[0:31] 22
CK40A 63 X2/CLKIN D0/HPID0/EMIFD0 152 TCD0 CY7C1327 1K00 TCSEPROM CE
F 470N
47N 151 TCD1 ECLK 89 4
31 WE
D1/HPID1/EMIFD1 CLK VDDQ TCD[0:15]
62 150 TCD2 11
X1 D2/HPID2/EMIFD2 VDDQ
149 TCD3 83 20 TCA0 12 13 TCD0
D3/HPID3/EMIFD3 TB1 ADV VDDQ
TCA[0:18]
A0 O0
TB46 54 CLKOUT D4/HPID4/EMIFD4 147 TCD4 84 ADSP VDDQ 27 TCA1 11 A1 O1 14 TCD1
146 TCD5 TCADSC 85 54 TCA2 10 15 TCD2
D5/HPID5/EMIFD5 ADSC VDDQ A2 O2
TCA0 112 145 TCD6 61 TCA3 9 17 TCD3
TCA[0:19] A2/HPIA0/EMIFA2 D6/HPID6/EMIFD6 VDDQ A3 O3
TCA1 111 143 TCD7 TCA0 37 70 TCA4 8 18 TCD4
A3/HPIA1/EMIFA3 D7/HPID7/EMIFD7 A0 VDDQ A4 O4
TCA2 110 142 TCD8 TCA1 36 77 TCA5 7 19 TCD5
TCA3 108 140 TCD9 TCA2 35 TCA6 6 20 TCD6
A5/HPIA3/EMIFA5 D9/HPID9/EMIFD9 A2 A6 O6
TCA4 107 139 TCD10 TCA3 34 TCA7 5 21 TCD7
TCA5 106 138 TCD11 TCA4 33 TCA8 27
A7/HPIA5/EMIFA7 D11/HPID11/EMIFD11 A4 A8
TCA6 104 137 TCD12 TCA5 32 TCA9 26
TCA7 103 136 TCD13 TCA6 100 TCA10 23
A9/HPIA7/EMIFA9 D13/HPID13/EMIFD13 A6 TCD[0:31] A10
TCA8 102 135 TCD14 TCA7 99 TCA11 25
TCA9 101 134 TCD15 TCA8 82 58 TCD0 TCA12 4
A11/HPIA9/EMIFA11 D15/HPID15/EMIFD15 A8 DQ0 A12
+3V3 A12/HPIA10/EMIFA12 D16/PGPIO4/EMIFD16 A9 DQ1 A13
R12 A13/HPIA11/EMIFA13 D17/PGPIO5/EMIFD17 A10 DQ2 A14
E TCA12 96 A14/HPIA12/EMIFA14 D18/PGPIO6/EMIFD18 131 TCD18 TCA11 44 A11 DQ3 63 TCD3 TCA15 3 A15
4K7
A15/HPIA13/EMIFA15 D19/PGPIO7/EMIFD19 A12 DQ4 A16
R15 A16/HPIA14/EMIFA16 D20/PGPIO8/EMIFD20 A13 DQ5 A17
TCA15 92 A17/HPIA15/EMIFA17 D21/PGPIO9/EMIFD21 127 TCD21 R40 TCA14 47 A14 DQ6 72 TCD6 TCA18 1 A18
4K7
TCA16 90 126 TCD22 33 TCA15 48 73 TCD7
A18/PGPIO0/EMIFA18 D22/PGPIO10/EMIFD22 A15 DQ7
TCWE
TCA17 89 125 TCD23 TCA16 49 8 TCD8 UP2
R14 A19/PGPIO1/EMIFA19 D23/PGPIO11/EMIFD23 A16 DQ8 +3V3
TCA18 88 123 TCD24 TCA17 50 9 TCD9
4K7 A20/PGPIO2/EMIFA20 D24/PGPIO12/EMIFD24 A17 DQ9 29F040-120
TCA19 87 122 TCD25 43 12 TCD10
A21/PGPIO3/EMIFA21 D25/PGPIO13/EMIFD25 NC(A18) DQ10 24
120 TCD26
+3V3 TCA[0:17]
88 13 TCD11 R145 OE
R17 D26/PGPIO14/EMIFD26 GW DQ11 22 CE
TCINT0 8 119 TCD27 18 TCD12 1K00
4K7 INT0 D27/PGPIO15/EMIFD27 DQ12 31 WE
TCINT1 10 118 TCD28 TCWE 87 19 TCD13
INT1 D28/PGPIO16/EMIFD28 BWE DQ13
TCINT2 11 116 TCD29 TCBE0 93 22 TCD14
R16 INT2 D29/PGPIO17/EMIFD29 BWS0 DQ14
TCA0 12 13 TCD8
TCINT3 13 115 TCD30 TCBE1 94 23 TCD15 A0 O0
1K00 INT3 D30/PGPIO18/EMIFD30 BWS1 DQ15 TCA[0:18]
4K7 TCA1 11 14 TCD9
14 114 TCD31 R146 A1 O1
NMI/WDTOUT D31/PGPIO19/EMIFD31
TCA2 10 15 TCD10
15 R43 31 A2 O2
IACK 4K7 MODE R148 TCA3 9 17 TCD11
TCRESET 162 86 TCADSC A3 O3
R13 RESET C0/PGPIO20/ARE 4K7 TCA4 8 18 TCD12
85 TCOE TCSRAM 98 74 A4 O4
4K7 C1/PGPIO21/AOE CE1 DP0
TCA5 7 19 TCD13
D BOOTM0 5 84 97 24 A5 O5
GPIO0 C2/PGPIO22/AWE CE2 DP1
TCA6 6 20 TCD14
R9 BOOTM1 4 GPIO1 C3/PGPIO23/ARDY 82 92 CE3
A6 O6
BOOTM2 3 81 TCSRAM R143 TCA7 5 A7 O7 21 TCD15
4K7 GPIO2 C4/PGPIO24/CE0
TCOE 86 4K7 TCA8 27

CLKSOURCE 2 79 TCSCTRL OE A8
GPIO4 C5/PGPIO25/CE1
TCA9 26
R10 EMIFEN 1 GPIO6 C6/PGPIO26/CE2 78 TCSFLASH A9
64 TCA10 23
4K7 SERIAL2EN 176 72 TCSEPROM ZZ A10
GPIO7 C7/PGPIO27/CE3
TCA11 25
XCCLKA 55 71 TCBE0 A11
XF C8/PGPIO28/BE0
TCA12 4
R7 C9/PGPIO29/BE1 70 TCBE1 A12
TCA13 28
4K7 TB33 17 CLKR0 C10/PGPIO30/BE2 69 TCBE2 A13
R147 R153 R142 TCA14 29
18 68 TCBE3 A14
DR0 C11/PGPIO31/BE3 +3V3 TCA15 3
R8 TB36 19 FSR0 C12/PGPIO32/SDCKE 67 R37
4K7 4K7 4K7 +3V3 U12 +3V3 A15
TCA16 2
4K7 TB37 20 CLKX0 C13/PGPIO33/SOE 66 TB48 1K00 CY7C1327 A16
TCA17 30
TB38 22 DX0 C14/PGPIO34/HOLD 58 ECLK 89 4
A17
CLK VDDQ TCA18 1
R183 TB39 23 FSX0 C15/PGPIO35/HOLDA 57
11
A18
VDDQ
4K7 24 CLKR1 MONTARE SU ZOCCOLO
83 ADV VDDQ 20
25 DR1 ECLKIN 74 R42 84 ADSP VDDQ 27
R18 26 FSR1 ECLKOUT1 76 TB47 33 TCADSC 85 54
ADSC VDDQ
28 75 ECLK
C 4K7 CLKX1 ECLKOUT2 61
VDDQ
27 DX1 EMIFCLKS 64 TCA0
R41 37 A0 VDDQ 70 +3V3
R21 30 FSX1 TCA1 36 A1 VDDQ 77 UP3
XDONEA 31 175 XDATA0 1K00
4K7 DR2 HD0/PGPIO36 TCA2 35 A2 28F128J3A
32 173 XDATA1
DX2 HD1/PGPIO37 TCA3 34 32 43
A3 A0 VCCQ
R25 HD2/PGPIO38 172 XDATA2 R39 TCA4 33 TCA0 28
A4 A1
FLASH 38 170 XDATA3 1K00 TCA[0:19]
1K00 SP0/GPIO3/CLKX2 HD3/PGPIO39 TCA5 32 TCA1 27 33 TCD0
A5 A2 DQ0 TCD[0:15]
TB43 37 SP1/UARTTX/CLKR2 HD4/PGPIO40 169 XDATA4
TCA6 100 TCA2 26 35 TCD1
A6 A3 DQ1
XPROGA 35 167 XDATA5
SP2/GPIO5/FSX2 HD5/PGPIO41 TCA7 99 TCA3 25 38 TCD2
R31 34 166 XDATA6
A7 A4 DQ2
SP3/UARTRX/FSR2 HD6/PGPIO42 TCA8 82 58 TCD16 TCA4 24 40 TCD3
4K7 A8 DQ0 A5 DQ3
40 164 XDATA7 XDATA[0:7]
SCL HD7/PGPIO43 TCA9 81 59 TCD17 TCA5 23 44 TCD4
A9 DQ1 A6 DQ4
41 SDA TCA10 TCD18 TCA6 TCD5
80 A10 DQ2 62 22 A7 DQ5 46
R24 HC0/PGPIO44/HAS 43 XINITA +3V3 TCA11 44 63 TCD19 TCA7 20 49 TCD6
A11 DQ3 A8 DQ6
TCTCK 160 42 HP0
4K7 TCK HC1/PGPIO45/HBIL R34 TCA12 45 A12 DQ4 68 TCD20 TCA8 19 A9 DQ7 51 TCD7
TCTDI 158 TDI 4K7 TCA13 46 69 TCD21 TCA9 18 34 TCD8
A13 DQ5 A10 DQ8
TCTDO 156 46 HP1
R30 TDO HCNTL0 TCA14 47 A14 DQ6 72 TCD22 TCA10 17 A11 DQ9 36 TCD9
TCTMS 161 45 HP2
4K7 TMS HCNTL1 TCA15 48 73 TCD23 TCA11 13 39 TCD10
A15 DQ7 A12 DQ10
TCTRST 159 44 XCSA
TRST HCS TCA16 49 8 TCD24 TCA12 12 41 TCD11
B A16 DQ8 A13 DQ11
TCEMU0 155 48 XWE HP[0:6]
EMU0 HR/W TCA17 50 9 TCD25 TCA13 11 45 TCD12
R33 TCEMU1 154 51 HP3
A17 DQ9 A14 DQ12
EMU1 HDS1 43 12 TCD26 TCA14 10 47 TCD13
4K7 NC(A18) DQ10 A15 DQ13
49 HP4 TCA[0:17]
HDS2 88 13 TCD27 TCA15 8 50 TCD14
GW DQ11 A16 DQ14
52 HP5
HRDY R184 DQ12 18 TCD28 TCA16 7 A17 DQ15 52 TCD15
R32 TCTIM0 7 TIM0 HINT 59 HP6
1K00 TCWE 87 19 TCD29 TCA17 6 TB2
BWE DQ13 A18
TCTIM1 6 163
4K7 TIM1 HPIENA TCBE2 93 22 TCD30 FADD[20:23] TCA18 5 14
BWS0 DQ14 A19 CE0 TCSFLASH
TCBE3 94 23 TCD31 TCA19 4 2
BWS1 DQ15 A20 CE1
R187 FADD20 3 A21 CE2 29
+3V3 TB45 31 FADD21 1
1K00 MODE R157 A22
TB44 4K7
FADD22 30 A23 WE 55 FHWE
TCSRAM 98 74 FADD23 56 54
CE1 DP0 NC OE TCOE
R35 97 CE2 DP1 24 RP 16 FHRES
R185 92 CE3 R150 FSTS 53 STS
R6 1K00
4K7 4K7 FVPEN 15 VPEN BYTE 31
4K7 P4 TCOE 86 OE R166
TCTRST 1K00
TCTMS 1 2
TCTDI R152 64 ZZ
3 4
A R149 R160
5 6 R5 1K00
4K7
837 0147 042 Rev.A
TCTDO 7 8 1K00 4K7 R158

1K00
TCTCK 4K7 4K7
9 10 R156 +3V3 R151
FORM:
R159 R167 R155 R154

11 12
4K7 4K7 4K7
TCEMU0 13 14 TCEMU1 4K7

"7300" CONTROL BOARD
A2 CIVIDINI DONNINI BERTINI 08/06/05
by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500284 Number: 950 1078 000 SE E 1 11
1 2 3 4 5 6 7 8 9 10 11
+3V3
U42
74LCX245
+3V3
R265 19 G RLB[0:15]
1 T/R
1K00
F 9 A1 B1 11 RLB0
U30 R261 R260 TB71
R217 4K7 4K7 U30 8 A2 B2 12 RLB1
XC2S100E TB62 1K00 RLB2
R220 U45 XC2S100E 7 A3 B3 13
4K7 +3V3 6 14 RLB3
XDATA[0:7] 74LCX245 A4 B4
BANK 0 BANK 2 5 15 RLB4
R212 19 BANK 4 BANK 6 A5 B5
1K00 G
R223 R221 4 16 RLB5
TCD[0:15] 4K7 1 A6 B6
TCD0 A3 B16 XDATA0 4K7
R218 4K7
T/R LD[0:15]
3 17 RLB6
I/O I/O(DIN,D0) LD12 M10 J1 A7 B7
FEXDONE0I 18 2 FEXDONE0 I/O I/O
TCD1 A4 C15 RFCSA B1 A1 2 18 RLB7
I/O I/O,(DOUT,BUSY) LD13 M11 J2 A8 B8
FEXINIT0I 17 3 FEXINIT0 I/O(VREFBank4) I/O
TCD2 A5 C16 RFCSB B2 A2
I/O I/O(VREFBank2) LD14 N9 J3
FEXDONE1I 16 4 FEXDONE1 I/O I/O
TCD3 A6 D14 RFXPROG B3 A3
I/O I/O LD15 N10 J4
FEXINIT1I 15 5 FEXINIT1 I/O I/O,(TRDY)
TCD4 A7 D15 SCXPROG B4 A4
I/O I/O LA0 N11 K1
TCD5 B3 D16 RFXDONE R213 R224 FEXPROG1 14 B5 A5 6 I/O I/O(VREFBank6) TXFRAMEI
I/O I/O(VREFBank2) LA1 N12 K2
4K7 FEXPROG0 13 7 I/O I/O RXSTBI
TCD6 B4 E13 RFXINIT 4K7 B6 A6
LA[0:4]
I/O I/O LA2 P9 K3
12 8 I/O I/O PII
TCD7 B5 I/O(VREFBank0) I/O E14 SCXINIT R264 B7 A7
LA3 P10 K4
11 9 I/O I/O TB84I
TCD8 B6 E15 XDATA1 33 B8 A8
I/O I/O,(D1) LA4 P11 K5
I/O I/O
TCD9 B7 E16 SCXDONE FEXCCLK0
I/O I/O LRW P12 L1 +3V3
I/O I/O
TCD10 C4 I/O I/O F12 R227 R263 SCXCS0 P13 L2
E TCD11 C5 F13 33 R251 R250 I/O I/O U62
I/O(VREFBank0) I/O 0 LSSCAN R9 L3
RFXCCLK 4K7 I/O(DLL) I/O
TCD12 C6 I/O I/O,(D2) F14 XDATA2 FEXCCLK1 4K7 LSFE R10 L4 74LCX245
I/O(VREFBank4) I/O
TCD13 C7 F15 SCCTRLRW 19
I/O I/O R228 TB83 R11 I/O I/O(VREFBank6) L5 G
TCD14 D5 F16 SCCTRLCS 1
I/O I/O(VREFBank2) 0 R12 M1 T/R
SCXCCLK I/O(VREFBank4) I/O
TCD15 D6 G12 SCCTRL13
I/O I/O R13 M2 2 18 LQ0
I/O I/O(VREFBank6) A1 B1
TCA0 D7 G13 SCCTRL12
I/O(VREFBank0) I/O R14 M3 3 17 LQ1 LQ[0:2]
I/O I/O A2 B2
TCA1 D8 G14 SCCTRL11
I/O(DLL) I/O T10 M4 4 16 LQ2
I/O I/O A3 B3
TCA2 E6 G15 XDATA3 R165 R225
I/O I/O,(D3) POS T11 N1 5 15 FES0
I/O I/O A4 B4
TCA3 E7 G16 SCCTRL10 82 82
I/O I/O FEXDONE0I T12 N2 6 14 FES1
I/O I/O A5 B5 FES[0:2]
H13 SCCTRL9
I/O FEXINIT0I T13 N3 7 13 FES2
C132 C333 I/O I/O A6 B6
H14 SCCTRL8
I/O FEXDONE1I T14 P1 8 12 TXSTB
I/O I/O A7 B7
H15 SCCTRL7 100P 100P
I/O FEXINIT1I P2 9 11 TXRES
I/O A8 B8
TCWE C8 H16 SCCTRL6
GCK3,I I/O,(IRDY) LSCNT T9
+3V3 GCK0,I
U44
+3V3 E8 G11
+3V3 +3V3 TP11
VCCOBank0 VCCOBank2 74LCX245 +3V3 L9 VCCOBank4 VCCOBank6 J5
F7 VCCOBank0 VCCOBank2 H11 XDATA0 TB56 19 L10 J6 TP12
G VCCOBank4 VCCOBank6
F8 H12
VCCOBank0 VCCOBank2 XDATA1 TB66 T/R 1 M9 VCCOBank4 VCCOBank6 K6 U60
D TCA[0:19]
XDATA2 TB75 SADD[0:19]
SADD0 18 B1 A1 2 74LCX245
BANK 1 BANK 3
SADD1 17 3 BANK 5 BANK 7 19
XDATA3 TB69 B2 A2 G
SADD2 16 4 1
TCA4 A8 J13 SCCTRL5 B3 A3 T/R
I/O(DLL) I/O,(TRDY) C1
SADD3 15 5 I/O TB53

TCA5 A9 J14 XDATA4 B4 A4 2 18
I/O I/O,(D4) M6 C2 TXREFBE A1 B1

SADD4 14 6 I/O I/O
TCA6 A10 J15 SCCTRL4 B5 A5 3 17
I/O I/O M7 D1 FADD20 A2 B2
SADD5 13 7 I/O(VREFBank5) I/O
TCA7 A11 J16 SCCTRL3 B6 A6 4 16
I/O I/O N5 D2 FADD21 A3 B3
SADD6 12 8 I/O I/O
TCA8 A12 K12 SCCTRL2 B7 A7 5 15 HF0
I/O I/O N6 D3 FADD22 A4 B4
SADD7 11 9 I/O I/O
XWE A13 K13 SCCTRL1 B8 A8 6 14 HF1 HF[0:2]
I/O(WRITE) I/O(VREFBank3) SCCTRL[0:13] N7 E1 FADD23 A5 B5
I/O I/O
XCSA A14 K14 SCCTRL0 7 13 HF2
I/O(CS) I/O N8 E2 FHWE A6 B6
I/O I/O
TCA9 B9 I/O I/O K15 LD0 74LCX245 P4 E3 FSTS 8 A7 B7 12 FEPRG
I/O I/O(VREFBank7)
TCA10 B10 K16 LD1 19 9 11 FERW
I/O I/O U63 G P5 E4 FVPEN A8 B8
I/O I/O
TCA11 B11 L12 LD2 1
I/O(VREFBank1) I/O T/R P6 F1 FHRES
I/O I/O
TCA12 B12 L13 XDATA5
I/O I/O,(D5) SADD8 18 2 P7 F2
B1 A1 I/O I/O U61
TCA13 B13 L14 LD3
I/O I/O SADD9 17 3 P8 F3
B2 A2 I/O I/O
TCA14 C9 I/O I/O(VREFBank3) L15 LD4
SADD10 16 4 R4 F4 74LCX245
B3 A3 I/O I/O(VREFBank7)
TCA15 C10 L16 XDATA6 19
I/O I/O,(D6) SADD11 15 5 R5 F5 G
B4 A4 I/O(VREFBank5) I/O
TCA16 C11 M13 LD5 1
I/O I/O SADD12 14 6 R6 G1 T/R
C B5 A5 I/O(VREFBank5) I/O
TCA17 C12 M14 LD6
I/O I/O SADD13 13 7 R7 G2 9 11 RLB8
B6 A6 I/O I/O(VREFBank7) A1 B1
TCA18 D9 M15 LD7
I/O(VREFBank1) I/O(VREFBank3) SADD14 12 8 R8 G3 8 12 RLB9
B7 A7 I/O(DLL) I/O A2 B2
TCA19 D10 M16 LD8
I/O I/O SADD15 11 9 T3 G4 7 13 RLB10
B8 A8 I/O I/O A3 B3
TCSCTRL D11 N14 LD9
I/O I/O T4 G5 6 14 RLB11
U43 I/O I/O A4 B4
TCSEPROM D12 N15 LD10
I/O(VREFBank1) I/O T5 H1 5 15 RLB12
I/O I/O,(IRDY) A5 B5
TCOE E10 I/O I/O N16 LD11 LD[0:15] 74LCX245 T6 H2 4 16 RLB13
I/O I/O A6 B6
SCXCS1 E11 P15 XINITA 19
I/O I/O,(INIT) G T7 H3 3 17 RLB14
I/O I/O A7 B7
DPTCLK2 B8 P16 XDATA7 1
GCK2,I I/O,(D7) T/R CK40B T8 H4 2 18 RLB15
GCK1,I I/O A8 B8
SADD16 18 2
+3V3 E9 J11
B1 A1 TB82 +3V3
VCCOBank1 VCCOBank3 +3V3 SADD17 17 3 L7 G6
B2 A2 +3V3 VCCOBank5 VCCOBank7
F9 VCCOBank1 VCCOBank3 J12 SADD18 16 B3 A3 4 L8 VCCOBank5 VCCOBank7 H5
F10 VCCOBank1 VCCOBank3 K11 SADD19 15 B4 A4 5 M8 VCCOBank5 VCCOBank7 H6
TXFRAME 14 B5 A5 6 TXFRAMEI TP10
RXSTB 13 7
B6 A6 RXSTBI
PI 12 8
B7 A7 PII
TB84 11 B8 A8 9 TB84I +3V3
R47 R46 R48

4K7 4K7 4K7
R302
33
+3V3 XTCK
U30
XC2S100E J2
TB54
T2 M0 TDI C13 1 2
R1 B14 XTD1 XTDO 3 4
R36 M1 TDO
R3 B1 XTMS 5 6
33 M2 TMS
XCCLKA A15 A2 7 8
CCLK TCK
XPROGA R16 XTDI 9 10
PROGRAM
XDONEA T15 DONE
A
837 0147 042 Rev.A
1K00 1K00
R58
FORM:
R57
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 2 11

1 2 3 4 5 6 7 8 9 10 11
82 R181 R201
100P C159 TCLK0 0
82 R177 R206
100P C181 0
DPTCLK0
F 100P C282 82 R209 33 R203

DPTCLK1
100P C286 82 R211 33 R202

DPTCLK2
100P C302 82 R215 33 R205

TXS1
82 R180 R204
100P C158 0
TXS0
U27 U27 U27 U27

RFI[0:15] XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4
TB58 TB72
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
E RFI15 B4 IO IO/GCLK3P F12 FIROUTCK HWC0 C21 IO IO M21 TB80 AB19 IO/DOUT IO/GCLK7S AA11 TCWE V5 IO IO L2
RFI14 A4 IO IO/GCLK2S F13 HWC1 C22 IO IO M20 TB81 RFXINIT AA19 IO/INIT_B IO/GCLK6P Y11 LSCNT U5 IO IO L3
RFI13 C4 E12 E18 M19 XDATA0 V18 W11 LA0 Y2 L4 TCINT0
IO IO/GCLK1P IO/VRP2 IO IO/D0 IO/GCLK5S IO/VRN6 IO
RFI12 C5 D12 F18 M18 XDATA1 V17 V11 LA1 Y1 L5 TCINT1
IO IO/GCLK0S IO/VRN2 IO IO/D1 IO/GCLK4P IO/VRP6 IO
RFI11 B5 C12 REAL0 PBA/BI D21 M17 XDATA2 W18 U11 LA2 LA[0:4] V4 K1 TCINT2
IO/VRP0 IO IO IO/VREF3 IO/D2/ALT_VRP4 IO IO IO/VREF7
RFI10 A5 B12 REAL1 PEDI D22 N17 XDATA3 Y18 U10 LA3 V3 K2 TCINT3
IO/VRN0 IO/VREF1 IO/VREF2 IO IO/D3/ALT_VRN4 IO/VREF5 IO/VREF6 IO
RFI9 D6 A13 REAL2 E19 N22 TB79 MPADLDAC AA18 AB10 LA4 TB49 W2 K3
REAL[0:15]
IO/VREF0 IO IO IO IO/VREF4 IO IO IO
RFI8 C6 IO IO B13 REAL3 E20 IO IO N21 TB78 MPADLOAD AB18 IO IO AA10 LD0 W1 IO IO K4 TCOE
RFI7 B6 C13 REAL4 SELA/BI E21 N20 MPADDATA W17 Y10 LD1 SCSTOP U4 L6 TCSCTRL
IO IO IO IO IO/VRP4 IO IO IO
RFI6 A6 D13 REAL5 SELPEDI E22 N19 MPADCK Y17 W10 LD2 U3 K6 TCSEPROM
IO IO IO IO IO/VRN4 IO LD[0:15] IO IO
E7 E13 REAL6 F19 N18 MOTORON AA17 V10 LD3 CTRLD3 V2 K5 TCD0
IO IO IO IO IO IO IO IO
E8 IO IO/VREF1 E14 REAL7 F20 IO IO P18 TB70 AB17 IO IO/VREF5 V9 LD4 DL V1 IO IO J5 TCD1
D7 IO IO A14 REAL8 GSEL0I F21 IO IO/VREF3 P22 TB77 V16 IO IO AB9 LD5 ML U2 IO IO/VREF7 J1 TCD2
RFI5 C7 IO/VREF0 IO B14 REAL9 GSEL1I F22 IO/VREF2 IO P21 TB76 V15 IO IO AA9 LD6 IL U1 IO/VREF6 IO J2 TCD3
RFI4 B7 C14 REAL10 G18 P20 W16 Y9 LD7 ACFM0 T5 J3 TCD4
RFI3 A7 D14 REAL11 H18 P19 Y16 W9 LD8 ACFM1 R5 J4 TCD5
IO IO IO IO IO/VREF4 IO IO IO
CFMON
D8 A15 REAL12 G19 R22 AA16 AB8 LD9 T4 H1 TCD6
IO IO/VREF1 IO IO IO IO/VREF5 IO IO
D RFI2 C8 IO IO B15 REAL13 G20 IO IO R21 CFMOFF TB68 AB16 IO IO AA8 LD10 TB52 T3 IO IO H2 TCD7
RFI1 B8 IO IO C15 REAL14 MOT1 G21 IO IO R20 W15 IO IO Y8 LD11 TB51 T2 IO IO H3 TCD8
RFI0 A8 IO IO D15 REAL15 MOT0 G22 IO IO R19 Y15 IO IO W8 LD12 TB50 T1 IO IO H4 TCD9
E9 F14 IMG0 H19 R18 AA15 U9 LD13 TCTIM0 R4 J6 TCD10

IO IO IO IO/VREF3 IO IO IO IO/VREF7
TB67
F9 E15 IMG1 H20 P17 AB15 V8 LD14 TCTIM1 R3 H5 TCD11

IO/VREF0 IO IO/VREF2 IO IO IO IO/VREF6 IO
CTAUX4 D9 A16 IMG2 PROBE H21 T22 MLN0 U14 AB7 LD15 TCA0 R2 G1 TCD12
IMG[0:15]
TCA[0:19]
CTAUX5 C9 B16 IMG3 H22 T21 MLN1 V14 AA7 LRW TCA1 R1 G2 TCD13
CTAUX6 B9 C16 IMG4 J17 T20 W14 Y7 TCA2 P6 G3 TCD14 TCD[0:15]
CTAUX7 A9 D16 IMG5 J18 T19 Y14 W7 HP0 TCA3 P5 G4 TCD15
E10 E16 IMG6 J19 U22 MLN2 AA14 AB6 HP1 TCA4 P4 F1
CTAUX[0:7]
IO/VREF0 IO IO IO IO IO IO IO
HP[0:6]
F10 IO IO E17 IMG7 J20 IO IO U21 MLN3 TB65 AB14 IO IO AA6 HP2 TCA5 P3 IO IO F2 DACCLK
CTAUX0 D10 A17 IMG8 J21 U20 U13 Y6 HP3 TCA6 P2 F3 DACDATA0
IO IO IO IO/VREF3 IO/VREF4 IO IO IO/VREF7
CTAUX1 C10 B17 IMG9 J22 U19 V13 W6 HP4 TCA7 P1 F4 DACDATA1
IO IO IO/VREF2 IO IO IO IO/VREF6 IO
CTAUX2 B10 C17 IMG10 K17 T18 W13 V7 HP5 TCA8 N6 G5 DACDATA2
IO IO IO IO IO IO/VRP5 IO IO
CTAUX3 A10 D17 IMG11 K18 U18 Y13 V6 HP6 TCA9 N5 F5 DACDATA3
IO IO/VREF1 IO IO IO IO/VRN5 IO IO
E11 A18 K19 V22 AA13 AB5 TCA10 N4 E1 DACDATA4
IO/VREF0 IO/VRP1 IO IO IO IO IO IO
F11 IO IO/VRN1 B18 K20 IO IO V21 ACFM TB64 AB13 IO IO/VREF5 AA5 TCA11 N3 IO IO E2 DACDATA5
D11 C18 IMG12 K21 V20 U12 Y5 XDATA4 TCA12 N2 E3 DACDATA6
C IO/GCLK7P IO IO IO IO/VREF4 IO/D4/ALT_VRP5 IO IO
C11 D18 IMG13 K22 V19 V12 W5 XDATA5 TCA13 N1 E4 DACDATA7
IO/GCLK6S IO IO IO IO IO/D5/ALT_VRN5 IO IO
B11 IO/GCLK5P IO A19 IMG14 L17 IO IO/VREF3 W22 DREADY0 TB61 W12 IO/GCLK3S IO/D6 AB4 XDATA6 TCA14 M6 IO IO/VREF7 D1 DACDATA8
A11 B19 IMG15 L18 W21 Y12 AA4 XDATA7 TCA15 M5 D2 DACDATA9
IO/GCLK4S IO IO/VREF2 IO IO/GCLK2P IO/D7 IO/VREF6 IO
L19 Y22 DREADY1 TXREFBE AA12 Y4 XWE TCA16 M4 C1 DACDATA10
IO IO/VRP3 IO/GLCK1S IO/RDWR_B IO IO/VRN7
L20 Y21 CK40C AB12 AA3 RFCSA TCA17 M3 C2 DACDATA11
IO IO/VRN3 IO/GCLK0P IO/CS_B IO IO/VRP7
L21 W20 TCA18 M2 E5 DACDATA12
IO IO IO IO
+3V3 +3V3
L22 AA20
+3V3 TB57 +3V3 TCA19 M1 E6 DACDATA13
IO IO IO IO
G11 VCCOBank0 VCCOBank1 G14 L16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 L7
G10 VCCOBank0 VCCOBank1 G13 K16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 K7
G9 G12 J16 P16 T14 T11 P7 J7 +3V3
VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6
J4
B 33 R230 2 1 RFTEST1
R222 33 4 3 RFTEST2 +3V3
+3V3 R26 +5V
6 5 U19 10
8 7 THS5671A
10 9 DACCLK 28 24
CLK AVDD
+3V3
25 MODE
100N C14 C17
1K00 COMP1 19 C12 47U
33 DACDATA0 14
SMP R235 +3V3
TB55 R229 U27 D0 100N
U37 DACDATA1 13 23
D1 COMP2
XC2V1000-4 DACDATA2 12
74LCX245 RFXCCLK Y19 C19 XTCK
D2
100N C13
33 CCLK TCK DACDATA3 11 22
R234 19 G RFXPROG A2 D3 XTD2
D3 IOUT1
TXS PROG_B TDI DACDATA4 10
1 D4 RFTEST1
T/R RFXDONE AB20 D20 XTD3
DONE TDO DACDATA5 9 21
D5 IOUT2
33 R233 SELPEDI 2 A1 B1 18 SELPED AB2 M0 TMS B20 XTMS
DACDATA6 8
RFTEST2
DPTCK D6 100N
SELA/BI 3 17 SELA/B W3 D5
A2 B2 M1 DXN DACDATA7 7 16 C16
D7 EXTLO
PEDI 4 16 PED AB3 A3
A3 B3 M2 DXP DACDATA8 6 17
33 R232 D8 EXTIO
TCLK
PBA/BI 5 A4 B4 15 PBA/B B3 HSWAP_EN VBATT A21 DACDATA9 5 18 TP5 TP4
D9 BIASJ
A 6 A5 B5 14 AB21 PWRDWN_B RSVD A20 DACDATA10 TP7
4 D10 2K2 R28 R27
837 0147 042 Rev.A
7 A6 B6 13 1K00 DACDATA11 3 D11 SLEEP 15 R29 47 47

GSEL0I 8 A7 B7 12 GSEL0 R207 DACDATA12 2 D12
FORM:
GSEL1I 9 11 GSEL1
A8 B8 DACDATA13 1 20
D13 AGND
DACDATA[0:13]
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 3 11

1 2 3 4 5 6 7 8 9 10 11
+3V3
R219
33
U28 R226 U28 U28 U28
XC2V1000-4 33 XC2V1000-4 XC2V1000-4 XC2V1000-4
TCA[0:19]
F BANK 0 BANK 1 BANK 2 BANK 3 TB74 BANK 4 BANK 5 BANK 6 BANK 7
LD[0:15]
RFADD0 B4 F12 POTCS BDIG11 C21 M21 LD0 AB19 AA11 TCA6 BWD5 V5 L2 RFDC10
IO IO/GCLK3P IO IO IO/DOUT IO/GCLK7S IO IO
RFADD1 A4 F13 TGCAB ADIG12 C22 M20 LD1 RFXINIT AA19 Y11 TCA7 BWD6 U5 L3 RFDC11
IO IO/GCLK2S IO IO IO/INIT_B IO/GCLK6P IO IO
RFDC[0:15]
RFADD2 C4 E12 TGCWE E18 M19 LD2 XDATA0 V18 W11 TCA8 BWD7 Y2 L4 RFDC12
RFADD[0:16]

RFADD3 C5 D12 POTCK F18 M18 LD3 XDATA1 V17 V11 TCA9 CTRLD0 Y1 L5 RFDC13
RFADD4 B5 C12 TGCD0 BDIG12 D21 M17 LD4 XDATA2 W18 U11 TCA10 CTRLD1 V4 K1 RFDC14
RFADD5 A5 B12 TGCD1 ADIG13 D22 N17 LD5 XDATA3 Y18 U10 TCA11 CND0 V3 K2 RFDC15
TGCD[0:7]
RFADD6 D6 A13 TGCD2 BDIG13 E19 N22 LD6 IMG7 AA18 AB10 TCA16 CND1 W2 K3 OEMEMC
RFADD7 C6 B13 TGCD3 ADIG14 E20 N21 LD7 IMG6 AB18 AA10 TCA17 CND2 W1 K4 WEMEMC
CND[0:7]
RFADD8 B6 C13 TGCD4 BDIG14 E21 N20 LD8 IMG5 W17 Y10 TCA18 CND3 U4 L6 RFADC14
RFADD9 A6 D13 TGCD5 ADIG15 E22 N19 LD9 IMG4 Y17 W10 TCA19 CND4 U3 K6 RFDB0
IO IO IO IO IO/VRN4 IO IO IO
RFADD10 E7 E13 TGCD6 BDIG15 F19 N18 LD10 IMG3 AA17 V10 TCD0 CND5 V2 K5 RFDB1
RFADD11 E8 E14 TGCD7 ADIGREF0 F20 P18 LD11 IMG2 AB17 V9 TCD1 CND6 V1 J5 RFDB2
RFADD12 D7 A14 POTEOC BDIGREF0 F21 P22 LD12 IMG1 V16 AB9 TCD2 CND7 U2 J1 RFDB3
RFADD13 C7 B14 POTADD DDIG0 F22 P21 LD13 IMG0 V15 AA9 TCD3 RFDA0 U1 J2 RFDB4
TCD[0:15]
RFADD14 B7 C14 POTDOUT DDIG1 G18 P20 LD14 REAL15 W16 Y9 TCD4 RFDA1 T5 J3 RFDB5
E RFADD15 A7 IO IO D14 ADIG0 DDIG2 H18 IO IO P19 LD15 REAL14 Y16 IO/VREF4 IO W9 TCD5 RFDA2 R5 IO IO J4 RFDB6
RFADD16 D8 A15 BDIG0 DDIG3 G19 R22 LSCNT REAL13 AA16 AB8 TCD6 RFDA3 T4 H1 RFDB7
RFDB[0:15]
OEMEMD C8 B15 ADIG1 DDIG4 G20 R21 LRW REAL12 AB16 AA8 TCD7 RFDA4 T3 H2 RFDB8
WEMEMD B8 C15 BDIG1 DDIG5 G21 R20 RFI0 REAL11 W15 Y8 TCD8 RFDA5 T2 H3 RFDB9
CSMEMD A8 D15 ADIG2 DDIG6 G22 R19 RFI1 REAL10 Y15 W8 TCD9 RFDA6 T1 H4 RFDB10
RFDD0 E9 F14 BDIG2 DDIG7 H19 R18 RFI2 REAL9 AA15 U9 TCD10 RFDA7 R4 J6 RFDB11
RFDD1 F9 E15 ADIG3 DDIG8 H20 P17 RFI3 REAL8 AB15 V8 TCD11 RFDA8 R3 H5 RFDB12
IO/VREF0 IO IO/VREF2 IO IO IO
RFDA[0:15]
IO/VREF6 IO
RFDD[0:15]
RFDD2 D9 A16 BDIG3 DDIG9 H21 T22 RFI4 REAL7 U14 AB7 TCD12 RFDA9 R2 G1 RFDB13
RFDD3 ADIG4 DDIG10 RFI5 REAL6 TCD13 RFDA10 RFDB14
RFI[0:15]
C9 IO IO B16 H22 IO IO T21 V14 IO/VREF4 IO AA7 R1 IO IO G2
RFDD4 BDIG4 DDIG11 RFI6 REAL5 TCD14 RFDA11 RFDB15
REAL[0:15]
B9 IO IO/VREF1 C16 J17 IO IO T20 W14 IO IO/VREF5 Y7 P6 IO IO G3
RFDD5 A9 D16 ADIG5 DDIG12 J18 T19 RFI7 REAL4 Y14 W7 TCD15 RFDA12 P5 G4 OEMEMB
RFDD6 E10 E16 BDIG5 DDIG13 J19 U22 RFI8 REAL3 AA14 AB6 TCWE RFDA13 P4 F1 WEMEMB
RFDD7 F10 E17 ADIG6 DDIG14 J20 U21 RFI9 REAL2 AB14 AA6 TCOE RFDA14 P3 F2 RFADB14
RFDD8 D10 A17 BDIG6 DDIG15 J21 U20 RFI10 REAL1 U13 Y6 TCSCTRL RFDA15 P2 F3 RFAD0
RFDD9 C10 B17 ADIG7 DDIG16 J22 U19 RFI11 REAL0 V13 W6 BWD0 OEMEMA P1 F4 RFAD1
RFDD10 B10 C17 BDIG7 DDIG17 K17 T18 RFI12 TCA0 W13 V7 BWD1 WEMEMA N6 G5 RFAD2
BWD[0:7]
RFAD[0:13]
IMG[0:15]
RFDD11 A10 D17 ADIG8 DDIG18 K18 U18 RFI13 TCA1 Y13 V6 BWD2 RFADA14 N5 F5 RFAD3
D RFDD12 E11 A18 BDIG8 DDIG19 K19 V22 RFI14 TCA2 AA13 AB5 BWD3 RFDC0 N4 E1 RFAD4
TCA[0:19]
RFDD13 F11 B18 ADIG9 ADIGREF1 K20 V21 RFI15 TCA3 AB13 AA5 BWD4 RFDC1 N3 E2 RFAD5
IO IO/VRN1 IO IO IO IO/VREF5 IO IO
RFDD14 D11 C18 BDIG9 BDIGREF1 K21 V20 IMG15 TCA4 U12 Y5 XDATA4 RFDC2 N2 E3 RFAD6
IO/GCLK7P IO IO IO IO/VREF4 IO/D4/ALT_VRP5 IO IO
RFDD15 C11 D18 ADIG10 LA0 K22 V19 IMG14 TCA5 V12 W5 XDATA5 RFDC3 N1 E4 RFAD7
RFDC[0:15]
TB60
B11 A19 BDIG10 LA1 L17 W22 IMG13 DPTCLK1 W12 AB4 XDATA6 RFDC4 M6 D1 RFAD8
IO/GCLK5P IO IO IO/VREF3 IO/GCLK3S IO/D6 IO IO/VREF7
TB59 A11 IO/GCLK4S IO B19 ADIG11 LA2 L18 IO/VREF2 IO W21 IMG12 TXS1 Y12 IO/GCLK2P IO/D7 AA4 XDATA7 RFDC5 M5 IO/VREF6 IO D2 RFAD9
LA3 L19 Y22 IMG11 FIROUTCK AA12 Y4 XWE RFDC6 M4 C1 RFAD10
LA4 L20 Y21 IMG10 CK40D AB12 AA3 RFCSB RFDC7 M3 C2 RFAD11
ADIG[0:15]
DDIG[0:19]
BDIG[0:15]
L21 W20 IMG9 RFDC8 M2 E5 RFAD12

IO IO IO IO
LA[0:4]
+3V3 +3V3 +3V3

L22 IO IO AA20 IMG8 TB63 +3V3 RFDC9 M1 IO IO E6 RFAD13
G9 G12 J16 P16 T14 T11 P7 J7 +3V3
U20 U26 U25 U29

K6R1016V1D K6R1016V1D K6R1016V1D KM616V4002BT-15
OEMEMA 41 OEMEMB 41 OEMEMC 41 OEMEMD 41
OE OE OE OE
WEMEMA 17 WEMEMB 17 WEMEMC 17 WEMEMD 17
WE WE WE WE
6 6 6 CSMEMD 6
R198 CS R200 CS R199 CS CS
1K00 40 UB 1K00 40 UB 1K00 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB +3V3
RFAD0 44 7 RFDA0 RFAD0 44 7 RFDB0 RFAD0 44 7 RFDC0 RFADD0 5 7 RFDD0
B A0 I/O0 A0 I/O0 A0 I/O0 A0 I/O0
RFAD1 43 8 RFDA1 RFAD1 43 8 RFDB1 RFAD1 43 8 RFDC1 RFADD1 4 8 RFDD1 +3V3
A1 I/O1 A1 I/O1 A1 I/O1 A1 I/O1
A2 I/O2 A2 I/O2 A2 I/O2 A2 I/O2
A3 I/O3 A3 I/O3 A3 I/O3 A3 I/O3
A4 I/O4 A4 I/O4 A4 I/O4 A4 I/O4
RFAD5 25 14 RFDA5 RFAD5 25 14 RFDB5 RFAD5 25 14 RFDC5 RFADD5 44 14 RFDD5 1K00
A5 I/O5 A5 I/O5 A5 I/O5 A5 I/O5
RFAD6 24 15 RFDA6 RFAD6 24 15 RFDB6 RFAD6 24 15 RFDC6 RFADD6 43 15 RFDD6 R231 U28 R210
A6 I/O6 A6 I/O6 A6 I/O6 A6 I/O6 TB73 4K7
RFAD7 21 A7 I/O7 16 RFDA7 RFAD7 21 A7 I/O7 16 RFDB7 RFAD7 21 A7 I/O7 16 RFDC7 RFADD7 42 A7 I/O7 16 RFDD7 XC2V1000-4
RFAD8 20 29 RFDA8 RFAD8 20 29 RFDB8 RFAD8 20 29 RFDC8 RFADD8 27 29 RFDD8 RFXCCLK Y19 C19 XTCK
A8 I/O8 A8 I/O8 A8 I/O8 A8 I/O8 CCLK TCK
RFAD9 19 30 RFDA9 RFAD9 19 30 RFDB9 RFAD9 19 30 RFDC9 RFADD9 26 30 RFDD9 RFXPROG A2 D3 XTD1
A9 I/O9 A9 I/O9 A9 I/O9 A9 I/O9 PROG_B TDI
RFAD10 18 31 RFDA10 RFAD10 18 31 RFDB10 RFAD10 18 31 RFDC10 RFADD10 25 31 RFDD10 RFXDONE AB20 D20 XTD2 J3
A10 I/O10 A10 I/O10 A10 I/O10 A10 I/O10 DONE TDO
RFAD11 5 32 RFDA11 RFAD11 5 32 RFDB11 RFAD11 5 32 RFDC11 RFADD11 24 32 RFDD11 AB2 B20 XTMS
A11 I/O11 A11 I/O11 A11 I/O11 A11 I/O11 M0 TMS 1 2
RFAD12 4 35 RFDA12 RFAD12 4 35 RFDB12 RFAD12 4 35 RFDC12 RFADD12 23 35 RFDD12 W3 D5
A12 I/O12 A12 I/O12 A12 I/O12 A12 I/O12 M1 DXN 3 4
RFAD13 3 36 RFDA13 RFAD13 3 36 RFDB13 RFAD13 3 36 RFDC13 RFADD13 22 36 RFDD13 AB3 A3
A13 I/O13 A13 I/O13 A13 I/O13 A13 I/O13 M2 DXP 5 6
RFADA14 2 37 RFDA14 RFADB14 2 37 RFDB14 RFADC14 2 37 RFDC14 RFADD14 21 37 RFDD14 B3 A21
A14 I/O14 A14 I/O14 A14 I/O14 A14 I/O14 HSWAP_EN VBATT 7 8
1 38 RFDA15 1 38 RFDB15 1 38 RFDC15 RFADD15 20 38 RFDD15 AB21 A20
A15 I/O15 A15 I/O15 A15 I/O15 A15 I/O15 PWRDWN_B RSVD 9 10
22 22 22 RFADD16 19
NC NC NC A16
23 NC 23 NC 23 NC 18 A17
A 28 28 28 1K00
NC NC NC
R208
837 0147 042 Rev.A
FORM:
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 4 11

1 2 3 4 5 6 7 8 9 10 11
U15 U15 U15 U15 TB35

TB12
XC2S300 XC2S300 XC2S300 XC2S300
TB23
DP2D0 A3 A11 CK40E SCCTRL8 C21 L22 CFM2D0 U12 U9 CFM1D0 M1 C1 BW1D0
I/O GCK2,I I/O(DOUT,BUSY) I/O(TRDY) I/O I/O I/O(TRDY) I/O
DP2D1 A4 A12 DP1D0 SCCTRL0 C22 M17 CFMPD22 U13 U10 CFM1D9 M2 C2 AVG_DATA3
I/O I/O(DLL) I/O(DIN,D0) I/O I/O I/O I/O I/O
DP2D2 A5 A13 DP1D1 BWPD7 D20 M18 CFMPD15 U14 U11 SCAN_MODEOUT4 M3 D1 BW1D1
I/O I/O I/O I/O I/O I/O I/O I/O
DP2D3 A6 A14 DP1D2 BW2D7 D21 M19 CFMPD7 V12 V6 LINK10 LD2 M4 D2 AVG_DATA4
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O
DP2D4 A7 A15 DP1D3 BW2D0 D22 M20 CFM2D15 V13 V7 LINK11 LD15 M5 D3 AVG_DATA12
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O
DP2D5 A8 I/O I/O A16 DP1D4 CNPD6 E19 I/O I/O M21 CFM2D8 V14 I/O I/O(VREFBank5) V8 TB30 M6 I/O I/O E1 BW1D2
DP2D6 A9 I/O I/O A17 DP1D5 CNPD0 E20 I/O I/O M22 CFM2D1 TB13 V15 I/O(VREFBank4) I/O V9 CFM1D1 N1 I/O I/O(VREFBank7) E2 AVG_DATA5
E DP2D7 A10 I/O I/O A18 DP1D6 BWPD0 E21 I/O I/O(D4) N17 SCCTRL4 V16 I/O I/O(VREFBank5) V10 TB25 CFM1D10 N2 I/O I/O E3 AVG_DATA13
QM2D0 B3 A19 DP1D7 BW2D1 E22 N18 CFMPD16 V17 V11 SCAN_MODEOUT5 N3 F1 BW1D3
I/O I/O I/O I/O(VREFBank3) I/O I/O I/O(VREFBank6) I/O
QM2D1 B4 A20 XWE SCCTRL10 F18 N19 CFMPD8 DDOTIN W12 W5 LINK8 LD3 N4 F2 AVG_DATA6
I/O I/O(WRITE) I/O I/O I/O I/O I/O I/O(VREFBank7)
QM2D2 B5 B12 QM1D0 CNPD7 F19 N20 CFMPD0 W13 W6 LINK9 LA0 N5 F3 AVG_DATA14
QM2D3 B6 I/O(VREFBank0) I/O(VREFBank1) B13 QM1D1 CNPD1 F20 I/O I/O N21 CFM2D9 TB20 W14 I/O I/O W7 DLINEIN N6 I/O I/O F4 DL
QM2D4 B7 B14 QM1D2 BWPD1 F21 N22 CFM2D2 W15 W8 CFM1D2 P1 F5 LD9
QM2D5 B8 B15 QM1D3 BW2D2 F22 P17 CFMPD23 W16 W9 CFM1D11 P2 G1 BW1D4
QM2D6 B9 B16 QM1D4 SCCTRL11 G18 P18 CFMPD17 LINK14 W17 W10 SCAN_MODEOUT6 P3 G2 AVG_DATA7
QM2D7 B10 B17 QM1D5 SCSTOP G19 P19 CFMPD9 LINK15 W18 W11 LD4 P4 G3 AVG_DATA15
QM2D8 B11 B18 QM1D6 CNPD2 G20 P20 CFMPD1 TXS0 Y12 Y5 DPD0 LA1 P5 G4 SCAUX0
I/O(DLL) I/O(VREFBank1) I/O I/O I/O(DLL) I/O I/O I/O
QM2D9 C4 I/O I/O B19 QM1D7 BWPD2 G21 I/O I/O P21 CFM2D10 DPD7 Y13 I/O I/O Y6 DPD1 TB32 P6 I/O I/O G5 LD10
QM2D10 C5 I/O(VREFBank0) I/O(CS) B20 SCXCS1 BW2D3 G22 I/O I/O(D5) P22 SCCTRL5 TB14 Y14 I/O I/O Y7 DPD2 CFM1D3 R1 I/O I/O H1 BW1D5
QM2D11 C6 C12 RHO_WEIGHT0 SCCTRL12 H18 R18 CFMPD18 DPAUX Y15 Y8 DPD3 CFM1D12 R2 H2 AVG_DATA8
I/O I/O I/O(VREFBank2) I/O(VREFBank3) I/O I/O I/O I/O
THETA_WEIGHT0 C7 C13 RHO_WEIGHT1 SCCTRL1 H19 R19 SCCTRL6 Y16 Y9 DPD4 SCAN_MODE7 R3 H3 SCAN_MODEOUT0
I/O I/O I/O(D1) I/O(D6) I/O I/O I/O(VREFBank6) I/O(VREFBank7)
THETA_WEIGHT1 C8 I/O I/O C14 RHO_WEIGHT2 SCCTRL2 H20 I/O(D2) I/O R20 CFMPD2 TB15 Y17 I/O(VREFBank4) I/O Y10 DPD5 LD5 R4 I/O I/O H4 SCAUX1
THETA_WEIGHT2 C9 C15 RHO_WEIGHT3 BWPD3 H21 R21 CFM2D11 LINK12 Y18 Y11 DPD6 LA2 R5 H5 LD11
THETA_WEIGHT3 C10 C16 QM1D8 BW2D4 H22 R22 CFM2D3 LINK13 Y19 AA3 BWD0 CFM1D4 T1 J1 BW1D6
D DPTCLK0 C11 C17 QM1D9 LINK7 J17 T18 CFMPD19 SCCLK1 AA12 AA5 BWD1 CFM1D13 T2 J2 AVG_DATA9
GCK3,I I/O I/O I/O GCK0/I I/O I/O I/O
QM2D12 D5 C18 QM1D10 SCCTRL13 J18 T19 CFMPD10 CND0 AA13 AA6 BWD2 SCAN_MODE8 T3 J3 SCAN_MODEOUT1
QM2D13 D6 I/O I/O D12 QM1D14 TB4 J19 I/O I/O T20 CFMPD3 CND1 AA14 I/O I/O AA7 BWD3 LD6 T4 I/O I/O J4 ESCANOUT
QM2D14 D7 D13 QM1D15 CNPD3 J20 T21 CFM2D12 CND2 AA15 AA8 BWD4 LA3 T5 J5 LD12
I/O I/O I/O I/O(VREFBank3) I/O I/O I/O I/O

QM2D15 D8 D14 CTRLD0 BWPD4 J21 T22 CFM2D4 CND3 AA16 AA9 BWD5 CFM1D5 U1 J6 LA4
I/O(VREFBank0) I/O I/O I/O I/O I/O I/O(VREFBank6) I/O
QM1D11 D9 D15 CTRLD1 BW2D5 J22 U18 CFMPD20 CND4 AA17 AA10 BWD6 CFM1D14 U2 K1 BW1D7
I/O I/O(VREFBank1) I/O I/O I/O I/O I/O I/O
QM1D12 D10 D16 TCLK0 K17 U19 CFMPD11 CND5 AA18 AA11 BWD7 SCAN_MODE9 U3 K2 AVG_DATA10
I/O(VREFBank0) I/O I/O I/O I/O I/O I/O I/O
QM1D13 D11 D17 CTRLD3 CFMPD13 K18 U20 CFMPD4 CND6 AA19 AB3 CFMD0 LD7 U4 K3 SCAN_MODEOUT2
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O(VREFBank7)
ML E7 D18 IL SCCTRL3 K19 U21 CFM2D13 CND7 AA20 AB4 CFMD1 CFM1D6 V1 K4 LD0
I/O I/O I/O(D3) I/O I/O I/O I/O I/O
MOT0 E8 E12 SCCTRLRW CNPD4 K20 U22 CFM2D5 CFMD9 AB13 AB5 CFMD2 CFM1D15 V2 K5 LD13
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O(VREFBank6) I/O
MOT1 E9 E13 SCCTRLCS BWPD5 K21 V19 CFMPD12 CFMD10 AB14 AB6 CFMD3 MCYCLE_START V3 K6 LSSCAN
E10 E14 SCCTRL9 BW2D6 K22 V20 CFMPD5 CFMD11 AB15 AB7 CFMD4 LD8 V4 L1 AVG_DATA0
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O I/O
ACFM0 E11 E15 DPTCLK0 CFMPD21 L17 V21 CFM2D14 CFMD12 AB16 AB8 CFMD5 CFM1D7 W1 L2 AVG_DATA11
LINK1 F9 E16 ACFM1 CFMPD14 L18 V22 CFM2D6 CFMD13 AB17 AB9 CFMD6 AVG_DATA1 W2 L3 SCAN_MODEOUT3
I/O I/O(VREFBank1) I/O I/O(VREFBank3) I/O I/O I/O I/O
LINK2 F10 E17 LINK0 CFMPD6 L19 W21 SCXINIT CFMD14 AB18 AB10 CFMD7 MRESET_DONE W3 L4 LD1
I/O I/O I/O I/O(INIT) I/O I/O I/O I/O
LINK3 F11 F12 LINK4 CNPD5 L20 W22 CFM2D7 CFMD15 AB19 AB11 CFMD8 CFM1D8 Y1 L5 LD14
I/O I/O I/O I/O I/O I/O(DLL) I/O I/O
F13 LINK5 BWPD6 L21 Y22 SCCTRL7 CFMD16 AB20 AB12 SCCLK0 AVG_DATA2 Y2 L6 LRW
I/O I/O(IRDY) I/O(D7) I/O GCK1,I I/O I/O(IRDY)
F14 LINK6 CFMD17 AB21
C I/O I/O
TB5
TB26 F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T9 TB19 N7 VCCOBank6 VCCOBank7 G6
F8 F16 H17 P16 T14 T10 P7 H6
TB29 VCCOBank0 VCCOBank1
TB11 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
G9 G13 J16 R17 U15 U7 R6 J7
TB24 VCCOBank0 VCCOBank1 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7
TB31 G10 VCCOBank0 VCCOBank1 G14 TB7 K16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
TB3
+3V3 +3V3 +3V3 +3V3
+3V3 +3V3 +3V3
+3V3
VICINO PIN U15
R174
TB27 VICINO PIN U15
82
C171
R11 VICINO PIN U15
100P
82
C7
100P
B +3V3
TB10
TB8
U15
TB9
XC2S300
SCXCCLK B22 E6 XTCK
CCLK TCK
SCXPROG Y21 PROGRAM
SCXDONE W20 DONE
AA1 C19 XTD4
M0 TDI
U5 A21 XTDO
M1 TDO
AB2 E4 XTMS
M2 TMS
R196
1K00
A
837 0147 042 Rev.A
FORM:
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 5 11

1 2 3 4 5 6 7 8 9 10 11
+3V3 +3V3
+3V3
+3V3
R189 R161
33 R186 R162 33 R172 33 R195
R170 R194
F 33
TB16 33 33 33 33
U14 R179
U14
XC2V1000-4 33 U14 U14
SCCLK1 XC2V1000-4
TB28 XC2V1000-4 XC2V1000-4 TB40
VICINO PIN U14
BANK 0 BANK 1
BANK 2 BANK 3
BANK 4 BANK 5 TB42
BANK 6 BANK 7
MICD11 B4 F12 LSSCAN
IO IO/GCLK3P BW2A9 C21 M21 CFM2A7
IO IO
MICD5 A4 F13 ML SCCTRL8 AB19 AA11 DPTCLK0
IO IO/GCLK2S BW2A0 C22 M20 CFM2A15 IO/DOUT IO/GCLK7S LD6 V5 L2 BW1A14
IO IO IO IO
LD13 C4 E12 DL SCXINIT AA19 Y11 TCLK0
IO IO/GCLK1P LINK14 E18 M19 CFMPA3 IO/INIT_B IO/GCLK6P LD5 U5 L3 SCAN_MODEOUT0
IO/VRP2 IO IO IO
LD14 C5 D12 MOT0 SCCTRL0 V18 W11 CTRLD1
IO IO/GCLK0S LINK15 F18 M18 CFMPA10 IO/D0 IO/GCLK5S LINK4 Y2 L4 SCAN_MODE7
IO/VRN2 IO IO/VRN6 IO
LINK11 B5 C12 MICUB SCCTRL1 V17 V11 CTRLD0
IO/VRP0 IO BW2A10 D21 M17 CFMPA16 IO/D1 IO/GCLK4P LINK5 Y1 L5 MRESET_DONE
IO IO/VREF3 IO/VRP6 IO
LINK10 A5 B12 MICA12 SCCTRL2 W18 U11 QM1D12
IO/VRN0 IO/VREF1 BW2A1 D22 N17 CFMPA17 IO/D2/ALT_VRP4 IO XY_ADD8 V4 K1 BW1A6
IO/VREF2 IO IO IO/VREF7
LA0 D6 A13 MICA5 SCCTRL3 Y18 U10 QM1D11
IO/VREF0 IO BWPA4 E19 N22 CFM2A0 IO/D3/ALT_VRN4 IO/VREF5 XY_ADD1 V3 K2 BW1A13
IO IO IO/VREF6 IO
LD15 C6 B13 MICA11 QM1D3 AA18 AB10 DP2D5
IO IO BW2A18 E20 N21 CFM2A8 IO/VREF4 IO CFM1A15 W2 K3 BW1WE
IO IO IO IO
MICD10 B6 C13 MICOE DP1D5 AB18 AA10 QM2D3
IO IO BW2A11 E21 N20 CFM2A16 IO IO CFM1A7 W1 K4 SCAN_MODEOUT6
IO IO IO IO
MICD4 A6 D13 MOT1 LINK3 W17 Y10 THETA_WEIGHT0
IO IO BW2A2 E22 N19 CFMPA4 IO/VRP4 IO XY_ADD7 U4 L6 LD9
IO IO IO IO
LA3 E7 E13 SCSTOP LINK2 Y17 W10 QM2D9
IO IO BWPA5 F19 N18 CFMPA11 IO/VRN4 IO XY_ADD0 U3 K6 LD8
IO IO IO IO
E DPAUX E8 E14 QM1D2 AA17 V10 QM1D8
IO IO/VREF1 BW2OE F20 P18 CFMPA12 IO IO CFM1A14 V2 K5 MCYCLE_START
IO IO IO IO
LA2 D7 A14 MICA4 DP1D4 AB17 V9 QM2D11
IO IO BW2A12 F21 P22 CFM2A1 IO IO/VREF5 CFM1A6 V1 J5 SCAUX1
IO IO/VREF3 IO IO
MICD15 C7 B14 MICA10 QM2D14 V16 AB9 DP2D4
IO/VREF0 IO BW2A3 F22 P21 CFM2A9 IO IO CFM1A13 U2 J1 BW1A5
MICD9 B7 C14 MICLB QM2D13 V15 AA9 QM2D2
IO IO BWPA11 G18 P20 CFM2A17 IO IO CFM1A5 U1 J2 BW1A12
IO IO IO/VREF6 IO
MICD3 A7 D14 ACFM1 RHO_WEIGHT3 W16 Y9 QM2D7
IO IO BWPA12 H18 P19 CFMPA5 IO IO LD4 T5 J3 BW1OE
IO IO IO IO
LA4 D8 A15 MICA3 QM1D7 Y16 W9 QM2D8
IO IO/VREF1 BWPA6 G19 R22 CFM2A2 IO/VREF4 IO LD3 R5 J4 SCAN_MODEOUT5
IO IO IO IO
MICD14 C8 B15 MICA9 QM1D1 AA16 AB8 DP2D3
IO IO BW2WE G20 R21 CFM2A10 IO IO/VREF5 XY_ADD6 T4 H1 BW1A4
IO IO IO IO
MICD8 B8 IO IO C15 TB17 BW2A13 G21 R20 CFM2A18
DP1D3 AB16 IO IO AA8 QM2D1
CFM1WE T3 H2 BW1A11
IO IO IO IO
MICD2 A8 D15 CFMPWE RHO_WEIGHT2 W15 Y8 QM2D6
IO IO BW2A4 G22 R19 CFMPA6 IO IO CFM1A12 T2 H3 BW1A18
IO IO IO IO
MICCS E9 F14 SCCTRL9 QM1D6 Y15 W8 THETA_WEIGHT3
IO IO BWPA7 H19 R18 CFMPA13 IO IO CFM1A4 T1 H4 SCAN_MODEOUT4
IO IO/VREF3 IO IO
SCCTRL12 F9 E15 CNPWE QM1D0 AA15 U9 QM2D15
IO/VREF0 IO BWPA0 H20 P17 CFMPA18 IO IO XY_ADD5 R4 J6 LD7
LRW D9 A16 MICA2 DP1D2 AB15 V8 QM2D10
IO IO BW2A14 H21 T22 CFM2A3 IO IO CFM1OE R3 H5 SCAUX0
IO IO IO/VREF6 IO
MICD13 C9 B16 MICA8 QM1D15 U14 AB7 DP2D2
IO IO BW2A5 H22 T21 CFM2A11 IO IO CFM1A11 R2 G1 BW1A3
IO IO IO IO
MICD7 B9 C16 MICA15 QM2D12 V14 AA7 QM2D0
IO IO/VREF1 BWPA16 J17 T20 CFM2OE IO/VREF4 IO CFM1A3 R1 G2 BW1A10
IO IO IO IO
MICD1 A9 D16 CNPOE RHO_WEIGHT1 W14 Y7 QM2D5
IO IO BWPA13 J18 T19 CFMPA7 IO IO/VREF5 LD12 P6 G3 BW1A17
IO IO IO IO
SCCTRLRW E10 E16 BWPWE QM1D5 Y14 W7 THETA_WEIGHT2
IO/VREF0 IO BWPA8 J19 U22 CFM2A4 IO IO LD2 P5 G4 SCAN_MODEOUT3
IO IO IO IO
SCCTRL11 F10 E17 CFMPOE DP1D7 AA14 AB6 DP2D1
IO IO BWPA1 J20 U21 CFM2A12 IO IO XY_ADD4 P4 F1 BW1A2
IO IO IO IO
ACFM0 D10 A17 MICA1 DP1D1 AB14 AA6 DP2D7
D IO IO BW2A15 J21 U20 CFM2WE IO IO CFM1A18 P3 F2 BW1A9
IO IO/VREF3 IO IO
MICD12 C10 B17 MICA7 QM1D14 U13 Y6 QM2D4
IO IO BW2A6 J22 U19 CFMPA8 IO/VREF4 IO CFM1A10 P2 F3 BW1A16
MICD6 B10 C17 MICA14 QM1D10 V13 W6 THETA_WEIGHT1
IO IO BWPA17 K17 T18 CFMPA14 IO IO CFM1A2 P1 F4 SCAN_MODEOUT2
IO IO IO/VREF6 IO
MICD0 A10 D17 BWPOE RHO_WEIGHT0 W13 V7 LINK1
IO IO/VREF1 BWPA14 K18 U18 CFMPA15 IO IO/VRP5 LD11 N6 G5 ESCANOUT

IO IO IO IO
SCCTRL13 E11 A18 LINK12 QM1D4 Y13 V6 LINK0
IO/VREF0 IO/VRP1 BWPA9 K19 V22 CFM2A5 IO IO/VRN5 LD1 N5 F5 SCAN_MODE9

IO IO IO IO
SCCTRL10 F11 B18 LINK13 DP1D6 AA13 AB5 DP2D0
IO IO/VRN1 BWPA2 K20 V21 CFM2A13 IO IO XY_ADD3 N4 E1 BW1A1
IO IO IO IO
IL D11 C18 MICA13 DP1D0 AB13 AA5 DP2D6
IO/GCLK7P IO BW2A16 K21 V20 CFMPA0 IO IO/VREF5 CFM1A17 N3 E2 BW1A8
IO IO IO IO
SCCTRLCS C11 D18 MICWE QM1D13 U12 Y5 SCCTRL4
IO/GCLK6S IO BW2A7 K22 V19 CFMPA9 IO/VREF4 IO/D4/ALT_VRP5 CFM1A9 N2 E3 BW1A15
IO IO IO IO
TXS0 B11 A19 MICA0 QM1D9 V12 W5 SCCTRL5
IO/GCLK5P IO BWPA18 L17 W22 CFM2A6 IO IO/D5/ALT_VRN5 CFM1A1 N1 E4 SCAN_MODEOUT1
SCCLK0 IO IO/VREF3 IO IO
A11 B19 MICA6 CTRLD3 W12 AB4 SCCTRL6
IO/GCLK4S IO BWPA15 L18 W21 CFM2A14 IO/GCLK3S IO/D6 LD10 M6 D1 BW1A0
33 DLINEIN Y12 AA4 SCCTRL7
BWPA10 L19 Y22 LINK7 IO/GCLK2P IO/D7 LD0 M5 D2 BW1A7
IO IO/VRP3 IO/VREF6 IO
DDOTIN AA12 Y4 XWE
VICINOR173
PIN U14 BWPA3 L20 Y21 LINK6 IO/GLCK1S IO/RDWR_B XY_ADD2 M4 C1 LINK8
IO IO/VRN3 IO IO/VRN7
CK40F AB12 AA3 SCXCS0
BW2A17 L21 W20 CFMPA1 IO/GCLK0P IO/CS_B CFM1A16 M3 C2 LINK9
IO IO IO IO/VRP7
BW2A8 L22 AA20 CFMPA2 TB18 CFM1A8 M2 E5 SCAN_MODE8
IO IO
TB22 TB34 IO IO
CFM1A0 M1 E6 LA1
IO IO
G11 VCCOBank0 VCCOBank1 G14
L16 T17 TB21 TB41
VCCOBank2 VCCOBank3
G10 VCCOBank0 VCCOBank1 G13 U16 VCCOBank4 VCCOBank5 U8
K16 VCCOBank2 VCCOBank3 R17 T6 VCCOBank6 VCCOBank7 L7
G9 VCCOBank0 VCCOBank1 G12 U15 VCCOBank4 VCCOBank5 U7
J16 VCCOBank2 VCCOBank3 P16 R6 VCCOBank6 VCCOBank7 K7
C F8 VCCOBank0 VCCOBank1 F16 T14 VCCOBank4 VCCOBank5 T11
H17 VCCOBank2 VCCOBank3 N16 P7 VCCOBank6 VCCOBank7 J7
F7 VCCOBank0 VCCOBank1 F15 T13 VCCOBank4 VCCOBank5 T10
G17 VCCOBank2 VCCOBank3 M16 N7 VCCOBank6 VCCOBank7 H6
T12 VCCOBank4 VCCOBank5 T9
M7 VCCOBank6 VCCOBank7 G6
+3V3 +3V3
+3V3 +3V3
+3V3 +3V3
+3V3 +3V3
33
R171
R169 33
33
R163 33
R164 R188 33
33 R190 33
R197 33
+3V3
+3V3 R192
+3V3
+3V3
B
+3V3 +3V3
R168
1K00 R193
U14 4K7
XC2V1000-4
SCXCCLK Y19 C19 XTCK
CCLK TCK
SCXPROG A2 D3 XTD3
PROG_B TDI
SCXDONE AB20 D20 XTD4 J1
DONE TDO
AB2 B20 XTMS
M0 TMS 1 2
TB6 W3 M1 DXN D5
3 4
AB3 M2 DXP A3
5 6
B3 HSWAP_EN VBATT A21
7 8
AB21 PWRDWN_B RSVD A20
9 10
A
R191
837 0147 042 Rev.A
1K00
FORM:
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 6 11

1 2 3 4 5 6 7 8 9 10 11
U23 U22
U21 U13
CY7C1049 CY7C1049
CFM1OE 37 CFM1OE 37 CY7C1049 K6R1016V1D
OE OE
F CFM1WE 15 CFM1WE 15
BW1OE 37 OE
MICOE 41 OE
WE WE
BW1WE 15 MICWE 17
8 8 WE WE
CS CS
8 MICCS 6
CS CS
MICUB 40
CFM1A0 3 9 CFM1D0 CFM1A0 3 9 CFM1D8 UB
A0 I/O0 A0 I/O0
BW1A0 3 9 BW1D0 MICLB 39
CFM1A1 4 10 CFM1D1 CFM1A1 4 10 CFM1D9 A0 I/O0 LB
A1 I/O1 A1 I/O1
BW1A1 4 10 BW1D1
CFM1A2 5 13 CFM1D2 CFM1A2 5 13 CFM1D10 A1 I/O1 MICA0 44 7 MICD0
A2 I/O2 A2 I/O2 A0 I/O0
BW1A2 5 13 BW1D2
A3 I/O3 A3 I/O3 A1 I/O1
BW1A3 6 14 BW1D3
A4 I/O4 A4 I/O4 A2 I/O2
BW1A4 7 31 BW1D4
A5 I/O5 A5 I/O5 A3 I/O3
BW1A5 16 32 BW1D5
A6 I/O6 A6 I/O6 A4 I/O4
BW1A6 17 35 BW1D6
A7 I/O7 A7 I/O7 A5 I/O5
BW1A7 18 36 BW1D7
CFM1A8 19 CFM1A8 19 A7 I/O7 MICA6 24 15 MICD6
A8 A8 A6 I/O6
BW1A8 19
CFM1A9 20 CFM1D[0:7] CFM1A9 20 CFM1D[8:15] A8 MICA7 21 16 MICD7
A9 A9 A7 I/O7
BW1A9 20
CFM1A10 26 CFM1A10 26 A9 BW1D[0:7] MICA8 20 29 MICD8
A10 A10 A8 I/O8
BW1A10 26
CFM1A11 27 CFM1A11 27 A10 MICA9 19 30 MICD9
A11 A11 A9 I/O9
BW1A11 27
A12 A12 A10 I/O10
BW1A12 28
A13 A13 A11 I/O11
E BW1A13 29
A14 A14 A12 I/O12
BW1A14 30
A15 A15 A13 I/O13
BW1A15 38
A16 A16 A14 I/O14
BW1A16 39
A17 A17 A15 I/O15
BW1A17 40
CFM1A18 41 CFM1A18 41 A17 22
A18 A18 NC
BW1A18 41 A18 23 NC MICD[0:15]
28 NC
CFM1A[0:18]
BW1A[0:18]
MICA[0:15]
U8 U1 U11
U3 U4
CY7C1049 CY7C1049 CY7C1049
CNPOE BWPOE CY7C1049 CY7C1049
D 37 OE 37 OE
CFMPOE CFMPOE
CFMPOE 37 OE
CNPWE BWPWE 37 OE 37 OE
15 WE 15 WE CFMPWE
CFMPWE CFMPWE 15 WE
15 WE 15 WE
8 CS 8 CS 8 CS
8 8
CS CS
BWPA0 3 9 CNPD0 BWPA0 3 9 BWPD0

A0 I/O0 A0 I/O0 CFMPA0 3 9 CFMPD16
CFMPA0 3 9 CFMPD0 CFMPA0 3 9 CFMPD8 A0 I/O0
BWPA1 4 10 CNPD1 BWPA1 4 10 BWPD1 A0 I/O0 A0 I/O0
BWPA8 19 BWPA8 19 A7 I/O7 A7 I/O7
A8 A8 CFMPA8 19
CFMPA8 19 CFMPA8 19 A8
BWPA9 20 BWPA9 20 A8 A8
A9 A9 CFMPD[0:7] CFMPD[8:15] CFMPA9 20 CFMPD[16:23]
BWPA10 26 CNPD[0:7] BWPA10 26 BWPD[0:7] A9 A9
A10 A10 CFMPA10 26
BWPA11 27 BWPA11 27 A10 A10
A11 A11 CFMPA11 27
BWPA12 28 BWPA12 28 A11 A11
A12 A12 CFMPA12 28
BWPA13 29 BWPA13 29 A12 A12
C A13 A13 CFMPA13 29
BWPA14 30 BWPA14 30 A13 A13
A14 A14 CFMPA14 30
BWPA15 38 BWPA15 38 A14 A14
A15 A15 CFMPA15 38
BWPA16 39 BWPA16 39 A15 A15
A16 A16 CFMPA16 39
BWPA17 40 BWPA17 40 A16 A16
A17 A17 CFMPA17 40
BWPA18 41 BWPA18 41 A17 A17
A18 A18 CFMPA18 41
A18 A18
BWPA[0:18] CFMPA[0:18]
+3V3 U36
74LCX245
19 G
1 T/R
ESCANOUT 2 18 ESCAN
A1 B1
U9 U2 SCAN_MODEOUT0 3 17 SCAN_MODE0
A2 B2
U10 SCAN_MODEOUT1 4 16 SCAN_MODE1
CY7C1049 CY7C1049 A3 B3
CFM2OE 37 CFM2OE 37 CY7C1049 SCAN_MODEOUT2 5 A4 B4 15 SCAN_MODE2
B OE OE
BW2OE 37 SCAN_MODEOUT3 6 14 SCAN_MODE3
CFM2WE 15 CFM2WE 15 OE A5 B5
WE WE
BW2WE 15 SCAN_MODEOUT4 7 13 SCAN_MODE4
8 8 WE A6 B6
CS CS
8 SCAN_MODEOUT5 8 12 SCAN_MODE5
CS A7 B7
SCAN_MODEOUT6 9 11 SCAN_MODE6
CFM2A0 3 9 CFM2D0 CFM2A0 3 9 CFM2D8 A8 B8
A0 I/O0 A0 I/O0
BW2A0 3 9 BW2D0
CFM2A1 4 10 CFM2D1 CFM2A1 4 10 CFM2D9 A0 I/O0
A1 I/O1 A1 I/O1 U49
BW2A1 4 10 BW2D1
CFM2A2 5 13 CFM2D2 CFM2A2 5 13 CFM2D10 A1 I/O1
A2 I/O2 A2 I/O2
CFM2A3 6 14 CFM2D3 CFM2A3 6 14 CFM2D11
BW2A2 5 A2 I/O2 13 BW2D2 74LCX245
A3 I/O3 A3 I/O3
BW2A3 6 14 BW2D3 19
CFM2A4 7 31 CFM2D4 CFM2A4 7 31 CFM2D12 A3 I/O3 G
A4 I/O4 A4 I/O4
BW2A4 7 31 BW2D4 1
CFM2A5 16 32 CFM2D5 CFM2A5 16 32 CFM2D13 A4 I/O4 T/R
A5 I/O5 A5 I/O5
BW2A5 16 32 BW2D5
CFM2A6 17 35 CFM2D6 CFM2A6 17 35 CFM2D14 A5 I/O5 2 18
A6 I/O6 A6 I/O6 A1 B1
BW2A6 17 35 BW2D6
CFM2A7 18 36 CFM2D7 CFM2A7 18 36 CFM2D15 A6 I/O6 3 17
A7 I/O7 A7 I/O7 A2 B2
BW2A7 18 36 BW2D7
CFM2A8 19 CFM2A8 19 A7 I/O7 4 16
A8 A8 A3 B3
CFM2D[0:7] BW2A8 19
CFM2A9 20 CFM2A9 20 CFM2D[8:15] A8 5 15
A9 A9 A4 B4
BW2A9 20
CFM2A10 26 CFM2A10 26 A9 BW2D[0:7] 6 14
A10 A10 A5 B5
BW2A10 26
CFM2A11 27 CFM2A11 27 A10 7 13
A11 A11 A6 B6
BW2A11 27
CFM2A12 28 CFM2A12 28 A11 DDOT 8 12 DDOTIN
A12 A12 A7 B7
BW2A12 28
CFM2A13 29 CFM2A13 29 A12 DLINE 9 11 DLINEIN
A13 A13 A8 B8
A CFM2A14 30 CFM2A14 30
BW2A13 29 A13
A14 A14 47
BW2A14
837 0147 042 Rev.A
CFM2A15 CFM2A15 30 A14 47

38 A15 38 A15
BW2A15 38 R259 R258 R175 R176
CFM2A16 39 A16
CFM2A16 39 A16
A15 R273
FORM:
BW2A16 39 1K00 1K00

CFM2A17 40 CFM2A17 40 A16 1K00
A17 A17 C179 C180
BW2A17 40
CFM2A18 41 CFM2A18 41 A17
A18 A18
BW2A18 41 33P 33P
A18
CFM2A[0:18]
BW2A[0:18]
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 7 11

1 2 3 4 5 6 7 8 9 10 11
+6V
R99 +5V
10 C399 100N
100N C60
+3V3C C48 R98
R89 +5V
100N R97 +5V
R278 U58
1K00 TP20 R82 1 R280 100N
10
F
3K3 C57 100N 10
1K00
12
+Vs L2726 C395
- 1
8
U40 20
11
15K 2
V+ TLE2062 R72
+
U39 R66
-
1 VCC
3
TGC 39K TP17 CR4
AD7302 +
BAS21
V-
TGCD0 1 15
DB7(MSB) VDD
4 R71 U50 R279 R120
TGCD1 2 8
DB6
TGCD2 3 16
R100 R101 10K V+ LMC662 220 1
DB5 REFin R81 VMOT 2 -
TGCD3 3K3 1K00
4 DB4 2K00 TP21 1 K1
TGCD4 3
5 19 +
R290 R291
DB3 VoutA
V- 5V 2VIE
TGCD5 6 DB2
8
U40 R84 R83 4 TP16 1K00 220 +
TGCD6 7 18
DB1 VoutB TLE2062
TGCD7 8
R80 6
V+ 10K 39K
DB0(LSB) -
2K00 7 DGAIN MPH1
5
+
R105 CR5
9 CS AGND 17 V- STPS1H100U TO CONNECTOR Y0
TGCWE 10
39K R277 1
U59 100N
WR C55 C56 4 -5V R275 MPH2
TGCAB 11 A/B C42 R90 1K00
12
+Vs L2726 C393
470P 470P - 1
E 12 20 TO CONNECTOR Z0
PD 1U 10 R104 8
U50 11
13 LDAC +
14 20 CR2 10K
6
V+ LMC662
CLR DGND C49 VMOT -
7
LM385BM1.2 100N 5
+
V-
R276 R119
R92 R91 4
220 1
10K 39K 1K00 1K00
+3V3 R299 R298
R289 R288 CR6
U51 STPS1H100U
R74 R77 -5V 1K00 220
+5V
Q1 TLV5620 VCC
R70 10
14 C45 10
BC817 VDD
220 POTREF -6V
100N 100N
MPADCK 7 C394 C408 C409
CLK
R63 R73 MPADDATA 6 DATA DACA 12 47N 47N
+5V
C40 MPADLOAD 8 100N
1K2
0
1K5 LOAD R87
11 C58 +6V
R69 47U DACB 10 100N
D VMOT 2 REFA C400
CR3 3 REFB DACC 10
TP19
TL431AC 4 REFC R76
2K2
5 9 39K
REFD DACD
R285 U58
R68 C44 1 100N

R67 R286
MPADLDAC 13 LDAC R109 R108 R107 R106 R75 U52 1K00 +Vs L2726
10K 100N 8 9 - 1 C398
15K 15K 15K 15K 10K LMC662 2
LM385BM1.2 1 2
V+
10 R300 R301
CR1 GND VMOT -
1
+
1K00 1K00
3
+
V-
R85 R86 4 TP18
+5V 10K 39K R284 R122
R54 220 1
100N R111
10
C33 39K VCC
K2
R294 R295 CR7
STPS1H100U 5V 2VIE
1K00 220
R296 RV2 R297 R110 8
U52 +
C 4K7 1K 4K7 10K V+ LMC662
POTREF VMOT 6 -
7 R283 U59 100N MPH3
TP13 5
1 R281
R56 + 1K00 +Vs L2726 C396 TO CONNECTOR W0
V- 9 1
2K -
2
4 MPH4
L1 R55 8
U31 R93 R94 10
+
R52
TEMP1 33U 10K
2
V+ LMC662 10K 39K TO CONNECTOR X0
- 1K00
1
3
+
C35 C29 V- C28 -5V R282 R121
R51 R78
100N 100N 1U TP15 100N
150K
4 C46 10
220 1
C27 R293 R292 CR8 R127

STPS1H100U MOTORON
BC817 2K7
1K00 220
1U
R134 -6V Q2
C397 100N R126
1K00
B POT0 4K7
R274 RV1 R287 R133

U41 +3V3C
1K00 R88
4K7 1K 4K7 POT1 TLV1543
POTREF 10
1 20 P5
R132 A0 VCC
R61 1K00
2 A1 1 2
2K POT2 3 19 POTEOC C47 PSENSE 3 4 TSENSE
A2 EOC
L2 R59 8
U31 R131 4 A3 I/O CLK 18 POTCK
100N 5 6
R62 5 17 POTADD POFFS VREF
TEMP2 33U 10K
6
V+ LMC662 1K00 A4 ADDRESS 7 8
- 1K00 POT3 6 16 POTDOUT 9 10
7 A5 DATA OUT
5 7 15 POTCS AUX 11 12 VA
+ R130 A6 CS
C34 C31 V- C32 8 A7 REF+ 14 POTREF 13 14
1K00
100N 100N 4 1U POT4 9 13 CTAUX0 15 16 CTAUX4
A8 REF-
11 C59 CTAUX1 17 18 CTAUX5
R129 A9 +3V3C
R60 C73 C71 C69 12 A10 GND 10 100N CTAUX2 19 20 CTAUX6
1K00 +5V
150K POT5 1U 1U 1U CTAUX3 21 22 CTAUX7
23 24 -5V
R128 C72 C70 C68
A C74 25 26
C30 POT[0:6] 1K00 1U 1U 1U
POT6 1U
837 0147 042 Rev.A
27 28
29 30 POTREF
1U
FORM:
R95 R79 C54 C43 31 32

820K 820K 100N 100N 33 34
35 36
37 38
39 40
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 8 11

1 2 3 4 5 6 7 8 9 10 11
+3V3 P1
P3 P2
R266 B1 A1
TXS B1 A1 SMP
U34 B2 A2
DPTCK TCLK +2V2
B1 A1
4K7 HWC0 HWC1 B2 A2
B3 A3 L7 B2 A2
74LCX245 CFMON B3 A3 CFMOFF
BDIG0 B4 A4 ADIG0 B3 A3
G 19 LSFE MLN0 MLN1 15U
BDIG1 ADIG1 B4 A4
B5 A5 B4 A4
T/R 1 LCRW MLN2 MLN3
F BDIG2 ADIG2 B5 A5
B6 A6 B5 A5
LC0 18 2 LD0 DL B6 A6 ACFM
B1 A1 BDIG3 B7 A7 ADIG3 C64 FEXPROG1 B6 A6 FEXPROG0
LC1 17 3 LD1 B7 A7
B2 A2 BDIG4 B8 A8 ADIG4 FEXDONE1 B7 A7 FEXDONE0
47U
LC2 16 4 LD2 CFMD16 B8 A8 CFMD17
B3 A3 BDIG5 B9 A9 ADIG5 FEXINIT1 B8 A8 FEXINIT0
B4 A4 BDIG6 B10 A10 ADIG6 FEXCCLK1 B9 A9 FEXCCLK0
B5 A5 BDIG7 B11 A11 ADIG7 SADD0 B10 A10 SADD1
CFMD4 B14 A14 CFMD5
BDIG11 B15 A15 ADIG11 SADD8 B14 A14 SADD9
U46 CFMD2 B15 A15 CFMD3
BDIG12 B16 A16 ADIG12 SADD10 B15 A15 SADD11
LC[0:15]
CFMD0 B16 A16 CFMD1
LD[0:15]
74LCX245 BDIG13 B17 A17 ADIG13 SADD12 B16 A16 SADD13
DPD6 B17 A17 DPD7
19 BDIG14 B18 A18 ADIG14 SADD14 B17 A17 SADD15
G
DPD4 B18 A18 DPD5
1 BDIG15 B19 A19 ADIG15 SADD16 B18 A18 SADD17
T/R
DPD2 B19 A19 DPD3
BDIGREF0 B20 A20 ADIGREF0 SADD18 B19 A19 SADD19
LC8 18 2 LD8
B1 A1 DPD0 B20 A20 DPD1
B21 A21 LQ0 B20 A20 PI
LC9 17 3 LD9
B2 A2 B21 A21
DDIG0 B22 A22 DDIG1 LQ1 B21 A21 LQ2
LC10 16 4 LD10
B3 A3 SCAUX0 B22 A22 SCAUX1
E DDIG2 B23 A23 DDIG3 FES1 B22 A22 FES0
LC11 15 5 LD11
B4 A4 AVG_DATA0 B23 A23 AVG_DATA1
DDIG4 B24 A24 DDIG5 POS B23 A23 FES2
LC12 14 6 LD12
DDIG6 B25 A25 DDIG7 TXFRAME B24 A24 TXSTB
LC13 13 7 LD13
DDIG8 B26 A26 DDIG9 TXRES B25 A25 RXSTB
LC14 12 8 LD14
+3V3 DDIG10 B27 A27 DDIG11 B26 A26
LC15 11 9 LD15
DDIG12 B28 A28 DDIG13 RLB15 B27 A27 RLB14
AVG_DATA10 B28 A28 AVG_DATA11
R269 ESCAN B31 A31 MRESET_DONE
R270 B32 A32 RLB7 B31 A31 RLB6
U48 4K7 DDOT B32 A32 DLINE
4K7 POT0 B33 A33 POT1 RLB5 B32 A32 RLB4
B33 A33
74LCX244 POT2 B34 A34 POT3 RLB3 B33 A33 RLB2
R272 R271 R253 POT4 POT5
XY_ADD0 B34 A34 XY_ADD1
RLB1 RLB0
LSFE 1 1G R252 B35 A35
XY_ADD2 XY_ADD3
B34 A34
4K7 4K7 POT6 POTREF B35 A35 FEPRG FERW
19 2G 4K7 4K7 B36 A36 B35 A35
XY_ADD4 B36 A36 XY_ADD5
TGC B37 A37 DGAIN B36 A36
LCA0 2 18 LA0
1A1 1Y1 XY_ADD6 B37 A37 XY_ADD7
B38 A38 D40C B37 A37
LCA1 4 16 LA1
1A2 1Y2 XY_ADD8 B38 A38 SCAN_MODE1
CONF4 B39 A39 CONF5 B38 A38
LCA2 6 14 LA2
1A3 1Y3 SCAN_MODE0 B39 A39 SCAN_MODE3
CONF2 B40 A40 CONF3 TSENSE B39 A39 POFFS
D LCA3 8 12 LA3
CONF0 B41 A41 CONF1 PSENSE B40 A40 VREF
LCA4 11 9 LA4
CONFOE2 B42 A42 CONFOE0 VA B41 A41 AUX
LCRW 13 7 LRW
CONFOE1 B43 A43 R141 B42 A42
15 5
2A3 2Y3 SCAN_MODE8 B43 A43 MCYCLE_START

PED B44 A44 PBA/B 33 R135 TEMP1 B43 A43 TEMP2
17 2A4 2Y4 3 LSGR

SELPED SELA/B LSSCAN B44 A44
B45 A45 33 B44 A44
LSGW B45 A45 LSCNT BDIGREF1 ADIGREF1
B46 A46 B45 A45
33 LCA0 B46 A46 LCA1
MPH1 B47 A47 MPH3 DREADY1 B46 A46 DREADY0
U56 LCA2 B47 A47 LCA3
MPH2 B48 A48 MPH4 R140 HF1 B47 A47
74HC139 B49 A49
LCA4 B48 A48 LCRW
HF2 B48 A48 HF0
LCA0 2 4 CONFOE0 B49 A49 VCC
1A 1Y0 C79 C80 B49 A49
LCA1 3 5 CONFOE1
1B 1Y1
47P 47P L5 C76
6 CONFOE2
1Y2 B50 A50 100U 47P
1 7 CONFOE3 B50 A50
1G 1Y3 GSEL0 B51 A51 GSEL1 B50 A50
LCA2 -6V MOT0 MOT1 B51 A51
14 2A 2Y0 12 L3 B52 A52
LC0 LC1
C66 B51 A51
LCRW PROBE B52 A52 D40B
13 2B 2Y1 11 B53 A53 47U B52 A52
22U LC2 B53 A53 LC3
10 B54 A54 D40A B53 A53 D40M
2Y2
+6V LC4 B54 A54 LC5
LSGR 15 9 CONFOECPU B55 A55 D5M B54 A54
2G 2Y3 L4 LC6 LC7
C B56 A56
B55 A55
B55 A55
22U LC8 B56 A56 LC9
B57 A57 B56 A56
LC10 B57 A57 LC11
+3V3C B58 A58 B57 A57
+3V3 LC12 B58 A58 LC13
B59 A59 B58 A58
L6 B60 A60
LC14 B59 A59 LC15
B59 A59
22U B60 A60
B60 A60
C67 47U
R257 R256 R255 R254 R267 R268 U47 47U
C51
4K7 4K7 4K7 4K7 4K7 4K7 74LCX244
1 1G C20 C376 C305
19 2G 100P 100P 100P
R139
CONF0 2 18 LC0
1A1 1Y1 33
CONF[0:5]
CONF1 4 16 LC1
1A2 1Y2 +3V3
CONF2 6 14 LC2 U65 R236 R216
1A3 1Y3 R38
CONF3 8 12 LC3 R116
1A4 1Y4 CY2305 82 82
82
CONF4 11 9 LC4 33
2A1 2Y1 6 8 CK40A
VDD CLKout
B CONF5 13 7 LC5
2A2 2Y2 LC[0:5] 3
15 5
CLK1 R117
2A3 2Y3 D40M 1 2
REF CLK2 33
17 2A4 2Y4 3 CK40B
+3V3 CLK3 5
4 GND CLK4 7 R115
33
CK40C
+3V3
R245 R118
R244 R243 R242 R241 R246 R247 U35 33
100 100 100 100 100 100
470K U33 CK40D
74LCX244
1 74LVT273 +3V3
1G U53
1 2 2 2 2 2 LSGW 11
CONFOE3 19 CLK
2G
1
R114 74AC161
RES
2 18 CONF0 33
1A1 1Y1 CK40B 2
CONF[0:5] LC12 3 2 TCRESET CK40E CLK
4 16 CONF1 1D 1Q
1A2 1Y2 1
LC13 4 5 FLASH CLR
6 1A3 1Y3 14 CONF2 2D 2Q +3V3 R113 9
LC14 7 6 U64 LOAD
8 12 CONF3 3D 3Q 33
1A4 1Y4 10 15
LC15 8 9 CK40F ENT RCO
11 2A1 2Y1 9 CONF4 4D 4Q CY2305 7
13 12 ENP
13 7 CONF5 5D 5Q 6 8
A 2A2 2Y2 C378 14 15
VDD CLKout R136 3 14
2 15 2A3 2Y3 5 6D 6Q
CLK1 3 R178 R182 R214 A QA R262
837 0147 042 Rev.A
17 16 33 4 13
R238 R237 R248 R249 17 3 470N 7D 7Q 1 2 D40A 82 82 82 B QB 33
R240 R239 2A4 2Y4 REF CLK2
18 19 5 12 D5M
8D 8Q C QC
FORM:
CLK3 5 R137
100 100 100 100 100 100
4 GND CLK4 7 C182 C196 C301 6 D QD 11
33
D40B 100P 100P 100P
R138
33
D40C
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 9 11

1 2 3 4 5 6 7 8 9 10 11
+2V2
+1V8B +1V5
+2V2 U18
U5
TPS72501 TPS72501
2 IN OUT 4
2 IN OUT 4
-6V
C155 C186 C184 C183 C199 C131
C142 C204 C210 C188 C145 C197 U38 -5V 47N 470N
1 EN FB 5 47N 47N 47N 470N
F 1 EN FB 5 47K 47N 47N 47N 47N 470N 470N UCC384DP-ADJ R20
GND
R3 C5 2 VIN VOUT 5 GND 27K
C15
47U 3 VIN C19 C18 47U
C3 C1 3 6 VIN VOUTS 1 C37 1U
3 C130
1U C203 C151 R64 4U7 4U7 C153 C152 C187 C156 C206
4U7 100K C143 C146 C192 C150 7 VIN 22P 120K
470N
470N
470N 470N 120K C41 47N 47N 47N 47N
R1 47N 47N 47N 47N R19
8 SD/CT GND 4
C38 +1V5B
4U7
22N
R65 +2V2 U16
+2V2 39K
U57 +1V5A C53 TPS72501
TPS72501 2 IN OUT 4
2 IN OUT 4
1 EN FB 5 C299 C335 C297 C300 C349 C357
C328 C294 C295 C292 C351 C280 R22 C11 47N 47N 47N 47N 470N 470N
1 EN FB 5
R96 C50 47N 47N 47N 47N 470N 470N
GND 47U
27K
GND 47U +6V C9 C8
27K
E C62 C52 U54 1U 4U7
3
1U 3 +5V C265 C269
4U7 LP2951-3.1
C350 C281 R23 C296 C338 C334 C337 470N 470N
8 VIN OUTPUT 1
R102 C331 C291 C330 C327 470N 470N
120K 47N 47N 47N 47N
120K 47N 47N 47N 47N
3 SHUTDWN Vtap 6 C61
82K 47N
C63
5 7 4U7
ERROR FB R103
C77
VCC +3V3C
4U7 4 2
GND SENSE U55
+1V8A
+2V2 U24 27K LP2951-3.1
R112 8 1
TPS72501 VIN OUTPUT
2 IN OUT 4
3 SHUTDWN Vtap 6
R123 R124 C75
1 EN FB 5 C352 C372 C289 C353 C377 C285 47N C407 C382 C388 C401 C404 C383
C21 47N 47N 47N 47N 470N 470N
VCC U32 +3V3AUX 5 ERROR FB 7 150K 820K
C65 47N 47N 47N 47N 47N 47N
GND
R45 47U C78
47K LP3964-ADJ 4U7
4U7 4 2
D 2 3 GND SENSE
3 VIN VOUT
R125
C288 C374 1 SD ADJ 4 75K
C22 C23 R44 C314 C290 C315 C373
470N 470N 10K R50 C25

1U 100K 47N 47N 47N 47N GND C26 C389 C406 C387 C405 C386
4U7
R53 18K 82P
33U 47N 47N 47N 47N 47N
5
C36
+2V2
100U
U6 +1V26 R49
TPS72501 10K5
2 IN OUT 4
+3V3AUX
1 EN FB 5 C242 C202 C177 C234 C207 C233 C235 C240
+3V3
R4 47N 47N 47N 47N 47N 47N 470N 470N
GND
3K9
C4 C2 C6
3
C 1U 4U7 47U
C237 C236 C213 C157 C139 C218
R2 C195 C208 C198 C175 C172 470N 470N
120K 47N 47N 47N 470N
47N 47N 47N 47N 47N
C24 C101 C106 C93 C102 C89 C100 C118 C121 C111 C117 C115 C125
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47U
C263 C272 C229 C126
+3V3
47N 47N 47N 470N
C214 C209 C138 C216 C227 C313 C168 C154 C167 C164 C165 C127 C232 C129 C215 C194 C275 C94 C95 C119 C116 C120 C246 C251 C256 C247 C255 C277 C344 C324
C141 C10 10U 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 10U 47N 47N
470N 47U
C189
C267 C363 C271 TP14
C190 C191 C162 C169 C163 C222 C221 C147 C148 C149 C133 C134 C226 C161 C166 C220 C273
47N 47N 470N
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 47N
47N 470N 470N
C108 C97 C107 C96 C88 C84 C87 C83 C86 C82 C85 C81
B 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N TP8
C219 C306 C135 C369 C321 C341 C310 C258 C307 C311 C319 C136 C283 C284 C39 C128 C354 C303 C370 C274
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 10U 10U 47N 47N 47N 470N
47N 470N 470N TP2
C185 C268 C318 C359 C329 C293 C356 C316 C304 C312 C320 C368 C137 C361 C317 C309 C160 C140 C254 C250 C253 C249 C252 C248 C110 C99 C109 C98
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
C260 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N TP6
47N 470N 470N 47N 47N 10U
470N
C298
C339 C340 C325 C326 C347 C348 C345 C346 C332 C278 TP3
C336 C362 C266 C279 C270 C323 C322 C259 C371
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47N 470N 470N 470N 47N 47N 47N 470N
470N
C245 C244 C380 C384 C391 C381 C390 C379 C392 C403 C402 C385
TP22
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
C170 C264 C367 C276 C355 C360 C261 C262 C364 C173 C178 C375 C287 C343 C342 C358 C308 C366 C217
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 47N 47N 47N 470N
47N 47N 470N
C144 TP1
A
837 0147 042 Rev.A
C224 C205 C174 C257 C365 C225 C123 C124 C122 C112 C113 C114 C105 C103 C104 C90 C91 C92
C231 C230 C228 C201 C200 C241 C223 C211 C243 C212 C193 C176
FORM:
470N 470N 470N 47N 47N

10U
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N TP9
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 10 11

1 2 3 4 5 6 7 8 9 10 11
ALIMENTAZIONI IMPLICITE ALIMENTAZIONI MODIFICATE

----------------------- ------------------------
NET: +1V26 NET: +3V3 NET: +1V8B NET: +3V3AUX

---------- --------- ---------- ------------
F U17.100 U19.27 U15.E18 U14.A12
U17.113 U53.16 U15.E5 U14.AA1
U17.121 U15.F17 U14.AA22
U17.148 NET: +3V3C U15.F6 U14.AB11
U17.165 ---------- U15.G15 U14.B1
U17.171 U35.20 U15.G16 U14.B22
U17.21 U37.20 U15.G7 U14.L1
U17.33 U42.20 U15.G8 U14.M22
U17.50 U43.20 U15.H16 U27.A12
U17.77 U44.20 U15.H7 U27.AA1
U17.9 U45.20 U15.R16 U27.AA22
U56.16 U15.R7 U27.AB11
NET: +1V5 U60.20 U15.T15 U27.B1
--------- U61.20 U15.T16 U27.B22
U14.F17 U62.20 U15.T7 U27.L1
U14.F6 U63.20 U15.T8 U27.M22
U14.G15 U15.U17 U28.A12
U14.G16 NET: +1V8A U15.U6 U28.AA1
U14.G7 ---------- U15.V18 U28.AA22
U14.G8 U30.C14 U15.V5 U28.AB11
U14.H16 U30.C3 U28.B1
U14.H7 U30.D13 NET: +1V5B U28.B22
U14.R16 U30.D4 ---------- U28.L1
U14.R7 U30.E12 U28.F17 U28.M22
U14.T15 U30.E5 U28.F6
U14.T16 U30.M12 U28.G15 NET: -6V
E U14.T7 U30.M5 U28.G16 --------
U14.T8 U30.N13 U28.G7 U58.14
U14.U17 U30.N4 U28.G8 U58.15
U14.U6 U30.P14 U28.H16 U58.16
U30.P3 U28.H7 U58.17
NET: +3V3 U28.R16 U58.4
--------- NET: +1V5A U28.R7 U58.5
U1.11 U17.168 U25.33 U7.15 ---------- U28.T15 U58.6
U1.33 U17.36 U26.11 U7.41 U27.F17 U28.T16 U58.7
U10.11 U17.53 U26.33 U7.65 U27.F6 U28.T7 U59.14
U10.33 U17.80 U29.11 U7.91 U27.G15 U28.T8 U59.15
U11.11 U17.94 U29.33 U8.11 U27.G16 U28.U17 U59.16
U11.33 U2.11 U3.11 U8.33 U27.G7 U28.U6 U59.17
U12.15 U2.33 U3.33 U9.11 U27.G8 U59.4
U12.41 U20.11 U33.20 U9.33 U27.H16 U59.5
U12.65 U20.33 U34.20 UP1.32 U27.H7 U59.6
U12.91 U21.11 U36.20 UP2.32 U27.R16 U59.7
U13.11 U21.33 U4.11 UP3.37 U27.R7
U13.33 U22.11 U4.33 UP3.9 U27.T15
U17.105 U22.33 U46.20 U27.T16
U17.12 U23.11 U47.20 U27.T7
U17.124 U23.33 U48.20 U27.T8
U17.141 U25.11 U49.20 U27.U17
U27.U6
NET: GND
D --------
U1.12 U14.M11 U15.L7 U22.34 U27.P12 U28.P13 U47.10
U1.34 U14.M12 U15.L9 U23.12 U27.P13 U28.P14 U48.10
U10.12 U14.M13 U15.M10 U23.34 U27.P14 U28.P9 U49.10
U10.34 U14.M14 U15.M11 U25.12 U27.P9 U28.W19 U53.8

U11.12 U14.M9 U15.M12 U25.34 U27.W19 U28.W4 U56.8

U11.34 U14.N10 U15.M13 U26.12 U27.W4 U28.Y20 U60.10

U12.10 U14.N11 U15.M14 U26.34 U27.Y20 U28.Y3 U61.10
U12.17 U14.N12 U15.M16 U27.A1 U27.Y3 U29.12 U62.10
U12.21 U14.N13 U15.M7 U27.A22 U28.A1 U29.34 U63.10
U12.26 U14.N14 U15.M9 U27.AA2 U28.A22 U3.12 U7.10
U12.40 U14.N9 U15.N10 U27.AA21 U28.AA2 U3.34 U7.17
U12.5 U14.P10 U15.N11 U27.AB1 U28.AA21 U30.A1 U7.21
U12.55 U14.P11 U15.N12 U27.AB22 U28.AB1 U30.A16 U7.26
U12.60 U14.P12 U15.N13 U27.B2 U28.AB22 U30.B15 U7.40
U12.67 U14.P13 U15.N14 U27.B21 U28.B2 U30.B2 U7.5
U12.71 U14.P14 U15.N9 U27.C20 U28.B21 U30.F11 U7.55
U12.76 U14.P9 U15.P10 U27.C3 U28.C20 U30.F6 U7.60
U12.90 U14.W19 U15.P11 U27.D19 U28.C3 U30.G10 U7.67
U13.12 U14.W4 U15.P12 U27.D4 U28.D19 U30.G7 U7.71
U13.34 U14.Y20 U15.P13 U27.J10 U28.D4 U30.G8 U7.76
U14.A1 U14.Y3 U15.P14 U27.J11 U28.J10 U30.G9 U7.90
U14.A22 U15.A1 U15.P9 U27.J12 U28.J11 U30.H10 U8.12
U14.AA2 U15.A22 U15.T11 U27.J13 U28.J12 U30.H7 U8.34
U14.AA21 U15.AA2 U15.T12 U27.J14 U28.J13 U30.H8 U9.12
U14.AB1 U15.AA21 U15.Y20 U27.J9 U28.J14 U30.H9 U9.34
C U14.AB22 U15.AB1 U15.Y3 U27.K10 U28.J9 U30.J10 UP1.16
U14.B2 U15.AB22 U17.109 U27.K11 U28.K10 U30.J7 UP2.16
U14.B21 U15.B2 U17.117 U27.K12 U28.K11 U30.J8 UP3.21
U14.C20 U15.B21 U17.130 U27.K13 U28.K12 U30.J9 UP3.42
U14.C3 U15.C20 U17.144 U27.K14 U28.K13 U30.K10 UP3.48
U14.D19 U15.C3 U17.153 U27.K9 U28.K14 U30.K7 U28.M11
U14.D4 U15.G11 U17.157 U27.L10 U28.K9 U30.K8 U28.M12
U14.J10 U15.G12 U17.16 U27.L11 U28.L10 U30.K9
U14.J11 U15.J10 U17.174 U27.L12 U28.L11 U30.L11
U14.J12 U15.J11 U17.29 U27.L13 U28.L12 U30.L6
U14.J13 U15.J12 U17.39 U27.L14 U28.L13 U30.R15
U14.J14 U15.J13 U17.47 U27.L9 U28.L14 U30.R2
U14.J9 U15.J14 U17.56 U27.M10 U28.L9 U30.T1
U14.K10 U15.J9 U17.65 U27.M11 U28.M10 U30.T16
U14.K11 U15.K10 U17.73 U27.M12 U28.M13 U33.10
U14.K12 U15.K11 U17.83 U27.M13 U28.M14 U34.10
U14.K13 U15.K12 U17.91 U27.M14 U28.M9 U35.10
U14.K14 U15.K13 U17.97 U27.M9 U28.N10 U36.10
U14.K9 U15.K14 U19.26 U27.N10 U28.N11 U37.10
U14.L10 U15.K9 U2.12 U27.N11 U28.N12 U4.12
U14.L11 U15.L10 U2.34 U27.N12 U28.N13 U4.34
U14.L12 U15.L11 U20.12 U27.N13 U28.N14 U42.10
U14.L13 U15.L12 U20.34 U27.N14 U28.N9 U43.10
U14.L14 U15.L13 U21.12 U27.N9 U28.P10 U44.10
U14.L9 U15.L14 U21.34 U27.P10 U28.P11 U45.10
U14.M10 U15.L16 U22.12 U27.P11 U28.P12 U46.10
B
COMPONENTI NON MONTATI:

------------------------
C171 EQUIP_LEVEL 2 R188 EQUIP_LEVEL 2

J1 EQUIP_LEVEL 2 R224 EQUIP_LEVEL 2
R11 EQUIP_LEVEL 2 R240 EQUIP_LEVEL 2
A R162 EQUIP_LEVEL 2 R242 EQUIP_LEVEL 2
837 0147 042 Rev.A

FORM:

R186 EQUIP_LEVEL 2 U19 EQUIP_LEVEL 2
SHEET DESCRIPTION:
by EpD Number: 950 1078 000 SE E 11 11

1 2 3 4 5 6 7 8 9 10 11
+2V2
P1 P3 P2
L2
15U
B1 A1 TXS B1 A1 SMP 1 B1 A1
B2 A2 B2 A2 2 B2 A2
DPTCLK TCLK
SPKN1 B3 A3 SPKR1 CFMON B3 A3 CFMOFF
C53 B3 A3
B4 A4 B4 A4 47U B4 A4
SPKN2 SPKR2 MLN0 MLN1
B5 A5 MLN2 B5 A5 MLN3 B5 A5
E ADVIN B6 A6 RECIN DL B6 A6 ACFM B6 A6
ADVOUT B7 A7 RECOUT B7 A7 B7 A7
B8 A8 CFMD16 B8 A8 CFMD17 B8 A8
LINEINADV B9 A9 LINEINREC CFMD14 B9 A9 CFMD15 B9 A9
LINEOUTADV B10 A10 LINEOUTREC CFMD12 B10 A10 CFMD13 B10 A10
B11 A11 CFMD10 B11 A11 CFMD11 B11 A11
B17 A17 DPD6 B17 A17 DPD7 B17 A17
B18 A18 DPD4 B18 A18 DPD5 B18 A18
B19 A19 DPD2 B19 A19 DPD3 B19 A19
B20 A20 DPD0 B20 A20 DPD1 B20 A20
B21 A21 B21 A21 B21 A21
DDIG0 B22 A22 DDIG1 SCAUX0 B22 A22 SCAUX1 B22 A22
D DDIG2 B23 A23 DDIG3 B23 A23 B23 A23
DDIG4 B24 A24 DDIG5 B24 A24 B24 A24

+3V3 R144
DDIG10 B27 A27 DDIG11 B27 A27 B27 A27

47K
DDIG12 B28 A28 DDIG13 B28 A28 B28 A28
B29 A29
R175 B29 A29 B29 A29
DDIG14 DDIG15 33
DDIG16 B30 A30 DDIG17 LSDOP B30 A30 B30 A30
DDIG18 B31 A31 DDIG19 B31 A31 B31 A31
B32 A32 C57 DDOT B32 A32 DLINE B32 A32
B33 A33 47P B33 A33 B33 A33
B34 A34 B34 A34 B34 A34
B35 A35 B35 A35 B35 A35
B36 A36
+3V3 R143 B36 A36 B36 A36
47K
B37 A37 B37 A37 B37 A37
B38 A38
R174 B38 A38 +3V3 B38 A38
33
B39 A39 LSGW B39 A39 B39 A39
B40 A40 B40 A40 B40 A40
C C56
B41 A41 B41 A41 B41 A41
B42 A42 47P B42 A42
R142 B42 A42
47K
B43 A43 B43 A43 B43 A43
B44 A44 B44 A44 LSGR B44 A44
B45 A45 B45 A45 B45 A45
B46 A46 LCA0 B46 A46 LCA1 B46 A46
B47 A47 VCC B47 A47 B47 A47
DSIN LCA2 LCA3
B48 A48 -6V L3 B48 A48 B48 A48
DCOS 22U LCA4 LCRW
B49 A49 L6 1 B49 A49 B49 A49
100U 2
1 R146
2
C54 47K
B50 A50 C42 47U B50 A50 B50 A50
B51 A51 47U B51 A51 B51 A51
B52 A52 LC0 B52 A52 LC1 B52 A52 D40B
B53 A53 LC2 B53 A53 LC3 B53 A53
+6V
B54 A54 LC4 B54 A54 LC5 B54 A54
B55 A55
L5 B55 A55 B55 A55
100U LC6 LC7
B B56 A56 1 LC8 B56 A56 LC9 B56 A56
+3V3 B57 A57 2 B57 A57 B57 A57
LC10 LC11
L4 B58 A58 C41 B58 A58 B58 A58
22U LC12 LC13
1 B59 A59 47U B59 A59 B59 A59
LC14 LC15
2 B60 A60 B60 A60 B60 A60
C40
47U
A
837 0147 042 Rev.A
FORM:
CONNETTORI SCHEDA

"7300" DOPPLER BOARD
A2 CORRADDOSSI DONNINI BERTINI 25/05/04
by EpD
Nr. O.V.:
E.O.C. EVENT: IND200400081 Number: 950 1079 000 SE D 1 16
1 2 3 4 5 6 7 8 9 10 11
+3V3
+2V2 U28 +1V8A U3 +3V3_DSP U48

VCC R276
TPS72501 TPS72501 C303 470K 74LVT273
2 4 2 4 470N 11
F IN OUT IN OUT LSGW CLK
1 RES
C10 C11 C17 C3 C4 C2
R105
1 EN FB 5 1 EN FB 5
3 2
180K
4U7 1U 4U7 1U LC9 1D 1Q DSP_RESET
56K
R4
47U 47U
GND R104 GND LC10 4 2D 2Q 5 PRGMODE
120K 7 6
R296 LC11 3D 3Q CPUAUX0
3 3 LC15 8 4D 4Q 9 CPUAUX1
10
13 5D 5Q 12 FLASH_RESET
22K
R5
R6 14 6D 6Q 15
120K 17 16
7D 7Q
18 8D 8Q 19
+2V2 U22 +1V8B
TPS72501
2 IN OUT 4
C12 C13 C19

1 EN FB 5
R98
4U7 1U
56K
47U
GND R99
120K
E +3V3 +3V3AUX
3
W1
VCC
U5
LP3964-ADJ W2
+2V2 U23 2 3
+1V8C VIN VOUT
TPS72501
C326 C325
R299
1 SD ADJ 4
2 IN OUT 4 C327
18K
100U 82P
R298 GND 33U
C14 C15 C18 10K
R101
1 EN FB 5
4U7 1U
R297 C302
56K
47U
GND R102 5 10K5
+3V3
47N
120K 33 R112
XIL1_40M
3
U42
33 R116
CY2305 XIL2_40M
D 6 VDD CLKout 8
CLK1 3 R111
33
D40B 1 REF CLK2 2 XIL3_40M
+2V2 U24
+1V5 5
CLK3
TPS72501
4 GND CLK4 7 R117

33
2 IN OUT 4 XIL0_40M
C16 C21 C20
R103
1 EN FB 5 R113
4U7 1U 33
27K
47U
GND R100 DSP_CLK
120K
+2V2 U20 +1V26
C TPS72501
2 IN OUT 4
C22 C9 C8 R150
1 EN FB 5
R93
4U7 1U
3K9
47U 33
GND R92 XIL0_TXS
120K
R151
3
33
XIL1_TXS
U61
R145 R154
1K00
74LCX244
1 33
1G
+6V U47 +5V XIL2_TXS
19 2G
TPS72501 2 18 R177
TXS 1A1 1Y1
2 IN OUT 4
4 1A2 1Y2 16 33
C39 C34 6 14 XIL3_TXS
C28 1A3 1Y3 R176
R118
1 EN FB 5
4U7 1U 8 1A4 1Y4 12
56K
4U7 33
B GND R115 DPTCLK 11 2A1 2Y1 9 XIL2_DPTCLK
18K 13 7
2A2 2Y2
15 5
R149
3 2A3 2Y3
17 3 33
2A4 2Y4
XIL3_DPTCLK
R148
33
XIL1_DPTCLK
-6V U54 -5V
UCC384DP-ADJ R147
2 5 33
VIN VOUT
XIL0_DPTCLK
3
C45 VIN C310 C46
120K
R291
6 VIN VOUTS 1
4U7 22P 4U7
7 VIN R292
39K
8 SD/CT GND 4
C311
A 22N
837 0147 042 Rev.A
FORM:
REGOLATORI DI TENSIONE E TIMING DI BASE
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 2 16

1 2 3 4 5 6 7 8 9 10 11
R12
0 +3V3_DSP
CLKOUT2/GP2 R44
100P
C7
2
82 2 2
R22 R11
33 4K7
R181
47N
C75
U9 U9
1K00
CLKOUT3
2 P4
F TMS320C6711C TMS320C6711C
R37 A3 E20 TB8 1 2
DSP_CLK CLKIN HD0 R2 ED0 K18 ED0
DSP_TMS DSP_TRST
4K7 D20 TB6 3 4
HD1 1K00 K19 DSP_TDI
ED1 ED1
Y12 CLKOUT2 HD2 D18 TB1 L18 Y6 5 6
ED2 ED2 EA2 EA2
R41 D10 CLKOUT3 HD3 C20 R1 DSP_TDO 7 8
ED3 L19 ED3 EA3 V7 EA3
HD4 C19 9 10
+3V3_DSP 1K00 1K00 ED4 M19 ED4 EA4 W7 EA4
L1 +3V3_DSP C4 CLKMODE0 HD5 B18 TB12 +3V3_DSP M20 V8 DSP_TCK 11 12
ED5 ED5 EA5 EA5
300MA HD6 C17 TB20 R7 N18 W8 DSP_EMU0 13 14 DSP_EMU1
ED6 ED6 EA6 EA6
C5 PLLHV HD7 A18 TB24 1K00 N19 Y8
C5 ED7 ED7 EA7 EA7
R183
4K7
R182
C6 HD8 B17 +3V3_DSP
ED8 N20 ED8 EA8 V9 EA8
4K7
10U
100N
DSP_EMU0 D9 EMU0 HD9 C16 TB23 P18 Y9
ED9 ED9 EA9 EA9
DSP_EMU1 B9 EMU1 HD10 B16 TB25 R8 P20 V10
ED10 ED10 EA10 EA10
D3 EMU2 HD11 A16 TB28 R19 W13
TB37 B10 C15
1K00 ED11 ED11 EA11 EA11
TB32 EMU3 HD12 +3V3_DSP R20 V14
ED12 ED12 EA12 EA12
C11 EMU4 HD13 A15 TB30 T18 W14
R45 TB31 ED13 ED13 EA13 EA13 +3V3_DSP
B12 EMU5 HD14 C14 TB26 T20 Y14
0 TB29 ED14 ED14 EA14 EA14 0 R68
HD15 B14 TB27 T19 W15
DSP_CLK ED15 ED15 EA15 EA15 PRGMODE
E 2 DSP_RESET A13 RESET
ED16 V4 ED16 EA16 Y15 EA16
+3V3_DSP
R9 DSP_TRST B6 TRST HINT J20 TB15 W4 V16 0 R201
ED17 ED17 EA17 EA17
1K00 HCNTL0 G18 TB5 Y3 Y16
XIL0_PROG
ED18 ED18 EA18 EA18
C13 NMI HCNTL1 G19 TB7 V2 W17 0 R62
AWE TB21 C2 H20 TB14 ED19 ED19 EA19 EA19
DSP_INT0 EXT_INT4 HHWIL V1 Y18 XIL0_CCLK
R38
R300
ED20 ED20 EA20 EA20
TB69 C1 G20 TB13
R65
R52
R67
R66
R51
1K00
1K00
1K00
1K00
AOE DSP_INT1 EXT_INT5 HR/W U2 U18 R200
1K2
1K5
33 ED21 ED21 EA21 EA21 0
D2
XIL0_CCLK TB76 DSP_INT2 EXT_INT6 U1
2
ECLKOUT ED22 ED22 XIL0_DONE
2 DSP_INT3 E3 EXT_INT7 U3 K3
XIL0_DIN TB75 E18 TB2 ED23 ED23 CLKS0
R63
R39 HAS
ED24 T1 ED24 CLKR0 H3 0
DSP_INT0 TB38 4K7
Y11 ECLKIN HCS F20 TB10 T2 G3
XIL0_DIN
ED25 ED25 CLKX0
TB41 Y10 ECLKOUT HDS1 E19 TB3 R3 J1 0 R202
DSP_INT1 ED26 ED26 DR0
V11 ARE/SDCAS/SSADS HDS2 F18 TB4 R2 H2 XIL0_INIT
TB39 TB33 ED27 ED27 DX0
DSP_INT2
R40 AOE W10 AOE/SDRAS/SSOE HRDY H19 TB9 P1 J3
TB40 V12 AWE/SDWE/SSWE
ED28 ED28 FSR0 0 R199
DSP_INT3 4K7 AWE P2 H1
ED29 ED29 FSX0 XIL0_AUX
Y5
CE0 TB68 +3V3_DSP ARDY
ED30 P3 ED30 0 R46
CE0 V17 CE0 N3 E1
CE1 TB19 R42 B7 W18
ED31 ED31 CLKS1 DSP_CLKS1
DSP_TMS TMS CE1 CE1 M1
CLKR1 DSP_CLKR1
CE2 TB22 0 DSP_TDO A8 TDO CE2 W6 CE2
D READY/BUSY
DSP_TOUT0 G1 TOUT0 CLKX1 L3 DSP_CLKX1 0 R71
A7 V6
CE3 TB34 2
DSP_TDI TDI CE3 CE3
DSP_TINP0 G2 TINP0 DR1 M2 DSP_DR1
DSP_TCK A6 TCK BE0 V20 BE0 L2
BE0 TB18 U19
DX1 DSP_DX1
R3
BE1 BE1 F1 M3
DSP_TOUT1 TOUT1 FSR1 DSP_FSR1

TB17 J18 Y4
BE1 HOLDA BE2 BE2 F2 L1

1K00 TB11 J17 V5
DSP_TINP1 TINP1 FSX1 DSP_FSX1
BE2 TB36 +3V3_DSP HOLD BE3 BE3
J19 BUSREQ
TB16 C12
TB35 RSV
R49
R50
R48
R64
R70
R47
R53
R72
R69
R54
BE3
1K5
1K5
1K5
1K5
10K
10K
1K5
1K5
1K5
1K5
A5 RSV RSV D7
DSP_DX1 TB42 A12 D12
RSV RSV
B5 RSV RSV N1
B11 RSV RSV N2
+3V3_DSP
R56
R55
R10
R20
10K
10K
10K
10K
TP21
2
+3V3_DSP
+3V3_DSP
+3V3_DSP
C
+3V3 +3V3
UP4 UP5 UP1 U8 U17

29F040-120 29F040-120 AM29LV160 K6R4016V1D K6R4016V1D
R208
R217
1K00
1K00
AOE 24 OE AOE 24 OE EA2 25 A0 DQ0 29 ED0 AOE 41 OE AOE 41 OE

CE1 22 CE CE1 22 CE EA3 24 A1 DQ1 31 ED1 AWE 17 WE AWE 17 WE
31 WE 31 WE EA4 23 A2 DQ2 33 ED2 CE2 6 CS CE2 6 CS
EA5 22 A3 DQ3 35 ED3 BE1 40 UB BE3 40 UB
EA6 21 A4 DQ4 38 ED4 BE0 39 LB BE2 39 LB
EA2 12 A0 O0 13 ED0 EA2 12 A0 O0 13 ED8
EA7 20 A5 DQ5 40 ED5
EA3 11 A1 O1 14 ED1 EA3 11 A1 O1 14 ED9 EA2 1 A0 I/O0 7 ED0 EA2 1 A0 I/O0 7 ED16
EA8 19 A6 DQ6 42 ED6
EA9 18 A7 DQ7 44 ED7
EA10 8 A8 DQ8 30 ED8
EA11 7 A9 DQ9 32 ED9
EA12 6 A10 DQ10 34 ED10
B EA13 5 A11 DQ11 36 ED11
EA14 4 A12 DQ12 39 ED12
EA10 27 A8 EA10 27 A8 EA9 20 A7 I/O7 16 ED7 EA9 20 A7 I/O7 16 ED23
EA15 3 A13 DQ13 41 ED13
EA16 2 A14 DQ14 43 ED14
EA17 1 A15 DQ15(A-1) 45 ED15
EA18 48 A16
EA19 17 A17 RY/BY 15 READY/BUSY
EA20 16 A18
22K
R43
EA21 9 A19
CE0 26 CE
EA19 30 A17 EA19 30 A17 EA18 43 A16 EA18 43 A16
AOE 28 OE
EA20 1 A18 EA20 1 A18 EA19 44 A17 EA19 44 A17
AWE 11 WE
+3V3
FLASH_RESET 12 RESET
47 BYTE
R220
1K00
A
837 0147 042 Rev.A
FORM:
+3V3
DSP
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 3 16

1 2 3 4 5 6 7 8 9 10 11
R240 R239
4K7
4K7
+3V3
XIL_INIT
+3V3
XIL_PROG
R241 R238
1K00 XIL_DONE 4K7
+3V3
2
C294
F 100P
U36 U36 U36 U36
2
XC2S300 XC2S300 XC2S300 XC2S300
R260
BANK 0 BANK 1 82 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
2
SCAUX1 A3 I/O GCK2,I A11 XIL0_40M C21 I/O(DOUT,BUSY) I/O(TRDY) L22 XIL1_CS DOPAUXCTL1 U12 I/O I/O U9 EA2 ED0 M1 I/O(TRDY) I/O C1 XIL1_AUX0
A4 A12
TB74 C22 M17 U13 U10 M2 C2
SCAUX0 I/O I/O(DLL) DDIG0 XIL0_DIN I/O(DIN,D0) I/O XIL2_CS DOPAUXCTL0 I/O I/O EA3 ED1 I/O I/O XIL1_AUX1
DPD4 A5 I/O I/O A13 DDIG1 XIL0_AUX D20 I/O I/O M18 XIL3_CS DOPAUX0 U14 I/O I/O U11 EA4 ED2 M3 I/O I/O D1 XIL1_AUX2
DPD5 A6 I/O I/O A14 DDIG2 CPUAUX0 D21 I/O(VREFBank2) I/O M19 XIL_WRITE DOPAUX1 V12 I/O I/O V6 EA5 ED3 M4 I/O I/O D2 XIL1_AUX3
DPD2 A7 I/O I/O A15 DDIG3 CPUAUX1 D22 I/O I/O M20 XIL_BUSY DOPAUX2 V13 I/O(VREFBank4) I/O V7 EA6 ED4 M5 I/O I/O D3 XIL2_AUX0
DPD3 A8 I/O I/O A16 DDIG4 E19 I/O I/O M21 XIL_CCLK DOPAUX3 V14 I/O I/O(VREFBank5) V8 EA7 ED5 M6 I/O I/O E1 XIL2_AUX1
DPD0 A9 I/O I/O A17 DDIG5 E20 I/O I/O M22 DOPAUX4 V15 I/O(VREFBank4) I/O V9 EA8 ED6 N1 I/O I/O(VREFBank7) E2 XIL2_AUX2
DPD1 A10 I/O I/O A18 DDIG6 SMP E21 I/O I/O(D4) N17 DOPAUX5 V16 I/O I/O(VREFBank5) V10 EA9 ED7 N2 I/O I/O E3 XIL2_AUX3
DPD6 B3 I/O I/O A19 DDIG7 TCLK E22 I/O I/O(VREFBank3) N18 DOPAUX6 V17 I/O I/O V11 EA10 ED8 N3 I/O(VREFBank6) I/O F1 XIL3_AUX0
DPD7 B4 I/O I/O(WRITE) A20 DDIG8 SMPIN F18 I/O I/O N19 XIL_DATA0 DOPAUX7 W12 I/O I/O W5 EA11 ED9 N4 I/O I/O(VREFBank7) F2 XIL3_AUX1
B5 B12 F19 N20 +3V3 W13 W6 N5 F3
TB106 I/O I/O DDIG9 FFTCK I/O I/O XIL_DATA1 DOPAUX8 I/O I/O EA12 ED10 I/O I/O XIL3_AUX2
B6 I/O(VREFBank0) I/O(VREFBank1) B13 DDIG10 DL F20 I/O I/O N21 XIL_DATA2 DOPAUX9 W14 I/O I/O W7 EA13 ED11 N6 I/O I/O F4 XIL3_AUX3
E TB105 B7 I/O I/O B14 DDIG11 SININ F21 I/O(VREFBank2) I/O N22 XIL_DATA3 DOPAUX10 W15 I/O I/O W8 EA14 ED12 P1 I/O I/O F5 VOL_CLK
TB104 B8 B15 F22 P17 W16 W9 P2 G1
TB103 I/O I/O DDIG12 COSIN I/O I/O XIL_DATA4 DOPAUX11 I/O I/O EA15 ED13 I/O I/O VOL_DIN
B9 I/O I/O B16 DDIG13 CFMD16 G18 I/O I/O P18 XIL_DATA5 DOPAUX12 W17 I/O I/O W10 EA16 ED14 P3 I/O I/O G2 VOL_LDSH
B10 I/O I/O B17 DDIG14 CFMD17 G19 I/O I/O P19 XIL_DATA6 DOPAUX13 W18 I/O(VREFBank4) I/O W11 EA17 ED15 P4 I/O I/O G3 SPKOFF
B11 I/O(DLL) I/O(VREFBank1) B18 DDIG15 XIL0_TXS G20 I/O I/O P20 XIL_DATA7 DOPAUX15 Y12 I/O(DLL) I/O Y5 EA18 ED16 P5 I/O I/O G4 ACLKX0
C4 I/O I/O B19 DDIG16 XIL0_DPTCLK G21 I/O I/O P21 DOPAUXCTL3 DOPAUX14 Y13 I/O I/O Y6 EA19 ED17 P6 I/O I/O G5 ADLL
+3V3 C5 B20 G22 P22 Y14 Y7 R1 H1
I/O(VREFBank0) I/O(CS) DDIG17 I/O I/O(D5) DOPAUXCTL2 DSP_INT0 I/O I/O EA20 ED18 I/O I/O ADLR
C6 I/O I/O C12 DDIG18 H18 I/O(VREFBank2) I/O(VREFBank3) R18 DOPAUX21 DSP_INT1 Y15 I/O I/O Y8 EA21 ED19 R2 I/O I/O H2 ADX0
C7 C13 H19 R19 Y16 Y9 R3 H3
4K7
I/O I/O DDIG19 I/O(D1) I/O(D6) DOPAUX20 DSP_INT2 I/O I/O AOE ED20 I/O(VREFBank6) I/O(VREFBank7) VTRAUDIO
C8 C14 H20 R20 Y17 Y10 R4 H4
R110
I/O I/O PRGMODE I/O(D2) I/O DOPAUX19 DSP_INT3 I/O(VREFBank4) I/O AWE ED21 I/O I/O PCAUDIO
2
R225
C9 C15 R250 H21 R21 Y18 Y11 R5 H5
4K7
I/O I/O LA0 CFMON I/O I/O DOPAUX18 DSP_TINP0 I/O I/O CE0 ED22 I/O I/O
C10 I/O I/O C16 LA2 CFMOFF H22 I/O I/O R22 DOPAUX16 DSP_TOUT0 Y19 I/O I/O AA3 CE1 ED23 T1 I/O I/O J1
0
C11 GCK3,I I/O C17 LD0 ACFM J17 I/O I/O T18 DOPAUX25 AA12 GCK0/I I/O AA5 CE2 ED24 T2 I/O I/O J2
LD10 D5 I/O I/O C18 LD3 LD8 J18 I/O I/O T19 DOPAUX24 DSP_TINP1 AA13 I/O I/O AA6 CE3 ED25 T3 I/O I/O J3
DDOT D6 I/O I/O D12 LD15 LD13 J19 I/O I/O T20 DOPAUX23 DSP_TOUT1 AA14 I/O I/O AA7 BE0 ED26 T4 I/O I/O J4
DLINE D7 I/O I/O D13 LNA2 LD9 J20 I/O I/O(VREFBank3) T21 DOPAUX22 READY/BUSY AA15 I/O I/O AA8 BE1 ED27 T5 I/O I/O J5
LD7 D8 I/O(VREFBank0) I/O D14 LNA8 MLN0 J21 I/O I/O T22 DOPAUX26 CLKOUT2/GP2 AA16 I/O I/O AA9 BE2 ED28 U1 I/O(VREFBank6) I/O J6
D LD12 D9 I/O I/O(VREFBank1) D15 LA1 MLN1 J22 I/O I/O U18 DOPAUX31 CLKOUT3 AA17 I/O I/O AA10 BE3 ED29 U2 I/O I/O K1
D10 I/O(VREFBank0) I/O D16 LA3 MLN2 K17 I/O I/O U19 DOPAUX30 AA18 I/O I/O AA11 ED30 U3 I/O I/O K2
D11 I/O I/O D17 LD1 LNA4 K18 I/O(VREFBank2) I/O U20 DOPAUX29 AA19 I/O I/O AB3 ED31 U4 I/O I/O(VREFBank7) K3
E7 I/O I/O D18 LD4 LNA0 K19 I/O(D3) I/O U21 DOPAUX28 AA20 I/O I/O AB4 DSP_CLKS1 V1 I/O I/O K4
TB77
E8 I/O I/O E12 LD5 LD14 K20 I/O I/O U22 DOPAUX27 AB13 I/O I/O(VREFBank5) AB5 DSP_CLKR1 V2 I/O(VREFBank6) I/O K5
TB78 E9 E13 K21 V19 AB14 AB6 V3 K6
TB80 I/O I/O LD6 LNA5 I/O I/O DOPAUX17 I/O I/O DSP_CLKX1 I/O I/O
E10 I/O I/O E14 LD2 MLN3 K22 I/O I/O V20 AB15 I/O I/O(VREFBank5) AB7 DSP_DR1 V4 I/O I/O L1
TB107 E11 E15 L17 V21 AB16 AB8 W1 L2
TB108 I/O I/O LSDOP LNA10 I/O I/O I/O I/O DSP_DX1 I/O I/O
F9 I/O I/O(VREFBank1) E16 LNA3 LNA7 L18 I/O I/O(VREFBank3) V22 AB17 I/O I/O AB9 DSP_FSR1 W2 I/O I/O L3
TB79 F10 E17 L19 W21 AB18 AB10 W3 L4
TB110 I/O I/O LNA9 LNA6 I/O I/O(INIT) XIL0_INIT I/O I/O DSP_FSX1 I/O I/O
F11 I/O I/O F12 LA4 LNA1 L20 I/O I/O W22 AB19 I/O I/O(DLL) AB11 ECLKOUT Y1 I/O I/O L5
TB109 F13 L21 Y22 AB20 AB12 Y2 L6
I/O LRW LNA11 I/O(IRDY) I/O(D7) I/O GCK1,I I/O I/O(IRDY)
I/O F14 LD11 AB21 I/O
R226
4K7
F7 VCCOBank0 VCCOBank1 F15 G17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T9 N7 VCCOBank6 VCCOBank7 G6
F8 VCCOBank0 VCCOBank1 F16 H17 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T10 P7 VCCOBank6 VCCOBank7 H6
G9 VCCOBank0 VCCOBank1 G13 J16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 J7
C G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
+3V3
U36
+3V3 +3V3 +3V3 +3V3
+3V3 XC2S300
TB102
XIL0_CCLK B22 CCLK TCK E6 XIL_TCK
XIL0_PROG Y21 PROGRAM
W20
R228
XIL0_DONE DONE
1K00
AA1 M0 TDI C19 XIL_TDI
2 U5 A21
M1 TDO XIL0_TDO
AB2 M2 TMS E4 XIL_TMS
TB73
R227
R234
R236
XIL1_CS
1K00
1K00
1K00
XIL2_CS TB61
XIL3_CS TB81
B +3V3
XIL_WRITE TB62 +3V3
TP1
XIL_BUSY TB55
TB56
R109
R108
R107
XIL_CCLK
4K7
4K7
4K7
XIL_DATA0 TB54
XIL_DATA1 TB58 +3V3

J1
1
XIL_DATA2 TB57 XIL_TCK 1 2
C1
+3V3
XIL_TDO 3 4
XIL_DATA3 TB43 47U 5 6
XIL_TMS
TB44 7 8
XIL_DATA4
XIL_TDI 9 10
XIL_DATA5 TB53
XIL_DATA6 TB52
A XIL_DATA7 TB49
837 0147 042 Rev.A
FORM:
FPGA DI CONTROLLO
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 4 16

1 2 3 4 5 6 7 8 9 10 11
F U34 U34 U34 U34

XIL_INIT
XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4
R235
0
CFI0 B4 IO IO/GCLK3P F12 TB70 1J_0 C21 IO IO M21 4J_0 XIL_BUSY AB19 IO/DOUT IO/GCLK7S AA11 DDIG18 V5 IO IO L2 LD5
CFI1 A4 IO IO/GCLK2S F13 TB67 1J_1 C22 IO IO M20 4J_1 AA19 IO/INIT_B IO/GCLK6P Y11 XIL1_TXS DDIG19 U5 IO IO L3 LA0
CFI2 C4 IO IO/GCLK1P E12 TB71 1J_2 E18 IO/VRP2 IO M19 4J_2 XIL_DATA0 V18 IO/D0 IO/GCLK5S W11 DDIG8 Y2 IO/VRN6 IO L4 LA2
CFI3 C5 IO IO/GCLK0S D12 TB72 1J_3 F18 IO/VRN2 IO M18 4J_3 XIL_DATA1 V17 IO/D1 IO/GCLK4P V11 DDIG9 Y1 IO/VRP6 IO L5 LD10
CFI4 B5 IO/VRP0 IO C12 MTI_COR0 1J_4 D21 IO IO/VREF3 M17 4J_4 XIL_DATA2 W18 IO/D2/ALT_VRP4 IO U11 DOPAUX8 DDIG0 V4 IO IO/VREF7 K1 LD2
CFI5 A5 IO/VRN0 IO/VREF1 B12 MTI_COR1 1J_5 D22 IO/VREF2 IO N17 4J_5 XIL_DATA3 Y18 IO/D3/ALT_VRN4 IO/VREF5 U10 DOPAUX17 DDIG1 V3 IO/VREF6 IO K2 LNA8
CFI6 D6 IO/VREF0 IO A13 FIRST/SECOND 1J_6 E19 IO IO N22 4J_6 MTICS AA18 IO/VREF4 IO AB10 DOPAUX22 DDIG10 W2 IO IO K3 LA3
CFI7 C6 IO IO B13 TEST_CLK 1J_7 E20 IO IO N21 4J_7 MTIOE AB18 IO IO AA10 DOPAUX3 DDIG11 W1 IO IO K4 LD6
CFI8 B6 IO IO C13 TESTSIN8 1J_8 E21 IO IO N20 4J_8 MTIWE W17 IO/VRP4 IO Y10 DOPAUX11 DDIG2 U4 IO IO L6 LA4
CFI9 A6 IO IO D13 TESTSIN9 1J_9 E22 IO IO N19 4J_9 ADCK Y17 IO/VRN4 IO W10 DOPAUX10 DDIG3 U3 IO IO K6 LNA5
CFI10 E7 IO IO E13 TESTSIN10 1J_10 F19 IO IO N18 4J_10 ADOFF AA17 IO IO V10 DOPAUX26 DDIG12 V2 IO IO K5 LD1
CFI11 E8 IO IO/VREF1 E14 TESTSIN11 1J_11 F20 IO IO P18 4J_11 DOPAUX31 AB17 IO IO/VREF5 V9 DOPAUX28 DDIG13 V1 IO IO J5 LD4
E CFI12 D7 IO IO A14 TESTSIN12 1J_12 F21 IO IO/VREF3 P22 4J_12 DOPAUXCTL1 V16 IO IO AB9 DOPAUX18 DDIG14 U2 IO IO/VREF7 J1 LD7
CFI13 C7 IO/VREF0 IO B14 TESTSIN13 1J_13 F22 IO/VREF2 IO P21 4J_13 DOPAUXCTL0 V15 IO IO AA9 DOPAUX16 DDIG15 U1 IO/VREF6 IO J2 LA1
CFI14 B7 IO IO C14 TESTSIN14 1J_14 G18 IO IO P20 4J_14 W16 IO IO Y9 DOPAUX13 DDIG4 T5 IO IO J3 LD3
CFI15 A7 IO IO D14 TESTSIN15 1J_15 H18 IO IO P19 4J_15 DOPAUX1 Y16 IO/VREF4 IO W9 DOPAUX12 DDIG7 R5 IO IO J4 LD11
CFQ0 D8 IO IO/VREF1 A15 TESTCOS8 2J_0 G19 IO IO R22 3J_0 DOPAUX29 AA16 IO IO/VREF5 AB8 DOPAUXCTL3 DDIG6 T4 IO IO H1 LD15
CFQ1 C8 IO IO B15 TESTCOS9 2J_1 G20 IO IO R21 3J_1 DOPAUX25 AB16 IO IO AA8 DOPAUXCTL2 DDIG5 T3 IO IO H2 LD12
CFQ2 B8 IO IO C15 TESTCOS10 2J_2 G21 IO IO R20 3J_2 DOPAUX2 W15 IO IO Y8 DOPAUX24 DDIG16 T2 IO IO H3 LD8
CFQ3 A8 IO IO D15 TESTCOS11 2J_3 G22 IO IO R19 3J_3 DOPAUX15 Y15 IO IO W8 DOPAUX30 DDIG17 T1 IO IO H4 LD9
CFQ4 E9 IO IO F14 TESTCOS12 2J_4 H19 IO IO/VREF3 R18 3J_4 DOPAUX9 AA15 IO IO U9 DOPAUX27 CPUAUX0 R4 IO IO/VREF7 J6 MLN0
CFQ5 F9 IO/VREF0 IO E15 TESTCOS13 2J_5 H20 IO/VREF2 IO P17 3J_5 DOPAUX23 AB15 IO IO V8 DOPAUX20 CPUAUX1 R3 IO/VREF6 IO H5 LSDOP
CFQ6 D9 IO IO A16 TESTCOS14 2J_6 H21 IO IO T22 3J_6 DOPAUX4 U14 IO IO AB7 LNA11 R2 IO IO G1 LRW
CFQ7 C9 IO IO B16 TESTCOS15 2J_7 H22 IO IO T21 3J_7 DOPAUX0 V14 IO/VREF4 IO AA7 SCAUX1 R1 IO IO G2 LD0
CFQ8 B9 IO IO/VREF1 C16 XIL1_XIL2_AUX0 2J_8 J17 IO IO T20 3J_8 DOPAUX7 W14 IO IO/VREF5 Y7 P6 IO IO G3 LD13
CFQ9 A9 IO IO D16 XIL1_XIL2_AUX1 2J_9 J18 IO IO T19 3J_9 DOPAUX14 Y14 IO IO W7 P5 IO IO G4 LNA3
CFQ10 E10 IO/VREF0 IO E16 XIL1_XIL3_AUX0 2J_10 J19 IO IO U22 3J_10 DOPAUX19 AA14 IO IO AB6 P4 IO IO F1 LNA2
CFQ11 F10 IO IO E17 XIL1_XIL3_AUX1 2J_11 J20 IO IO U21 3J_11 DOPAUX21 AB14 IO IO AA6 P3 IO IO F2 LNA4
CFQ12 D10 IO IO A17 XIL1_AUX0 2J_12 J21 IO IO/VREF3 U20 3J_12 DOPAUX5 U13 IO/VREF4 IO Y6 P2 IO IO/VREF7 F3 LNA0
D CFQ13 C10 IO IO B17 XIL1_AUX1 2J_13 J22 IO/VREF2 IO U19 3J_13 V13 IO IO W6 P1 IO/VREF6 IO F4 LNA9
CFQ14 B10 IO IO C17 XIL1_AUX2 2J_14 K17 IO IO T18 3J_14 W13 IO IO/VRP5 V7 N6 IO IO G5 LD14
CFQ15 A10 IO IO/VREF1 D17 XIL1_AUX3 2J_15 K18 IO IO U18 3J_15 Y13 IO IO/VRN5 V6 N5 IO IO F5 LNA1
E11 A18 K19 V22 AA13 AB5 N4 E1

IO/VREF0 IO/VRP1 AA0 IO IO AA15 IO IO IO IO SCAUX0

F11 IO IO/VRN1 B18 AA1 K20 IO IO V21 AA14 AB13 IO IO/VREF5 AA5 N3 IO IO E2 LNA10
D11 IO/GCLK7P IO C18 TB66 AA2 K21 IO IO V20 AA13 U12 IO/VREF4 IO/D4/ALT_VRP5 Y5 XIL_DATA4 N2 IO IO E3 LNA6
TB101
C11 IO/GCLK6S IO D18 TB63 AA3 K22 IO IO V19 AA12 DOPAUX6 V12 IO IO/D5/ALT_VRN5 W5 XIL_DATA5 N1 IO IO E4 LNA7
TB100
XIL1_40M B11 IO/GCLK5P IO A19 TB65 AA4 L17 IO IO/VREF3 W22 AA11 W12 IO/GCLK3S IO/D6 AB4 XIL_DATA6 M6 IO IO/VREF7 D1 MLN1
TB94
A11 IO/GCLK4S IO B19 TB64 AA5 L18 IO/VREF2 IO W21 AA10 Y12 IO/GCLK2P IO/D7 AA4 XIL_DATA7 M5 IO/VREF6 IO D2 MLN2
2 TB95
R237
AA6 L19 IO IO/VRP3 Y22 AA9 AA12 IO/GLCK1S IO/RDWR_B Y4 XIL_WRITE M4 IO IO/VRN7 C1 MLN3
L20 Y21 AB12 AA3
TB96 M3 C2
82
AA7 IO IO/VRN3 AA8 XIL1_DPTCLK IO/GCLK0P IO/CS_B XIL1_CS TB97 IO IO/VRP7 ACFM
L21 IO IO W20 M2 IO IO E5 CFMON
L22 AA20
TB99 M1 E6
IO IO TB98 IO IO CFMOFF
2
100P
C230
G9 VCCOBank0 VCCOBank1 G12 J16 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T11 P7 VCCOBank6 VCCOBank7 J7
C
XIL_DONE
TB59
U34
+3V3 +3V3 +3V3 +3V3
XC2V1000-4
R233
+3V3 Y19 C19
XIL_CCLK CCLK TCK XIL_TCK
0
XIL_PROG A2 PROG_B TDI D3 XIL0_TDO
AB20 DONE TDO D20 XIL1_TDO
AB2 B20
R248
M0 TMS XIL_TMS
1K00
W3 M1 DXN D5
2 AB3 A3
M2 DXP
B3 HSWAP_EN VBATT A21
R243
R249
R251
R242
1K00
1K00
1K00
1K00
R232
1K00
B
TP10 +3V3 +3V3
+3V3
C23
47U
A
837 0147 042 Rev.A
FORM:
FPGA RFII E MTI
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 5 16

1 2 3 4 5 6 7 8 9 10 11
F
U25 U25 U25 U25
XC2S300 XC2S300 XC2S300 XC2S300
DPX1 A3 I/O GCK2,I A11 XIL2_DPTCLK XIL_BUSY C21 I/O(DOUT,BUSY) I/O(TRDY) L22 M1X16 M2X0 U12 I/O I/O U9 OCI0 CFI12 M1 I/O(TRDY) I/O C1 MTI_COR0
DPX0 A4 I/O I/O(DLL) A12 DPX9 XIL_DATA0 C22 I/O(DIN,D0) I/O M17 M1X17 M2X1 U13 I/O I/O U10 OCI1 CFI13 M2 I/O I/O C2 CPUAUX0
DPX3 A5 I/O I/O A13 DPX17 DPY3 D20 I/O I/O M18 M1X15 M2X2 U14 I/O I/O U11 OCI2 CFI2 M3 I/O I/O D1 CFQ15
DPX2 A6 I/O I/O A14 DPX19 DPY0 D21 I/O(VREFBank2) I/O M19 M1Y1 M2X3 V12 I/O I/O V6 OCI3 CFI3 M4 I/O I/O D2 CFMOFF
DPX4 A7 I/O I/O A15 DPX20 DPY1 D22 I/O I/O M20 M1X20 M2X4 V13 I/O(VREFBank4) I/O V7 OCI4 CFI4 M5 I/O I/O D3 CFQ9
DPX5 A8 I/O I/O A16 DPX22 RXYCS E19 I/O I/O M21 M1X21 M2X5 V14 I/O I/O(VREFBank5) V8 OCI5 CFI5 M6 I/O I/O E1 CFQ10
DPX7 A9 I/O I/O A17 XIL2_XIL3_AUX0 RXYOE E20 I/O I/O M22 M1X19 M2X6 V15 I/O(VREFBank4) I/O V9 OCI6 CFI6 N1 I/O I/O(VREFBank7) E2 CFQ14
DPX14 A10 I/O I/O A18 DPY19 RXYWE E21 I/O I/O(D4) N17 XIL_DATA4 M2X7 V16 I/O I/O(VREFBank5) V10 OCI7 CFI7 N2 I/O I/O E3 LD2
TY2 B3 I/O I/O A19 DPY17 MEM1CS E22 I/O I/O(VREFBank3) N18 TB45 M2X8 V17 I/O I/O V11 OCI8 CFI8 N3 I/O(VREFBank6) I/O F1 CPUAUX1
TY3 B4 I/O I/O(WRITE) A20 XIL_WRITE MEM1OE F18 I/O I/O N19 M1Y0 M2X9 W12 I/O I/O W5 OCI9 CFI9 N4 I/O I/O(VREFBank7) F2 XIL2_TXS
TY4 B5 I/O I/O B12 PEROE MEM1WE F19 I/O I/O N20 M1X23 M2X10 W13 I/O I/O W6 OCI10 CFI10 N5 I/O I/O F3 LD5
TY5 B6 I/O(VREFBank0) I/O(VREFBank1) B13 DPX16 MEM2CS F20 I/O I/O N21 M1X22 M2X11 W14 I/O I/O W7 OCI11 CFI11 N6 I/O I/O F4 LD6
E
TY6 B7 I/O I/O B14 DPX18 MEM2OE F21 I/O(VREFBank2) I/O N22 M1Y3 M2X12 W15 I/O I/O W8 OCI12 CFI0 P1 I/O I/O F5 LD7
TX1 B8 I/O I/O B15 DPX21 MEM2WE F22 I/O I/O P17 TB48 M2X13 W16 I/O I/O W9 OCI13 CFI1 P2 I/O I/O G1 MTI_COR1
DPX6 B9 I/O I/O B16 DPX23 DPY8 G18 I/O I/O P18 TB47 M2X14 W17 I/O I/O W10 OCI14 CFI14 P3 I/O I/O G2 FIRST/SECOND
DPX15 B10 I/O I/O B17 DPY21 M1X1 G19 I/O I/O P19 TB46 M2X15 W18 I/O(VREFBank4) I/O W11 OCI15 CFI15 P4 I/O I/O G3 LD10
DPX13 B11 I/O(DLL) I/O(VREFBank1) B18 DPY18 XIL1_XIL2_AUX1 G20 I/O I/O P20 M1X18 M2X16 Y12 I/O(DLL) I/O Y5 OCQ0 CFQ0 P5 I/O I/O G4 LD11
CFMAUX2 C4 I/O I/O B19 DPY16 XIL2_XIL3_AUX1 G21 I/O I/O P21 M1Y8 M2X17 Y13 I/O I/O Y6 OCQ1 CFQ1 P6 I/O I/O G5 LD12
C5 B20 G22 P22 +3V3 Y14 Y7 R1 H1
CFMAUX3 I/O(VREFBank0) I/O(CS) XIL2_CS M1X6 I/O I/O(D5) XIL_DATA5 M2X18 I/O I/O OCQ2 LN0 I/O I/O ACFM
CFMAUX5 C6 I/O I/O C12 DPY22 M1X14 H18 I/O(VREFBank2) I/O(VREFBank3) R18 M1Y9 M2X19 Y15 I/O I/O Y8 OCQ3 LN1 R2 I/O I/O H2 CFMON
CFMAUX7 C7 I/O I/O C13 DPY12 XIL_DATA1 H19 I/O(D1) I/O(D6) R19 XIL_DATA6 M2X20 Y16 I/O I/O Y9 OCQ4 CFQ4 R3 I/O(VREFBank6) I/O(VREFBank7) H3 LD15
TX3 C8 I/O I/O C14 DPY14 XIL_DATA2 H20 I/O(D2) I/O R20 M1Y10 M2X21 Y17 I/O(VREFBank4) I/O Y10 OCQ5 CFQ5 R4 I/O I/O H4 LSDOP
R203
C9 C15 H21 R21 Y18 Y11 R5 H5
4K7
TY7 I/O I/O PERWE M1X5 I/O I/O M1Y11 M2X22 I/O I/O OCQ6 CFQ6 I/O I/O LRW
TY8 C10 I/O I/O C16 DPY6 M1X4 H22 I/O I/O R22 M1Y12 M2X23 Y19 I/O I/O AA3 OCQ7 LNA6 T1 I/O I/O J1 CFQ12
XIL2_40M C11 GCK3,I I/O C17 DPY4 M1X0 J17 I/O I/O T18 M1Y13 AA12 GCK0/I I/O AA5 OCQ8 LNA7 T2 I/O I/O J2 CFQ13
CFMAUX1 D5 I/O I/O C18 DPY2 M1X11 J18 I/O I/O T19 M1Y14 AA13 I/O I/O AA6 OCQ9 LA4 T3 I/O I/O J3 LNA2
CFMAUX4 D6 I/O I/O D12 DPY10 M1X13 J19 I/O I/O T20 M1Y15 M2Y0 AA14 I/O I/O AA7 OCQ10 LD1 T4 I/O I/O J4 LNA3
CFMAUX6 D7 I/O I/O D13 DPY13 M1X12 J20 I/O I/O(VREFBank3) T21 M1Y16 M2Y1 AA15 I/O I/O AA8 OCQ11 CFQ11 T5 I/O I/O J5 LNA4
CFMAUX0 D8 I/O(VREFBank0) I/O D14 DPY15 M1Y7 J21 I/O I/O T22 M1Y17 M2Y2 AA16 I/O I/O AA9 OCQ12 LNA0 U1 I/O(VREFBank6) I/O J6 LNA5
D TY0 D9 I/O I/O(VREFBank1) D15 TX8 M1Y6 J22 I/O I/O U18 M1Y18 M2Y3 AA17 I/O I/O AA10 OCQ13 LNA1 U2 I/O I/O K1 LNA8
TY1 D10 I/O(VREFBank0) I/O D16 DPY5 DPY9 K17 I/O I/O U19 M1Y19 M2Y4 AA18 I/O I/O AA11 OCQ14 LD0 U3 I/O I/O K2 CFQ8
DPX12 D11 I/O I/O D17 XIL2_AUX0 M1X7 K18 I/O(VREFBank2) I/O U20 M1Y20 M2Y5 AA19 I/O I/O AB3 OCQ15 LA3 U4 I/O I/O(VREFBank7) K3 CFQ7
TX4 E7 I/O I/O D18 XIL2_AUX1 XIL_DATA3 K19 I/O(D3) I/O U21 M1Y21 M2Y6 AA20 I/O I/O AB4 M2Y23 LD13 V1 I/O I/O K4 LNA9
TX5 E8 I/O I/O E12 DPY11 M1X10 K20 I/O I/O U22 M1Y22 M2Y7 AB13 I/O I/O(VREFBank5) AB5 M2Y22 LD14 V2 I/O(VREFBank6) I/O K5 LNA10
TX6 E9 I/O I/O E13 DPY23 M1Y5 K21 I/O I/O V19 M1Y23 M2Y8 AB14 I/O I/O AB6 M2Y21 LA2 V3 I/O I/O K6 LNA11
TX0 E10 I/O I/O E14 DPY20 M1Y4 K22 I/O I/O V20 FLAG2 M2Y9 AB15 I/O I/O(VREFBank5) AB7 M2Y20 LA1 V4 I/O I/O L1 CFQ2
DPX10 E11 I/O I/O E15 DPY7 M1X2 L17 I/O I/O V21 TB51 M2Y10 AB16 I/O I/O AB8 M2Y19 LD8 W1 I/O I/O L2 CFQ3
TX7 F9 I/O I/O(VREFBank1) E16 XIL2_AUX2 M1X3 L18 I/O I/O(VREFBank3) V22 M2Y11 AB17 I/O I/O AB9 M2Y18 LD9 W2 I/O I/O L3 LN2
TX2 F10 I/O I/O E17 XIL2_AUX3 M1X9 L19 I/O I/O(INIT) W21 M2Y12 AB18 I/O I/O AB10 M2Y17 LA0 W3 I/O I/O L4 LN3
DPX11 F11 I/O I/O F12 DPX8 M1X8 L20 I/O I/O W22 TB50 M2Y13 AB19 I/O I/O(DLL) AB11 M2Y16 LD3 Y1 I/O I/O L5 SCAUX0
I/O F13 PERCS M1Y2 L21 I/O(IRDY) I/O(D7) Y22 XIL_DATA7 M2Y14 AB20 I/O GCK1,I AB12 LD4 Y2 I/O I/O(IRDY) L6 SCAUX1
I/O F14 XIL1_XIL2_AUX0 M2Y15 AB21 I/O
4K7
R204
R210
0
C G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 XIL_INIT U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
+3V3
XIL_DONE U25
+3V3 +3V3 +3V3 +3V3 +3V3
XC2S300
R209
TB60
XIL_CCLK B22 CCLK TCK E6 XIL_TCK
0
XIL_PROG Y21 PROGRAM
R205
W20 DONE
1K00
AA1 M0 TDI C19 XIL1_TDO
2 U5 A21
M1 TDO XIL2_TDO
R206
R211
R207
1K00
1K00
1K00
B XIL2_40M +3V3
2
R218
82
2
100P
C166
TP3
A +3V3
837 0147 042 Rev.A
C24
FORM:
47U
FPGA CORRELATOR
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 6 16

1 2 3 4 5 6 7 8 9 10 11
F
U33 U33 U33 U33
XC2S300 XC2S300 XC2S300 XC2S300
CFMD0 A3 I/O GCK2,I A11 XIL3_DPTCLK XIL_BUSY C21 I/O(DOUT,BUSY) I/O(TRDY) L22 OCS TX0 U12 I/O I/O U9 TO1 CFI0 M1 I/O(TRDY) I/O C1 LA0
CFMD2 A4 I/O I/O(DLL) A12 TB85 XIL_DATA0 C22 I/O(DIN,D0) I/O M17 OOE TX1 U13 I/O I/O U10 TO2 CFI1 M2 I/O I/O C2 LA1
CFMD5 A5 I/O I/O A13 TB84 M1O13 D20 I/O I/O M18 OWE TX2 U14 I/O I/O U11 TO3 CFI2 M3 I/O I/O D1 LA2
CFMD9 A6 I/O I/O A14 TB83 M1O14 D21 I/O(VREFBank2) I/O M19 OCLK TX3 V12 I/O I/O V6 TO4 CFI3 M4 I/O I/O D2 LA3
CFMD13 A7 I/O I/O A15 TB82 M1O15 D22 I/O I/O M20 TH1 TX4 V13 I/O(VREFBank4) I/O V7 TO5 CFI4 M5 I/O I/O D3 LA4
CFMD17 A8 I/O I/O A16 M2O0 M1O9 E19 I/O I/O M21 TH2 TX5 V14 I/O I/O(VREFBank5) V8 TO6 CFI5 M6 I/O I/O E1 LD0
A9 I/O I/O A17 M2O1 M1O10 E20 I/O I/O M22 VARIANCE TX6 V15 I/O(VREFBank4) I/O V9 TO7 CFI6 N1 I/O I/O(VREFBank7) E2 LD1
A10 I/O I/O A18 M2O2 M1O11 E21 I/O I/O(D4) N17 XIL_DATA4 TX7 V16 I/O I/O(VREFBank5) V10 TO8 CFI7 N2 I/O I/O E3 LD2
CFMD1 B3 I/O I/O A19 M2O3 M1O12 E22 I/O I/O(VREFBank3) N18 ADP10 TX8 V17 I/O I/O V11 CFMAUX0 CFI8 N3 I/O(VREFBank6) I/O F1 LD3
CFMD3 B4 I/O I/O(WRITE) A20 XIL_WRITE M1O4 F18 I/O I/O N19 ADP11 TY0 W12 I/O I/O W5 CFMAUX1 CFI9 N4 I/O I/O(VREFBank7) F2 LD4
CFMD6 B5 I/O I/O B12 Q0 M1O5 F19 I/O I/O N20 ADP12 TY1 W13 I/O I/O W6 CFMAUX2 CFI10 N5 I/O I/O F3 LD5
CFMD10 B6 I/O(VREFBank0) I/O(VREFBank1) B13 Q1 M1O6 F20 I/O I/O N21 ADP13 TY2 W14 I/O I/O W7 CFMAUX3 CFI11 N6 I/O I/O F4 LD6
E
CFMD14 B7 I/O I/O B14 Q2 M1O7 F21 I/O(VREFBank2) I/O N22 ADP14 TY3 W15 I/O I/O W8 CFMAUX4 CFI12 P1 I/O I/O F5 LD7
XIL3_AUX0 B8 I/O I/O B15 Q3 M1O8 F22 I/O I/O P17 ADP15 TY4 W16 I/O I/O W9 CFMAUX5 CFI13 P2 I/O I/O G1 LD8
XIL3_AUX1 B9 I/O I/O B16 M2O4 M1O0 G18 I/O I/O P18 ADP16 TY5 W17 I/O I/O W10 CFMAUX6 CFI14 P3 I/O I/O G2 LD9
XIL3_AUX2 B10 I/O I/O B17 M2O5 M1O1 G19 I/O I/O P19 ADP17 TY6 W18 I/O(VREFBank4) I/O W11 CFMAUX7 CFI15 P4 I/O I/O G3 LD10
XIL3_AUX3 B11 I/O(DLL) I/O(VREFBank1) B18 M2O6 M1O2 G20 I/O I/O P20 TY7 Y12 I/O(DLL) I/O Y5 VA0 CFQ0 P5 I/O I/O G4 LD11
CFMD4 C4 I/O I/O B19 M2O7 M1O3 G21 I/O I/O P21 TY8 Y13 I/O I/O Y6 VA1 CFQ1 P6 I/O I/O G5 LD12
C5 B20 G22 P22 +3V3 Y14 Y7 R1 H1
CFMD7 I/O(VREFBank0) I/O(CS) XIL3_CS I/O I/O(D5) XIL_DATA5 I/O I/O VA2 CFQ2 I/O I/O LD13
CFMD11 C6 I/O I/O C12 Q4 H18 I/O(VREFBank2) I/O(VREFBank3) R18 Y15 I/O I/O Y8 VA3 CFQ3 R2 I/O I/O H2 LD14
CFMD15 C7 I/O I/O C13 Q5 XIL_DATA1 H19 I/O(D1) I/O(D6) R19 XIL_DATA6 Y16 I/O I/O Y9 VA4 CFQ4 R3 I/O(VREFBank6) I/O(VREFBank7) H3 LD15
C8 C14 H20 R20 Y17 Y10 R4 H4
R221
I/O I/O Q6 XIL_DATA2 I/O(D2) I/O AD0 I/O(VREFBank4) I/O VA5 CFQ5 I/O I/O LSDOP
C9 C15 H21 R21 Y18 Y11 R5 H5
4K7
I/O I/O Q7 ADB10 I/O I/O AD1 I/O I/O VA6 CFQ6 I/O I/O LRW
FLAG2 C10 I/O I/O C16 M2O8 ADB11 H22 I/O I/O R22 AD2 Y19 I/O I/O AA3 VA7 CFQ7 T1 I/O I/O J1 LNA0
XIL3_40M C11 GCK3,I I/O C17 M2O9 ADB12 J17 I/O I/O T18 AD3 AA12 GCK0/I I/O AA5 VE0 CFQ8 T2 I/O I/O J2 LNA1
CFMD8 D5 I/O I/O C18 M2O10 ADB13 J18 I/O I/O T19 AD4 AA13 I/O I/O AA6 VE1 CFQ9 T3 I/O I/O J3 LNA2
CFMD12 D6 I/O I/O D12 Q8 ADB14 J19 I/O I/O T20 AD5 DPO1 AA14 I/O I/O AA7 VE2 CFQ10 T4 I/O I/O J4 LNA3
CFMD16 D7 I/O I/O D13 Q9 ADR10 J20 I/O I/O(VREFBank3) T21 AD6 DPO3 AA15 I/O I/O AA8 VE3 CFQ11 T5 I/O I/O J5 LNA4
XIL1_XIL3_AUX0 D8 I/O(VREFBank0) I/O D14 Q10 ADR11 J21 I/O I/O T22 AD7 DPO11 AA16 I/O I/O AA9 VE4 CFQ12 U1 I/O(VREFBank6) I/O J6 LNA5
D XIL1_XIL3_AUX1 D9 I/O I/O(VREFBank1) D15 Q11 ADR12 J22 I/O I/O U18 AD8 DPO13 AA17 I/O I/O AA10 VE5 CFQ13 U2 I/O I/O K1 LNA6
XIL2_XIL3_AUX0 D10 I/O(VREFBank0) I/O D16 M2O11 ADR13 K17 I/O I/O U19 AD9 DPO14 AA18 I/O I/O AA11 VE6 CFQ14 U3 I/O I/O K2 LNA7
XIL2_XIL3_AUX1 D11 I/O I/O D17 M2O12 ADR14 K18 I/O(VREFBank2) I/O U20 ADA10 DPO15 AA19 I/O I/O AB3 VE7 CFQ15 U4 I/O I/O(VREFBank7) K3 LNA8
E7 I/O I/O D18 M2O13 XIL_DATA3 K19 I/O(D3) I/O U21 ADA11 DPO12 AA20 I/O I/O AB4 ACFM V1 I/O I/O K4 LNA9
TB93
E8 I/O I/O E12 Q12 ADQ10 K20 I/O I/O U22 ADA12 DPO7 AB13 I/O I/O(VREFBank5) AB5 CFMON V2 I/O(VREFBank6) I/O K5 LNA10
TB92 E9 E13 K21 V19 AB14 AB6 V3 K6
TB91 I/O I/O Q13 ADQ11 I/O I/O ADA13 DPO0 I/O I/O CFMOFF I/O I/O LNA11
E10 I/O I/O E14 Q14 ADQ12 K22 I/O I/O V20 ADA14 DPO2 AB15 I/O I/O(VREFBank5) AB7 MTI_COR0 V4 I/O I/O L1 LN0
TB89 E11 E15 L17 V21 AB16 AB8 W1 L2
TB87 I/O I/O Q15 ADQ13 I/O I/O ADA15 DPO4 I/O I/O MTI_COR1 I/O I/O LN1
F9 I/O I/O(VREFBank1) E16 M2O14 ADQ14 L18 I/O I/O(VREFBank3) V22 DPO5 AB17 I/O I/O AB9 FIRST/SECOND W2 I/O I/O L3 LN2
TB90 F10 E17 L19 W21 AB18 AB10 W3 L4
TB88 I/O I/O M2O15 ADDAUX I/O I/O(INIT) DPO6 I/O I/O CPUAUX0 I/O I/O LN3
F11 I/O I/O F12 L20 I/O I/O W22 DPO10 AB19 I/O I/O(DLL) AB11 CPUAUX1 Y1 I/O I/O L5 SCAUX0
TB86 F13 L21 Y22 AB20 AB12 Y2 L6
I/O I/O(IRDY) I/O(D7) XIL_DATA7 DPO9 I/O GCK1,I XIL3_TXS I/O I/O(IRDY) SCAUX1
I/O F14 DPO8 AB21 I/O
4K7
R222
R229
0
C G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 XIL_INIT U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
+3V3
XIL_DONE U33
+3V3 +3V3 +3V3 +3V3
+3V3 XC2S300
R230
XIL_CCLK B22 CCLK TCK E6 XIL_TCK
0
XIL_PROG Y21 PROGRAM
W20 DONE
R223
AA1 C19
1K00
M0 TDI XIL2_TDO
2 U5 M1 TDO A21 XIL_TDO
R224
R231
R219
1K00
1K00
1K00
XIL3_40M
B 2 +3V3
R253
82
2
100P
C283
TP15
+3V3
A
C25
837 0147 042 Rev.A
47U
FORM:
FPGA CORRELATOR
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 7 16

1 2 3 4 5 6 7 8 9 10 11
U27 U2 U7 U19 U11

74LVT273 K6R1016V1D K6R1016V1D K6R1016V1D K6R1016V1D
ADCK 11 CLK MTIOE 41 OE MTIOE 41 OE MTIOE 41 OE MTIOE 41 OE
F ADOFF 1 RES MTIWE 17 WE MTIWE 17 WE MTIWE 17 WE MTIWE 17 WE
MTICS 6 CS MTICS 6 CS MTICS 6 CS MTICS 6 CS
AA0 3 1D 1Q 2 AD_MTI0
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB
AA3 8 4D 4Q 9 AD_MTI3 AD_MTI0 44 A0 I/O0 7 1J_0 AD_MTI0 44 A0 I/O0 7 2J_0 AD_MTI0 44 A0 I/O0 7 3J_0 AD_MTI0 44 A0 I/O0 7 4J_0
AD_MTI5 25 A5 I/O5 14 1J_5 AD_MTI5 25 A5 I/O5 14 2J_5 AD_MTI5 25 A5 I/O5 14 3J_5 AD_MTI5 25 A5 I/O5 14 4J_5
U26
74LVT273 20 29 20 29 20 29 20 29
AD_MTI8 A8 I/O8 1J_8 AD_MTI8 A8 I/O8 2J_8 AD_MTI8 A8 I/O8 3J_8 AD_MTI8 A8 I/O8 4J_8
ADCK 11 CLK
ADOFF 1 RES
AA8 3 1D 1Q 2 AD_MTI8 LN0 5 A11 I/O11 32 1J_11 LN0 5 A11 I/O11 32 2J_11 LN0 5 A11 I/O11 32 3J_11 LN0 5 A11 I/O11 32 4J_11
AA9 4 2D 2Q 5 AD_MTI9 LN1 4 A12 I/O12 35 1J_12 LN1 4 A12 I/O12 35 2J_12 LN1 4 A12 I/O12 35 3J_12 LN1 4 A12 I/O12 35 4J_12
E AA10 7 3D 3Q 6 AD_MTI10 LN2 3 A13 I/O13 36 1J_13 LN2 3 A13 I/O13 36 2J_13 LN2 3 A13 I/O13 36 3J_13 LN2 3 A13 I/O13 36 4J_13
AA11 8 4D 4Q 9 LN0 LN3 2 A14 I/O14 37 1J_14 LN3 2 A14 I/O14 37 2J_14 LN3 2 A14 I/O14 37 3J_14 LN3 2 A14 I/O14 37 4J_14
AA12 13 5D 5Q 12 LN1 1 A15 I/O15 38 1J_15 1 A15 I/O15 38 2J_15 1 A15 I/O15 38 3J_15 1 A15 I/O15 38 4J_15
AA13 14 6D 6Q 15 LN2 22 NC 22 NC 22 NC 22 NC
AA14 17 7D 7Q 16 LN3 23 NC 23 NC 23 NC 23 NC
AA15 18 8D 8Q 19 28 NC 28 NC 28 NC 28 NC
R198
TP11
U16
1K00
TP8
TP5
TP6
TP9
TP7
7ALCX374
1 OE
TEST_CLK 11 CLK
TESTCOS8 3 D1 Q1 2 TCOS0
D
8 9
R90 R77 R214 R97
TESTCOS11 D4 Q4 TCOS3
13 12 1K2 1K2 82K 82K

TCOS7 TSIN7 CFI10 CFQ10
R88
R91
R78
R79
18 19 R86 R75 R212 R94
1K2
1K2
1K2
1K2
1K2 1K2 39K 39K
R89
R87
R61
R76
R84 R59 R216 R95
1K2
1K2
1K2
1K2
1K2 1K2 22K 22K
R197
R85
R82
R74
R60
U15 R80 R57 R215 R96
1K2
1K2
1K2
1K2
1K00
C 7ALCX374 1K2 1K2 10K 10K
1 TCOS4 TSIN4 CFI13 CFQ13
OE
TEST_CLK 11 CLK
R83
R81
R73
R58
3 2 R30 R23 R213 R106
1K2
1K2
1K2
1K2
TESTSIN8 D1 Q1 TSIN0
TESTSIN9 4 D2 Q2 5 TSIN1 1K2 1K2 4K7 4K7
TESTSIN10 7 D3 Q3 6 TSIN2 TCOS3 TSIN3 CFI14 CFQ14
TESTSIN11 8 D4 Q4 9 TSIN3
R29
R27
R14
R13
R31 R24
1K2
1K2
1K2
1K2
TESTSIN14 17 D7 Q7 16 TSIN6 1K2 1K2
18 19 TCOS2 TSIN2
TESTSIN15 D8 Q8 TSIN7
R33
R28
R21
R16
R35 R25
1K2
1K2
1K2
1K2
1K2 1K2
TCOS1 TSIN1
R34
R32
R19
R17
B R36 R26
1K2
1K2
1K2
1K2
1K2 1K2
TCOS0 TSIN0
R18
R15
TP13
1K2
1K2
A
837 0147 042 Rev.A
FORM:
MEMORIE MTI E TEST POINT RFII E MTI
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 8 16

1 2 3 4 5 6 7 8 9 10 11
U58 U39 U46 U32

K6R1016V1D K6R1016V1D K6R1016V1D K6R4016V1D
OOE 41 OE MEM1OE 41 OE MEM2OE 41 OE PEROE 41 OE
F OWE 17 WE MEM1WE 17 WE MEM2WE 17 WE PERWE 17 WE
OCS 6 CS MEM1CS 6 CS MEM2CS 6 CS PERCS 6 CS
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB
AD0 44 A0 I/O0 7 Q0 AD0 44 A0 I/O0 7 M1O0 AD0 44 A0 I/O0 7 M2O0 AD0 1 A0 I/O0 7 DPO0
ADDAUX 19 A9 I/O9 30 Q9 AD9 19 A9 I/O9 30 M1O9 AD9 19 A9 I/O9 30 M2O9 AD9 22 A9 I/O9 30 DPO9
ADQ10 18 A10 I/O10 31 Q10 ADA10 18 A10 I/O10 31 M1O10 ADB10 18 A10 I/O10 31 M2O10 ADP10 23 A10 I/O10 31 DPO10
E ADQ13 3 A13 I/O13 36 Q13 ADA13 3 A13 I/O13 36 M1O13 ADB13 3 A13 I/O13 36 M2O13 ADP13 26 A13 I/O13 36 DPO13
1 A15 I/O15 38 Q15 ADA15 1 A15 I/O15 38 M1O15 1 A15 I/O15 38 M2O15 ADP15 42 A15 I/O15 38 DPO15
22 NC 22 NC 22 NC ADP16 43 A16
23 NC 23 NC 23 NC ADP17 44 A17
28 NC 28 NC 28 NC
R187
R186
U4 UP3
1K00
1K00
R185
R184
R193
UP2
1K00
1K00
1K00
7ACT374 29F040-70
D 1 24 U14 27C4096-70 U12
OE R192 OE R196 R194
OCLK 11 CLK 1K00
22 CE 1K00
74LCX244 22 OE 1K00
74LCX244
VCC
31 WE 1 1G 3 CS 1 1G
R0 3 D1 Q1 2 RT0
VCC
19 2 19
4 5 2G Vpp 2G
R1 D2 Q2 RT1
R2 7 D3 Q3 6 RT2 RT0 12 A0 O0 13 2 1A1 1Y1 18 VA0 TY0 24 A0 O0 21 2 1A1 1Y1 18 VE0

RT6 6 A6 O6 20 15 2A3 2Y3 5 VA6 TY6 30 A6 O6 15 15 2A3 2Y3 5 VE6
RT7 5 A7 O7 21 17 2A4 2Y4 3 VA7 TY7 31 A7 O7 14 17 2A4 2Y4 3 VE7
U13 27 32 11
R195 PO0 A8 TY8 A8 O8 R0
1K00
7ACT374 PO1 26 A9 TX0 35 A9 O9 10 R1
1 OE PO2 23 A10 TX1 36 A10 O10 9 R2
OCLK 11 CLK PO3 25 A11 TX2 37 A11 O11 8 R3
PO4 4 A12 TX3 38 A12 O12 7 R4
TO1 3 D1 Q1 2 PO0
C TO2 4 D2 Q2 5 PO1
PO5 28 A13 TX4 39 A13 O13 6 R5
PO6 29 A14 TX5 40 A14 O14 5 R6
TO3 7 D3 Q3 6 PO2
PO7 3 A15 TX6 41 A15 O15 4 R7
TO4 8 D4 Q4 9 PO3
VARIANCE 2 A16 TX7 42 A16
TO5 13 D5 Q5 12 PO4
TH1 30 A17 TX8 43 A17
TO6 14 D6 Q6 15 PO5
TH2 1 A18
TO7 17 D7 Q7 16 PO6
TO8 18 D8 Q8 19 PO7
TP14
TP16
TP12
R256 R246
100K 100K
CFMD2 CFMD7
R259 R245
B 47K 47K
CFMD3 CFMD12
R247 R254
22K 22K
CFMD4 CFMD13
R255 R257
10K 10K
CFMD5 CFMD14
R258 R244
4K7 4K7
CFMD6 CFMD15
A
837 0147 042 Rev.A
FORM:
MEMORIE E TEST POINT CORRELATOR
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 9 16

1 2 3 4 5 6 7 8 9 10 11
U6 U1 U35 U30
RXYOE 41 OE RXYOE 41 OE MEM1OE 41 OE MEM1OE 41 OE
F RXYWE 17 WE RXYWE 17 WE MEM1WE 17 WE MEM1WE 17 WE
RXYCS 6 CS RXYCS 6 CS MEM1CS 6 CS MEM1CS 6 CS
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB
AD0 44 A0 I/O0 7 OCI0 AD0 44 A0 I/O0 7 OCQ0 AD0 44 A0 I/O0 7 M1X0 AD0 44 A0 I/O0 7 M1X16
AD8 20 A8 I/O8 29 OCI8 AD8 20 A8 I/O8 29 OCQ8 AD8 20 A8 I/O8 29 M1X8 AD8 20 A8 I/O8 29 M1Y0
AD9 19 A9 I/O9 30 OCI9 AD9 19 A9 I/O9 30 OCQ9 AD9 19 A9 I/O9 30 M1X9 AD9 19 A9 I/O9 30 M1Y1
ADR10 18 A10 I/O10 31 OCI10 ADR10 18 A10 I/O10 31 OCQ10 ADA10 18 A10 I/O10 31 M1X10 ADA10 18 A10 I/O10 31 M1Y2
E ADR13 3 A13 I/O13 36 OCI13 ADR13 3 A13 I/O13 36 OCQ13 ADA13 3 A13 I/O13 36 M1X13 ADA13 3 A13 I/O13 36 M1Y5
1 A15 I/O15 38 OCI15 1 A15 I/O15 38 OCQ15 ADA15 1 A15 I/O15 38 M1X15 ADA15 1 A15 I/O15 38 M1Y7
22 NC 22 NC 22 NC 22 NC
23 NC 23 NC 23 NC 23 NC
28 NC 28 NC 28 NC 28 NC
U29 U21 U18 U10

MEM1OE 41 OE MEM2OE 41 OE MEM2OE 41 OE MEM2OE 41 OE
MEM1WE 17 WE MEM2WE 17 WE MEM2WE 17 WE MEM2WE 17 WE
MEM1CS 6 CS MEM2CS 6 CS MEM2CS 6 CS MEM2CS 6 CS
40 UB 40 UB 40 UB 40 UB
39 LB 39 LB 39 LB 39 LB
AD0 44 A0 I/O0 7 M1Y8 AD0 44 A0 I/O0 7 M2X0 AD0 44 A0 I/O0 7 M2X16 AD0 44 A0 I/O0 7 M2Y8
D AD1 43 A1 I/O1 8 M1Y9 AD1 43 A1 I/O1 8 M2X1 AD1 43 A1 I/O1 8 M2X17 AD1 43 A1 I/O1 8 M2Y9
AD8 20 A8 I/O8 29 M1Y16 AD8 20 A8 I/O8 29 M2X8 AD8 20 A8 I/O8 29 M2Y0 AD8 20 A8 I/O8 29 M2Y16
AD9 19 A9 I/O9 30 M1Y17 AD9 19 A9 I/O9 30 M2X9 AD9 19 A9 I/O9 30 M2Y1 AD9 19 A9 I/O9 30 M2Y17
ADA10 18 A10 I/O10 31 M1Y18 ADB10 18 A10 I/O10 31 M2X10 ADB10 18 A10 I/O10 31 M2Y2 ADB10 18 A10 I/O10 31 M2Y18
ADA15 1 A15 I/O15 38 M1Y23 1 A15 I/O15 38 M2X15 1 A15 I/O15 38 M2Y7 1 A15 I/O15 38 M2Y23
22 NC 22 NC 22 NC 22 NC
23 NC 23 NC 23 NC 23 NC
C 28 NC 28 NC 28 NC 28 NC
U38
U37 U31
K6R4016V1D
41 K6R4016V1D K6R4016V1D
PEROE OE
PEROE 41 OE PEROE 41 OE
PERWE 17 WE
PERWE 17 WE PERWE 17 WE
PERCS 6 CS
PERCS 6 CS PERCS 6 CS
40 UB
40 UB 40 UB
39 LB
39 LB 39 LB
AD0 1 A0 I/O0 7 DPX0
AD0 1 A0 I/O0 7 DPX16 AD0 1 A0 I/O0 7 DPY8
AD3 4 A3 I/O3 10 DPX3
AD4 5 A4 I/O4 13 DPX4
AD5 18 A5 I/O5 14 DPX5
B AD6 19 A6 I/O6 15 DPX6
AD7 20 A7 I/O7 16 DPX7
AD8 21 A8 I/O8 29 DPX8
AD8 21 A8 I/O8 29 DPY0 AD8 21 A8 I/O8 29 DPY16
AD9 22 A9 I/O9 30 DPX9
AD9 22 A9 I/O9 30 DPY1 AD9 22 A9 I/O9 30 DPY17
ADP10 23 A10 I/O10 31 DPX10
ADP10 23 A10 I/O10 31 DPY2 ADP10 23 A10 I/O10 31 DPY18
ADP11 24 A11 I/O11 32 DPX11
ADP12 25 A12 I/O12 35 DPX12
ADP13 26 A13 I/O13 36 DPX13
ADP14 27 A14 I/O14 37 DPX14
ADP15 42 A15 I/O15 38 DPX15
ADP16 43 A16
ADP16 43 A16 ADP16 43 A16
ADP17 44 A17
ADP17 44 A17 ADP17 44 A17
A
837 0147 042 Rev.A
FORM:
MEMORIE CORRELATOR
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 10 16

FORM:
837 0147 042 Rev.A The information in this document is confidential and proprietary to ESAOTE S.p.A.; no part of this
by EpD
SHEET
A2
B
C
F
A
E
D
1
2
47U
C27
CR2 R272
TL431AC
22
DSIN
DCOS
+6V
R273 R114
C70 2K0 2K0 C69
220N 220N
3
18K
18K
R158
R155
5
6
3
2
+
-
4
8
V-
V+
4
8
V-
V+
C59
33
100N C60 C58
7
U62
47P
1
R152
18K
U62
4
47P
18K
R159
R153
LMC662
LMC662
+5V
SMPIN
R265
2K2 TP20 TP19
1
U43
74ACT14
5
2
5
3
2
1
5
3
2
1
C317 C315
100N 100N
6
-IN
-IN
FFTCK
+IN
+IN
Vref
Vref
U56
U55
R268
CS/SHDN
CS/SHDN
2K2
ADS8320
ADS8320
DCLOCK
DCLOCK
DOUT
VCC
DOUT
VCC
GND
GND
4
6
7
8
4
6
7
8
U43
74ACT14
+5V
+5V
C318 C316
100N 100N
7
8
R274 R269
4K7 4K7
VCC
VCC
8
6
4
2
17
15
13
11
1
1
1
1
U45
U45
U45
U45
U45
U45
U45
U45
19
19
19
19
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
74LCX244
3
5
7
9
12
14
16
18
9
SININ
COSIN
1K
1K
R301
R302
Number:
Document
DESCRIPTION:
10
950 1079 000 SE

Revision:
D
SHEET:
11
INGRESSO DOPPLER CW
11
OF:
16
1 2 3 4 5 6 7 8 9 10 11
C37
1N2
1500P
C71
R125 R172
5K6 C38
R122 4K7 C65
TP17
100N
100N R167
33
E
+5V
33
+5V
R121 8
U53
R178 4
U66
U43
5K6
2
V+ LF353
-
1
2K2
6
V+ TL064
74ACT14 -
VCC 3 7
+ REC
ACLKX0 5 6 V-
5
+ C52
V-
4 220N
+5V
R171
C297
11
R271
100N
4K7
2K2
R132
R128
1K00
R168
U66
12K
12K
4
R267
U43 U41 TL064
C299
V+
13
100N
-
10
74ACT14 14
AD1866 12
RECOUT
+
ADLL 9 8 1 VL VS 9 V-
4 CLK VS 15
11
R275
22K
R141
2K2
2 LL VBL 16
VOL 14
D
3 DL NRL 13
U43
74ACT14 6 8
LR VBR
11 10 10
ADX0 VOR
5 DR NRR 11
R270
2K2
7 DGND AGND 12
C48
1500P
C51
1N2
C33 C32
U43 10U 10U
74ACT14
ADLR 13 12 R135 R140

5K6 4K7
R266
2K2
R129 8
U53
R134 4
U66
5K6 V+ LF353
C 6 - 2K2 V+ TL064
7 2 -
5 1 ADV
+
R137 V-
R133 3
+ C72
12K 33 V-
TP18
4 220N
-5V
R165
11
C47
4K7
R136
100N
1K00
R179
U66
12K
4
9
V+ TL064
-
8 ADVOUT
10
+
V- R173
11 33
22K
R180
-5V
C68
100N
A
837 0147 042 Rev.A
FORM:
USCITA AUDIO PER IL VTR
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 12 16

1 2 3 4 5 6 7 8 9 10 11
C312
R281
100N
C309
33
+5V
1U
F ADV
R283
10K
U52
74HCT4052
C323
U57 16 VCC
100N
4
R123 TL064 U40
C35
220N
V+ 1 0
2
VCC
-
2K2 1 5 1 COM 3 74ACT14
ADVIN 3
+ 2 2 5 6
C49
10U
C30
V- VOL_CLK
47U
4 3 +5V
R126
11
R262
7
22K
VEE
R119
2K2
C26
100N
6
R303
INH U65
33
R130
10
1K
R163 A TPA0211
-5V
9
U40
33
B 3
10K
74ACT14 R166 VDD
C43
100N
8 R120
C29
GND
100N
9 8 1K8
E VOL_DIN 1 5
IN VO+ SPKR1
R170 4
U63 33
+5V
R264
10K
9
V+ TL064 2 SHTDWN VO- 8 SPKN1
2K2
LINEOUTADV -
8 U57
10 U44 4
C64
+
U40 4 BYPASS SE/BTL 6
LM1972 TL064
1U
V- V+
74ACT14
9 - C67
11 VDD1 13 8
470N 7 GND
10
VOL_LDSH 11 10 9 CLOCK GND1 3 +
V-
VSS1 18
11
R263
11 DATA-IN
2K2
12 DATA-OUT VDD2 15
U40 19
GND2
74ACT14 10 7
LOAD/SHIFT VSS2
VTRAUDIO 1 2
4 IN1 OUT1 2
R252
2K2
20 IN2 OUT2 17
C324
100N
D 1 GND_AC GND_AC 16
VCC
5 GND_AC GND_AC 14
6 GND_AC GND_LOGIC 8
U57
C50
R261
U40 4
C63
47U
TL064
2K2
1U
V+
74ACT14 6 -
7
PCAUDIO 3 4 5
+
V-
U64
11
TPA0211
R164 3 VDD
C44
100N
1K8
1 5
C319
IN VO+ SPKR2
R138
1U
R157 2 SHTDWN VO- 8 SPKN2

10K
R131
REC
33
33
+5V
4 6
R294
BYPASS SE/BTL
C61 C66
10K
U52 100N 7
470N GND
C
74HCT4052 -5V
4
U57 16 VCC R156 4
U63
R124 TL064 10K TL064
C36
220N
V+ 12 0
V+
13 -
2 -
2K2 14 14 1 COM 13 1 LINEINADV
RECIN 12
+ 15
3
+
U40
2
10U
C31
V- V- 74ACT14
11 3
R127
11 11 13 12
7 SPKOFF
22K
VEE
6 R139
R304
INH
10 10K
1K
A
9 B
R161 8 GND
10K
R160 4
U63
R169 U63
C313
4 R293 10K TL064

100N
V+
10K V+ TL064 13 -
B LINEOUTREC 6 - 33 14 LINEINREC
7 12
-5V
+
5 V-
+
V-
11
11
R162
33
-5V
C62
100N
A
837 0147 042 Rev.A
FORM:
USCITA AUDIO PER GLI ALTOPARLANTI E PC AUDIO IN/OUT
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 13 16

1 2 3 4 5 6 7 8 9 10 11
F U59
74LCX138
LCA0 1 A Y0 15
LCA1 2 B Y1 14
LCA2 3 C Y2 13
Y3 12
Y4 11
LCRW 6 G1 Y5 10
4 G2A Y6 9
LSGR 5 G2B Y7 7
+3V3
U51
E 74LCX244
R278
R279
R282
R285
R288
R287
100
100
100
100
100
100
1 1G
2 2 2 2 2 2 19 2G
2 1A1 1Y1 18 LC0
4 1A2 1Y2 16 LC1
6 1A3 1Y3 14 LC2
8 1A4 1Y4 12 LC3
11 2A1 2Y1 9 LC4
13 2A2 2Y2 7 LC5
15 2A3 2Y3 5
17 2A4 2Y4 3
R277
R280
R284
R286
R290
R289
100
100
100
100
100
100
D U60
R295
1K00
74LCX244
1 1G
19
2G
LCA0 2 1A1 1Y1 18 LA0

LCA1 4 1A2 1Y2 16 LA1
LCA2 6 1A3 1Y3 14 LA2
LCA3 8 1A4 1Y4 12 LA3
LCA4 11 2A1 2Y1 9 LA4
LCRW 13 2A2 2Y2 7 LRW
15 2A3 2Y3 5
17 2A4 2Y4 3
C
U50
74LCX245
LSDOP 19 G
LCRW 1 T/R
LD0 2 A1 B1 18 LC0
LD1 3 A2 B2 17 LC1
LD2 4 A3 B3 16 LC2
LD3 5 A4 B4 15 LC3
LD4 6 A5 B5 14 LC4
LD5 7 A6 B6 13 LC5
LD6 8 A7 B7 12 LC6
LD7 9 A8 B8 11 LC7
B
U49
74LCX245
LSDOP 19 G
LCRW 1 T/R
LD8 2 A1 B1 18 LC8
LD9 3 A2 B2 17 LC9
LD10 4 A3 B3 16 LC10
LD11 5 A4 B4 15 LC11
LD12 6 A5 B5 14 LC12
LD13 7 A6 B6 13 LC13
LD14 8 A7 B7 12 LC14
LD15 9 A8 B8 11 LC15
A
837 0147 042 Rev.A
FORM:
CONFIGURAZIONE SCHEDA E BUS CPU
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 14 16

1 2 3 4 5 6 7 8 9 10 11
+1V5 +1V8A +1V8B +1V8C
C244 C246 C233 C242 C225 C226 C216 C218 C268 C262 C258 C260 C252 C253 C248 C250 C157 C159 C152 C154 C147 C149 C161 C145 C238 C240 C222 C227 C213 C214 C207 C210
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
F
CORE VIRTEX2 CORE SPARTAN2 CORE SPARTAN2 CORE SPARTAN2
+1V5 +1V8A +1V8B +1V8C
C187 C211 C235 C288 C198 C263 C270 C190 C175 C171 C142 C134 C284 C272 C201 C182
470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N
CORE VIRTEX2 CORE SPARTAN2 CORE SPARTAN2 CORE SPARTAN2
E +3V3 +3V3 +3V3 +3V3
I/O VIRTEX2 I/O SPARTAN2 I/O SPARTAN2 I/O SPARTAN2
+3V3 +3V3 +3V3 +3V3
D

+3V3 +3V3 +3V3 +3V3
470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N 470N
+3V3AUX
C
C285 C247 C186 C184 C289 C229 C188 C287

47N 47N 47N 47N 47N 47N 47N 47N
AUX VIRTEX2
+1V26 +3V3_DSP
C88 C90 C114 C119 C110 C111 C107 C108 C99 C94 C97 C118 C91 C116 C117 C105 C112 C100 C101 C95
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
B
CORE DSP I/O DSP
+1V26 +3V3_DSP
C93 C92 C115 C113 C96 C89 C106 C104

470N 470N 470N 470N 470N 470N 470N 470N
CORE DSP I/O DSP
A
837 0147 042 Rev.A
FORM:
BYPASS FPGA E DSP
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 15 16

1 2 3 4 5 6 7 8 9 10 11
COMPONENTI NON MONTATI : ALIMENTAZIONI IMPLICITE (1079000D_2)

-----------------------
C166 EQUIP_LEVEL 2 NET: +1V26

C230 EQUIP_LEVEL 2 ----------
C283 EQUIP_LEVEL 2 U9.A10 U9.C3 U9.D6 U9.K4 U9.R4 U9.U6
C294 EQUIP_LEVEL 2 U9.A4 U9.C7 U9.F17 U9.L17 U9.U10 U9.V18
C7 EQUIP_LEVEL 2 U9.A9 U9.D11 U9.F4 U9.L20 U9.U11 U9.V3
R12 EQUIP_LEVEL 2 U9.B19 U9.D14 U9.K1 U9.L4 U9.U14 U9.W19
F R20 EQUIP_LEVEL 2 U9.B2 U9.D15 U9.K17 U9.R17 U9.U15 U9.W2
R205 EQUIP_LEVEL 2 U9.C18 U9.D5
R218 EQUIP_LEVEL 2
R22 EQUIP_LEVEL 2 NET: GND
R223 EQUIP_LEVEL 2 --------
R228 EQUIP_LEVEL 2 UP1.27 U9.M12 U25.J14 U33.C3 U34.J10 U36.J9
+3V3 R237 EQUIP_LEVEL 2 UP1.46 U9.M17 U25.J9 U33.G11 U34.J11 U36.K10
R238 EQUIP_LEVEL 2 UP2.12 U9.M4 U25.K10 U33.G12 U34.J12 U36.K11
R248 EQUIP_LEVEL 2 UP2.34 U9.M9 U25.K11 U33.J10 U34.J13 U36.K12
R250 EQUIP_LEVEL 2 UP3.16 U9.N17 U25.K12 U33.J11 U34.J14 U36.K13
R253 EQUIP_LEVEL 2 UP4.16 U9.N4 U25.K13 U33.J12 U34.J9 U36.K14
R260 EQUIP_LEVEL 2 UP5.16 U9.P17 U25.K14 U33.J13 U34.K10 U36.K9
C109 C120 C103 C121 C122 C102 C176 C177 C178 C74 R278 EQUIP_LEVEL 2 U1.12 U9.P19 U25.K9 U33.J14 U34.K11 U36.L10
R279 EQUIP_LEVEL 2 U1.34 U9.P4 U25.L10 U33.J9 U34.K12 U36.L11
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
R282 EQUIP_LEVEL 2 U2.12 U9.T17 U25.L11 U33.K10 U34.K13 U36.L12
R285 EQUIP_LEVEL 2 U2.34 U9.T4 U25.L12 U33.K11 U34.K14 U36.L13
R287 EQUIP_LEVEL 2 U4.10 U9.U13 U25.L13 U33.K12 U34.K9 U36.L14
R288 EQUIP_LEVEL 2 U6.12 U9.U17 U25.L14 U33.K13 U34.L10 U36.L16
R44 EQUIP_LEVEL 2 U7.34 U9.U8 U25.L9 U33.L10 U34.L13 U36.M10
R45 EQUIP_LEVEL 2 U8.12 U9.U9 U25.M10 U33.L11 U34.L14 U36.M11
+3V3 R66 EQUIP_LEVEL 2 U8.34 U9.W1 U25.M11 U33.L12 U34.L9 U36.M12
U9.A1 U9.W11 U25.M12 U33.L13 U34.M10 U36.M13
U9.A11 U9.W16 U25.M13 U33.L14 U34.M11 U36.M14
E U9.A14 U9.W20 U25.M14 U33.L16 U34.M12 U36.M16
U9.A19 U9.W5 U25.M16 U33.L7 U34.M13 U36.M7
U9.A2 U9.Y1 U25.M7 U33.L9 U34.M14 U36.M9
C204 C203 C271 C124 C200 C199 C123 C85 C81 C80 U9.A20 U9.Y13 U25.M9 U33.M10 U34.M9 U36.N10
U9.B1 U9.Y19 U25.N10 U33.M11 U34.N10 U36.N11
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
U9.B15 U9.Y2 U25.N11 U33.M12 U34.N11 U36.N12
U9.B20 U9.Y20 U25.N12 U33.M13 U34.N12 U36.N13
U9.B4 U10.12 U25.N13 U33.M14 U34.N13 U36.N14
U9.C6 U10.34 U25.N14 U33.M16 U34.N14 U36.N9
U9.C8 U11.12 U25.N9 U33.M7 U34.N9 U36.P10
U9.C9 U11.34 U25.P10 U33.M9 U34.P10 U36.P11
U9.D13 U12.10 U25.P11 U33.N10 U34.P11 U36.P12
U9.D17 U13.10 U25.P12 U33.N11 U34.P12 U36.P13
+3V3 U9.D4 U14.10 U25.P13 U33.N12 U34.P13 U36.P14
U9.D8 U15.10 U25.P14 U33.N13 U34.P14 U36.P9
U9.E17 U16.10 U25.P9 U33.N14 U34.P9 U36.T11
U9.E2 U17.12 U25.T11 U33.N9 U34.W19 U36.T12
U9.E4 U17.34 U25.T12 U33.P10 U34.W4 U36.Y20
U9.F19 U18.12 U25.Y20 U33.P11 U34.Y20 U36.Y3
C277 C55 C133 C265 C73 C264 C132 C98 C131 C86 U9.G17 U18.34 U25.Y3 U33.P12 U34.Y3 U37.12
U9.G4 U19.12 U26.10 U33.P13 U35.12 U37.34
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
U9.H17 U19.34 U27.10 U33.P14 U35.34 U38.12
U9.H4 U21.12 U29.12 U33.P9 U36.A1 U38.34
U9.J10 U21.34 U29.34 U33.T11 U36.A22 U39.12
U9.J11 U25.A1 U30.12 U33.T12 U36.AA2 U39.34
U9.J12 U25.A22 U30.34 U33.Y20 U36.AA21 U40.7
D U9.J4 U25.AA2 U31.12 U33.Y3 U36.AB1 U43.7
U9.J9 U25.AA21 U31.34 U34.A1 U36.AB22 U45.10
U9.K10 U25.AB1 U32.12 U34.A22 U36.B2 U46.12
+3V3 U9.K11 U25.AB22 U32.34 U34.AA2 U36.B21 U46.34
U9.K12 U25.B2 U33.A1 U34.AA21 U36.C20 U48.10
U9.K2 U25.B21 U33.A22 U34.AB1 U36.C3 U49.10

U9.K20 U25.C20 U33.AA2 U34.AB22 U36.G11 U50.10

U9.K9 U25.C3 U33.AA21 U34.B2 U36.G12 U51.10
U9.L10 U25.G11 U33.AB1 U34.B21 U36.J10 U58.12
C130 C129 C301 C128 C127 C298 C279 C126 C278 C205 U9.L11 U25.G12 U33.AB22 U34.C20 U36.J11 U58.34
U9.L12 U25.J10 U33.B2 U34.C3 U36.J12 U59.8
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
U9.L9 U25.J11 U33.B21 U34.D19 U36.J13 U60.10
U9.M10 U25.J12 U33.C20 U34.D4 U36.J14 U61.10
U9.M11 U25.J13
NET: +1V5
---------
U34.F17 U34.G16 U34.H16 U34.R7 U34.T7 U34.U17
U34.F6 U34.G7 U34.H7 U34.T15 U34.T8 U34.U6
+3V3 U34.G15 U34.G8 U34.R16 U34.T16
NET: VCC
--------
UP2.44 UP3.32 U4.20 U13.20 U40.14 U43.14
C170 C307 C168 C306 C165 C305 C304 C164 C300 C163 NET: +3V3
C ---------
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
UP1.37 U7.33 U16.20 U27.20 U35.33 U48.20
UP4.32 U8.11 U17.11 U29.11 U37.11 U49.20
UP5.32 U8.33 U17.33 U29.33 U37.33 U50.20
U1.11 U10.11 U18.11 U30.11 U38.11 U51.20
U1.33 U10.33 U18.33 U30.33 U38.33 U58.11
U2.11 U11.11 U19.11 U31.11 U39.11 U58.33
U2.33 U11.33 U19.33 U31.33 U39.33 U59.16
U6.11 U12.20 U21.11 U32.11 U45.20 U60.20
+3V3 U6.33 U14.20 U21.33 U32.33 U46.11 U61.20
U7.11 U15.20 U26.20 U35.11 U46.33
ALIMENTAZIONI MODIFICATE
------------------------
C308 C314 C151 C320 C321 C141 C140 C139 C322
NET: +3V3_DSP
47N 47N 47N 47N 47N 47N 47N 47N 47N
-------------
U9.A17 U9.D1 U9.J2 U9.U12 U9.V13 U9.W3
U9.B13 U9.D16 U9.M18 U9.U16 U9.V15 U9.W9
U9.B3 U9.D19 U9.R1 U9.U5 U9.V19 U9.Y17
U9.B8 U9.F3 U9.R18 U9.U7 U9.W12 U9.Y7
U9.C10 U9.H18 U9.T3
NET: +3V3AUX
VCC ------------
B U34.A12 U34.AA22 U34.B1 U34.B22 U34.L1 U34.M22
U34.AA1 U34.AB11
NET: +1V8A
C76 C125 C82 C84 C83 ----------
U36.E18 U36.G15 U36.H16 U36.R7 U36.T7 U36.U6
47N 47N 47N 47N 47N U36.E5 U36.G16 U36.H7 U36.T15 U36.T8 U36.V18
U36.F17 U36.G7 U36.R16 U36.T16 U36.U17 U36.V5
U36.F6 U36.G8
NET: +1V8B
----------
U25.E18 U25.G15 U25.H16 U25.R7 U25.T7 U25.U6
U25.E5 U25.G16 U25.H7 U25.T15 U25.T8 U25.V18
U25.F17 U25.G7 U25.R16 U25.T16 U25.U17 U25.V5
U25.F6 U25.G8
NET: +1V8C
----------
U33.E18 U33.G15 U33.H16 U33.R7 U33.T7 U33.U6
U33.E5 U33.G16 U33.H7 U33.T15 U33.T8 U33.V18
U33.F17 U33.G7 U33.R16 U33.T16 U33.U17 U33.V5
U33.F6 U33.G8
A
837 0147 042 Rev.A
FORM:
BYPASS COMPONENTI DIGITALI
SHEET DESCRIPTION:
by EpD Number: 950 1079 000 SE D 16 16

1 2 3 4 5 6 7 8 9 10 11
P1 P3 P2 +2V2
L10
15U
B1 A1 VMRW B1 A1 VMACK VCC B1 A1
B2 A2 VMMODE B2 A2 TCLK B2 A2
B3 A3 VMA12 B3 A3 VMA13 GRA0 B3 A3 GRA1
C293
F 47U
B4 A4 VMA14 B4 A4 VMA15 R160 GRA2 B4 A4 GRA3
B5 A5 VMA16 B5 A5 VMA17 10K GRA4 B5 A5 GRA5
B6 A6 VMA18 B6 A6 VMA19 GRA6 B6 A6 GRA7
B7 A7 B7 A7 VID_HSYNC B7 A7 VID_VBLANK
A
B8 A8 VMA20 B8 A8 VMA21 W78 B8 A8 DASP_S
B9 A9 B9 A9 B9 A9
B
LINEINADV LINEINREC VMA22 VMA23 SIDE_CS3 SIDE_CS1
LINEOUTADV B10 A10 LINEOUTREC VMA24 B10 A10 VMA25 SIDE_A2 B10 A10 SIDE_A0
B11 A11 VMA26 B11 A11 VMA27 PDIAG_S B11 A11 SIDE_A1
DTR1 B12 A12 DSR1 VMA28 B12 A12 VMA29 IOCS16 B12 A12 SIDE_INT
RTS1 B13 A13 RXD1 VMD0 B13 A13 VMD1 SIDE_AK B13 A13 SIDE_RDY
DCD1 B14 A14 CTS1 VMD2 B14 A14 VMD3 SIDE_IOW B14 A14 SIDE_IOR
TXD1 B15 A15 VMD4 B15 A15 VMD5 SIDE_DRQ B15 A15 SIDE_D0
B16 A16 VMD6 B16 A16 VMD7 SIDE_D15 B16 A16 SIDE_D1
PANPOS B17 A17 VMD8 B17 A17 VMD9 SIDE_D14 B17 A17 SIDE_D2
VMAUX0 B20 A20 VMD14 B20 A20 VMD15 SIDE_D11 B20 A20 SIDE_D5
E BUZZER B21 A21 B21 A21 SIDE_D10 B21 A21 SIDE_D6
TRKXA B22 A22 TRKXB B22 A22 SIDE_D9 B22 A22 SIDE_D7
TRKYA B23 A23 TRKYB 5V_SB B23 A23 SIDE_D8 B23 A23 HDRST
ENCRA B24 A24 ENCRB PS_ON B24 A24 CDOUTR B24 A24 CDOUTL
ENCLA B25 A25 ENCLB PWRBTN B25 A25 PHYSIO B25 A25 TBASE
ROW0 B26 A26 ROW1 B26 A26 ECG B26 A26 MOT0
ROW2 B27 A27 ROW3 B27 A27 POS B27 A27 MOT1
ROW4 B28 A28 ROW5 B28 A28 B28 A28 TIMING
ROW6 B29 A29 ROW7 B29 A29 ESCAN B29 A29 PROBE
ROW8 B30 A30 ROW9 B30 A30 B30 A30 GRA8
ROW10 B31 A31 ROW11 B31 A31 GRA9 B31 A31 GRA10
ROW12 B32 A32 ROW13 LSVID B32 A32 LSECG GRA11 B32 A32 GRA12
ROW14 B33 A33 ROW15 B33 A33 B33 A33 GRA13
COL0 B34 A34 COL1 B34 A34 VGA_LVN1 B34 A34 GRA14
COL2 B35 A35 COL3 B35 A35 VGA_LVP1 B35 A35 GRA15
COL4 B36 A36 COL5 B36 A36 B36 A36
COL6 B37 A37 COL7 B37 A37 VGA_LVN4 B37 A37 VGA_LVN3
D COL8 B38 A38 COL9 B38 A38 VGA_LVP4 B38 A38 VGA_LVP3
COL10 B39 A39 COL11 B39 A39 B39 A39
COL12 B40 A40 COL13 B40 A40 VGA_LVN2 B40 A40 VGA_LVN0
COL14 B41 A41 COL15 B41 A41 VGA_LVP2 B41 A41 VGA_LVP0
VMA0 B42 A42 VMA1 B42 A42 B42 A42

VMA2 B43 A43 VMA3 LSPS B43 A43 LSSCAN B43 A43
VMA4 B44 A44 VMA5 LSDOP B44 A44 LSGR B44 A44 +3V3
VMA6 B45 A45 VMA7 LSGW B45 A45 LSCNT B45 A45
B46 A46 LCA0 B46 A46 LCA1 B46 A46
4 Y1
VMA8 B47 A47 VMA9 LCA2 B47 A47 LCA3 B47 A47 40MHZ
VMA10 B48 A48 VMA11 LCA4 B48 A48 LCRW B48 A48 VCC
B49 A49 B49 A49 B49 A49 1 OE OSC 3 +3V3
VCC
L12 GND U108
15U 74LVC1GU04
B50 A50 B50 A50 VCCB B50 A50 5
B
2
VMAS B51 A51 VMDS
C294 B51 A51 B51 A51 W77 2 VCC 4 D40M
A
B52 A52 47U B52 A52 B52 A52 33
VMBH VMBL LC0 LC1
B53 A53 LC2 B53 A53 LC3 B53 A53 R168
C
B54 A54 B54 A54 B54 A54
-6V
LC4 LC5
B55 A55 B55 A55 +12V B55 A55
LC6 LC7
+6V
B56 A56 LC8 B56 A56 LC9 B56 A56

B57 A57 LC10 B57 A57 LC11 B57 A57
+3V3 L13 B58 A58 LC12 B58 A58 LC13 MM_SO B58 A58 MM_CS
B59 A59 LC14 B59 A59 LC15 MM_HOLD B59 A59 MM_WP
22U
B60 A60 B60 A60 MM_SI B60 A60 MM_SCK
C297
47U
+3V3
+3V3 +3V3 +3V3
3
4
2
1
7
5
6
8
8
7
5
6
3
4
2
1
B
U68 U54 U50 U63
10K 10K 10K 10K
U115 U114 U113 U112

6
5
7
8
2
4
3
1
1
2
4
3
6
5
7
8
100 100 100 100
COL0 8 1 ICOL0 COL4 8 1 ICOL4 COL8 8 1 ICOL8 COL12 8 1 ICOL12
+3V3
5
6
7
8
1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P
C310 C311 C312 C313 C306 C307 C308 C309 C302 C303 C304 C305 C298 C299 C300 C301 4K7 C76 C75 C69 C70
U43 10N 10N 10N 10N
U119 U118 U117 U116
100 100 100 100
4
3
2
1
IROW0 1 8 ROW0 IROW4 1 8 ROW4 IROW8 1 8 ROW8 IROW12 1 8 ROW12 ENCLA IENCLA
4 5
2 7 2 7 2 7 2 7
A IROW1 ROW1 IROW5 ROW5 IROW9 ROW9 IROW13 ROW13 ENCLB 3 6 IENCLB
IROW2 3 6 ROW2 IROW6 3 6 ROW6 IROW10 3 6 ROW10 IROW14 3 6 ROW14 ENCRA IENCRA
837 0147 042 Rev.A
2 7
IROW3 4 5 ROW3 IROW7 4 5 ROW7 IROW11 4 5 ROW11 IROW15 4 5 ROW15 ENCRB IENCRB
1 8
FORM:
1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P 1000P
10K
C326 C328 C330 C331 C322 C323 C324 C325 C318 C319 C320 C321 C314 C315 C316 C317 U42

"7300" PROCESSORS BOARD
by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500250 Number: 950 1080 000 SE H 1 10
1 2 3 4 5 6 7 8 9 10 11
470 470
1U 1U P5
R173 R172
C329 C327 1 2
LINEINADV AUXAL LINEINREC AUXAR
3 4
F CDOUTL CDOUTR J6
470 1U 470 1U
1 2
R127 C250 R128 C251
3 4
L11 L9 5 6
HDRST 7 8
1U 1U
VCCB VCCB PIDE_D7 9 10 PIDE_D8
PIDE_D6 11 12 PIDE_D9
P7
C259 C151 P8 P9 C249 C169 P6
470U 470U PIDE_D5 13 14 PIDE_D10
470U 470U
1 2 1 2 1 2 1 2 W55 PIDE_D4 15 16 PIDE_D11
PCI_CLK2 3 4 3 4 R 3 4 B 5V_SB 3 4 PC_RESET PIDE_D3 17 18 PIDE_D12
5 6 5 6 HSYNC 5 6 G PS_ON 5 6 PIDE_D2 19 20 PIDE_D13
249
PCI_CLKO 7 8 PCI_CLK1 7 8 VSYNC 7 8 DDCK PWRBTN 7 8 PIDE_D1 21 22 PIDE_D14
9 10 9 10 9 10 9 10
BT1 23 24
DDDA R174 PIDE_D0 PIDE_D15
PCI_GNT2 11 12 11 12 4K7 11 12 11 12 ACTLED 25 26
PCI_REQ2 13 14 PCI_GNT1 13 14 R151 13 14 13 14 SPEEDLED PIDE_DRQ 27 28
PCI_REQ1 15 16 15 16 15 16 15 16 PIDE_IOW 29 30
PCI_GNT0 17 18 17 18 17 18 17 18 PIDE_IOR 31 32 W41
E
19 20 19 20 19 20 USB_OVCR 19 20 PIDE_RDY 33 34
21 22 PCI_REQ0 21 22 21 22 21 22 PIDE_AK 35 36 W34
IOCS16
PCI_AD0 23 24 23 24 VGA_LVN4 23 24 23 24 PIDE_INT 37 38
25 26 25 26 25 26 25 26 39 40
W33
PCI_AD1 PCI_AD2 VGA_LVP4 SIDE_CS3 PIDE_A1 CBLID_P
PCI_AD4 27 28 PCI_AD3 27 28 27 28 SIDE_CS1 27 28 DASP_S PIDE_A0 41 42 PIDE_A2
PCI_AD6 29 30 PCI_AD5 29 30 VGA_LVN2 29 30 VGA_LVP3 SIDE_A2 29 30 PIDE_CS3 VCC PIDE_CS1 43 44 PIDE_CS3
PCI_CBE0 31 32 PCI_AD7 31 32 VGA_LVP2 31 32 VGA_LVN3 SIDE_A0 31 32 PIDE_CS1 F2 DASP_P 45 46 VCC
PCI_AD8 33 34 PCI_AD9 33 34 IOCS16 33 34 33 34 47 48
35 36 35 36 VGA_LVP0 35 36 VGA_LVP1 PDIAG_S 35 36 PIDE_A2 C134 49 50
PCI_AD10 37 38 AUXAL 37 38 VGA_LVN0 37 38 VGA_LVN1 SIDE_A1 37 38 PIDE_A0 47U 680
39 40 39 40 39 40 39 40
DS2
PCI_AD11 SIDE_INT PIDE_A1 Hard Disk
41 42 41 42 41 42 41 42 DASP_P 2 3
R74
PCI_AD12 AUXAR
PCI_AD13 43 44 43 44 43 44 SIDE_AK 43 44 PIDE_INT
45 46 45 46 45 46 VCC 45 46 DASP_S 1 4 GIALLO
PCI_AD14 LINEOUTADV SIDE_RDY PIDE_AK
PCI_AD15 47 48 47 48 47 48 SIDE_IOR 47 48 PIDE_RDY R123 HARD DISK ACTIVITY
BAV23
49 50 49 50 W68 49 50 49 50 10K
PCI_CBE1 LINEOUTREC CR3
VCC
51 52 51 52 51 52 R130 SIDE_IOW 51 52 PIDE_IOR P11
D PCI_PAR 53 54 PCI_SERR 53 54 53 54 10K
SIDE_DRQ 53 54 PIDE_IOW 1 26 CF_CD1
PCI_PERR 55 56 55 56 55 56 DENSEL SIDE_D15 55 56 PIDE_DRQ
SIDE_D3 2 27 SIDE_D11
PCI_PME 57 58 57 58 57 58 SIDE_D0 57 58 PIDE_D15 3 28
SIDE_D4 SIDE_D12
59 60 PCI_DEVSEL 59 60 59 60 HDSEL SIDE_D14 59 60 PIDE_D0 4 29

SIDE_D5 SIDE_D13
PCI_TRDY 61 62 61 62 61 62 SIDE_D1 61 62 PIDE_D14
PCI_IRDY 63 64 PCI_STOP 63 64 RXD2 63 64 DIR SIDE_D13 63 64 PIDE_D1 VCC
PCI_FRAME 65 66 65 66 65 66 65 66
SIDE_CS1 7 32 SIDE_CS3
67 68 67 68 RTS2 67 68 SIDE_D2 67 68 PIDE_D13 8 33
PCI_AD16 69 70 PCI_CBE2 69 70 DTR2 69 70 STEP SIDE_D12 69 70 PIDE_D2
R124
9 34 SIDE_IOR
PCI_AD17 71 72 71 72 DCD2 71 72 DSKCHG SIDE_D3 71 72 PIDE_D12 10K
10 35
VCC
SIDE_IOW
PCI_AD19 73 74 PCI_AD18 73 74 DSR2 73 74 RDATA SIDE_D11 73 74 PIDE_D3 11 36 CF_WE
PCI_AD20 75 76 USB0 75 76 CTS2 75 76 WP SIDE_D4 75 76 PIDE_D11 C247 C245 12 37 SIDE_INT
77 78 77 78 77 78 77 78
VCC
PCI_AD22 PCI_AD21 TXD2 TRK0 SIDE_D10 PIDE_D4 13 38
470N 47U
PCI_AD23 79 80 USB1 79 80 RI2 79 80 INDEX SIDE_D5 79 80 PIDE_D10 14 39
PCI_AD24 81 82 PCI_CBE3 81 82 81 82 81 82
15 40 W60 R125
83 84 83 84 RXD1 83 84 DRV SIDE_D9 83 84 PIDE_D5 16 41 HDRST 10K
PCI_AD25 85 86 PCI_AD26 85 86 RTS1 85 86 MOT SIDE_D6 85 86 PIDE_D9 17 42 SIDE_RDY
W61
C PCI_AD28 87 88 USB0 87 88 DTR1 87 88 WDATA SIDE_D8 87 88 PIDE_D6
SIDE_A2 18 43 SIDE_DRQ
PCI_AD27 89 90 PCI_AD29 89 90 DCD1 89 90 WGATE 89 90 CBLID_P
SIDE_A1 19 44 SIDE_AK
PCI_AD30 91 92 USB1 91 92 DSR1 91 92 MS_CLK LAN_RXD 91 92 PIDE_D8
SIDE_A0 20 45 DASP_S
PCI_RST 93 94 PCI_AD31 93 94 CTS1 93 94 MS_DAT LAN_RXD 93 94 SIDE_D7 21 46
W62
SIDE_D0 PDIAG_S
PCI_INTC 95 96 95 96 TXD1 95 96 KB_CLK LAN_TXD 95 96 PIDE_D7
PCI_INTA 97 98 PCI_INTB 97 98 RI1 97 98 KB_DAT LAN_TXD 97 98 HDRST W63 SIDE_D2 23 48 SIDE_D9
Compact Flash
99 100 99 100 99 100 99 100
IOCS16 24 49 SIDE_D10
CF_CD2 25 50 VCC
VCC
X1 X2 X3 X4 10K
6
5
8
7
2
1
3
4
R126
J7
+3V3
U99 U100
LAN 1K2 1K2 VCC
J10
VCC
U86 W80 1
USB-0 J2
3
4
1
2
7
8
6
5
TPS2042 2
B INDEX
2 IN A B 3
1 2 3 4 5 6 7 8
1 2 3 4 75 R68 DRV 4
8 OC1 OUT1 7
T1 5
3 EN1 C148 C147 USB0
H1012
75 R69 DSKCHG 6
47N 5 OC2 10
47U 10N 7
USB0 LAN_TXD 16
4K7 4 EN2 OUT2 6
75 R70 8
C150 R87 14 12
12
9
1 GND
LAN_TXD 15 MOT 10
11
11
DIR 12
LAN_RXD 1 7 R54 13
VCC 75 STEP 14
5
15
C93
WDATA 16
USB-1 J1 LAN_RXD 2 6 10N
17
R86
WGATE 18
10K 3 19
A 1 2 3 4 C104
USB_OVCR USB1 TRK0 20
100N
837 0147 042 Rev.A
DS1 R53 +3V3 21

C133 C130 USB1
RO/VE 3MM 820 WP 22
FORM:
47U 10N
ACTLED V 23
Link Activity RDATA 24
DS1 R52 +3V3
25
RO/VE 3MM 820
HDSEL 26
SPEEDLED R
Floppy Disk
Link Speed 10/100 Mbit/sec
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 2 10

1 2 3 4 5 6 7 8 9 10 11
U95 U95 U95 U95

XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4
BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

BANK 0 BANK 1
F C21 M21 AB19 AA11 V5 L2

PCI_IRDY
B4 F12 DBG_SA9 IO IO CPU_D9 EA14 IO/DOUT IO/GCLK7S DTRA VMAS IO IO
VMA25 IO IO/GCLK3P CPU_CLKOUT PCI_FRAME
A4 F13 DBG_SA7 C22 IO IO M20 CPU_D15 FPGA_INIT AA19 IO/INIT_B IO/GCLK6P Y11 TB44 VMDS U5 IO IO L3
33 R140
VMA26 IO IO/GCLK2S EA2
E18 M19 ED0 V18 W11 Y2 L4
C4 E12 EA12 IO/VRP2 IO CPU_D10 IO/D0 IO/GCLK5S DSRA EA19 IO/VRN6 IO PCI_AD21
VMA27 IO IO/GCLK1P AWE
F18 M18 ED1 V17 V11 Y1 L5
C5 D12 DBG_SD4 IO/VRN2 IO CPU_D5 IO/D1 IO/GCLK4P MNYIRQ EA20 IO/VRP6 IO PCI_PAR
VMA28 IO IO/GCLK0S EA3 ED[0:31]
D21 M17 ED2 W18 U11 V4 K1
B5 C12 DBG_SA6 IO IO/VREF3 CPU_D4 IO/D2/ALT_VRP4 IO DCDA VMBH IO IO/VREF7 PCI_GNT2
VMA29 IO/VRP0 IO LCRW
D22 N17 ED3 Y18 U10 V3 K2
A5 B12 DBG_SA5 IO/VREF2 IO CPU_D12 IO/D3/ALT_VRN4 IO/VREF5 RIA VMBL IO/VREF6 IO PCI_REQ2
VMD0 IO/VRN0 IO/VREF1 LC0
DBG_SA8 E19 IO IO N22 CPU_D8 EA15 AA18 IO/VREF4 IO AB10 DSP_EINT4 VMA0 W2 IO IO K3 PCI_CBE2
VMD1 D6 IO/VREF0 IO A13 LC1
C6 B13 TB53 E20 IO IO N21 CPU_A1 LINK0 AB18 IO IO AA10 DSP_EINT5 VMA1 W1 IO IO K4 PCI_CBE3
VMD2 IO IO LC2
E21 N20 W17 Y10 U4 L6 PCI_AD16
B6 C13 DBG_SA4 IO IO CPU_D14 LINK1 IO/VRP4 IO ARDY VMA2 IO IO
VMD3 IO IO LC3
E22 N19 Y17 W10 U3 K6 PCI_AD17
A6 D13 DBG_SA3 IO IO CPU_D2 LINK2 IO/VRN4 IO ED27 VMA3 IO IO
VMD4 IO IO LC4
F19 N18 AA17 V10 V2 K5 PCI_AD18
E7 E13 DBG_SD1 IO IO CPU_D11 LINK3 IO IO ED8 VMA4 IO IO
VMD5 IO IO LC5
F20 P18 AB17 V9 V1 J5 PCI_AD19
E8 E14 DBG_SD8 IO IO CPU_D6 CPU_RW IO IO/VREF5 ED9 VMA5 IO IO
VMD6 IO IO/VREF1 LC6
F21 P22 V16 AB9 U2 J1 PCI_AD20
D7 A14 DBG_SA2 IO IO/VREF3 CPU_A2 CPU_SIZ0 IO IO ED10 VMA6 IO IO/VREF7
VMD7 IO IO LC7
F22 P21 V15 AA9 U1 J2 PCI_AD21
C7 B14 DBG_SA1 IO/VREF2 IO CPU_A19 DCDB IO IO ED11 VMA7 IO/VREF6 IO
VMD8 IO/VREF0 IO LC8
B7 C14 TB54 G18 IO IO P20 CPU_D13 CPU_FC0 W16 IO IO Y9 ED12 VMA8 T5 IO IO J3 PCI_AD22
VMD9 IO IO LC9
PCI_AD[0:31]
H18 P19 Y16 W9 R5 J4 PCI_AD23
A7 D14 DBG_SD3 IO IO CPU_A17 CPU_FC1 IO/VREF4 IO ED13 VMA9 IO IO
VMD10 IO IO LC10
G19 R22 AA16 AB8 T4 H1 PCI_AD24
D8 A15 DBG_SD9 IO IO CPU_A18 CPU_FC2 IO IO/VREF5 ED21 VMA10 IO IO
E VMD11 IO IO/VREF1 LC11
G20 R21 AB16 AA8 T3 H2 PCI_AD25
C8 B15 DBG_SD10 IO IO CPU_A3 CPU_FC3 IO IO ED24 VMA11 IO IO
VMD12 IO IO LC12
G21 R20 W15 Y8 PCI_AD0 T2 H3 PCI_AD26
B8 C15 DBG_SA0 IO IO CPU_A15 CPU_DSACK0 IO IO ED16 IO IO
VMD13 IO IO LC13
G22 R19 Y15 W8 PCI_AD1 T1 H4 PCI_AD27
A8 D15 DBG_LA23 IO IO CPU_A16 CPU_DSACK1 IO IO ED31 IO IO
VMD14 IO IO LC14
H19 R18 AA15 U9 PCI_AD2 R4 J6 PCI_AD28
E9 F14 DBG_SD11 IO IO/VREF3 CPU_D7 LINK4 IO IO ED14 IO IO/VREF7
VMD15 IO IO LC15
H20 P17 AB15 V8 PCI_AD3 R3 H5 PCI_AD29
F9 E15 DBG_SD12 IO/VREF2 IO CPU_D1 LINK5 IO IO ED15 IO/VREF6 IO
LSGR IO/VREF0 IO EA4
H21 T22 U14 AB7 PCI_AD4 R2 G1 PCI_AD30
D9 A16 DBG_LA22 IO IO CPU_A4 DTRB IO IO ED20 IO IO
LSGW IO IO EA5
H22 T21 V14 AA7 PCI_AD5 R1 G2 PCI_AD31
C9 B16 DBG_LA21 IO IO CPU_A5 DSRB IO/VREF4 IO ED23 IO IO
LSCNT IO IO EA6
J17 T20 W14 Y7 PCI_AD6 P6 G3
B9 C16 DBG_SD6 IO IO CPU_D3 LINK6 IO IO/VREF5 ED17 IO IO PCI_RST
LSDOP IO IO/VREF1 EA7
J18 T19 Y14 W7 PCI_AD7 P5 G4
PCI_AD[0:31]
A9 D16 DBG_SD5 IO IO CPU_A6 LINK7 IO IO ED30 IO IO VMACK
LSSCAN IO IO EA8
J19 U22 AA14 AB6 PCI_AD8 P4 F1
E10 E16 DBG_SD13 IO IO CPU_D0 ARE IO IO ED22 IO IO VMMODE
LSPS IO/VREF0 IO EA9
J20 U21 AB14 AA6 PCI_AD9 P3 F2
F10 E17 DBG_LA18 IO IO CPU_A12 AOE IO IO ED28 IO IO VMA12
LSECG IO IO EA10
J21 U20 U13 Y6 PCI_AD10 P2 F3
D10 A17 DBG_LA20 IO IO/VREF3 CPU_A13 AUXIN_0 IO/VREF4 IO ED18 IO IO/VREF7 VMA13
LSVID IO IO EA11
J22 U19 V13 W6 PCI_AD11 P1 F4
C10 B17 DBG_LA19 IO/VREF2 IO CPU_A8 AUXIN_1 IO IO EA18 IO/VREF6 IO VMA14
LCA0 IO IO DBG_SA16
K17 T18 W13 V7 PCI_AD12 N6 G5
B10 C17 DBG_SD7 IO IO CPU_A14 BE0 IO IO/VRP5 ED29 IO IO VMA15
LCA1 IO IO DBG_SD0
K18 U18 Y13 V6 PCI_AD13 N5 F5
A10 D17 DBG_SD14 IO IO CPU_A20 BE1 IO IO/VRN5 ED19 IO IO VMA16
LCA2 IO IO/VREF1 DBG_SD2
K19 V22 AA13 AB5 PCI_AD14 N4 E1
E11 A18 DBG_MEMR IO IO CPU_A7 BE2 IO IO ED26 IO IO VMA17
LCA3 IO/VREF0 IO/VRP1 DBG_SA15
K20 V21 AB13 AA5 PCI_AD15 N3 E2
F11 B18 DBG_MEMW IO IO CPU_A9 BE3 IO IO/VREF5 ED25 IO IO VMA18
LCA4 IO IO/VRN1 DBG_SA14
D K21 V20 U12 Y5 PCI_CBE0 N2 E3
D11 C18 DBG_IOR IO IO CPU_A11 REMOTE IO/VREF4 IO/D4/ALT_VRP5 ED4 IO IO VMA19
PCI_CLK2 IO/GCLK7P IO DBG_SA12
K22 V19 V12 W5 PCI_CBE1 N1 E4
C11 D18 DBG_IOW IO IO CPU_A22 EA16 IO IO/D5/ALT_VRN5 ED5 IO IO VMA20
TB39 IO/GCLK6S IO DBG_SA10
L17 W22 W12 AB4 M6 D1
B11 A19 DBG_SBHE IO IO/VREF3 CPU_A21 EA17 IO/GCLK3S IO/D6 ED6 IO IO/VREF7 VMA21
TCLK IO/GCLK5P IO DBG_SA13
L18 W21 Y12 AA4 PCI_SERR M5 D2

USB_OVCR A11 IO/GCLK4S IO B19

TB52 TB51 IO/VREF2 IO CPU_A0 DSPIOCLK IO/GCLK2P IO/D7 ED7 IO/VREF6 IO VMA22
L19 Y22 AA12 Y4 PCI_PERR M4 C1

DBG_SD15 IO IO/VRP3 CPU_A23 VMAUX0 IO/GLCK1S IO/RDWR_B FPGA_WR IO IO/VRN7 EA21
L20 Y21 AB12 AA3 PCI_STOP M3 C2
EA13 IO IO/VRN3 CPU_A10 MNY_CLK IO/GCLK0P IO/CS_B MANNYCS IO IO/VRP7 VMRW
L21 W20 PCI_DEVSEL M2 E5
TB49 IO IO CPU_AS IO IO VMA23
L22 AA20 PCI_TRDY M1 E6
TB50 IO IO CPU_DS IO IO VMA24
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
L16 T17 U16 U8 T6 L7
+3V3
+3V3
G11 G14 VCCOBank2 VCCOBank3 VCCOBank4 VCCOBank5 VCCOBank6 VCCOBank7

VCCOBank0 VCCOBank1
K16 VCCOBank2 VCCOBank3 R17 U15 VCCOBank4 VCCOBank5 U7 R6 VCCOBank6 VCCOBank7 K7
J16 VCCOBank2 VCCOBank3 P16 T14 VCCOBank4 VCCOBank5 T11 P7 VCCOBank6 VCCOBank7 J7
H17 VCCOBank2 VCCOBank3 N16 T13 VCCOBank4 VCCOBank5 T10 N7 VCCOBank6 VCCOBank7 H6
F8 VCCOBank0 VCCOBank1 F16
G17 VCCOBank2 VCCOBank3 M16 T12 VCCOBank4 VCCOBank5 T9 M7 VCCOBank6 VCCOBank7 G6
F7 VCCOBank0 VCCOBank1 F15
100 U110 100 U109

MOT0 8 1 IMOT0 ECG 4 5 IECG
C
MOT1 7 2 IMOT1 POS 3 6 IPOS A B
6 3 2 7 PCI_INTC
TIMING ITIMING TBASE ITBASE
PROBE 5 4 IPROBE ESCAN 1 8 IESCAN W75 A B
100P 100P 100P 100P 100P 100P 100P 100P PCI_INTB
W76
C288 C289 C291 C292 C284 C285 C286 C287 PCI_INTA
+3V3
CR10
BAV99 R165
2 +3V3
4K7 U104 R51
3
100 R166 10K +3V3 UP7
1 1 2 AUXIN_0 CY2071A
+3V3
CR9 10 U52 4 U52 7 VDD
BAV99 R163 C275 74LCX14
74LCX74 74LCX74 4
B XTALOUT
J4 2 100P
12 S 9 2 S 5 3
33 R65
D Q D Q XTALIN
U104 CPU_CLK
1
3
4
2
3 4K7 R164 11 3
1 100 CK CK
1 3 4 REMOTE
Q 8 Q 6 8 OE CLKA 1 33 R67
6 CR8 R R 5 U101
2 BAV99 R157 C273 74LCX14
R50 CLKB DSP_CLK
2 6 10K
7 2 100P 10K 13 1 GND CLKC
U104
33 R66
3 3 4K7
100 R158 XDSP_CLK
U95
8
6
5
7
8 1 5 6 FSWITCH XC2V1000-4 P4
4 +3V3
CR7 C268 74LCX14 AWE Y19 CCLK TCK C19 1 2
9 BAV99 R149 33 +3V3
100P +3V3
U60 FPGA_PROG A2 PROG_B TDI D3 3 4
C256
5 2 R64 AB20 D20 5 6
3 4K7 U104 CY2305 FPGA_DONE DONE TDO
100 R150 6 8 33 R63 AB2 M0 TMS B20 7 8
1 9 8 VDD CLKout 47N
AUXIN_1 10K W3 D5 9 10
3 MNY_CLK M1 DXN
CLK1
CR6 C266 74LCX14 1 2 R116 AB3 M2 DXP A3
BAV99 R147 D40M REF CLK2
B3 A21
100P 5 HSWAP_EN VBATT
2 CLK3
Foot Switch R148 47N 4 7
33 R58 AB21 PWRDWN_B RSVD A20
3 4K7 U104 C110
GND CLK4
SID_CLK
100 A B A B A B
1 13 12
A EXTECG
837 0147 042 Rev.A
C264 74LCX14
W57 W56 W58
100P U104
FORM:
11 10
74LCX14
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 3 10

1 2 3 4 5 6 7 8 9 10 11
U77 R77
+3V3 +3V3
+3V3 L7 CY2305 33
300MA SDCLK_0
6 VDD CLKout 8 R81
+3V3
CLK1 3
33
F U72 U53 C238 1 REF CLK2 2 SDCLK_1
MT48LCM16A2 10U 100N +3V3 47NC131 CLK3 5 R82
MT48LCM16A2 +3V3
1 VDD VDDQ 3
1 VDD VDDQ 3 C254 4 GND CLK4 7 33
14 9 TB38 DSPIOCLK
VDD VDDQ 14 9 R101
VDD VDDQ
27 VDD VDDQ 43
27 VDD VDDQ 43 22K R135
VDDQ 49
49 U96 22K R136
38
VDDQ C239 W2
22K
SDCLK_0 CLK
SDCLK_1 38 CLK TMS320C6205 TCK_RET P10
J3 E17 TMS 1 2
TB33 DSP_CLK CLKIN TMS
37 CKE TB30 37 CKE
27N T19 CLKOUT2 TDO D19 TDO 3 4
2 ED0 560P R129
DQ0 2 ED16 L3 D18 TDI 5 6
DQ0 4.7 CLKMODE0 TDI
EA2 23 4 ED1
A0 DQ1 EA2 23 4 ED17 R119 K5 D17 TCK 7 8 22K
EA3 24 5 ED2
A0 DQ1 C237 PLLV TCK
A1 DQ2 EA3 24 5 ED18 L2 C19 TRST 9 10
A1 DQ2 PLLG TRST
EA4 25 7 ED3
A2 DQ3 EA4 25 7 ED19 L1 F15 EMU0 11 12
A2 DQ3 PLLF EMU0
EA5 26 8 ED4
A3 DQ4 EA5 26 A3 DQ4 8 ED20
56
W64 EMU1 E18 EMU1 13 14
EA6 29 10 ED5
A4 DQ5 EA6 29 10 ED21 C3
EA7 30 11 ED6
ED[0:31] A4 DQ5
ED[0:31] R118 DSP_RESET RESET +3V3
EA[2:21]
A5 DQ6 EA7 30 A5 DQ6 11 ED22 A8 NMI RSV0 C8 R105 22K
EA8 31 13 ED7 R184
A6 DQ7 EA8 31 A6 DQ7 13 ED23 1K00 B15 EXT_INT7 RSV1 A4 R107 22K
E EA9 32 42 ED8
A7 DQ8 EA9 32 A7 DQ8 42 ED24
XDSPREQ C15 EXT_INT6 RSV2 K3 R117 22K
EA10 33 44 ED9
A8 DQ9 EA10 33 44 ED25 A16 L5
A8 DQ9 EXT_INT5 RSV3
EA11 34 45 ED10 DSP_EINT5
A9 DQ10 EA[2:21] EA11 34 45 ED26 B16 T18 UP1
A9 DQ10 EXT_INT4 RSV4
22 47 ED11 DSP_EINT4
A10 DQ11 22 A10 DQ11 47 ED27 A15 IACK RSV5 A3 AM29LV160
EA13 35 48 ED12
A11 DQ12 EA13 35 48 ED28 B3
A11 DQ12 RSV6 EA2 25 29 ED0
36 50 ED13 A0 DQ0
NC/(A12) DQ13 36 50 ED29 C14 B4
NC/(A12) DQ13 INUM0 RSV7 EA3 24 31 ED1
EA15 21 51 ED14 A1 DQ1
BA1 DQ14 EA14 21 51 ED30 B14 C4
BA1 DQ14 INUM1 RSV8 EA4 23 33 ED2
EA14 20 53 ED15 A2 DQ2
BA0 DQ15 EA15 20 53 ED31 A14 K2
BA0 DQ15 INUM2 RSV9 EA5 22 35 ED3
A3 DQ3
SDA10 F12 J17
SDA10 INUM3 RSV10 EA6 21 38 ED4
18 39 A4 DQ4
SDRAS RAS DQMH BE1 18 39 N18
SDRAS RAS DQMH BE3 RSV11 EA7 20 40 ED5
17 15 A5 DQ5
SDCAS CAS DQML BE0 17 15 A18
SDCAS CAS DQML BE2 DMAC0 EA8 19 42 ED6
16 A6 DQ6
SDWE WE
SDWE 16 WE
+3V3 C16 DMAC1 TOUT0 E5 TB41 EA9 18 44 ED7
19 A7 DQ7
ED[0:31]
SDCS1 CS 19 B17 C5
EA[2:21]
SDCS1 CS DMAC2 TINP0 EA10 8 30 ED8
6 A8 DQ8
VSSQ 6 A17
VSSQ DMAC3 EA11 7 32 ED9
28 12 A9 DQ9
VSS VSSQ 28 12 A5 10K
VSS VSSQ TOUT1 EA12 6 34 ED10
41 VSS VSSQ 46
41 46 R46 R45 B18 B5
A10 DQ10
VSS VSSQ PD TINP1 EA13 5 36 ED11
54 52 DSPREQ 10K 1K00 A11 DQ11
VSS VSSQ 54 52 R106
VSS VSSQ R104 EA14 4 39 ED12
A12 DQ12
D 1K00
C9 CLKX0 CLKX1 E6 CLKX0R1 EA15 3 A13 DQ13 41 ED13
DSP_SAFE A9 FSX0 FSX1 A6 FSX0R1 EA16 ED14
2 A14 DQ14 43
FPGA_WR B10 DX0 DX1 B7 DX0R1 EA17 ED15
1 A15 DQ15(A-1) 45
B9 B6
FPGA_PROG CLKR0 CLKR1 CLKX1R0 EA18 48 A16

FPGA_INIT E10 FSR0 FSR1 C7 FSX1R0 EA19 17 A17 RY/BY 15

FPGA_DONE A10 DR0 DR1 A7 DX1R0 EA20 16 A18
+3V3 BOOTMODE0
EA21 9 A19
A12 CLKS0 CLKS1 C6
B A
W52 A B
FLASHCS 26 CE
+3V3
DSP_MODE
TB47 TB46 TB45 CR4 AOE 28 OE
W42 BOOTMODE1 1K00 R91 BAT54 AWE 11 WE
12 RESET
B A U96
ED[0:31] 47 BYTE
22K U74 TMS320C6205 22K
5 4 ED0 ED0 R17 V13 EA2 R89
W45 BOOTMODE2 ED0 EA2 22K
+3V3
6 3 ED1 ED1 R18 ED1 EA3 W13 EA3 R180
B A 7 2 ED2 ED2 R19 R12 EA4 U96 +3V3 4K7 R92
ED2 EA4 W69
8 1 ED3 ED3 P17 ED3 EA5 U12 EA5 TMS320C6205
C ED4 EA6
W35 BOOTMODE3 P18 ED4 EA6 W12 PCI_CLKO W5 PCLK VIOP U3
22K U78 ED5 N15 R11 EA7 P3 +3V3 +12V
ED5 EA7 VIOP 47N 47N
5 4 ED4 BAT54
B A ED6 P19 U11 EA8 PCI_AD0 U7 G1
ED6 EA8 AD0 VIOP U102
6 3 ED5
ED7 N19 ED7 EA9 V11 EA9 PCI_AD1 W6 AD1 C218 C236 R152 CR11
7 2 ED6
ED8 M17 W11 EA10 PCI_AD2 V3 V4 LP2951-3.1
W36 BOOTMODE4
8 1 ED7
ED8 EA10 AD2 PCBE0 PCI_CBE0
8 1
ED9 M18 U10 EA11 PCI_AD3 V6 T2 10K VIN OUTPUT
ED9 EA11 AD3 PCBE1 PCI_CBE1
EA[2:21]
B A ED10 M19 V10 EA12 PCI_AD4 U6 M3

22K U67 ED10 EA12 AD4 PCBE2 PCI_CBE2
3 6
ED11 L19 W10 EA13 PCI_AD5 V5 G2 SHUTDWN Vtap 470K C381
1 8 ED8 ED11 EA13 AD5 PCBE3 PCI_CBE3
W46 EES0
2 7 ED9
ED12 L18 ED12 EA14 U9 EA14 PCI_AD6 U5 AD6
W65 470N
5 7
3 6 ED10
ED13 L17 ED13 EA15 V9 EA15 PCI_AD7 W4 AD7 PREQ F2 PCI_REQ0 PCI_AD19
ERROR FB R132
B A ED14 K19 W9 EA16 PCI_AD8 U4 D1 B A
4 5 ED11 ED14 EA16 AD8 PGNT PCI_GNT0
ED15 EA17 PCI_AD9 4 GND SENSE 2
K18 ED15 EA17 W8 V1 AD9 R138
EES1 33 PCI_INTC
W47 22K U66 ED16 K17 ED16 EA18 V8 EA18 PCI_AD10 W2 AD10 PIDSEL H5
ED12 ED17 EA19 PCI_AD11 47K 7K5
1 8 K15 ED17 EA19 U8 W3 AD11 PDEVSEL R2 PCI_DEVSEL W73
B
B A 2 7 ED13 ED18 J19 W7 EA20 PCI_AD12 U1 N5 PCI_INTB
ED18 EA20 AD12 PFRAME PCI_FRAME
A
3 6 ED14 ED19 J18 ED19 EA21 V7 EA21 PCI_AD13 U2 AD13 PINTA C1 R134 R133
B
W37 EES2 4 5 ED15 ED20 H19 ED20 TB35 PCI_AD14 V2 AD14 PPAR T3 PCI_PAR
B ED21 PCI_AD15
W70
H18 W16 T1 C2
A
ED21 BE0 BE0 AD15 PRST PCI_RST
B A 22K U61 ED22 H17 V16 PCI_AD16 N1 P1
ED22 BE1 BE1 AD16 PIRDY PCI_IRDY
1 8 ED16 PCI_INTA
ED23 G19 W17 PCI_AD17 N2 R1
ED23 BE2 BE2 AD17 PSTOP PCI_STOP
2 7 ED17
ED24 G18 U16 PCI_AD18 M1 N3 2 UP5
W43 LENDIAN
3 6 ED18
ED24 BE3 BE3 AD18 PTRDY PCI_TRDY SCLK
ED25 G17 ED25
PCI_AD19 M2 AD19 93C56W
4 5 ED19
B A ED26 F19 V17 PCI_AD20 H1 B19 3 4
ED26 CE0 SDCS1 AD20 XSP_DO DI DO
ED27 F18 W18 PCI_AD21 J1 C11
22K U62 ED27 CE1 FLASHCS AD21 XSP_CS
ED28 G15 U17 PCI_AD22 H2 C17 6
W29 EEA1 1 8 ED20 ED28 CE2 MANNYCS AD22 XSP_CLK ORG
ED29 F17 V18 PCI_AD23 H3 C18 7
2 7 ED21 ED29 CE3 AD23 XSP_DI DU
B A
3 6 ED22
ED30 E19 ED30 R95 PCI_AD24 G3 AD24 1 CS
+3V3
ED31 F14 P14 PCI_AD25 F1 D3

4 5 ED23 ED31 HOLD AD25 PME PCI_PME
V15 PCI_AD26 F5 B1
W28 PLL_CNF0 HOLDA 10K AD26 3.3VauxDET 22K R109
22K U47 ARE U14 ARE
PCI_AD27 F3 AD27 PWR_WKP A2
B A 1 8 ED24 W14 PCI_AD28 E1 B2 22K
AOE AOE AD28 3.3Vaux R108 22K
+3V3
2 7 ED25 V14 U18 PCI_AD29 E2
AWE AWE SDRAS/SSOE SDRAS AD29 R90
3 6 ED26 W15 V19 PCI_AD30 E3 P5
W26 PLL_CNF1 ARDY ARDY SDCAS/SSADS SDCAS AD30 PSERR PCI_SERR
4 5 ED27 U19 T17 PCI_AD31 D2 P2 47N
SDA10 SDA10 SDWE/SSWE SDWE AD31 PPERR PCI_PERR
A B A
PCI_AD[0:31] C143
22K U46 R99
837 0147 042 Rev.A
+3V3
1 8 ED28
W22 PLL_CNF2
ED29
FORM:
2 7 10K
3 6 ED30
B A
4 5 ED31
W21
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 4 10

1 2 3 4 5 6 7 8 9 10 11
CPU_CKO
U3
U35
R40 R3 74LCX244
MC68340PV-16VE 33 1
33P 1G
90 VDDSYN CLKOUT 95 CPU_CLKOUT
C384 1K00 19 2G
U59 CPULA0 CPULA0 CPU_A0
CPU_CLK 91 EXTAL A0 113 2 1A1 1Y1 18
F 74LCX245 89 37 CPULA1 CPULA1 4 16 CPU_A1
CPU_XTAL XTAL A1 1A2 1Y2
CPU_FC3 19 G CPULA2 CPULA2 CPU_A2
CPU_XFC 93 XFC A2 38 6 1A3 1Y3 14
CPU_RW 1 T/R CPULA3 CPULA3 CPU_A3
A3 39 8 1A4 1Y4 12
CPU_D0 7 13 CPULD0 CPULD0 144 42 CPULA4 CPULA4 11 9 CPU_A4
A1 B1 D0 A4 2A1 2Y1
A2 B2 D1 A5 2A2 2Y2 UP3 UP2
A3 B3 D2 A6 2A3 2Y3
CPU_D3 8 12 CPULD3 CPULD3 141 45 CPULA7 CPULA7 17 3 CPU_A7 AM29LV160 AM29LV160
A4 B4 D3 A7 2A4 2Y4
CPU_A1 25 29 CPU_D0 CPU_A1 25 29 CPU_D0
CPU_D4 5 15 CPULD4 CPULD4 138 46 CPULA8 A0 DQ0 A0 DQ0
A5 B5 D4 A8
CPU_D5 3 17 CPULD5 CPULD5 137 47 CPULA9 U2 A1 DQ1 A1 DQ1
A6 B6 D5 A9 CPULA[0:23] CPU_A[0:23]
A7 B7 D6 A10
R2 74LCX244 CPU_A4 22 35 CPU_D3 CPU_A4 22 35 CPU_D3
A8 B8 D7 A11 1 1G CPU_A5 21 38 CPU_D4 CPU_A5 21 38 CPU_D4
CPULD8 134 52 CPULA12 A4 DQ4 A4 DQ4
D8 A12 1K00 19 2G CPU_A6 20 40 CPU_D5 CPU_A6 20 40 CPU_D5
CPULD9 133 53 CPULA13 A5 DQ5 A5 DQ5
U58 D9 A13
CPULD[0:15]
CPULA8 CPU_A8 CPU_A7 CPU_D6 CPU_A7 CPU_D6
CPU_D[0:15]
CPULD10 CPULA14 2 1A1 1Y1 18 19 A6 DQ6 42 19 A6 DQ6 42

132 D10 A14 55
74LCX245 CPULA9 CPU_A9 CPU_A8 CPU_D7 CPU_A8 CPU_D7
CPU_D[0:15]
CPULD11 CPULA15 4 1A2 1Y2 16 18 A7 DQ7 44 18 A7 DQ7 44
131 D11 A15 56
CPU_D[0:15]
CPULA10 CPU_A10 CPU_A9 CPU_D8 CPU_A9 CPU_D8
CPU_A[0:23]
19 G CPULD12 CPULA16 6 1A3 1Y3 14 8 A8 DQ8 30 8 A8 DQ8 30
128 D12 A16 57
CPU_A[0:23]
1 CPULA11 8 12 CPU_A11 CPU_A10 7 32 CPU_D9 CPU_A10 7 32 CPU_D9
T/R CPULD13 126 60 CPULA17 1A4 1Y4 A9 DQ9 A9 DQ9
D13 A17
E CPULA12 11 9 CPU_A12 CPU_A11 6 34 CPU_D10 CPU_A11 6 34 CPU_D10
CPU_D8 9 11 CPULD8 CPULD14 125 61 CPULA18 2A1 2Y1 A10 DQ10 A10 DQ10
A1 B1 D14 A18
CPULA13 13 7 CPU_A13 CPU_A12 5 36 CPU_D11 CPU_A12 5 36 CPU_D11
CPU_D9 8 12 CPULD9 CPULD15 124 62 CPULA19 2A2 2Y2 A11 DQ11 A11 DQ11
A2 B2 D15 A19
CPU_D10 5 15 CPULD10 63 CPULA20 2A3 2Y3 A12 DQ12 A12 DQ12
A3 B3 A20
CPU_D11 6 14 CPULD11 69 64 CPULA21 2A4 2Y4 A13 DQ13 A13 DQ13
A4 B4 CPU_FC0 FC0 A21
CPU_D12 7 13 CPULD12 70 65 CPULA22 A14 DQ14 A14 DQ14
U1 CPU_A16 1 45 CPU_D15 CPU_A16 1 45 CPU_D15
CPU_D13 4 16 CPULD13 71 66 CPULA23 A15 DQ15(A-1) A15 DQ15(A-1)
CPU_A17 48 CPU_A17 48
CPU_D14 3 A7 B7 17 CPULD14
CPU_FC3 72 FC3 A24/PA0 123
R1 74LCX244 A16 A16
CPU_A18 17 15 CPU_A18 17 15
CPU_D15 2 18 CPULD15 122 19 A17 RY/BY A17 RY/BY
A8 B8 A25/PA1/IACK1 DSP_RST 1G
CPU_A19 16 CPU_A19 16
97 121 1K00 1 A18 A18
RESET A26/PA2/IACK2 DSP_MODE 2G
CPU_A20 9 CPU_A20 9
A B 99 120 A19 A19
CPU_BERR BERR A27/PA3/IACK3 XDSP_RST CPULA16 11 9 CPU_A16
1A1 1Y1
CPU_RESET 98 117
CPU_HALT HALT A28/PA4/IACK4 XDSP_MODE CPULA17 13 7 CPU_A17
1A2 1Y2 26 26
103 116 FLASH0 CE FLASH1 CE
W16 +3V3 CPU_AS AS A29/PA5/IACK5 PRTPWRON CPULA18 15 1A3 1Y3 5 CPU_A18
28 28
104 115 OE OE
CPU_DS DS A30/PA6/IACK6 LINK0 CPULA19 17 3 CPU_A19
1A4 1Y4 11 11
107 114 WE WE
CPU_RW R/W A31/PA7/IACK7 LINK1 CPULA20 4 16 CPU_A20
2A1 2Y1 12 12
105 RESET RESET
CPU_SIZ0 SIZ0 CPULA21 8 12 CPU_A21
2A2 2Y2 47 47
106 87 BYTE BYTE
R48
R49
CPU_SIZ1 SIZ1 MODCK/PB0 CPU_MCKPB0 CPULA22 6 14 CPU_A22

4K7
4K7
2A3 2Y3
CS0/AVEC 1 CPU_CS0AVEC CPULA23 CPU_A23
2 2A4 2Y4 18 22K 22K
+3V3
+3V3
D CPU_DSACK0 112 DSACK0 CS1/IRQ1/PB1 2 INT1
111 3
CR2
CPU_DSACK1 DSACK1 CS2/IRQ2/PB2 INT2
PC_RESET R85 R76
4 BAT54
IRQ3/PB3 INT3 R41
100 5 CPU_RESET
4K7 Q1
CPU_BR BR CS3/IRQ4/PB4 INT4

CPU_BG 101 BG IRQ5/PB5 8 INT5 BC817

CPU_BGACK 102 BGACK IRQ6/PB6 9 INT6
CPU_RMC 108 RMC IRQ7/PB7 10 INT7 W32 U57
CPU_DS 13
4K7 11
16 29 PC_RST 12
CPU_DREQ1_X DREQ1 RTSA/OP0 CPU_RTSA +3V3 +12V U57
15 23 R181 74LCX00 10
CPU_DACK1_X DACK1 RTSB/OP1 CPU_RTSB BAT54 8
CPU_DONE1_X 14 DONE1 TxRDYA/OP6 26 CPU_TXRDYA U71 9
CR12 U57
RxRDYA/FFULLA/OP4 27 CPU_RXRDYA R75 LP2951-3.1 1 74LCX00 +3V3
CPU_DREQ2_X 13 DREQ2 10K 3
8 VIN OUTPUT 1
2 U57
CPU_DACK2_X 12 DACK2 SCLK 21 CPU_SCLK_X
CPU_DONE2_X 11 DONE2 X1 17 CPU_X1_X
74LCX00 4 R4
PRTPWRON 3 SHUTDWN Vtap 6 100N 470N 6
20 470K 5 10K
X2 CPU_X2_X CPU_RW
CPU_TGATE1_X 79 TGATE1 5 7 R71 C120 C382 74LCX00 U4
ERROR FB
CPU_TIN1_X 81 TIN1 RxDA 33 CPU_RXDA U4 11
C 13
CPU_TOUT1_X 80 TOUT1 TxDA 32 CPU_TXDA CPU_A20 5
4 GND SENSE 2 12
4
CTSA 28 CPU_CTSA
RAM 6 74LCX02
CPU_TGATE2_X 36 TGATE2 U5
34 25
47K 7K5 74LCX02 U5 13
CPU_TIN2_X TIN2 RxDB CPU_RXDB 10 11
CPU_SIZ0
CPU_TOUT2_X 35 TOUT2 TxDB 24 CPU_TXDB R73 R72 8 12
CPU_A0 9
CTSB 22 CPU_CTSB 74LCX00
78 74LCX00
CPU_TCK_X TCK
CPU_TMS_X 77 TMS BKPT/DSCLK 83 CPU_BKPT U4 U5
82
U5 1
FREEZE CPU_FREEZE 74LCX02 5 3
CPU_TDI_X 76 TDI IPIPE/DSO 85 CPU_DSO 8 6 2
10 4
CPU_TDO_X 75 TDO IFETCH/DSI 84 CPU_DSI +3V3 74LCX00
9
74LCX00
R11 R21
10K 10K
TB5
U51 U39
U8 CY7C1049 CY7C1049
B
DSP_RST 1 74LCX11 37 OE 37 OE
2 12 DSP_RESET 15 WE 15 WE
8 CS 8 CS
13
TB6
+3V3 U8 A0 I/O0 A0 I/O0
+3V3 R55 9
CPU_A2 4 A1 I/O1 10 CPU_D1 CPU_A2 4 A1 I/O1 10 CPU_D9
XDSP_RST 74LCX11
5K6 CPU_A3 5 13 CPU_D2 CPU_A3 5 13 CPU_D10
A2 I/O2 A2 I/O2
CPU_D[0:15]
10 8 XDSP_RESET CPU_A4 CPU_D3 CPU_A4 CPU_D11
CPU_D[0:15]
6 A3 I/O3 14 6 A3 I/O3 14
R22 U9 CPU_A5 CPU_D4 CPU_A5 CPU_D12
11 7 A4 I/O4 31 7 A4 I/O4 31
10K 74LCX138 R61 R57 U56 CPU_A6 16 32 CPU_D5 CPU_A6 16 32 CPU_D13
+3V3 A5 I/O5 A5 I/O5
CPU_A21 1 A Y0 15 FLASH0 100K 33K CPU_A7 CPU_D6 CPU_A7 CPU_D14
17 35 17 35
2 14 TLC7701 +3V3 A6 I/O6 A6 I/O6
CPU_A22 B Y1 FLASH1 CPU_A8 18 36 CPU_D7 CPU_A8 18 36 CPU_D15
3 13
7 SENSE VDD 8 U4 A7 I/O7 A7 I/O7
CPU_A23 C Y2 RAM 2 CPU_A9 19 CPU_A9 19
A8 A8
CPU_A[0:23]
CPU_A[0:23]
12 1
U8 Y3
2 6 3 R47 CPU_A10 20 A9
CPU_A10 20 A9
11 RESIN RESET
Y4 4K7 CPU_A11 26 CPU_A11 26
5 74LCX11 74LCX02 A10 A10
CPU_FC0 6 10
G1 Y5 CPU_A12 27 CPU_A12 27
3 5 A11 A11
CPU_FC1 3 6 4 G2A Y6 9 R56 C106 CT RESET CPU_RESET
CPU_A13 28 CPU_A13 28
A 5 7 C119 BAT54
A12 A12
4 G2B Y7 CPU_A14 29 CPU_A14 29
CPU_FC2 A13 A13
837 0147 042 Rev.A
22K 1 4
W25 47N 470N CNTRL GND
CR1 CPU_A15 30 CPU_A15 30
A14 A14
CPU_AS CPU_A16 CPU_A16
FORM:
38 A15 38 A15
CPU_A17 39 CPU_A17 39
A16 A16
CPU_A18 40 CPU_A18 40
A17 A17
CPU_A19 41 CPU_A19 41
A18 A18
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 5 10

1 2 3 4 5 6 7 8 9 10 11
FL9
600OHM
47P
U98 U120 KB_CLK
C379
+3V3 +3V3
100N C202 75C3243 100N C280 75C3243 FL6
U36 28 C1+ 28 C1+
Keyboard
24 26
100N C201 24 26
100N C279 600OHM
47P
MC68340 C1- VCC C1- VCC
KB_DAT
C377
1 C2+ 1 C2+
N8 VDDSYN CLKOUT P10 CPU_CKO 100N C199 100N C278
F 100N C246 2 C2- V+ 27 100N C333 2 C2- V+ 27 FL8
Q9 M14 CPULA0 600OHM
CPU_CLK EXTAL A0 C378 47P
CPU_XTAL P8 XTAL A1 B1 CPULA1 TXD2 14 DIN1 DOUT1 9 CPU_TXDB 14 DIN1 DOUT1 9 TXD1 MS_CLK
Q10 C2 CPULA2 13 10 13 10
CPU_XFC XFC A2 RTS2 DIN2 DOUT2 CPU_RTSB DIN2 DOUT2 RTS1
FL7
A3 C1 CPULA3
DTR2 12 DIN3 DOUT3 11 DTRB 12 DIN3 DOUT3 11 DTR1 Mouse
CPULD0 B14 D0 A4 D1 CPULA4 VTR 600OHM C380 47P
CPULD1 C13 E3 CPULA5 19 4 P12 19 4 MS_DAT
D1 A5 RXD2 ROUT1 RIN1 CPU_RXDB ROUT1 RIN1 RXD1 (to Video board)
CPULD2 A15 D2 A6 E2 CPULA6
CTS2 18 ROUT2 RIN2 5 1 2 CPU_CTSB 18 ROUT2 RIN2 5 CTS1 FL10
CPULD3 B15 E1 CPULA7 20 3 4 20 600OHM
D3 A7 ROUT2B ROUT2B C376 47N
VCC
CPULD4 C15 F3 CPULA8 17 6 5 6 17 6
D4 A8 DSR2 ROUT3 RIN3 DSRB ROUT3 RIN3 DSR1
CPULD5 D14 F2 CPULA9 16 7 7 8 16 7
D5 A9 DCD2 ROUT4 RIN4 DCDB ROUT4 RIN4 DCD1
CPULD6 D15 F1 CPULA10 15 8 9 10 15 8
D6 A10 RI2 ROUT5 RIN5 ROUT5 RIN5
CPULD7 E13 G1 CPULA11 F1
D7 A11
CPULD[0:15] CPULA[0:23] R103 R167
CPULD8 E14 H1 CPULA12
D8 A12 23 3 23 3
CPULD9 E15 H2 CPULA13 10K FORCEON V- 10K FORCEON V- C332 10K R178
+3V3
+3V3
D9 A13 22 22
+3V3
FORCEOFF FORCEOFF
CPULD10 F15 J1 CPULA14 100N 100N EXTDEV
D10 A14 21 25 21 25
INVALID GND INVALID GND
CPULD11 F14 J2 CPULA15 C248
D11 A15 B A B A
CPULD12 CPULA16 10K R179
E G14 D12 A16 K1
+3V3
CPULD13 G15 K2 CPULA17 W79 DSP1T1
D13 A17
CPULD14 H14 L1 CPULA18 W59
D14 A18
CPULD15 H15 L2 CPULA19 J5
D15 A19 1
A20 M1 CPULA20 U94 U33 14
N2 L3 CPULA21 +3V3 +3V3
CPU_FC0 FC0 A21 100N C152 75C3243 100N C44 75C3243 2 -TXD
Q1 N1 CPULA22
CPU_FC1 FC1 A22 +3V3 28 28 15
C1+ 100N C154 C1+ 100N C43
P2 P1 CPULA23
CPU_FC2 FC2 A23 24 26 24 26 3
C1- VCC C1- VCC -RXD
CPU_FC3 Q2 FC3 A24/PA0 J14 PC_RST 1 C2+ 1 C2+ 16
A25/PA1/IACK1 J13 DSP_RESET 2 27
100N C153 2 27
100N C42
Q11 J15 R175 R176 100N C198 C2- V+ 100N C73 C2- V+ 4
RTS
CPU_RESET RESET A26/PA2/IACK2 DSP_MODE 17
CPU_BERR Q12 BERR A27/PA3/IACK3 K15 XDSP_RESET 10K 10K TXD1 14 DIN1 DOUT1 9 CPU_TXDA 14 DIN1 DOUT1 9 5 CTS
CPU_HALT P11 HALT A28/PA4/IACK4 L15 XDSP_MODE
RTS1 13 DIN2 DOUT2 10 CPU_RTSA 13 DIN2 DOUT2 10 18
CPU_AS Q14 AS A29/PA5/IACK5 L14 PRTPWRON
DTR1 12 DIN3 DOUT3 11 DTRA 12 DIN3 DOUT3 11 6 DSR
CPU_DS P13 DS A30/PA6/IACK6 M15 LINK0 19
CPU_RW P14 R/W A31/PA7/IACK7 L13 LINK1 P13
RXD1 19 ROUT1 RIN1 4 CPU_RXDA 19 ROUT1 RIN1 4 7
CPU_SIZ0 N12 SIZ0
CTS1 18 ROUT2 RIN2 5 1 2 CPU_CTSA 18 ROUT2 RIN2 5 20 DTR
CPU_SIZ1 Q15 SIZ1 MODCK/PB0 Q8 CPU_MCKPB0
D 20 ROUT2B 3 4 20 ROUT2B 8 DCD
CS0/AVEC A14 CPU_CS0AVEC
DSR1 17 ROUT3 RIN3 6 5 6 DSRA 17 ROUT3 RIN3 6 21
CPU_DSACK0 N15 DSACK0 CS1/IRQ1/PB1 B13 INT1
DCD1 16 ROUT4 RIN4 7 7 8 DCDA 16 ROUT4 RIN4 7 9
N14 C12
CPU_DSACK1 DSACK1 CS2/IRQ2/PB2 INT2 15 8 9 10 15 8 22

RI1 ROUT5 RIN5 RIA ROUT5 RIN5 RI

A13
IRQ3/PB3 INT3 10
CPU_BR Q13 BR CS3/IRQ4/PB4 B12 INT4 R88 R29 10K R27 23
+3V3
23 FORCEON V- 3 23 FORCEON V- 3
CPU_BG N11 BG IRQ5/PB5 A12 INT5 +3V3 10K 10K C74 11
+3V3
22 FORCEOFF 22 FORCEOFF
CPU_BGACK P12 BGACK IRQ6/PB6 A11 INT6 100N 100N
21 25 21 25 DSP_SAFE 24
P15 C10 INVALID GND INVALID GND
CPU_RMC RMC IRQ7/PB7 INT7 C200 12
B A B A
PHYSIO 25
CPU_DREQ1_X A8 DREQ1 RTSA/OP0 B4 CPU_RTSA 13
CPU_DACK1_X C9 DACK1 RTSB/OP1 B6 CPU_RTSB W54 W14
CPU_DONE1_X B9 DONE1 TxRDYA/OP6 A4 CPU_TXRDYA
RxRDYA/FFULLA/OP4 B5 CPU_RXRDYA C374 10P 120OHM FL5
CPU_DREQ2_X A9 DREQ2 R RS-232
A10 A7 CPU_X1_X
CPU_DACK2_X DACK2 SCLK CPU_SCLK_X 120OHM FL4 (Debug)
CPU_DONE2_X B10 DONE2 X1 B8
1M Y2 G
X2 B7 R183 3.686400MHZ J8 J9
C N5 120OHM FL3
CPU_TGATE1_X TGATE1 10P 1 1
Q5 A2 CPU_X2_X R177 C375 DBG_SA0 DBG_SD0
B
CPU_TIN1_X TIN1 RxDA CPU_RXDA 2 2
DBG_SA1 DBG_SD1
CPU_TOUT1_X P5 TOUT1 TxDA B3 CPU_TXDA 15P 15P 15P
470 3 DBG_SA2 3 DBG_SD2
CTSA A3 CPU_CTSA 75 75 75
4 DBG_SA3 4 DBG_SD3
C3
CPU_TGATE2_X TGATE2 5 DBG_SA4 5 DBG_SD4 R28 R26 R20 C39 C29 C15
CPU_TIN2_X A1 TIN2 RxDB A5 CPU_RXDB 6 DBG_SA5 6 DBG_SD5
CPU_TOUT2_X B2 TOUT2 TxDB C6 CPU_TXDB 7 DBG_SA6 7 DBG_SD6
CTSB A6 CPU_CTSB FL2
8 DBG_SA7 8 DBG_SD7 R19 120OHM
Q4 22
CPU_TCK_X TCK 9 9
DBG_SA8 DBG_SD8 HSYNC
CPU_TMS_X P4 TMS BKPT/DSCLK P6 CPU_BKPT 10 DBG_SA9 10 DBG_SD9 FL1
FREEZE Q6 CPU_FREEZE 11 11 22 R18 120OHM
DBG_SA10 DBG_SD10
Q3 Q7 VSYNC
CPU_TDI_X TDI IPIPE/DSO CPU_DSO 12 12 DBG_SD11
P3 N6 1N 1N R31
CPU_TDO_X TDO IFETCH/DSI CPU_DSI 13 13
DBG_SA12 DBG_SD12
100
14 DBG_SA13 14 DBG_SD13
C14 C11 DDCK
15 DBG_SA14 15 DBG_SD14
16 DBG_SA15 16 DBG_SD15 R30
17 17 DDDA
DBG_SA16
B U26 18 18
100
+3V3 U30 DBG_MEMW
10K +3V3 19 19
10K DBG_MEMR 1N 1N
CPU_BERR 8 1 20 20 DBG_IOW
CPU_TGATE1_X 2 7
CPU_TCK_X 5 4 21 21 DBG_IOR
CPU_TIN1_X 3 6 C46 C45
CPU_TMS_X 6 3 22 22
CPU_TGATE2_X 4 5
CPU_TDI_X 7 2 23 DBG_LA18 23
CPU_TIN2_X 1 8
24 DBG_LA19 24 DBG_SBHE
25 DBG_LA20 25
U38 U34 26 26
+3V3 +3V3 +3V3 DBG_LA21
10K 10K P14 27 27
DBG_LA22
CPU_DREQ1_X 1 8 CPU_SCLK_X 2 7
CPU_DS 1 2 CPU_BERR 28 DBG_LA23 28
CPU_DONE1_X 2 7 1 8
3 4 CPU_BKPT 29 29
CPU_DREQ2_X 3 6 CPU_BKPT 4 5
5 6 CPU_FREEZE 30 30
CPU_DONE2_X 4 5 CPU_DSI 3 6
CPU_RESET 7 8 CPU_DSI 31 31
9 10 CPU_DSO 32 32
VCC +3V3
VCC +3V3
U44 33 33
+3V3 BDM 34 34
10K
A 1 8 35 35
CPU_BR
R32
837 0147 042 Rev.A
2 7 36 36
CPU_BGACK
3 6 4K7 37 37
CPU_HALT
FORM:
CPU_MCKPB0 38 38
CPU_CS0AVEC 4 5
39 39
40 40
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 6 10

1 2 3 4 5 6 7 8 9 10 11
W1
DM_CLKFB
U7
MT48LCM16A2
33 U13 1 VDD VDDQ 3
+3V3
DM_CLK 1 8 14 VDD VDDQ 9
F 2 7 27 43
DM_CKE VDD VDDQ
DM_A0 3 6 VDDQ 49
DM_A1 4 5 38 CLK
33 U14 37
U37 CKE
DM_A2 1 8
DQ0 2 U37
XC2V1000-4 DM_A3 2 7
23 4
3 6
A0 DQ1 XC2V1000-4
DM_A4 24 5
A1 DQ2
BANK 0 BANK 1 4 5
DM_A5 25 7
A2 DQ3 BANK 4 BANK 5
U21 26 A3 DQ4 8 TB29
B4 F12 33
CRT_GREEN0 IO IO/GCLK3P SID_CLK 29 10
4 5 A4 DQ5 AB19 AA11
CRT_GREEN1 A4 IO IO/GCLK2S F13 TB24 DM_A6
30 11
EXTDEV IO/DOUT IO/GCLK7S TB16
3 6 A5 DQ6 AA19 Y11
CRT_RED3 C4 IO IO/GCLK1P E12 DM_CLKFB
DM_A7
31 13
XFPGA_INIT IO/INIT_B IO/GCLK6P TB9
2 7 A6 DQ7 V18 W11
CRT_RED1 C5 IO IO/GCLK0S D12 DM_CLK
DM_A8
32 42
XED0 IO/D0 IO/GCLK5S TB10
1 8 A7 DQ8 V17 V11
CRT_BLUE6 B5 IO/VRP0 IO C12 DM_CAS
DM_A9
33 44
XED1 IO/D1 IO/GCLK4P TB12
A8 DQ9 W18 U11 TB14
A5 B12 XED2 IO/D2/ALT_VRP4 IO
CRT_GREEN3 IO/VRN0 IO/VREF1 DM_DQ7 33 U20 34 A9 DQ10 45 Y18 U10
D6 A13 XED3 IO/D3/ALT_VRN4 IO/VREF5 MS_DAT
CRT_RED5 IO/VREF0 IO DM_DQ8 4 5 22 47
DM_A10 A10 DQ11 AA18 AB10
E C6 B13 XEA17 IO/VREF4 IO ICOL0
CRT_GREEN2 IO IO DM_DQMH 2 7 35 48
DM_A11 A11 DQ12 AB18 AA10
B6 C13 XAOE IO IO ICOL1
CRT_GREEN4 IO IO DM_BA0 1 8 36 50
DM_A12 NC/(A12) DQ13 W17 Y10
A6 D13 XEA6 IO/VRP4 IO IROW1
CRT_BLUE2 IO IO DM_RAS 3 6 21 51
BA1 DQ14 Y17 W10
E7 E13 XEA9 IO/VRN4 IO KB_DAT
CRT_RED2 IO IO DM_DQ5 20 53
BA0 DQ15 AA17 V10
E8 E14 XEA10 IO IO MS_CLK
CRT_RED4 IO IO/VREF1 DM_DQ6
ICOL11 AB17 IO IO/VREF5 V9 LINK0
CRT_RED7 D7 IO IO A14 DM_CS 18 RAS DQMH 39 V16 AB9
C7 B14 IROW10 IO IO XAWE
CRT_GREEN5 IO/VREF0 IO DM_DQML 17 15
CAS DQML V15 AA9
CRT_GREEN7 B7 IO IO C14 DM_CKE 33 U12 16
IROW8 IO IO XARE
WE W16 Y9
A7 D14 4 5 XEA7 IO IO LINK7
CRT_GREEN6 IO IO DM_BA1 DM_BA1 19 CS Y16 W9
D8 A15 3 6 XEA11 IO/VREF4 IO LINK6
CRT_RED6 IO IO/VREF1 DM_WE DM_BA0 6
VSSQ AA16 AB8
C8 B15 2 7 XEA18 IO IO/VREF5 VID_HSYNC
CRT_BLUE3 IO IO DM_A12 DM_RAS 28 12
VSS VSSQ AB16 AA8
B8 C15 1 8 ICOL14 IO IO VID_VBLANK
CRT_BLUE1 IO IO DM_A1 DM_CAS 41 46
VSS VSSQ W15 Y8
A8 D15 XEA13 IO IO GRA0
CRT_BLUE0 IO IO DM_A0 54 52
VSS VSSQ Y15 W8
CRT_BLUE4 E9 IO IO F14 DM_A6 33 U19 GRA7 IO IO LINK1
ICOL2 AA15 IO IO U9 KB_CLK
CRT_RED0 F9 IO/VREF0 IO E15 DM_A4 DM_WE 4 5
ICOL15 AB15 IO IO V8 LINK2 470 470
CRT_BLUE7 D9 IO IO A16 DM_A11 DM_CS 2 7
C9 B16 3 6 IROW14 U14 IO IO AB7 GRA4 R43 R42
CRT_BLUE5 IO IO DM_A10 DM_DQML
GRA1 V14 IO/VREF4 IO AA7 GRA5
DM_DQ11 B9 IO IO/VREF1 C16 DM_A3 DM_DQMH 1 8
D GRA2 W14 IO IO/VREF5 Y7 GRA6
DM_DQ15 A9 IO IO D16 DM_A2
U17 GRA3 Y14 IO IO W7 LINK5
DM_DQ1 E10 IO/VREF0 IO E16 DM_A5 33
ICOL10 AA14 IO IO AB6 GRA8
F10 E17 1 8
DM_DQ0 IO IO DM_A7 DM_DQ15

ICOL12 AB14 IO IO AA6 GRA9

D10 A17 2 7
DM_DQ2 IO IO DM_A9 DM_DQ14

ICOL5 U13 IO/VREF4 IO Y6 GRA10
DM_DQ14 C10 IO IO B17 DM_A8 DM_DQ13 3 6
ICOL7 V13 IO IO W6 GRA13
DM_DQ9 B10 IO IO C17 MM_CS DM_DQ12 4 5
ICOL8 W13 IO IO/VRP5 V7 LINK3
DM_DQ10 A10 IO IO/VREF1 D17 MM_WP
ICOL13 Y13 IO IO/VRN5 V6 LINK4
DM_DQ13 E11 IO/VREF0 IO/VRP1 A18 MM_HOLD U18
33 AA13 AB5
F11 B18 ICOL6 IO IO GRA14
DM_DQ12 IO IO/VRN1 MM_SCK 1 8
DM_DQ11 AB13 AA5
D11 C18 ICOL4 IO IO/VREF5 GRA15
DM_DQ3 IO/GCLK7P IO MM_SI 2 7
DM_DQ10 U12 Y5
C11 D18 ICOL3 IO/VREF4 IO/D4/ALT_VRP5 XED4
DM_DQ4 IO/GCLK6S IO MM_SO 3 6
DM_DQ9 V12 W5
B11 A19 ICOL9 IO IO/D5/ALT_VRN5 XED5
TB11 IO/GCLK5P IO XDM_CLK
DM_DQ8 4 5
W12 AB4
TB13 A11 IO/GCLK4S IO B19 TB22 TB15 IO/GCLK3S IO/D6 XED6
Y12 AA4
33 U11 TB23 IO/GCLK2P IO/D7 XED7
AA12 Y4
4 5 TB21 IO/GLCK1S IO/RDWR_B XFPGA_WR
DM_DQ7 AB12 AA3
XDSPIOCLK IO/GCLK0P IO/CS_B SIDCS
DM_DQ6 3 6
DM_DQ5 2 7
C
DM_DQ4 1 8
+3V3
+3V3
+3V3
+3V3
U16 VCCOBank4 VCCOBank5 U8
G10 VCCOBank0 VCCOBank1 G13 U10
33 U15 U7
G9 G12 VCCOBank4 VCCOBank5
VCCOBank0 VCCOBank1 4 5
DM_DQ3 T14 T11
F8 F16 VCCOBank4 VCCOBank5
DM_DQ2 T13 T10
F7 F15 VCCOBank4 VCCOBank5
DM_DQ1 T12 T9
VCCOBank4 VCCOBank5
DM_DQ0 1 8
+3V3
1
2
3
4
U15
10K
U37
8
7
6
5
XC2V1000-4 P15
+3V3
XAWE Y19 CCLK TCK C19 1 2
+3V3 A2 D3 3 4
XFPGA_PROG PROG_B TDI
XFPGA_DONE AB20 DONE TDO D20 5 6 C10
AB2 M0 TMS B20 7 8
47N
10K W3 M1 DXN D5 9 10
AB3 M2 DXP A3
R44 B3 A21
HSWAP_EN VBATT
A B A B A B
A W19 W18 W20

837 0147 042 Rev.A
FORM:
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 7 10

1 2 3 4 5 6 7 8 9 10 11
+2V2 U6 +1V5X
+1V5X
TPS72501
+3V3
2 IN OUT 4
27K
1 EN FB 5
1U 4U7 GND R23

C8 C88 C91 C58 C78 C334 C337 C345 C340 C33 C36 C67 C72 C51 C80 C60 C81 C38 C71 C54 C41 C37 C53 C140 C265 C282 C283
F 120K 47U 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N
3 470N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
C25 C24 R24
+2V2 U105 +1V5

TPS72501 +1V5 +1V5DSP +1V5XDSP
2 IN OUT 4
27K
1 EN FB 5
C347 C350 C357 C361 C353 C367 C352 C369 C373 C355 C372 C354
GND R155
1U 4U7 C267 C204 C170 C171 C205 C234 C230 C157 C161 C163 C211 C156 C210 47N 47N 47N 47N
47N 47N 47N 47N 47N 47N 47N 47N
120K 47U 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
3
C269 C276 R154
+2V2 U106 +1V5DSP

+2V2 U107 +1V5XDSP
TPS72501 TPS72501
2 IN OUT 4
2 IN OUT 4
27K
27K
1 EN FB 5
1 EN FB 5
GND R159 R162
1U 4U7 C270 C215 C188 C167 C191 C166 C214 C216 C207 C173 C172 1U 4U7
GND C272 C225 C178 C224 C195 C177 C192 C220 C226 C175 C181
120K 47U 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
3 120K 47U 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
C271 C277 R156 C274 C281 3
R161
+3V3
D Virtex (XC2V1000) -M-

TP4 TP3 TP5 TP2 TP1
C359 C138 C348 C356 C351 C360 C139 C358 C346 C126 C125 C349 C185 C158 C160 C182 C186 C197 C231 C233 C253
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N
47U
+3V3 +3V3AUX
Virtex (XC2V1000) -S-
C35 C65 C90 C61 C343 C335 C338 C336 C339 C341 C342 C344 C40 C32 C87 C92 C83 C66 C68 C34 C89 C82 C59 C79 C52
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N 47U 47N 47N 47N 47N 47N 47N 47N 47N
C +3V3
TMS320C6205
U111 +3V3AUX
C165 C213 C206 C190 C189 C368 C117 C366 C362 C363 C208 C212 C168 C164 C217 C255 VCC
LP3964-ADJ
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U 2 3
VIN VOUT
10K
R170 C290
1 SD ADJ 4
18K
R171 GND
82P C296 C155 C159 C162 C184 C187 C229 C232 C235
470N 47N 470N 47N 47N 470N 47N 470N
+3V3 C295 33U
100U 5
TMS320C6205 (extra) R169
10K5
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U
B
+3V3
Miscellanea
C77 C109 C12 C3 C107 C2 C16 C18 C17 C1 C64 C55 C108 C135 C132 C118 C122 C101 C103 C102 C123 C121 C124 C94 C137 C146 C98 C99 C203 C47 C9
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U 47U 47U
+3V3
Miscellanea
C142 C97 C105 C100 C129 C22 C95 C20 C111 C96 C62 C112 C19 C13 C86 C21 C84 C5 C6 C57 C63 C4 C7 C56 C114 C144 C113 C115 C252 C128 C85
A
47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 47N 470N 470N 470N 470N
47U 47U 47U
837 0147 042 Rev.A
FORM:
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 8 10

1 2 3 4 5 6 7 8 9 10 11
+3V3
+3V3 +3V3
U81
L8 CY2305 33 R84
300MA XSDCLK_0
6 VDD CLKout 8
+3V3
CLK1 3 R83
F U73 U55
33
C241 1 REF CLK2 2 XSDCLK_1
MT48LCM16A2 MT48LCM16A2 10U 100N +3V3 47N CLK3 5
1 3 +3V3
VDD VDDQ 1 3 4 7 33 R78
14 9
VDD VDDQ C257 C136 GND CLK4
VDD VDDQ 14 9 TB36 R102 XDSPIOCLK
VDD VDDQ
27 VDD VDDQ 43
27 VDD VDDQ 43 22K
VDDQ 49 R146
VDDQ 49
TB32 U97 22K R145
XSDCLK_0 38 CLK 38
C244 W3
P16 22K
XSDCLK_1 CLK TMS320C6205 XTCK_RET
TB34 J3 E17 XTMS 1 2

37 TB31 XDSP_CLK CLKIN TMS
CKE 37 CKE 27N T19 D19 XTDO 3 4
2 XED0 560P CLKOUT2 TDO
DQ0 2 XED16
DQ0 L3 D18 XTDI 5 6 R144
XEA2 23 4 XED1 4.7 CLKMODE0 TDI
A0 DQ1 XEA2 23 4 XED17
A0 DQ1 K5 D17 XTCK 7 8 22K
XEA3 24 5 XED2 R122 PLLV TCK
A1 DQ2 XEA3 24 A1 DQ2 5 XED18 C242 L2 C19 XTRST 9 10
XEA4 25 7 XED3 PLLG TRST
A2 DQ3 L1 F15 XEMU0 11 12
XEA5 26 8 XED4 PLLF EMU0
A3 DQ4 56 E18 XEMU1 13 14
XEA6 29 A4 DQ5 10 XED5
XEA6 29 10 XED21 W67 EMU1
A4 DQ5 C3
XEA7 30 A5 DQ6 11 XED6
XEA7 XED22 R121 XDSP_RESET RESET +3V3
XEA[2:21]
XED[0:31]
30 A5 DQ6 11 A8 C8 R111 22K
XEA8 XED7 NMI RSV0
XED[0:31]
31 A6 DQ7 13 XEA8 XED23
31 A6 DQ7 13 1K00 B15 A4 R113 22K
E XEA9 32 A7 DQ8 42 XED8
XEA9 XED24
R185 EXT_INT7 RSV1
32 A7 DQ8 42 C15 K3 R120 22K
XEA10 XED9 DSPREQ EXT_INT6 RSV2
XEA[2:21]
33 A8 DQ9 44 XEA10 XED25
33 A8 DQ9 44
XEA11 34 A9 DQ10 45 XED10
XEA11 XED26
XDSP_EINT5 A16 EXT_INT5 RSV3 L5 UP4
34 A9 DQ10 45 B16 T18
22 A10 DQ11 47 XED11
22 47 XED27
XDSP_EINT4 EXT_INT4 RSV4 AM29LV160
A10 DQ11 A15 A3
XEA13 35 48 XED12 IACK RSV5 XEA2 25 29 XED0
A11 DQ12 XEA13 35 48 XED28 A0 DQ0
A11 DQ12 B3
36 50 XED13 RSV6 XEA3 24 31 XED1
NC/(A12) DQ13 36 50 XED29 A1 DQ1
NC/(A12) DQ13 C14 B4
XEA15 21 51 XED14 INUM0 RSV7 XEA4 23 33 XED2
BA1 DQ14 XEA14 21 51 XED30 A2 DQ2
BA1 DQ14 B14 C4
XEA14 20 53 XED15 INUM1 RSV8 XEA5 22 35 XED3
BA0 DQ15 XEA15 20 53 XED31 A3 DQ3
BA0 DQ15 A14 K2
INUM2 RSV9 XEA6 21 38 XED4
XSDA10 A4 DQ4
XSDA10 F12 J17
18 39 INUM3 RSV10 XEA7 20 40 XED5
XSDRAS RAS DQMH XBE1 18 39 A5 DQ5
XSDRAS RAS DQMH XBE3 N18
17 15 RSV11 XEA8 19 42 XED6
XSDCAS CAS DQML XBE0 17 15 A6 DQ6
XSDCAS CAS DQML XBE2 A18
16 DMAC0 XEA9 18 44 XED7
XSDWE WE 16 A7 DQ7
XSDWE WE +3V3 TB43
XED[0:31]
C16 DMAC1 TOUT0 E5 XEA10 XED8
XSDCS1 19 CS 8 A8 DQ8 30
XSDCS1 19 CS B17 C5
DMAC2 TINP0 XEA11 XED9
XEA[2:21]
VSSQ 6 7 A9 DQ9 32
VSSQ 6 A17
28 12 DMAC3 XEA12 6 34 XED10
VSS VSSQ 28 12 A10 DQ10
VSS VSSQ A5
41 46 R59 TOUT1 DSP1T1 XEA13 5 36 XED11
VSS VSSQ 41 46 R60 A11 DQ11
+3V3
VSS VSSQ B18 B5
54 52 XDSPREQ 10K PD TINP1 XEA14 4 39 XED12
VSS VSSQ 54 52 1K00 A12 DQ12
VSS VSSQ 10K R112
R110 XEA15 3 41 XED13
D A13 DQ13
C9 CLKX0 CLKX1 E6 CLKX1R0 XEA16 XED14
1K00 2 A14 DQ14 43
DSP_SAFE A9 FSX0 FSX1 A6 FSX1R0 XEA17 XED15
1 A15 DQ15(A-1) 45
XFPGA_WR B10 DX0 DX1 B7 DX1R0 XEA18 48
A16
XFPGA_PROG B9 CLKR0 CLKR1 B6 CLKX0R1 XEA19 17 15

A17 RY/BY
XFPGA_INIT E10 FSR0 FSR1 C7 FSX0R1 XEA20 16 A18
XFPGA_DONE A10 DR0 DR1 A7 DX0R1 XEA21
+3V3 XBOOTMODE0 9 A19
A12 C6
B A
W53 CLKS0 CLKS1
XFLASHCS 26 CE
A B
CR5 28
+3V3
XAOE OE
XDSP_MODE
TB48 TB42 TB40 BAT54 XAWE 11 WE
W44 XBOOTMODE1 1K00 R97 12 RESET
B A U97 47 BYTE
XED[0:31] 22K
22K U79 TMS320C6205 R96 22K
+3V3
5 4 XED0 XED0 R17 V13 XEA2
W48 XBOOTMODE2 ED0 EA2 4K7
6 3 XED1 XED1 R18 W13 XEA3
ED1 EA3 R182
B A 7 2 XED2 XED2 R19 ED2 EA4 R12 XEA4 U97 +3V3 W71 R94
8 1 XED3 XED3 P17 U12 XEA5
C ED3 EA5 TMS320C6205
XED4 P18 W12 XEA6
W39 XBOOTMODE3
U80 ED4 EA6
PCI_CLK1 W5 PCLK VIOP U3 +3V3 +12V
22K XED5 N15 R11 XEA7
ED5 EA7 P3
B A
5 4 XED4
XED6 P19 U11 XEA8
VIOP
U103 CR13 BAT54
ED6 EA8 PCI_AD0 U7 G1 47N 47N
6 3 XED5 AD0 VIOP
XED7 N19 V11 XEA9
7 2 XED6
ED7 EA9 PCI_AD1 W6 AD1 C227 C240 LP2951-3.1
XED8 M17 W11 XEA10
W38 XBOOTMODE4
8 1 XED7
ED8 EA10 PCI_AD2 V3 AD2 PCBE0 V4 PCI_CBE0 10K 8 VIN OUTPUT 1
XED9 XEA11
XEA[2:21]
M18 ED9 EA11 U10 PCI_AD3

XED10 XEA12
V6 AD3 PCBE1 T2 PCI_CBE1 R153
B A
U70 M19 ED10 EA12 V10 PCI_AD4
22K U6 AD4 PCBE2 M3 PCI_CBE2 3 SHUTDWN Vtap 6
XED8
XED11 L19 ED11 EA13 W10 XEA13
PCI_AD5
470K C383
1 8 V5 AD5 PCBE3 G2 PCI_CBE3
XED12 L18 U9 XEA14 470N
W49 XEES0 2 7 XED9 ED12 EA14 PCI_AD6 U5 AD6 5 ERROR FB 7 R143
3 6 XED10
XED13 L17 ED13 EA15 V9 XEA15
PCI_AD7 W4 F2
W66
AD7 PREQ PCI_REQ1
B A XED14 K19 W9 XEA16
4 5 XED11 ED14 EA16 PCI_AD8 U4 D1 PCI_AD20 4 2
AD8 PGNT PCI_GNT1 GND SENSE
XED15 K18 W8 XEA17 B A
ED15 EA17 PCI_AD9 V1
U69 XED16 K17 V8 XEA18
AD9 33 R139 PCI_INTC
W51 XEES1 22K ED16 EA18 PCI_AD10 W2 AD10 PIDSEL H5 47K 7K5
1 8 XED12 XED17 K15 U8 XEA19 W74
ED17 EA19 PCI_AD11 W3 R2
AD11 PDEVSEL PCI_DEVSEL
B
B A 2 7 XED13 XED18 J19 W7 XEA20
ED18 EA20 PCI_AD12 U1 AD12 PFRAME N5 PCI_FRAME
PCI_INTB R142 R141
3 6 XED14 XED19 J18 V7 XEA21
A
ED19 EA21 PCI_AD13 U2 C1
AD13 PINTA
4 5 XED15 XED20 H19
B
W40 XEES2 ED20 TB37 PCI_AD14 V2 AD14 PPAR T3 PCI_PAR W72
B XED21 H18 ED21 BE0 W16 XBE0 PCI_AD15 T1 C2
A
B A 22K U64 XED22 H17 V16
AD15 PRST PCI_RST
ED22 BE1 XBE1 PCI_AD16 N1 P1
1 8 XED16 AD16 PIRDY PCI_IRDY
XED23 G19 W17 UP6 PCI_INTA
ED23 BE2 XBE2 PCI_AD17 N2 R1
2 7 XED17 AD17 PSTOP PCI_STOP
XED24 G18 U16
W50 XLENDIAN
3 6 XED18
ED24 BE3 XBE3 PCI_AD18 M1 AD18 PTRDY N3 PCI_TRDY 2 SCLK
XED25 G17 ED25 PCI_AD19 M2 93C56W
4 5 XED19 AD19
B A XED26 F19 V17
ED26 CE0 XSDCS1 PCI_AD20 H1 B19 3 4
AD20 XSP_DO DI DO
XED27 F18 W18
22K U65 ED27 CE1 XFLASHCS PCI_AD21 J1 AD21 XSP_CS C11
XED28 G15 U17
W31 XEEA1 1 8 XED20 ED28 CE2 SIDCS PCI_AD22 H2 AD22 XSP_CLK C17 6 ORG
XED29 F17 V18
2 7 XED21 ED29 CE3 PCI_AD23 H3 C18 7
AD23 XSP_DI DU
B A XED30 E19
3 6 XED22 ED30 R98 PCI_AD24 G3 AD24 1 CS
+3V3
XED31 F14 P14

4 5 XED23 ED31 HOLD PCI_AD25 F1 D3
AD25 PME PCI_PME
W30 XPLL_CNF0 HOLDA V15 10K PCI_AD26 F5 B1
22K U49 U14
AD26 3.3VauxDET 22K R115
XARE ARE PCI_AD27 F3 A2
AD27 PWR_WKP R93
B A 1 8 XED24 W14
XAOE AOE PCI_AD28 E1 AD28 3.3Vaux B2 22K R114 22K
+3V3
2 7 XED25 V14 U18
XAWE AWE SDRAS/SSOE XSDRAS PCI_AD29 E2 AD29
3 6 XED26 W15 V19
W27 XPLL_CNF1 XARDY ARDY SDCAS/SSADS XSDCAS PCI_AD30 E3 AD30 PSERR P5 PCI_SERR
4 5 XED27 U19 T17 47N
XSDA10 SDA10 SDWE/SSWE XSDWE PCI_AD31 D2 P2
AD31 PPERR PCI_PERR C145
A B A
22K U48 10K PCI_AD[0:31]
837 0147 042 Rev.A
+3V3
1 8 XED28
W24 XPLL_CNF2
XED29 R100
FORM:
2 7
3 6 XED30
B A
4 5 XED31
W23
SHEET DESCRIPTION:
by EpD Number: 950 1080 000 SE H 9 10

1 2 3 4 5 6 7 8 9 10 11
U37
XC2V1000-4
U29
BANK 6 BANK 7
MT48LCM16A2
33 U27 1 VDD VDDQ 3
+3V3 V5 L2
1 8 14 9 EXTECG IO IO CPU_A1
XDM_CLK VDD VDDQ
IMOT1 U5 IO IO L3 CPU_A14
F XDM_CKE 2 7 27 VDD VDDQ 43
U37 XDM_A0 3 6 VDDQ 49 CPU_D8 Y2 IO/VRN6 IO L4 CPU_A13
Y1 L5
XC2V1000-4 XDM_A1 4 5 38 CLK
CPU_D10 IO/VRP6 IO CPU_D14
IESCAN V4 IO IO/VREF7 K1 CPU_D2
BANK 2 BANK 3 33 U41 37 IPROBE V3 IO/VREF6 IO K2 CPU_D5
CKE
XDM_A2 1 8 ITIMING W2 IO IO K3 CPU_A23
DQ0 2
XDM_A3 2 7 CPU_A6 W1 IO IO K4 CPU_D12
XDM_DQ0 C21 IO IO M21 XEA4 23 A0 DQ1 4
XDM_A4 4 5 IECG U4 IO IO L6 CPU_D4
XDM_DQ2 C22 IO IO M20 IROW11 24 A1 DQ2 5
3 6 U3 K6
XDM_DQ15 E18 IO/VRP2 IO M19 XEA8
XDM_A5 25 A2 DQ3 7 CPU_A7 IO IO TB1
V2 K5
XDM_DQ14 F18 IO/VRN2 IO M18 IROW2 33 U40 26 A3 DQ4 8 CPU_A10 IO IO TB2
V1 J5
XDM_DQ3 D21 IO IO/VREF3 M17 IROW0 4 5 29 A4 DQ5 10 CPU_D11 IO IO TB3
XDM_A6 U2 J1
XDM_DQ4 D22 IO/VREF2 IO N17 IROW4 3 6 30 A5 DQ6 11 CPU_SIZ0 IO IO/VREF7 TB4
XDM_A7 U1 J2
E19 N22 31 13 CPU_A8 IO/VREF6 IO CPU_D7
XDM_DQ13 IO IO XARDY 2 7 A6 DQ7
XDM_A8 T5 J3
E20 N21 32 42 INT7 IO IO CPU_A4
XDM_DQ1 IO IO IROW3 1 8 A7 DQ8
XDM_A9 R5 J4
E21 N20 33 44 ITBASE IO IO CPU_A5
XDM_DQ5 IO IO XED8 A8 DQ9
U31 IPOS T4 IO IO H1 CRT_CLK
XDM_DQ6 E22 IO IO N19 XED9 33 34 A9 DQ10 45
CPU_A9 T3 IO IO H2 CPU_D0
XDM_DQ12 F19 IO IO N18 XED10 XDM_A10 1 8 22 A10 DQ11 47
CPU_D9 T2 IO IO H3 CPU_D6
XDM_DQ11 F20 IO IO P18 XED11 XDM_A11 3 6 35 A11 DQ12 48
E INT6 T1 IO IO H4 CPU_FC2
XDM_DQ7 F21 IO IO/VREF3 P22 XEA12 XDM_A12 2 7 36 NC/(A12) DQ13 50
FSWITCH R4 IO IO/VREF7 J6 CPU_A12
XDM_DQML F22 IO/VREF2 IO P21 XEA3 4 5 21 BA1 DQ14 51
IMOT0 R3 IO/VREF6 IO H5 CPU_A17
XDM_DQ10 G18 IO IO P20 XEA19 20 BA0 DQ15 53
CPU_A0 R2 IO IO G1 INT5
XDM_A11 H18 IO IO P19
CPU_RW R1 IO IO G2 INT4
XDM_DQ8 G19 IO IO R22 IENCLA 18 RAS DQMH 39
CPU_DSACK0 P6 IO IO G3 INT1
XDM_DQ9 G20 IO IO R21 IENCLB 17 CAS DQML 15
G21 R20 33 U32 16 CPU_FC0 P5 IO IO G4 INT3
XDM_WE IO IO XEA16 WE
XDM_BA1 4 5 CPU_A21 P4 IO IO F1 CRT_BLANK
XDM_DQMH G22 IO IO R19 XEA5 19 CS
XDM_BA0 3 6 CPU_A22 P3 IO IO F2 CPU_SIZ1
XDM_A0 H19 IO IO/VREF3 R18 VSSQ 6
XDM_RAS 2 7 CPU_DS P2 IO IO/VREF7 F3 CPU_FC3
XDM_CKE H20 IO/VREF2 IO P17 IROW6 28 VSS VSSQ 12
XDM_CAS 1 8 CPU_D1 P1 IO/VREF6 IO F4 INT2
XDM_CS H21 IO IO T22 IENCRA 41 VSS VSSQ 46
CPU_DSACK1 N6 IO IO G5 CPU_FC1
XDM_CAS H22 IO IO T21 IENCRB 54 VSS VSSQ 52
J17 T20 33 U28 CPU_A20 N5 IO IO F5 CPU_A19
XDM_A6 IO IO XED12
XDM_WE 2 7 CPU_D3 N4 IO IO E1
XDM_A8 J18 IO IO T19 GRA12
XDM_CS 4 5 CPU_D13 N3 IO IO E2
XDM_A10 J19 IO IO U22 XED13
XDM_DQML 1 8 CPU_A18 N2 IO IO E3 MNYIRQ
XDM_A1 J20 IO IO U21 GRA11
TB27 XDM_DQMH 3 6 CPU_D15 N1 IO IO E4 BRDREV4
XDM_RAS J21 IO IO/VREF3 U20 XEA14
D XDM_BA0 J22 IO/VREF2 IO U19 XEA15
CPU_AS M6 IO IO/VREF7 D1 BRDREV0
K17 T18 33 U22 CPU_A16 M5 IO/VREF6 IO D2 BRDREV1
XDM_A5 IO IO XDSP_EINT4
XDM_DQ15 1 8 CPU_A15 M4 IO IO/VRN7 C1 BRDREV2
XDM_A7 K18 IO IO U18 IROW7
2 7 M3 C2
K19 V22 XDM_DQ14 CPU_A11 IO IO/VRP7 BRDREV3

XDM_A9 IO IO IROW5
XDM_DQ13 3 6 CPU_A2 M2 IO IO E5 BRDREV5

XDM_A12 K20 IO IO V21 XED14
TB28 XDM_DQ12 4 5 CPU_A3 M1 IO IO E6 PANPOS
XDM_BA1 K21 IO IO V20 XED15
XDM_A2 K22 IO IO V19
+3V3
+3V3
U24 T6 VCCOBank6 VCCOBank7 L7
XDM_A4 L17 IO IO/VREF3 W22 XDSP_EINT5 33
R6 VCCOBank6 VCCOBank7 K7
XDM_A3 L18 IO/VREF2 IO W21 IROW15 XDM_DQ11 1 8
P7 VCCOBank6 VCCOBank7 J7
XEA2 L19 IO IO/VRP3 Y22 IROW13 XDM_DQ10 2 7
N7 VCCOBank6 VCCOBank7 H6
IROW12 L20 IO IO/VRN3 Y21 XEA20 XDM_DQ9 3 6
M7 VCCOBank6 VCCOBank7 G6
L21 IO IO W20 XDM_DQ8 4 5
IROW9 L22 IO IO AA20 XEA21 TRKYB +3V3
33 U25
TRKYA
+3V3
+3V3
L16 VCCOBank2 VCCOBank3 T17 XDM_DQ7 4 5

TRKXB
K16 VCCOBank2 VCCOBank3 R17 XDM_DQ6 3 6
TRKXA
J16 VCCOBank2 VCCOBank3 P16 XDM_DQ5 2 7
C H17 N16 1 8
6
5
7
8
VCCOBank2 VCCOBank3 XDM_DQ4 22K 22K 22K 22K 22K 22K

G17 M16
VCCOBank2 VCCOBank3 R7 R10 R8 R5 R6 R9
10K 33 U23
2
BRDREV0
R36 U45 XDM_DQ3 4 5
BRDREV1
BUZZER XDM_DQ2 3 6
BRDREV2
XDM_DQ1 2 7
1K00 BRDREV3
3
4
2
1
XDM_DQ0 1 8
BRDREV4
BRDREV5
ALIMENTAZIONI IMPLICITE
1
----------------------- +3V3
NET: GND 22K 22K 22K 22K 22K 22K +3V3
NET: +1V5 ALIMENTAZIONI MODIFICATE COMPONENTI NON MONTATI:
--------
U1.10 U37.D19 U95.A22 U96.C10 U97.A11 U97.N7
--------- ------------------- ------------------ R14 R17 R15 R12 R13 R16
U95.F17 U95.H16 U95.T7
U104.7 U37.D4 U95.AA2 U96.C12 U97.A13 U97.N8 NET: +1V5DSP
U95.F6 U95.H7 U95.T8 C106 EQUIP_LEVEL 2 C368 EQUIP_LEVEL 2
U108.3 U37.J10 U95.AA21 U96.C13 U97.B11 U97.N9 ------------
U95.G15 U95.R16 U95.U17 C120 EQUIP_LEVEL 2 C369 EQUIP_LEVEL 2
U16.1 U37.J11 U95.AB1 U96.E12 U97.B13 U97.V12
U95.G16 U95.R7 U95.U6
U96.B12 U96.J5
C152 EQUIP_LEVEL 2 C370 EQUIP_LEVEL 2 L1
U16.14 U37.J12 U95.AB22 U96.G10 U97.C10 UP1.27
U95.G7 U95.T15
U96.E14 U96.M15
C153 EQUIP_LEVEL 2 C371 EQUIP_LEVEL 2
U16 Board Revision 100U
U16.15 U37.J13 U95.B2 U96.G11 U97.C12 UP1.46
U95.G8 U95.T16
U96.F10 U96.M5
C154 EQUIP_LEVEL 2 C372 EQUIP_LEVEL 2 ADV7125-140
U16.2 U37.J14 U95.B21 U96.G12 U97.C13 UP2.27 U96.F9 U96.N17
C198 EQUIP_LEVEL 2 C373 EQUIP_LEVEL 2
U16.25 U37.J9 U95.C20 U96.G13 U97.E12 UP2.46 U96.G5 U96.P12 24 13
C199 EQUIP_LEVEL 2 C384 EQUIP_LEVEL 2 CRT_CLK CLK VAA
U16.26 U37.K10 U95.C3 U96.G7 U97.G10 UP3.27 NET: +3V3 U96.H15 U96.P6
C200 EQUIP_LEVEL 2 C48 EQUIP_LEVEL 2 29
U16.39 U37.K11 U95.D19 U96.G8 U97.G11 UP3.46 --------- U96.J15 U96.P9 11 VAA C28 C48 C50 C31 C26 C27 C30 C49 C23
B C201 EQUIP_LEVEL 2 C49 EQUIP_LEVEL 2 CRT_BLANK BLANK
U16.40 U37.K12 U95.D4 U96.G9 U97.G12 UP4.27 U1.20 U8.14 U97.E8 U96.J2 U96.U13 30
C202 EQUIP_LEVEL 2 C50 EQUIP_LEVEL 2 12 VAA
U2.10 U37.K13 U95.J10 U96.H10 U97.G13 UP4.46 U104.14 U9.16 U97.E9
C23 EQUIP_LEVEL 2 J10 EQUIP_LEVEL 2
SYNC R33 100N 100N 10N 10N 10N 100N 100N 100N 10U
U3.10 U37.K14 U95.J11 U96.H11 U97.G7 UP5.5 U2.20 U96.B8 U97.F6 NET: +3V3 560
C246 EQUIP_LEVEL 2 J8 EQUIP_LEVEL 2
U35.109 U37.K9 U95.J12 U96.H12 U97.G8 UP6.5 U3.20 U96.E11 U97.H14 --------- 37
C248 EQUIP_LEVEL 2 J9 EQUIP_LEVEL 2 1K00 41 Rset
U35.118 U37.L10 U95.J13 U96.H13 U97.G9 U35.110 U96.E13 U97.J6 U36.B11 U36.K3 CRT_RED0 R0
C26 EQUIP_LEVEL 2 L1 EQUIP_LEVEL 2 36
U35.127 U37.L11 U95.J14 U96.H7 U97.H10 U35.119 U96.E7 U97.K14 U36.C14 U36.M13
C27 EQUIP_LEVEL 2 P12 EQUIP_LEVEL 2 R25 CRT_RED1 42 R1
Vref
U35.129 U37.L12 U95.J9 U96.H8 U97.H11 U35.130 U96.E8 U97.L15 U36.C4 U36.M3 35
C28 EQUIP_LEVEL 2 P13 EQUIP_LEVEL 2 43 COMP
U35.139 U37.L13 U95.K10 U96.H9 U97.H12 U35.140 U96.E9 U97.L6 U36.C7 U36.N4 CRT_RED2 R2
C30 EQUIP_LEVEL 2 P14 EQUIP_LEVEL 2
U35.18 U37.L14 U95.K11 U96.J10 U97.H13 U35.19 U96.F6 U97.M14 U36.D2 U36.N9 44
C31 EQUIP_LEVEL 2 P17 EQUIP_LEVEL 2 CRT_RED3 R3
U35.30 U37.L9 U95.K12 U96.J11 U97.H7 U35.31 U96.H14 U97.P15 U36.F13 U36.P7
C334 EQUIP_LEVEL 2 P5 EQUIP_LEVEL 2 45
U35.40 U37.M10 U95.K13 U96.J12 U97.H8 U35.41 U96.J6 U97.R10 U36.G3 U36.P9 CRT_RED4 R4
U35.49 U37.M11 U95.K14 U96.J13 U97.H9 U35.50 U96.K14 U97.R13 U36.K14 46
C336 EQUIP_LEVEL 2 R10 EQUIP_LEVEL 2 CRT_RED5 R5
U35.54 U37.M12 U95.K9 U96.J7 U97.J10 U35.59 U96.L15 U97.R14
C337 EQUIP_LEVEL 2 R103 EQUIP_LEVEL 2 47 34 P17 R34 75
U35.58 U37.M13 U95.L10 U96.J8 U97.J11 U35.68 U96.L6 U97.R3 NET: +1V5X CRT_RED6 R6 IOR
C338 EQUIP_LEVEL 2 R13 EQUIP_LEVEL 2 1 2
U35.6 U37.M14 U95.L11 U96.J9 U97.J12 U35.7 U96.M14 U97.R6 ----------
C339 EQUIP_LEVEL 2 R25 EQUIP_LEVEL 2 CRT_RED7 48 R7 R37
U35.67 U37.M9 U95.L12 U96.K1 U97.J13 U35.74 U96.P15 U97.R7 U37.F17 U37.R16 33 3 4
C340 EQUIP_LEVEL 2 R33 EQUIP_LEVEL 2 IOR
U35.73 U37.N10 U95.L13 U96.K10 U97.J7 U35.86 U96.R10 U97.R8 U37.F6 U37.R7
C341 EQUIP_LEVEL 2 R34 EQUIP_LEVEL 2 75 5 6
U35.88 U37.N11 U95.L14 U96.K11 U97.J8 U35.92 U96.R13 U97.R9 U37.G15 U37.T15 3
U35.96 U37.N12 U95.L9 U96.K12 U97.J9 U35.94 U96.R14 U97.U15 U37.G16 U37.T16
C342 EQUIP_LEVEL 2 R35 EQUIP_LEVEL 2 CRT_GREEN0 G0 7 8
R35 75
C343 EQUIP_LEVEL 2 R37 EQUIP_LEVEL 2 4
U36.C11 U37.N13 U95.M10 U96.K13 U97.K1 U39.11 U96.R3 UP1.37 U37.G7 U37.T7 CRT_GREEN1 G1
C344 EQUIP_LEVEL 2 R38 EQUIP_LEVEL 2 32 9 10
U36.C5 U37.N14 U95.M11 U96.K7 U97.K10 U39.33 U96.R6 UP2.37 U37.G8 U37.T8 5 IOG
C345 EQUIP_LEVEL 2 R39 EQUIP_LEVEL 2 CRT_GREEN2 G2
U36.C8 U37.N9 U95.M12 U96.K8 U97.K11 U4.14 U96.R7 UP3.37 U37.H16 U37.U17
U36.D13 U37.P10 U95.M13 U96.K9 U97.K12 U5.14 U96.R8 UP4.37 U37.H7 U37.U6
CRT_GREEN3 6
G3
R38
C347 EQUIP_LEVEL 2 R7 EQUIP_LEVEL 2 31
U36.D3 U37.P11 U95.M14 U96.L10 U97.K13 U51.11 U96.R9 UP5.8 7 IOG
NET: +3V3AUX C348 EQUIP_LEVEL 2 R8 EQUIP_LEVEL 2 CRT_GREEN4
TB17
TB18
TB19
TB20
TB25
TB26
U36.G13 U37.P12 U95.M9 U96.L11 U97.K7 U51.33 U96.U15 UP6.8 G4

TB7
TB8
------------ C349 EQUIP_LEVEL 2 R88 EQUIP_LEVEL 2 8 75

U36.G2 U37.P13 U95.N10 U96.L12 U97.K8 U52.14 U97.B8 CRT_GREEN5 G5
A U36.H13 U37.P14 U95.N11 U96.L13 U97.K9 U57.14 U97.E11
U37.A12 U95.A12 C350 EQUIP_LEVEL 2 U16 EQUIP_LEVEL 2
9
U37.AA1 U95.AA1 C351 EQUIP_LEVEL 2 U36 EQUIP_LEVEL 2 CRT_GREEN6 G6
U36.H3 U37.P9 U95.N12 U96.L7 U97.L10 U58.20 U97.E13
837 0147 042 Rev.A
U37.AA22 U95.AA22 C352 EQUIP_LEVEL 2 U94 EQUIP_LEVEL 2 10 IOB 28

U36.J3 U37.W19 U95.N13 U96.L8 U97.L11 U59.20 U97.E7 CRT_GREEN7 G7
U37.AB11 U95.AB11 C353 EQUIP_LEVEL 2 U98 EQUIP_LEVEL 2
U36.K13 U37.W4 U95.N14 U96.L9 U97.L12
U37.B1 U95.B1 C354 EQUIP_LEVEL 2 UP5 EQUIP_LEVEL 2 R39
FORM:
U36.M2 U37.Y20 U95.N9 U96.M10 U97.L13 27

U37.B22 U95.B22 C355 EQUIP_LEVEL 2 UP6 EQUIP_LEVEL 2 16 IOB
U36.N10 U37.Y3 U95.P10 U96.M11 U97.L7 CRT_BLUE0 B0
U37.L1 U95.L1 C356 EQUIP_LEVEL 2 Y1 EQUIP_LEVEL 2 75
U36.N13 U39.12 U95.P11 U96.M12 U97.L8 17
U37.M22 U95.M22 C357 EQUIP_LEVEL 2 CRT_BLUE1 B1
U36.N3 U39.34 U95.P12 U96.M13 U97.L9
C358 EQUIP_LEVEL 2 18
U36.N7 U4.7 U95.P13 U96.M7 U97.M10 CRT_BLUE2 B2
NET: +1V5XDSP C359 EQUIP_LEVEL 2
U37.A1 U5.7 U95.P14 U96.M8 U97.M11 19
------------- C360 EQUIP_LEVEL 2 CRT_BLUE3 B3
U37.A22 U51.12 U95.P9 U96.M9 U97.M12
U97.B12 U97.J5 C361 EQUIP_LEVEL 2 20
U37.AA2 U51.34 U95.W19 U96.N10 U97.M13 CRT_BLUE4 B4
U97.E14 U97.M15 C362 EQUIP_LEVEL 2
U37.AA21 U52.7 U95.W4 U96.N11 U97.M7 21
U97.F10 U97.M5 C363 EQUIP_LEVEL 2 CRT_BLUE5 B5 +3V3
U37.AB1 U57.7 U95.Y20 U96.N12 U97.M8
U97.F9 U97.N17 C364 EQUIP_LEVEL 2 22
SHEET U37.AB22 U58.10 U95.Y3 U96.N13 U97.M9 CRT_BLUE6 B6 DESCRIPTION:
U97.G5 U97.P12 C365 EQUIP_LEVEL 2 "7300" PROCESSORS BOARD
A2 U37.B2
U37.B21
U37.C20
U59.10
U8.7
U9.8
U96.A11
U96.A13
U96.B11
U96.N7
U96.N8
U96.N9
U97.N10
U97.N11
U97.N12
U97.H15
U97.J15
U97.P6
U97.P9
C366 EQUIP_LEVEL 2
C367 EQUIP_LEVEL 2
CRT_BLUE7 23 B7 PSAVE 38
by EpD U37.C3 U95.A1 U96.B13 U96.V12 U97.N13

U97.J2 U97.U13
Number: 950 1080 000 SE H 10 10
1 2 3 4 5 6 7 8 9 10 11
+3V3 +3V3
+3V3
R176
330U
L8
U18
R209
4K7
U7
R184
4K7
TMS320VC5502 U16
1K00
74LCX00
60 PVDD PSENSE 61 CY7C1327 EMIFCE3 1
F EMIFCLK2 3 UP3
C242 C241 89 CLK VDDQ 4 EMIFA19 2 U7
CLK40A 63 152 EMIFD0 11 29F040-120
470N 47N X2/CLKIN D0/HPID0/EMIFD0 VDDQ 74LCX00 EAOE/ESOE 24
151 EMIFD1 83 20 4 OE
D1/HPID1/EMIFD1 ADV VDDQ
EMIFD2 6 22 CE
R251 62 X1 D2/HPID2/EMIFD2 150 84 ADSP VDDQ 27
5
EMIFD3 EARE/ESADS 31 WE
D3/HPID3/EMIFD3 149 85 ADSC VDDQ 54
33
TMSCLK 54 147 EMIFD4 61
CLKOUT D4/HPID4/EMIFD4 VDDQ
146 EMIFD5 EMIFA0 37 70 EMIFA0 12 13 EMIFD0
D5/HPID5/EMIFD5 A0 VDDQ A0 O0
R227
2
EMIFA0 112 145 EMIFD6 EMIFA1 36 77 EMIFA1 11 14 EMIFD1
47
EMIFA1 111 143 EMIFD7 EMIFA2 35 EMIFA2 10 15 EMIFD2

C186 EMIFA2 110 142 EMIFD8 EMIFA3 34 EMIFA3 9 17 EMIFD3
47P A5/HPIA3/EMIFA5 D9/HPID9/EMIFD9 A4 A4 O4
2 A6/HPIA4/EMIFA6 D10/HPID10/EMIFD10 A5 A5 O5
+3V3 EMIFA6 104 137 EMIFD12 EMIFA7 99 EMIFA7 5 21 EMIFD7
EMIFD0
EMIFA7 103 136 EMIFD13 EMIFA8 82 58 EMIFA8 27
EMIFD1
R216 EMIFA9 101 134 EMIFD15 EMIFA10 80 62
EMIFD2
EMIFA10 23
E 4K7 EMIFD3
EMIFD4
EMIFD5
R218 A14/HPIA12/EMIFA14 D18/PGPIO6/EMIFD18 A13 DQ5
EMIFD6
A13
4K7 A15/HPIA13/EMIFA15 D19/PGPIO7/EMIFD19 A14 DQ6 A14
EMIFD7
EMIFD8
R219 EMIFA16 90 126 EMIFD22 EMIFA17 50 9
EMIFD9
EMIFA17 30
A18/PGPIO0/EMIFA18 D22/PGPIO10/EMIFD22 A17 DQ9 A17
4K7 EMIFD10
EMIFA17 89 125 EMIFD23 43 12 EMIFA18 1
A19/PGPIO1/EMIFA19 D23/PGPIO11/EMIFD23 NC(A18) DQ10 A18
EMIFD11
EMIFA18 88 123 EMIFD24 88 13
A20/PGPIO2/EMIFA20 D24/PGPIO12/EMIFD24 GW DQ11
EMIFD12 +3V3
EMIFA19 87 122 EMIFD25 18
A21/PGPIO3/EMIFA21 D25/PGPIO13/EMIFD25 DQ12
R220 EMIFA[0:19] 120 EMIFD26 EAWE/ESWE 87 19
EMIFD13 UP2
D26/PGPIO14/EMIFD26 BWE DQ13
4K7 EMIFD14
TMSINT0 8 INT0 D27/PGPIO15/EMIFD27 119 EMIFD27 EMIFBE0 93 BWS0 DQ14 22 29F040-120
R183
EMIFD15
TMSINT1 10 118 EMIFD28 EMIFBE1 94 23 24
1K00
INT1 D28/PGPIO16/EMIFD28 +3V3 BWS1 DQ15 OE
R221 TMSINT2 11 INT2 D29/PGPIO17/EMIFD29 116 EMIFD29 22 CE
4K7 TMSINT3 13 115 EMIFD30 31 31
INT3 D30/PGPIO18/EMIFD30 MODE WE
TMSINT[0:3]
TMSNMI 14 114 EMIFD31
NMI/WDTOUT D31/PGPIO19/EMIFD31
EMIFD[0:31]
TMSIACK 15 EMIFCE0 98 74
R217 IACK CE1 DP0 EMIFA0 12 A0 O0 13 EMIFD8
D RESET 162 RESET C0/PGPIO20/ARE 86 EARE/ESADS R246 97 CE2 DP1 24 EMIFA1 11 14 EMIFD9
4K7 A1 O1
85 EAOE/ESOE 4K7 92
C1/PGPIO21/AOE CE3 EMIFA2 10 15 EMIFD10
A2 O2
5 84 EAWE/ESWE
GPIO0 C2/PGPIO22/AWE EMIFA3 9 17 EMIFD11
R213
R215
R197
EAOE/ESOE 86 A3 O3
4 82 EARDY OE
1K00
1K00
GPIO1 C3/PGPIO23/ARDY EMIFA4 8 18 EMIFD12
FREADY A4 O4
R83
1K00
1K00
3 81 EMIFCE0
GPIO2 C4/PGPIO24/CE0 EMIFA5 7 19 EMIFD13
2 0 64 A5 O5
2 79 EMIFCE1 ZZ
GPIO4 C5/PGPIO25/CE1 EMIFA6 6 20 EMIFD14
A6 O6
R212 R252 1 GPIO6 C6/PGPIO26/CE2 78 EMIFCE2 R245 EMIFA7 5 21 EMIFD15
A7 O7
1K00 176 72 EMIFCE3
33 GPIO7 C7/PGPIO27/CE3 EMIFA8 27
EMIFCE[0:3] A8
XCCLK 55 71 EMIFBE0 EMIFD[0:15]
XF C8/PGPIO28/BE0 EMIFA9 26 A9
70 EMIFBE1
R199 C9/PGPIO29/BE1 EMIFA10 23 A10
SCLKR0 17 69 EMIFBE2
1K00 CLKR0 C10/PGPIO30/BE2 EMIFA11 25 A11
SDR0 18 68 EMIFBE3
DR0 C11/PGPIO31/BE3 U19 EMIFA12 4
EMIFBE[0:3] A12
SFSR0 19 67
R232 FSR0 C12/PGPIO32/SDCKE
CY7C1327 EMIFA13 28 A13
SCLKX0 20 66
4K7 CLKX0 C13/PGPIO33/SOE EMIFA14 29
89 4 A14
SDX0 22 58 TMSHOLD 4K7 CLK VDDQ
DX0 C14/PGPIO34/HOLD EMIFA15 3
11 A15
SFSX0 23 57 TMSHOLDA VDDQ
R229 FSX0 C15/PGPIO35/HOLDA R253 83 20
EMIFA16 2 A16
SCLKR1 24 ADV VDDQ
CLKR1 EMIFA17 30
4K7 84 27 A17
SDR1 25 74 ADSP VDDQ
C DR1 ECLKIN EMIFA18 1
85 54 A18
SFSR1 26 FSR1 ECLKOUT1 76 TB31 ADSC VDDQ
R234 SCLKX1 EMIFCLK2 VDDQ 61 EMIFA[0:18]
28 CLKX1 ECLKOUT2 75
EMIFA0 37 70
1K00 SDX1 27 64 A0 VDDQ
DX1 EMIFCLKS
R198
EMIFA1 36 77
SFSX1 30 A1 VDDQ
FSX1
EMIFA2 35
47
XDONE 31 175 HD0 A2

DR2 HD0/PGPIO36
R231 XPROG HD1
EMIFA3 34 A3
32 DX2 HD1/PGPIO37 173 C130 EMIFA4
4K7 HD2 33 A4
HD2/PGPIO38 172 33P
FLASH HD3
EMIFA5 32 A5
UP1
38 SP0/GPIO3/CLKX2 HD3/PGPIO39 170
SP1 37 169 HD4
EMIFA6 100 A6 AM29LV160
SP1/UARTTX/CLKR2 HD4/PGPIO40
EMIFA7 99 EMIFA0 25 29 EMIFD0
XINIT 35 167 HD5 A7 A0 DQ0
R233 SP2/GPIO5/FSX2 HD5/PGPIO41
EMIFA8 82 58
EMIFD16
EMIFA1 24 31 EMIFD1
SP3 34 166 HD6 A8 DQ0 A1 DQ1
4K7 SP3/UARTRX/FSR2 HD6/PGPIO42 EMIFD17
EMIFA9 81 59 EMIFA2 23 33 EMIFD2
40 164 HD7 A9 DQ1 A2 DQ2
SCL HD7/PGPIO43 EMIFD18
41 HD[0:7] A10 DQ2 A3 DQ3
SDA EMIFD19
R238 43 HAS
EMIFA11 44 A11 DQ3 63 EMIFA4 21 A4 DQ4 38 EMIFD4
HC0/PGPIO44/HAS EMIFD20
1K00 EMIFA12 45 68 EMIFA5 20 40 EMIFD5
160 42 XBUSY A12 DQ4 A5 DQ5
TCK HC1/PGPIO45/HBIL EMIFD21
158 A13 DQ5 A6 DQ6
TDI EMIFD22
R242 156 46 HCNTL0 4K7
TDO HCNTL0 EMIFD23
B 1K00 EMIFA15 48 73 EMIFA8 8 30 EMIFD8
161 45 HCNTL1 A15 DQ7 A8 DQ8
TMS HCNTL1 R249 EMIFA16 49 8
EMIFD24
EMIFA9 7 32 EMIFD9
159 44 XCS A16 DQ8 A9 DQ9
TRST HCS EMIFD25
R211 155 48 XWR
EMU0 HR/W EMIFD26
4K7 43 12 EMIFA11 5 36 EMIFD11
154 51 HDS1 NC(A18) DQ10 A11 DQ11
EMU1 HDS1 EMIFD27
88 13 EMIFA12 4 39 EMIFD12
49 HDS2 EMIFA[0:17] GW DQ11 A12 DQ12
HDS2 EMIFD28
18 EMIFA13 3 41 EMIFD13
HRDY 52 HRDY R256 DQ12
EMIFD29
A13 DQ13
87 19 EMIFA14 2 43 EMIFD14
TIMER0 7 59 HINT 4K7 BWE DQ13 A14 DQ14
4K7 TIM0 HINT EMIFD30
EMIFBE2 93 22 EMIFA15 1 45 EMIFD15
TIMER1 6 163 BWS0 DQ14 A15 DQ15(A-1)
TIM1 HPIENA EMIFD31
R210 EMIFBE3 94 BWS1 DQ15 23 EMIFA16 48 A16
EMIFD[0:15]
+3V3 1K00 EMIFBE[0:3] EMIFA17 17 15 FREADY
EMIFD[0:31] A17 RY/BY
31 EMIFA18 16
R206 MODE A18
EMIFA19 9
R243
R244
R248
A19
1K00
1K00
98 74 EMIFA[0:19]
4K7
CE1 DP0
R196
R186
R185
2
2 97 24 EMIFCE1 26
CE2 DP1 CE
4K7
4K7
R230
U7
47
92 EAOE/ESOE 28
CE3 OE
4K7
C104 J8
R200 R173 EAWE/ESWE 11 WE 74LCX00
86 OE RESET 13
47P 4K7 4K7 12 RESET 11
R266
R237
2 1
47 12
1K00
1K00
A 2 BYTE
+3V3
64
R85
4 3
1K00
ZZ
837 0147 042 Rev.A
6 5 U7
8 7 74LCX00
FORM:
4K7 10
10 9 8
R444 12 11
R180 9
47 14 13
VICINO PIN U18

33P
C448

"7300" VIDEO BOARD
by EpD
Nr. O.V.:
E.O.C. EVENT: IND200500121 Number: 950 1081 000 SE H 1 11
1 2 3 4 5 6 7 8 9 10 11
+3V3
R205
R208
R195
R194
R204
1K00
1K00
4K7
4K7
4K7
TB19
NOTE
F TMSINT[0:3]
TB1
NOTE VXD[0:7]
TB7
VMD[0:15]
NOTE
LA[0:4]
U15 U15 U15 U15
XC2S300 XC2S300 XC2S300 XC2S300
MADD[0:12]
NOTE
MDAT[0:15]
MBADD[0:1] R193
NOTE
33
MDAT0 A3 A11 MCLK XBUSY C21 L22 EMIFD15 VMA14 U12 U9 VMA28 VXD0 M1 C1 ECGSCLK
I/O GCK2,I I/O(DOUT,BUSY) I/O(TRDY) I/O I/O I/O(TRDY) I/O
MDAT1 A4 A12 MCS HD0 C22 M17 EMIFBE3 VMA8 U13 U10 VMA22 VXD4 M2 C2 PANPOS
I/O I/O(DLL) I/O(DIN,D0) I/O I/O I/O I/O I/O
MDAT2 A5 A13 MBADD0 SFSR1 D20 M18 EAWE/ESWE VMA2 U14 U11 VMA17 VXINIT1 M3 D1 ECGCONV
MDAT3 A6 I/O I/O A14 MBADD1 EMIFD6 D21 I/O(VREFBank2) I/O M19 EMIFA12 VMA15 V12 I/O I/O V6 LD3 TB8 M4 I/O I/O D2
MDAT4 A7 A15 MADD10 EMIFD4 D22 M20 EMIFD23 VMA9 V13 V7 LA4 BRD0 M5 D3
MDAT5 A8 A16 MADD0 SP3 E19 M21 EMIFD19 VMA3 V14 V8 LDEN BRD1 M6 E1 ECGDATA
E I/O I/O I/O I/O I/O I/O(VREFBank5) I/O I/O
MDAT6 A9 A17 MADD1 SFSX1 E20 M22 EMIFD18 VMD13 V15 V9 VMA29 VXD1 N1 E2
I/O I/O I/O I/O I/O(VREFBank4) I/O I/O I/O(VREFBank7)
MDAT7 A10 A18 MADD2 EMIFD3 E21 N17 HD4 VMD8 V16 V10 VMA23 VXD5 N2 E3
I/O I/O I/O I/O(D4) I/O I/O(VREFBank5) I/O I/O
MDAT15 B3 A19 MADD3 EMIFD1 E22 N18 HINT VMD3 V17 V11 VMA18 VXINIT0 N3 F1
I/O I/O I/O I/O(VREFBank3) I/O I/O I/O(VREFBank6) I/O
MDAT14 B4 A20 XWR HAS F18 N19 EMIFA0 VMA16 W12 W5 LD7 VXBUSY N4 F2
I/O I/O(WRITE) I/O I/O I/O I/O I/O I/O(VREFBank7)
R192
2
MDAT13 B5 B12 MCKE SP1 F19 N20 EMIFA13 VMA10 W13 W6 LD2 BRWR N5 F3
VICINO U6 PRIMA DI R21
47
MDAT12 B6 B13 MADD11 EMIFCE3 F20 N21 EMIFD16 VMA4 W14 W7 LA3 BRCS N6 F4
I/O(VREFBank0) I/O(VREFBank1) I/O I/O I/O I/O I/O I/O
MDAT11 B7 B14 MADD9 EMIFD2 F21 N22 EMIFD17 VMD14 W15 W8 LSECG VXD2 P1 F5 C102
MDAT10 B8 B15 MADD8 EMIFD5 F22 P17 TMSHOLDA VMD9 W16 W9 VMRW VXD6 P2 G1
I/O I/O I/O I/O I/O I/O I/O I/O 47P
MDAT9 B9 B16 MADD7 EMIFA10 G18 P18 HCNTL0 VMD4 W17 W10 VMA24 VXCS1 P3 G2
I/O I/O I/O I/O I/O I/O I/O I/O 2
MDAT8 B10 B17 MADD6 HDS1 G19 P19 EMIFA2 VMAUX1 W18 W11 VMA19 VXDONE1 P4 G3
MCLK B11 I/O(DLL) I/O(VREFBank1) B18 MADD5 HDS2 G20 I/O I/O P20 EMIFA1 TB22 Y12 I/O(DLL) I/O Y5 LD6 P5 I/O I/O G4
0 C4 B19 MADD4 EMIFD7 G21 P21 EMIFD20 VMA11 Y13 Y6 LD1 LCDSLEEP P6 G5
C5 B20 XCS EMIFD0 G22 P22 HD5 VMA5 Y14 Y7 LA2 VXD3 R1 H1
R69 I/O(VREFBank0) I/O(CS) I/O I/O(D5) I/O I/O I/O I/O
C6 C12 MCAS EAOE/ESOE H18 R18 HRDY VMD15 Y15 Y8 LSVIDEO VXD7 R2 H2
I/O I/O I/O(VREFBank2) I/O(VREFBank3) I/O I/O I/O I/O
C7 C13 MRAS HD1 H19 R19 HD6 VMD10 Y16 Y9 VMAS VXWRITE R3 H3
I/O I/O I/O(D1) I/O(D6) I/O I/O I/O(VREFBank6) I/O(VREFBank7)
C8 C14 MDQMH HD2 H20 R20 EMIFA3 VMD5 Y17 Y10 VMA25 VXDONE0 R4 H4
I/O I/O I/O(D2) I/O I/O(VREFBank4) I/O I/O I/O
MDQML C9 C15 SCLKX0 EMIFD8 H21 R21 EMIFD22 VMD0 Y18 Y11 VMA20 TIMING R5 H5
I/O I/O I/O I/O I/O I/O VXCCLK I/O I/O
D MWE C10 I/O I/O C16 TMSIACK EMIFD10 H22 I/O I/O R22 EMIFD21 PSTDO Y19 I/O I/O AA3 LD12 VICINO INTEGRATO T1 I/O I/O J1 ECG_AUX2
C11 C17 SDR0 FREADY J17 T18 EMIFBE2 TMSCLK AA12 AA5 LD5 0 TRACE1 T2 J2
GCK3,I I/O I/O I/O GCK0/I I/O I/O I/O
D5 C18 SCLKX1 EMIFCE2 J18 T19 EMIFA4 VMA12 AA13 AA6 LD0 VXCS0 T3 J3
I/O I/O I/O I/O I/O I/O R82 I/O I/O
D6 I/O I/O D12 MADD12 EMIFA9 J19 I/O I/O T20 EMIFA5 VMA6 AA14 I/O I/O AA7 LA1 VXPROG T4 I/O I/O J4 TB6
TB2 D7 I/O I/O D13 TIMER0 EMIFA8 J20 I/O I/O(VREFBank3) T21 EMIFD24 VMA0 AA15 I/O I/O AA8 TCLKI ECG T5 I/O I/O J5 BRD6
D8 D14 EMIFBE0 EMIFD9 J21 T22 EMIFD25 VMD11 AA16 AA9 VMDS VID_HSYNC U1 J6 BRD7
I/O(VREFBank0) I/O I/O I/O I/O I/O I/O(VREFBank6) I/O
D9 D15 SFSX0 EMIFD11 J22 U18 EMIFD29 VMD6 AA17 AA10 VMA26 TRACE0 U2 K1 ECG_AUX1
I/O I/O(VREFBank1) I/O I/O I/O I/O I/O I/O
D10 I/O(VREFBank0) I/O D16 SCLKR1 HCNTL1 K17 I/O I/O U19 EMIFA7 VMD1 AA18 I/O I/O AA11 VMA21 LD15 U3 I/O I/O K2 TB5
D11 D17 SDR1 EMIFA14 K18 U20 EMIFA6 AA19 AB3 LD11 LD10 U4 K3
I/O I/O I/O(VREFBank2) I/O I/O I/O I/O I/O(VREFBank7)
E7 D18 SDX1 HD3 K19 U21 EMIFD26 PSTDI AA20 AB4 LD8 MCYCLE_STARTV1 K4
I/O I/O I/O(D3) I/O I/O I/O I/O I/O
E8 E12 TMSINT3 EMIFA15 K20 U22 EMIFD27 VMA13 AB13 AB5 LD4 V2 K5 BRD4
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O(VREFBank6) I/O
E9 E13 SDX0 EMIFD14 K21 V19 EMIFA19 VMA7 AB14 AB6 LRW LD14 V3 K6 BRD5
TIMER1 E10 E14 TMSNMI EMIFD12 K22 V20 EMIFA18 VMA1 AB15 AB7 LA0 LD9 V4 L1 ECG_AUX0
I/O I/O I/O I/O I/O I/O(VREFBank5) I/O I/O
TMSINT1 E11 E15 TMSINT0 EMIFBE1 L17 V21 EMIFD30 VMD12 AB16 AB8 VMBL TBASE_INT W1 L2
EARE/ESADS F9
I/O I/O(VREFBank1) E16 TB3 EMIFA17 L18 I/O I/O(VREFBank3) V22 EMIFD28 VMD7 AB17 I/O I/O AB9 VMBH PHCONV W2 I/O I/O L3
TMSINT2 F10 I/O I/O E17 SCLKR0 EMIFA11 L19 I/O I/O(INIT) W21 XINIT VMD2 AB18 I/O I/O AB10 VMA27 LD13 W3 I/O I/O L4 TB9
F11 I/O I/O F12 TB4 EMIFA16 L20 I/O I/O W22 EMIFD31 VMAUX0 AB19
I/O I/O(DLL) AB11 TMSCLK VID_VSYNC Y1 I/O I/O L5 BRD2
C F13 SFSR0 EMIFD13 L21 Y22 HD7 PSTMS AB20 AB12 CLK40B PHDATA Y2 L6 BRD3
I/O I/O(IRDY) I/O(D7) I/O GCK1,I I/O I/O(IRDY)
F14 TMSHOLD +3V3 +3V3 PSPROG AB21 +3V3
+3V3 I/O I/O +3V3
G10 VCCOBank0 VCCOBank1 G14 K16 VCCOBank2 VCCOBank3 T17 U16 VCCOBank4 VCCOBank5 U8 T6 VCCOBank6 VCCOBank7 K7
NOTE NOTE NOTE NOTE
TB21
HD[0:7]
NOTE
+1V8A;V5
+1V8A;U17
+1V8A;U6
+1V8A;T16
+1V8A;T15
+1V8A;V18
+1V8A;T8
+1V8A;T7
+1V8A;R16
+1V8A;R7
+1V8A;H16
+1V8A;H7
+1V8A;G16
+1V8A;G15
+1V8A;G8
+1V8A;G7
+1V8A;E18
+1V8A;E5
+1V8A;F17
+1V8A;F6 +1V8A;V5
+1V8A;U17
+1V8A;U6
+1V8A;T16
+1V8A;T15
+1V8A;V18
+1V8A;T8
+1V8A;T7
+1V8A;R16
+1V8A;R7
+1V8A;H16
+1V8A;H7
+1V8A;G16
+1V8A;G15
+1V8A;G8
+1V8A;G7
+1V8A;E18
+1V8A;E5
+1V8A;F17
+1V8A;F6 +1V8A;V5
+1V8A;U17
+1V8A;U6
+1V8A;T16
+1V8A;T15
+1V8A;V18
+1V8A;T8
+1V8A;T7
+1V8A;R16
+1V8A;R7
+1V8A;H16
+1V8A;H7
+1V8A;G16
+1V8A;G15
+1V8A;G8
+1V8A;G7
+1V8A;E18
+1V8A;E5
+1V8A;F17
+1V8A;F6 TB20 +1V8A;V5
+1V8A;U17
+1V8A;U6
+1V8A;T16
+1V8A;T15
+1V8A;V18
+1V8A;T8
+1V8A;T7
+1V8A;R16
+1V8A;R7
+1V8A;H16
+1V8A;H7
+1V8A;G16
+1V8A;G15
+1V8A;G8
+1V8A;G7
+1V8A;E18
+1V8A;E5
+1V8A;F17
+1V8A;F6 +3V3
R175
EMIFD[0:31]
R181
2
NOTE
47
47
EMIFA[0:19] VMA[0:29]
C87 C95
33P
33P LD[0:15]
2 R228
33
TB17 PSTCK U48
B R214
NOTE
33
AD7302
NOTE
BRD7 1 15
PHSCLK DB7(MSB) VDD
BRD6 2
NOTE DB6
R432
2
2 BRD5 3 16
R380
+3V3 DB5 REFin
47
BRD4 4
R84
TB10 DB4
4K7
47
C442 BRD3 5 19 LCDBRITE
NOTE DB3 VoutA
+3V3
47P
C337 BRD2 6 DB2
+3V3 TB18 56P BRD1 7 18 C443
2 DB1 VoutB
NOTE
R179
R178
R177
BRD0 8 47N
U15 VICINO PIN J1 DB0(LSB)
R447
4K7
4K7
4K7
XC2S300 J1
0 TB16 BRCS 9 17
2
CS AGND
R430
XCCLK B22 E6 XTCK 1 2

R434
R433
CCLK TCK NOTE 10

VICINO PIN J7 WR
4K7
XPROG Y21 XVTDO 3 4

R446 R203
4K7
4K7
PROGRAM 11
J7 A/B
XDONE W20 5 6
0 DONE 33 12 PD
PSTCK 1 2 AA1 C19 XTDI 7 8
M0 TDI BRWR 13 LDAC
PSTDO 3 4 U5 A21 XVTDI 9 10
M1 TDO NOTE 14 20
CLR DGND
R415
PSTMS 5 6 AB2 E4 XTMS
2
M2 TMS
A 7 8
47
R223
PSTDI NOTE
837 0147 042 Rev.A
9 10
C439
1K00
47P
FORM:
+1V8A;V5
+1V8A;U17
+1V8A;U6
+1V8A;T16
+1V8A;T15
+1V8A;V18
+1V8A;T8
+1V8A;T7
+1V8A;R16
+1V8A;R7
+1V8A;H16
+1V8A;H7
+1V8A;G16
+1V8A;G15
+1V8A;G8
+1V8A;G7
+1V8A;E18
+1V8A;E5
+1V8A;F17
+1V8A;F6 2
SHEET DESCRIPTION:
"7300" VIDEO BOARD
by EpD Number: 950 1081 000 SE H 2 11

1 2 3 4 5 6 7 8 9 10 11
U23 U23 U23 U23

XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4
DECODER_Y[0:7]
SDR_DATA56 B4 F12 VMAUX2 XCOM35 C21 M21 DECODER_Y3 VXBUSY AB19 AA11 VMA17 VMD1 V5 L2 SDR_WE
F SDR_DATA57 A4 F13 C22 M20 DEC_VERTSYNC VXINIT1 AA19 Y11 VMA16 VMMODE U5 L3 SDR_DATA36
IO IO/GCLK2S IO IO IO/INIT_B IO/GCLK6P IO IO
SDR_DATA24 C4 E12 TCLKI XCOM22 E18 M19 XCOM2 VXD0 V18 W11 VMA20 Y2 L4 SDR_DATA11
IO IO/GCLK1P IO/VRP2 IO IO/D0 IO/GCLK5S TB26 IO/VRN6 IO
SDR_DATA25 C5 D12 XY_ADD1 XCOM23 F18 M18 XCOM4 VXD1 V17 V11 VMA12 Y1 L5 SDR_ADD3
IO IO/GCLK0S IO/VRN2 IO IO/D1 IO/GCLK4P TB25 IO/VRP6 IO
SDR_DATA26 B5 C12 AVG_DATA1 XCOM42 D21 M17 XCOM5 VXD2 W18 U11 VMA27 VMD4 V4 K1 SDR_ADD13
SDR_DATA58 A5 B12 AVG_DATA0 XCOM37 D22 N17 I2C_RESET1 VXD3 Y18 U10 VMA13 VMD0 V3 K2 SDR_S0
SDR_ADD7 D6 A13 AVG_DATA2 XCOM26 E19 N22 DECODER_UV5 LD10 AA18 AB10 VMA14 W2 K3 SDR_DATA43
IO/VREF0 IO IO IO IO/VREF4 IO TB28 IO IO
SDR_BA0 C6 B13 AVG_DATA3 XCOM31 E20 N21 DECODER_Y2 LD14 AB18 AA10 VMA18 W1 K4 SDR_DATA12
IO IO IO IO IO IO TB27 IO IO
SDR_DATA27 B6 C13 XY_ADD2 XCOM39 E21 N20 DEC_HORSYNC LD0 W17 Y10 VMA10 VMACK U4 L6 SDR_DATA8
SDR_DATA59 A6 D13 XY_ADD3 XCOM36 E22 N19 DEC_TREADY LD5 Y17 W10 VMA11 U3 K6 SDR_DATA9
SDR_ADD8 E7 E13 SCAN_MODE4 XCOM27 F19 N18 DEC_I2CCLK LD7 AA17 V10 VMA6 V2 K5 SDR_ADD4
SDR_ADD[7:11]
IO IO IO IO IO IO TB30 IO IO
SDR_DATA54 E8 E14 SCAN_MODE6 XCOM32 F20 P18 DEC_RTSTAT0 LD9 AB17 V9 VMA1 V1 J5 SDR_ADD5
IO IO/VREF1 IO IO IO IO/VREF5 TB29 IO IO
SDR_ADD9 D7 A14 AVG_DATA4 XCOM38 F21 P22 DECODER_Y1 LD11 V16 AB9 VMA15 SDR_DATA37 U2 J1 SDR_CK1
SDR_BA1 C7 B14 AVG_DATA5 XCOM40 F22 P21 DECODER_UV4 LD8 V15 AA9 VMA8 SDR_DATA5 U1 J2 SDR_S1
AVG_DATA[0:15]
SCAN_MODE[0:9]
SDR_DATA28 B7 C14 XY_ADD4 XCOM24 G18 P20 DECODER_Y7 LA1 W16 Y9 VMA4 T5 J3 SDR_DATA44
SDR_DATA60 A7 D14 XY_ADD5 XCOM29 H18 P19 LD1 Y16 W9 VMA5 R5 J4 SDR_DATA13
DECODER_UV[0:7]
SDR_ADD10 D8 A15 AVG_DATA6 XCOM28 G19 R22 DECODER_Y0 LD3 AA16 AB8 VMA2 SDR_DATA0 T4 H1 SDR_DATA48
SDR_ADD11 C8 B15 AVG_DATA7 XCOM33 G20 R21 DECODER_UV3 LD6 AB16 AA8 VMA9 T3 H2 SDR_DATA16
E SDR_DATA29 B8
IO IO C15 XY_ADD6 XCOM20 G21 IO IO R20 DECODER_Y6 VMBL W15 IO IO Y8 VMD15 SDR_DATA38 T2 IO IO H3 SDR_DATA45
SDR_DATA61 A8 D15 XY_ADD7 XCOM41 G22 R19 DEC_DQUAL LA2 Y15 W8 VMA0 SDR_DATA39 T1 H4 SDR_DATA14
SDR_DATA55 E9 F14 XCOM18 H19 R18 DEC_RTSTAT1 LA4 AA15 U9 VMA7 SDR_DATA1 R4 J6 SDR_DATA10
SDR_I2CCLK F9 E15 SCAN_MODE8 XCOM34 H20 P17 DEC_I2CDAT LD2 AB15 V8 VMD12 SDR_DATA32 R3 H5 SDR_DATA40
SDR_DQMB2 D9 A16 AVG_DATA8 XCOM16 H21 T22 DECODER_UV7 VMBH U14 AB7 VMA3 SDR_DATA6 R2 G1 SDR_DATA49
SDR_DQMB6 C9 B16 AVG_DATA9 XCOM19 H22 T21 DECODER_UV2 LA0 V14 AA7 VMD13 SDR_DATA7 R1 G2 SDR_DATA17
LA[0:4]
SDR_DATA30 B9 C16 XY_ADD8 XCOM25 J17 T20 DECODER_Y5 LSVIDEO W14 Y7 VMD10 SDR_ADD0 P6 G3 SDR_DATA46
SDR_DATA62 A9 D16 SCAN_MODE1 XCOM30 J18 T19 DECODER_Y4 VMRW Y14 W7 VMD11 P5 G4 SDR_DATA15
SDR_DATA22 E10 E16 SCAN_MODE7 XCOM13 J19 U22 DECODER_UV6 LRW AA14 AB6 VMD8 SDR_DATA2 P4 F1 SDR_DATA50
SDR_I2CDAT F10 E17 SCAN_MODE9 XCOM17 J20 U21 DECODER_UV1 LA3 AB14 AA6 VMD14 SDR_DATA33 P3 F2 SDR_DATA18
SDR_DQMB3 D10 A17 AVG_DATA10 XCOM11 J21 U20 DECODER_UV0 VMDS U13 Y6 VMD5 SDR_DQMB4 P2 F3 SDR_DATA47
SDR_DQMB7 C10 B17 AVG_DATA11 XCOM1 J22 U19 VID_VSYNC VMA26 V13 W6 VMD6 SDR_DQMB5 P1 F4 SDR_CK0
SDR_DATA31 B10 C17 SCAN_MODE0 XCOM15 K17 T18 DEC_GENPUR VMAS W13 V7 VMD7 SDR_ADD1 N6 G5 SDR_DATA41
SDR_DATA63 A10 D17 SCAN_MODE3 XCOM14 K18 U18 MRESET_DONE VMA24 Y13 V6 VMD2 N5 F5 SDR_DATA42
SDR_DATA23 E11 A18 AVG_DATA12 XCOM8 K19 V22 ECG_AUX0 VMA29 AA13 AB5 VMD9 SDR_DATA3 N4 E1 SDR_DATA51
ECG_AUX[0:2]
F11 IO IO/VRN1 B18 AVG_DATA13 XCOM12 K20 IO IO V21 TBASE_INT VMA28 AB13
IO IO/VREF5 AA5 VMD3 SDR_DATA34 N3 IO IO E2 SDR_DATA19
XY_ADD0 D11 C18 SCAN_MODE2 XCOM6 K21 V20 MCYCLE_START VMA21 U12 Y5 VXD4 SDR_DQMB0 N2 E3 SDR_CKE0
D XCOM21 C11 D18 SCAN_MODE5 XCOM0 K22 V19 VID_HSYNC VMA25 V12 W5 VXD5 SDR_DQMB1 N1 E4 SDR_CAS
B11 IO/GCLK5P IO A19 AVG_DATA14 XCOM10 L17 IO IO/VREF3 W22 ECG_AUX1 VMA19 W12
IO/GCLK3S IO/D6 AB4 VXD6 SDR_ADD2 M6 IO IO/VREF7 D1 SDR_DATA52
CLK40D A11 B19 AVG_DATA15 XCOM9 L18 W21 LD12 VMA23 Y12 AA4 VXD7 M5 D2 SDR_DATA20
XCOM3 L19 Y22 ECG_AUX2 VMA22 AA12 Y4 VXWRITE SDR_DATA4 M4 C1 SDR_DATA53


XCOM7 L20 Y21 LD13 DEC_PIXCLKA AB12 AA3 VXCS1 SDR_DATA35 M3 C2 SDR_DATA21
L21 W20 LD4 SDR_CKE1 M2 E5 SDR_RAS
IO IO IO IO
L22 IO IO AA20 LD15 SDR_ADD12 M1 IO IO E6 SDR_ADD6
+3V3 G10 G13 +3V3 +3V3 K16 R17 +3V3 +3V3 U15 U7 +3V3 +3V3 R6 K7 +3V3
TB23 VXINIT1
C +3V3 VXCS1
TB38
TB35
TB24 U23
XC2V1000-4
R448
U32
U35 R391
4K7
VXCCLK Y19 C19 XTCK
74LCX14 CCLK TCK
ADV7125-140 3K3 VXPROG A2 D3 VTDI/TDO
PROG_B TDI
PRN_CNT0 3 4
CRT_CLOCKA 24 13 CRTDAC_VCC VXDONE1 AB20 D20 XVTDO
CLK VAA DONE TDO
R400 29 AB2 B20 XTMS
CRT_BLANK 11 VAA M0 TMS
1K00 BLANK PRN_CONTROL0
R449
VAA 30 R405 U32 W3 M1 DXN D5
12 SYNC C420 C419 R390
4K7
BC817 AB3 M2 DXP A3
536 74LCX14
37 100N 100N B3 A21
CRT_RED0 41 R0
Rset
PRN_CNT1 5 6
3K3 Q2 HSWAP_EN VBATT
CRT_RED1 Vref 36 1K00 AB21 PWRDWN_B RSVD A20
42 R1
35 +3V3
CRT_RED2 43 R2
COMP
PRN_CONTROL1 R96
CRT_RED[0:7]
R450
CRT_RED3 44 J6 U32
R3
R393
4K7
CRT_RED4 45 BC817
R4 74LCX14
+3V3
CRT_RED5 46 R5 PRN_CNT2 1 2
3K3 Q3
B CRT_RED6 47 IOR 34 SVGA_RED 1 11 U32
R6
CRT_RED7 48 6 74LCX14
R7 PRN_CONTROL2 +3V3
R451
SVGA_GREEN
IOR 33 2 12 R399 12 13 CRT_HSYNC U32 R362 R363
R397
4K7
CRT_GREEN0 3 75 7 BC817
75 74LCX14
G0 SVGA_BLUE 4K7 4K7
CRT_GREEN1 4 R413 3 13
PRN_CNT3 9 8
3K3 Q1
G1
32 8 +3V3
CRT_GREEN[0:7]
CRT_GREEN2 5 IOG U32

CRT_GREEN3 6
G2
4 14 R133 R134 AL300_I2CDAT
G3 74LCX14 PRN_CONTROL3
CRT_GREEN4 7 31 9 75 4K7 4K7 AL300_I2CCLK
IOG
G4 10 11 CRT_VSYNC BC817
CRT_GREEN5 8 75 5 15 R398
G5 +3V3
CRT_GREEN6 9 R411 10 Q4 SDR_I2CDAT R378 R379
G6
CRT_GREEN7 10 IOB 28 SDR_I2CCLK
G7 4K7 4K7
CRT_BLUE0 16 IOB 27 +3V3

B0
CRT_BLUE1 17 75 R263 R272 ENC0_I2CDAT
B1 CRT OUT TB42 TB54
4K7 4K7 ENC0_I2CCLK
CRT_BLUE2 18 R408
CRT_BLUE[0:7]
B2 TB46 TB53
CRT_BLUE3 19 TB45 TB52
B3 +3V3
CRT_BLUE4 20 TB43 TB51 DEC_I2CDAT
B4 R140 R382
A CRT_BLUE5 21 B5
+3V3 DEC_I2CCLK
4K7 4K7
VXD0 VXD4
CRT_BLUE6
837 0147 042 Rev.A
22 B6
VXD1 VXD5
CRT_BLUE7 23 38
B7 PSAVE
VXD2 VXD6
FORM:
ENC1_I2CDAT
VXD3 VXD7 ENC1_I2CCLK
SHEET DESCRIPTION:
"7300" VIDEO BOARD
by EpD Number: 950 1081 000 SE H 3 11

1 2 3 4 5 6 7 8 9 10 11
U31 U31 U31 U31

XC2V1000-4 XC2V1000-4 XC2V1000-4 XC2V1000-4
FMEM_GW B4 F12 GRA1 LCD_GODD5 C21 M21 CRT_RED6 VXBUSY AB19 AA11 SCAL_CKOUTA XCOM3 V5 L2 FMEM_D2
F FMEM_OE A4
IO IO/GCLK2S F13 GRA0 LCD_GODD4 C22 IO IO M20 CRT_BLUE1 VXINIT0 AA19
IO/INIT_B IO/GCLK6P Y11 SCAL_ROUT1 XCOM19 U5
IO IO L3 FMEM_D1
FMEM_A13 C4 E12 GRA3 LCD_BEVEN7 E18 M19 CRT_BLUE6 VXD0 V18 W11 SCAL_GOUT4 XCOM4 Y2 L4 FMEM_D0
XCOM8
VXD[0:3]
FMEM_A14 C5 D12 GRA5 LCD_BEVEN6 F18 M18 CRT_GREEN3 VXD1 V17 V11 SCAL_BOUT5 Y1 L5 FMEM_D6
XCOM17 V4
GRA[0:7]
FMEM_AS B5 C12 GRA7 LCD_BODD3 D21 M17 CRT_GREEN7 VXD2 W18 U11 AL300_I2CCLK K1 FMEM_A3
FMEM_A17 A5 B12 LCD_BODD2 D22 N17 CRT_BLANK VXD3 Y18 U10 SCAL_BOUT1 XCOM5 V3 K2 FMEM_A18
LA1 D6 A13 VGA_LVN1 LCD_BEVEN2 E19 N22 CRT_RED3 SCAL_RIN6 AA18 AB10 SCAL_ROUT6 XCOM9 W2 K3 FMEM_D10
FMEM_A15 C6 B13 VGA_LVP1 LCD_GEVEN6 E20 N21 CRT_RED2 SCAL_RIN5 AB18 AA10 SCAL_HSOUT XCOM10 W1 K4 FMEM_D15
FMEM_A16 B6 C13 GRA6 LCD_REVEN4 E21 N20 CRT_BLUE2 SCAL_BIN4 W17 Y10 SCAL_ROUT0 XCOM12 U4 L6 FMEM_D11
LRW A6 D13 GRA4 LCD_REVEN5 E22 N19 CRT_BLUE7 SCAL_GIN1 Y17 W10 SCAL_GOUT3 XCOM13 U3 K6 FMEM_CK0
LA0 E7 E13 GRA2 LCD_BEVEN1 F19 N18 CRT_VSYNC SCAL_RIN0 AA17 V10 SCAL_BOUT4 XCOM18 V2 K5 FMEM_A1
LD8 E8 E14 LCD_VSYNC LCD_GEVEN5 F20 P18 CRT_BLUE3 SCAL_RIN7 AB17 V9 SCAL_BOUT3 XCOM15 V1 J5 FMEM_A0
LD9 D7 A14 VGA_LVN2 LCD_REVEN3 F21 P22 CRT_RED5 SCAL_BIN1 V16 AB9 SCAL_HROUT XCOM14 U2 J1 FMEM_D3
LA[0:4]
LA2 C7 B14 VGA_LVP2 LVDS_TXPD F22 P21 CRT_RED1 SCAL_BIN2 V15 AA9 SCAL_ROUT7 XCOM20 U1 J2 FMEM_D14
LSVID B7 C14 LCD_GODD3 LCD_BEVEN5 G18 P20 PRN_CNT2 SCAL_BIN5 W16 Y9 SCAL_GOUT7 XCOM42 T5 J3 FMEM_A2
V_HSYNC A7 D14 LCD_HSYNC LCD_BEVEN4 H18 P19 CRT_CLOCK SCAL_GIN2 Y16 W9 SCAL_GOUT2 XCOM40 R5 J4 FMEM_D7
LD14 D8 A15 VGA_LVN0 LCD_BEVEN0 G19 R22 PRN_CNT0 SCAL_GIN7 AA16 AB8 SCAL_VSOUT XCOM41 T4 H1 FMEM_D13
LD10 C8 B15 VGA_LVP0 LCD_GEVEN4 G20 R21 CRT_RED0 SCAL_HSIN AB16 AA8 SCAL_ROUT5 XCOM38 T3 H2 FMEM_D9
E LA3 B8 C15 LCD_GODD2 LCD_TXCK G21 R20 ENC_DATAREQ SCAL_BIN6 W15 Y8 SCAL_GOUT6 XCOM30 T2 H3 FMEM_D16
LA4 A8 D15 LCD_RODD6 LCD_REVEN6 G22 R19 PRN_CNT3 SCAL_GIN3 Y15 W8 SCAL_GOUT1 XCOM25 T1 H4 FMEM_D20
LD13 E9 F14 LCD_DRDY LCD_GEVEN7 H19 R18 ENC_HORSYNC SCAL_HRIN AA15 U9 SCAL_BOUT0 XCOM34 R4 J6 FMEM_CK1
LD12 F9 E15 LCD_RODD2 LCD_GEVEN3 H20 P17 CRT_HSYNC SCAL_CKIN AB15 V8 SCAL_BOUT2 XCOM37 R3 H5 FMEM_A11
LD2 D9 A16 LCD_BODD7 LVDS_TXDUAL H21 T22 ENC_SYNCRES SCAL_YUVIN U14 AB7 TRACE0 XCOM29 R2 G1 FMEM_D26
LD[0:15]
LD15 C9 B16 LCD_BODD1 LCD_REVEN7 H22 T21 PRN_CNT1 SCAL_BIN3 V14 AA7 TRACE1 XCOM36 R1 G2 FMEM_D8
LD11 B9 C16 LCD_GODD1 CRT_GREEN4 J17 T20 I2C_RESET0 SCAL_BIN7 W14 Y7 SCAL_ROUT3 FMEM_A5 P6 G3 FMEM_D21
LCD_RODD[7:0]
V_VSYNC A9 D16 LCD_RODD5 CRT_GREEN0 J18 T19 ENCODER_CYC1 SCAL_GIN4 Y14 W7 SCAL_ROUT4 XCOM39 P5 G4 FMEM_D12
LD1 E10 E16 LCD_RODD1 LCD_BEVEN3 J19 U22 ENCODER_CYC4 SCAL_RIN1 AA14 AB6 XCOM0 XCOM24 P4 F1 FMEM_D17
LD0 F10 E17 LCD_RODD0 LCD_GEVEN2 J20 U21 ENC1_I2CCLK SCAL_RIN2 AB14 AA6 XCOM1 XCOM33 P3 F2 FMEM_D31
LD6 D10 A17 LCD_BODD6 LCD_REVEN1 J21 U20 ENC_PIXCLK SCAL_PD U13 Y6 XCOM16 XCOM32 P2 F3 FMEM_D18
LD3 C10 B17 LCD_BODD0 LCD_REVEN2 J22 U19 ENCODER_CYC2 SCAL_BOUT7 V13 W6 XCOM11 XCOM35 P1 F4 FMEM_D22
ENCODER_CYC[0:7]
VGA_LVN4 B10 C17 LCD_GODD0 CRT_GREEN5 K17 T18 ENCODER_CYC0 SCAL_GIN0 W13 V7 SCAL_GOUT0 FMEM_A6 N6 G5 FMEM_A12
VGA_LVP4 A10 D17 LCD_RODD4 CRT_GREEN1 K18 U18 SCAL_BIN0 SCAL_GIN5 Y13 V6 XCOM6 FMEM_D5 N5 F5 FMEM_A8
LD5 E11 IO/VREF0 IO/VRP1 A18 LCD_BODD5 CRT_BLUE4 K19 IO IO V22 ENCODER_CYC5 SCAL_RIN3 AA13 IO IO AB5 XCOM2 XCOM31 N4
IO IO E1 FMEM_D24
LD4 F11 B18 LCD_GODD7 LCD_GEVEN1 K20 V21 ENC0_I2CCLK SCAL_RIN4 AB13 AA5 XCOM7 XCOM28 N3 E2 FMEM_D27
IO IO/VRN1 IO IO IO IO/VREF5 IO IO
CLK40C D11 C18 LCD_RODD7 CRT_RED4 K21 V20 ENC_PIXCLK AL300_I2CDAT U12 Y5 VXD4 XCOM23 N2 E3 FMEM_D23
VXD[4:7]
LD7 C11 D18 LCD_RODD3 LCD_REVEN0 K22 V19 ENCODER_CYC3 SCAL_BOUT6 V12 W5 VXD5 XCOM27 N1 E4 FMEM_D28
D IO/GCLK6S IO IO IO IO IO/D5/ALT_VRN5 IO IO
VGA_LVN3 B11 A19 LCD_BODD4 CRT_GREEN6 L17 W22 ENCODER_CYC6 SCAL_GOUT5 W12 AB4 VXD6 FMEM_A7 M6 D1 FMEM_D29
IO/GCLK5P IO IO IO/VREF3 IO/GCLK3S IO/D6 IO IO/VREF7
VGA_LVP3 A11 B19 LCD_GODD6 CRT_GREEN2 L18 W21 ENC1_I2CDAT SCAL_ROUT2 Y12 AA4 VXD7 FMEM_A4 M5 D2 FMEM_D25
CRT_BLUE5 L19 Y22 ENCODER_CYC7 ENC_CLKOUTA AA12 Y4 VXWRITE FMEM_D4 M4 C1 FMEM_D19

CRT_BLUE0 L20 Y21 ENC0_I2CDAT SCAL_VSIN AB12 AA3 VXCS0 XCOM22 M3 C2 FMEM_D30

LCD_GEVEN0 L21 W20 ENC_VERTSYNC XCOM26 M2 E5 FMEM_A9
IO IO IO IO
CRT_RED7 L22 AA20 XCLK27 XCOM21 M1 E6 FMEM_A10
IO IO IO IO
+3V3 G10 G13 +3V3 +3V3 K16 R17 +3V3 +3V3 U15 U7 +3V3 +3V3 R6 K7 +3V3
U27 +3V3 U28 +3V3 U33 +3V3 U34 +3V3

TB47 VXINIT0
CY7C1327 (RAM) CY7C1327 (RAM) CY7C1327 (RAM) CY7C1327 (RAM) VXCS0
C +3V3
FMEM_CKA0
+3V3
FMEM_CKA0
+3V3
FMEM_CKA1 89
+3V3
FMEM_CKA1 89
TB50 VICINO PIN U31
89 4 89 4 4 4
CLK VDDQ CLK VDDQ CLK VDDQ CLK VDDQ TB101
VDDQ 11 VDDQ 11 VDDQ 11 VDDQ 11 TB44 U31
83 20 83 20 83 20 83 20 TB100
ADV VDDQ ADV VDDQ ADV VDDQ ADV VDDQ XC2V1000-4
84 ADSP VDDQ 27 84 ADSP VDDQ 27 84 ADSP VDDQ 27 84 ADSP VDDQ 27 VXCCLK XTCK
Y19 CCLK TCK C19
FMEM_AS 85 54 FMEM_AS 85 54 FMEM_AS 85 54 FMEM_AS 85 54
ADSC VDDQ ADSC VDDQ ADSC VDDQ ADSC VDDQ VXPROG A2 D3 XVTDI
PROG_B TDI
VDDQ 61 VDDQ 61 VDDQ 61 VDDQ 61 VXDONE0 VTDI/TDO
AB20 DONE TDO D20
FMEM_A0 37 70 FMEM_A0 37 70 FMEM_A0 37 70 FMEM_A0 37 70
A0 VDDQ A0 VDDQ A0 VDDQ A0 VDDQ AB2 B20 XTMS
M0 TMS
FMEM_A1 36 77 FMEM_A1 36 77 FMEM_A1 36 77 FMEM_A1 36 77
A1 VDDQ A1 VDDQ A1 VDDQ A1 VDDQ W3 D5
M1 DXN
FMEM_A2 35 FMEM_A2 35 FMEM_A2 35 FMEM_A2 35
A2 A2 A2 A2 AB3 A3
M2 DXP
R4452
A3 A3 A3 A3 B3 A21
VICINO PIN U31

HSWAP_EN VBATT
A4 A4 A4 A4 1K00 AB21 A20
47
PWRDWN_B RSVD
A5 A5 A5 A5 +3V3
R395 C449
A6 A6 A6 A6
FMEM_A7 99 FMEM_A7 99 FMEM_A7 99 FMEM_A7 99 33P
A7 A7 A7 A7
FMEM_A[0:17]
FMEM_A[0:17]
FMEM_A[0:17]
FMEM_A[0:17]
FMEM_A8 82 58 FMEM_D0 FMEM_A8 82 58 FMEM_D0 FMEM_A8 82 58 FMEM_D16 FMEM_A8 82 58 FMEM_D16
A8 DQ0 A8 DQ0 A8 DQ0 A8 DQ0 +3V3 2
A9 DQ1 A9 DQ1 A9 DQ1 A9 DQ1
A10 DQ2 A10 DQ2 A10 DQ2 A10 DQ2
B FMEM_A11 44 A11 DQ3 63 FMEM_D3 FMEM_A11 44 A11 DQ3 63 FMEM_D3 FMEM_A11 44 A11 DQ3 63 FMEM_D19 FMEM_A11 44 A11 DQ3 63 FMEM_D19
FMEM_D[16:31]
FMEM_D[16:31]
A12 DQ4 A12 DQ4 A12 DQ4 A12 DQ4 VGA_LVP2
FMEM_D[0:15]
FMEM_D[0:15]

A13 DQ5 A13 DQ5 A13 DQ5 A13 DQ5
R144
A14 DQ6 A14 DQ6 A14 DQ6 A14 DQ6
FMEM_A15 FMEM_D7 FMEM_A15 FMEM_D7 FMEM_A15 FMEM_D23 FMEM_A15 FMEM_D23
100
48 A15 DQ7 73 48 A15 DQ7 73 48 A15 DQ7 73 48 A15 DQ7 73
A16 DQ8 A16 DQ8 A16 DQ8 A16 DQ8 VGA_LVP0
FMEM_A17 FMEM_D9 FMEM_A17 FMEM_D9 FMEM_A17 FMEM_D25 FMEM_A17 FMEM_D25 VGA_LVN2
+3V3 50 A17 DQ9 9 50 A17 DQ9 9 +3V3 50 A17 DQ9 9 50 A17 DQ9 9
R143
43 12 FMEM_D10 43 12 FMEM_D10 43 12 FMEM_D26 43 12 FMEM_D26
NC(A18) DQ10 NC(A18) DQ10 NC(A18) DQ10 NC(A18) DQ10
FMEM_GW FMEM_D11 +3V3 FMEM_GW FMEM_D11 FMEM_GW FMEM_D27 FMEM_GW FMEM_D27
100
88 GW DQ11 13 88 GW DQ11 13 88 GW DQ11 13 +3V3 88 GW DQ11 13
18 FMEM_D12 18 FMEM_D12 18 FMEM_D28 18 FMEM_D28 VGA_LVP3
DQ12 DQ12 DQ12 DQ12
FMEM_D13 FMEM_D13 FMEM_D29 FMEM_D29 VGA_LVN0
87 BWE DQ13 19 87 BWE DQ13 19 87 BWE DQ13 19 87 BWE DQ13 19
R402
BWS0 DQ14 BWS0 DQ14 BWS0 DQ14 BWS0 DQ14
100
BWS1 DQ15 BWS1 DQ15 BWS1 DQ15 BWS1 DQ15
VGA_LVP1
VGA_LVN3
31 R345 31 R389 31 R403 31 R344
R136
R141
R401
MODE MODE MODE MODE
1K00
1K00
100
1K00 1K00 1K00 1K00
98 CE1 DP0 74 98 CE1 DP0 74 98 CE1 DP0 74 98 CE1 DP0 74
VGA_LVP4
A 97 CE2 DP1 24 FMEM_A18 97 CE2 DP1 24 97 CE2 DP1 24 FMEM_A18 97 CE2 DP1 24 VGA_LVN1
R145
FMEM_A18 FMEM_A18
837 0147 042 Rev.A
92 CE3 1K00 92 CE3 1K00 92 CE3 1K00 92 CE3 1K00
100
R365 1K00 R404 R388 1K00 R364
FMEM_OE FMEM_OE FMEM_OE FMEM_OE
FORM:
86 OE 86 OE 86 OE 86 OE
R137 R142 VGA_LVN4
64 ZZ 64 ZZ 64 ZZ 64 ZZ
SHEET DESCRIPTION:
"7300" VIDEO BOARD
by EpD Number: 950 1081 000 SE H 4 11

1 2 3 4 5 6 7 8 9 10 11
U41 +3V3 U17 U20

DS90C387 (LVDS TX) SAA7115 (DECODER) AL300 (SCALER)
LCD_TXCKA 11 30 LVDS_VCC +3V3 1 23 DEC_VCC 40 128 SCALPLL_VCC
CLKIN LVDSVCC VDDE VDDA0 XIN PLLVCC
40 25 VDDE VDDA1 17 Y2
F LCD_REVEN0 10
LVDSVCC
48 51 11
R222 39 60
R10 LVDSVCC VDDE VDDA2 14.31818MHZ XOUT RB0
LCD_REVEN1 9 R11
Y1 75 VDDE VDDI 33 100K
RB1 59
LCD_REVEN2 LVDSPLL_VCC
C150 4
AL300_I2CCLK
8 12 R207 8 43 42 58
LCD_REVEN[0:7]
R12 PLLVCC VXDD VDDI C178 C179 SCL RB2
47N
LCD_REVEN3 7 18 VCC 58 AL300_I2CDAT 43 57
R13 PLLVCC 1K00 VDDI +3V3 SDA RB3
10P 10P
LCD_REVEN4 6 1 3 7 68 47 55
R14 OE OSC XTALI VDDI I2CADDR RB4
LCD_REVEN5 5 R15 TxA0+ 49 LCD_EVENP0 24.576MHZ VDDI 83 I2C_RESET0 122 RESETB RB5 54
GND
LCD_REVEN6 4 50 LCD_EVENN0 6 93 53
R16 TxA0- XTALO VDDI RB6
LCD_REVEN7 3 SCAL_PD 46 52
R17 2 PWRDN RB7
LCD_GEVEN0 2 46 LCD_EVENP1 4 37 SCAL_YUVIN 48
G10 TxA1+ XTOUT AMCLK YUVIN
LCD_GEVEN1 1 47 LCD_EVENN1 39 70
G11 TxA1- ASCLK GB0
LCD_GEVEN2 100 5 40 69
LCD_GEVEN[0:7]
G12 VXSS ALRCLK GB1

LCD_GEVEN3 99 44 LCD_EVENP2 41 1 68
G13 TxA2+ AMXCLK TVCLK GB2
LCD_GEVEN4 96 45 LCD_EVENN2 10 2 67
G14 TxA2- AI24 TVHREF GB3
C166
LCD_GEVEN5 95 12 45 DEC_PIXCLK 3 65
G15 R236 AI23 ICLK TVVS GB4
47N
LCD_GEVEN6 94 38 LCD_EVENP3 14 46 DEC_DQUAL 4 64
G16 TxA3+ 18 AI22 IDQ TVHS GB5
LCD_GEVEN7 93 39 LCD_EVENN3 VTR_CHROMIN 16 47 63
G17 TxA3- AI21 ITRI GB6
LCD_BEVEN0 92 13 48 DEC_GENPUR SCAL_VSIN 6 62
C172
B10 AI2D IGP0 GVS GB7
R247
47N
E LCD_BEVEN1 91 36 LCD_ODDP0 18 49 SCAL_HSIN 7
B11 TxA4+ AI12 IGP1 GHS
LCD_BEVEN2 90 37 LCD_ODDN0 18 20 52 DEC_VERTSYNC SCAL_HRIN 8 80
LCD_BEVEN[0:7]
B12 TxA4- VTR_COMPIN AI11 IGPV GHREF BB0

LCD_BEVEN3 89 19 53 DEC_HORSYNC SCAL_CKINA 9 79
B13 AI1D IGPH GCLK BB1
C173
LCD_BEVEN4 88 33 LCD_ODDP1 38 78
B14 TxA5+ R255 HOSTCLK BB2
47N
LCD_BEVEN5 87 34 LCD_ODDN1 28 77
B15 TxA5- 18 LCC BB3
LCD_BEVEN6 86 VTR_LUMIN 29 42 DEC_TREADY 75
B16 LCC2 ITRDY BB4
LCD_BEVEN7 85 31 LCD_ODDP2 SCAL_RIN0 18 74
B17 TxA6+ Rin0/Yin0 BB5
LCD_RODD0 84 32 LCD_ODDN2 30 62 DECODER_Y0 SCAL_RIN1 17 73
R20 TxA6- RESON IPD0 Rin1/Yin1 BB6
DECODER_Y[0:7]
LCD_RODD1 81 61 DECODER_Y1 SCAL_RIN2 16 72
SCAL_RIN[0:7]
R21 IPD1 Rin2/Yin2 BB7
R250
R239
R235
LCD_RODD2 80 28 LCD_ODDP3 44 60 DECODER_Y2 SCAL_RIN3 15
LCD_RODD[0:7]
R22 TxA7+ 47N 47N TEST0 IPD2 Rin3/Yin3

LCD_RODD3 79 29 LCD_ODDN3 73 59 DECODER_Y3 SCAL_RIN4 14 84
56
56
56
R23 TxA7- TEST1 IPD3 Rin4/Yin4 PCLKA
LCD_RODD4 78 C174 C176 74 57 DECODER_Y4 SCAL_RIN5 13 85
R24 TEST2 IPD4 Rin5/Yin5 PCLKB
LCD_RODD5 77 77 56 DECODER_Y5 SCAL_RIN6 12 86 SCAL_CKOUT
R25 TEST3 IPD5 Rin6/Yin6 SCLK
LCD_RODD6 76 41 LCD_EVENPCK 78 55 DECODER_Y6 SCAL_RIN7 11 88 SCAL_HSOUT
R26 TxCLK1+ TEST4 IPD6 Rin7/Yin7 PHS
LCD_RODD7 75 42 LCD_EVENNCK 79 54 DECODER_Y7 89 SCAL_VSOUT
R27 TxCLK1- TEST5 IPD7 PVS
LCD_GODD0 74 SCAL_GIN0 27 90 SCAL_HROUT
G20 Gin0/UVin0 PDSPEN
LCD_GODD1 73 26 LCD_ODDPCK 92 22 SCAL_GIN1 26
G21 TxCLK2+ XRH AOUT Gin1/UVin1
LCD_GODD2 72 27 LCD_ODDNCK 91 SCAL_GIN2 25 100 SCAL_ROUT0
LCD_GODD[0:7]
D G22 TxCLK2- XRV Gin2/UVin2 RA0

LCD_GODD3 71 +3V3 96 31 DEC_I2CCLK SCAL_GIN3 24 99 SCAL_ROUT1
SCAL_ROUT[0:7]
G23 XRDY SCL Gin3/UVin3 RA1
LCD_GODD4 70 95 32 DEC_I2CDAT SCAL_GIN4 23 98 SCAL_ROUT2
G24 XDQ SDA Gin4/UVin4 RA2
LCD_GODD5 69 15 94 SCAL_GIN5 22 97 SCAL_ROUT3
G25 PLLSEL XCLK Gin5/UVin5 RA3

LCD_GODD6 66 23 LVDS_TXDUAL 80 72 DECODER_UV0 21 95 SCAL_ROUT4

G26 DUAL XTRI HPD0 Gin6/UVin6 RA4
DECODER_UV[0:7]
LCD_GODD7 65 14 71 DECODER_UV1 SCAL_GIN7 20 94 SCAL_ROUT5
G27 PRE HPD1 Gin7/UVin7 RA5
LCD_BODD0 64 24 90 70 DECODER_UV2 93 SCAL_ROUT6
B20 BAL XPD0 HPD2 RA6
LCD_BODD1 63 20 89 69 DECODER_UV3 SCAL_BIN0 36 92 SCAL_ROUT7
B21 R_FB XPD1 HPD3 Bin0 RA7
LCD_BODD2 62 21 87 67 DECODER_UV4 SCAL_BIN1 35
LCD_BODD[0:7]
B22 R_FDE XPD2 HPD4 Bin1

LCD_BODD3 61 22 LVDS_TXPD 86 66 DECODER_UV5 SCAL_BIN2 34 110 SCAL_GOUT0
SCAL_BIN[0:7]
B23 PD XPD3 HPD5 Bin2 GA0
SCAL_GOUT[0:7]
LCD_BODD4 60 85 65 DECODER_UV6 SCAL_BIN3 33 109 SCAL_GOUT1
B24 XPD4 HPD6 Bin3 GA1
LCD_BODD5 59 25 84 64 DECODER_UV7 SCAL_BIN4 32 108 SCAL_GOUT2
B25 LVDSGND XPD5 HPD7 Bin4 GA2
LCD_BODD6 58 35 82 SCAL_BIN5 31 107 SCAL_GOUT3
B26 LVDSGND XPD6 Bin5 GA3
LCD_BODD7 57 43 81 34 DEC_RTSTAT0 SCAL_BIN6 30 105 SCAL_GOUT4
B27 LVDSGND XPD7 RTS0 Bin6 GA4
51 35 DEC_RTSTAT1 SCAL_BIN7 29 104 SCAL_GOUT5
LVDSGND RTS1 Bin7 GA5
I2C_RESET1 27 36 103 SCAL_GOUT6
CE RTCO GA6
LCD_HSYNC 54 HSYNC PLLGND 16 TB15 97 TRSTN GA7 102 SCAL_GOUT7
LCD_VSYNC 55 VSYNC PLLGND 17 TDI 3 TB11
C LCD_DRDY 56 DRDY(DE) PLLGND 19 26 VSSE TDO 2 TB12 140 ROMDATA0 BA0 120 SCAL_BOUT0
TB13
SCAL_BOUT[0:7]
50 99 139 119 SCAL_BOUT1
VSSE TMS ROMDATA1 BA1
76 VSSE TCK 98 TB14 138 ROMDATA2 BA2 118 SCAL_BOUT2
100 137 117 SCAL_BOUT3
VSSE ROMDATA3 BA3
24 135 115 SCAL_BOUT4
VSSA0 ROMDATA4 BA4
38 15 134 114 SCAL_BOUT5
VSSI VSSA1 ROMDATA5 BA5
63 9 133 113 SCAL_BOUT6
VSSI VSSA2 ROMDATA6 BA6
88 21 132 112 SCAL_BOUT7
VSSI AGND ROMDATA7 BA7
I2C ADDRESS 142 123

L18 +3V3 WRITE = 42H ROMADDR0 IHSREF
143 ROMADDR1 OHSREF 124
100U READ = 43H
CRTDAC_VCC 144 125
ROMADDR2 OHSFB
C386 C382 C381 C385 C384 C383 C61
145 ROMADDR3 OCLK 126 R241
10N 10N 10N 100N 100N 100N 147 ROMADDR4 OPLLCLK 127
10U 43K
148 ROMADDR5 VCOIN 129
149 ROMADDR6
R260 R394 150 ROMADDR7 GOUT1 81
B L1 +3V3 L2 +3V3 152 ROMADDR8 GOUT2 82 C201 C200
33 33
100U 100U ENC_CLKOUT ENC_CLKOUTA LCD_TXCK LCD_TXCKA 153 83
ROMADDR9 GOUT3 820P 100N
DEC_VCC SCALPLL_VCC
R377 R305 154 ROMADDR10 IREQ 41
C162 C149 C144 C168 C33
C32 100N 33 33
155 ROMADDR11
100N 100N 100N 10U ENC_PIXCLK ENC_PIXCLKA SCAL_CKOUT SCAL_CKOUTA 157 49
10U ROMADDR12 Test1
R139 R361 158 ROMADDR13 Test2 50
159 ROMADDR14
33 33
L20 +3V3 L19 +3V3 ENC_PIXCLK ENC_PIXCLKA SCAL_CKIN SCAL_CKINA 160 ROMADDR15 PLLGND 130
LVDS_VCC
100U
LVDSPLL_VCC
100U R384 R383
I2C ADDRESS
33 33
C424 C425 C426 C64 C421 C422 C423 C63 FMEM_CK0 FMEM_CKA0 CRT_CLOCK CRT_CLOCKA WRITE = 70
1N 10N 100N 1N 10N 100N READ = 71
10U 10U R

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百胜mylab30英文维修手册 unlocked PDF

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ESAOTE S.p.A.

The service manual is available in English only.

The manual is addressed to all the Service centres directly authorised by

• Section 1: 7300 Service Characteristics

In this manual a WARNING pertains to possible injury to the operator. A

1- 7300 Block Diagram ................................................................................................................1

1- Service Menu ...........................................................................................................................1

1- Maintenance Procedures ..........................................................................................................1

1- Error messages .........................................................................................................................1

1- Check List ................................................................................................................................1

1- Schematic Diagrams ................................................................................................................1

Identifying the boards

• by its Reference (950..), which is always indicated on the external side

The system configuration screen is organized in four folders:

Serial number It is the unit serial number

System Software The displayed data indicate:

• the release resident in the Processor board (RES).

System Licenses The active licences are listed in these fields.

To exit from the System Configuration screen press OK.

• the Configuration Index and the FW level of the boards

The initial self-test has a dual function:

System Configuration Error: Board(s) not available or not compatible

Updating the device

In order not to damage the parts during the disassembling procedures, it is

USB Pen Drive and Re-writable CD

1 - How to remove the

Recommandation Torque = 0,6 Nm

Recommandation Torque = 0,6 Nm

Recommandation Torque = 0,6 Nm

• Once access is gained to the fan/trackball group, remove the trackball

Recommandation Torque = 0,6 Nm

Recommandation Torque = 0,6 Nm

Recommandation Torque = 0,6 Nm

Recommandation Torque = 0,6 Nm

• the 7300 boards

The Mother board is affixed to the board’s chassis.

Recommandation Torque = 0,6 Nm

TRX1/TRX2, Control and Doppler Boards

TRX1 Board Removal procedure

Recommandation Torque = 0,6 Nm

Processor Board Processor Board

Recommandation Torque = 0,6 Nm

Programmed Hard Disk

Recommandation Torque = 0,4 Nm

Power Supply Board

Recommandation Torque = 0,6 Nm

Recommandation Torque ≤ 0,198 Nm

Recommandation Torque = 0,6 Nm

• Remove the CD burner by unscrewing the 3 slotted screws.

Recommandation Torque = 0,176 ÷ 0,235 Nm

LCD Cable Removal procedure

• Remove the LCD covers.

Recommandation Torque = 0,4 Nm

Recommandation Torque = 0,6 Nm

• Remove the three (3) the elastomer strips..

Upper Cover Removal procedure

Note: the accessing time has been qualified by multiples of 15 minutes

Parts with direct access

Parts with indirect access

Part Parts to be removed Time

Part Parts to be removed Time

1 - 7300 Block Diagram

SHEET PREPARED BY: CONTROLLED BY: APPROVED BY: DATE: DESCRIPTION: