SiFive Freedom Revolution

Krste  Asanovic,  Co-­‐Founder  and  Chief  Architect  

COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  

 SiFive Freedom Chip Platforms
•  Customer  designs  custom  SoC  by  combining:  
–  Pre-­‐integrated  configurable  base  SoC  architecture  
•  Processors,  interconnect,  on-­‐chip  IP,  off-­‐chip  interfaces  
–  Catalog  of  SiFive  +  DesignShare  partner  IP  
–  Customer  IP  

•  Each  plaJorm  built  for  specific  technology  

•  Two  SiFive  chip  plaJorms  previously  announced:  

–  Freedom  Everywhere,  TSMC  180nm  
–  Freedom  Unleashed,  TSMC  28nm  
 
2 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 Freedom Everywhere 32-bit Low-power microcontroller platform
FE310-G000 Chip GPIO Complex 3.3V MOFF Pads
UART0 1.8V MOFF Core
E31 Coreplex UART1
PWM0 (16-bit) GPIO
Instruction Cache Refill M
Instruction Cache PWM1 (8-bit)
(16KiB, 2-way) QSPI1 psd*
QSPI2
Branch Prediction

P-Bus: TileLink B32 D32

Instruction Fetch M
Instruction Buffer QSPI0 QSPI Flash
Inst. Decompressor OTP (8KiB)
Mask ROM (8KiB)
RV32IMAC
Clock Generation
vddpll
PLL vsspll
Multiplier/Divider
hfxoscin
Load/Store M HFXOSC hfxoscout

C-Bus: TileLink B32 D32

Data SRAM (16KiB) M HFROSC
dip Debug Module Always-On Domain
JTAG TAPC Debug RAM (28B) M 1.8V AON Pads
1.8V AON Core

A-Bus: TileLink B4 D32

Backup Registers
eip Platform-Level
Global PMU vddpaden
Interrupt Control
Interrupts hfclkrst
lip
Coreplex-Local Core Reset Sync corerst dwakeup_n
Interrupt Control rtccmpip Real-Time Clock
psdaon*
wdogcmpip Watchdog
Real-Time Clock Ticks LFROSC
Reset Unit erst_n

• 320+ MHz SiFive E31 CPU

• 16KB L1I$, 16KB Data Scratchpad
• Hardware Multiply/Divide, Debug
Module
• Multiple Power Domains Freedom E310, QFN48,
• Low-Power Standby manufactured in TSMC 180nm
3
• Wide Range of Clock Inputs
CONFIDENTIAL  –  COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 HiFive1: Arduino-Compatible RISC-V Dev Board

•  SiFive FE310-G000 (built in 180nm)

•  Operating Voltage: 3.3 V and 1.8 V
•  Input Voltage: 5 V USB or 7-12 VDC Jack
•  IO Voltages: Both 3.3 V or 5 V supported
•  Digital I/O Pins: 19
•  PWM Pins: 9
•  SPI Controllers/HW CS Pins: 1/3
•  External Interrupt Pins: 19
•  External Wakeup Pins: 1
•  Flash Memory: 16 MB Quad SPI
•  Host Interface (microUSB): Program, Debug, and
Serial Communication

Sold out, refresh coming soon!

4 CONFIDENTIAL  –  COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 Freedom Everywhere Example Tapeouts

•  TSMC 180nm
•  E2 series and E3 series cores
•  AlwaysOn, PMU
•  Scratchpad and/or caches
•  Analog and digital I/O
•  Alternate power supplies

5 CONFIDENTIAL  –  COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  

 Freedom Unleashed 64-bit Multi-Core RISC-V Linux Platform

• 1.5+ GHz U54-MC SiFive CPU

• 1x E51: 16KB L1I$, 8KB DTIM with ECC support
• 4x U54: 32KB L1I$, 32KB L1D$ with ECC support
• Single- and Double-precision floating-point support
• 2MB Banked L2$ with directory-based cache-coherence &
Freedom U540, FCBGA, manufactured in TSMC 28nm
ECC support
• ChipLink
• Serialized Chip-to-Chip Coherent TileLink Interconnect
• DDR3/4, GbE, Peripherals
6 CONFIDENTIAL  –  COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 HiFive Unleashed: World’s First Multi-Core RISC-V Linux Dev Board

•  SiFive FU540-C000 (built in 28nm)

•  8 GB 64-bit DDR4 with ECC
•  Gigabit Ethernet Port
•  32 MB Quad SPI Flash
•  MicroSD card for removable storage
•  MicroUSB for debug and serial
communication
•  Digital GPIO pins
•  FMC connector for future expansion
with add-in cards

Order for December delivery at crowdsupply.com for $999

7 CONFIDENTIAL  –  COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  

 Chip Templates: Pre-configured SoC starting points

Chip Designer
Preview at
8 sifive.com
COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 SiFive Freedom Revolution
•  High-­‐bandwidth  AI  and  networking  applicaSons  in  TSMC  16nm  
•  SiFive  7-­‐series  RISC-­‐V  processors  with  vector  units  
•  Cache-­‐coherent  TileLink  interconnect  
•  2.4  Gb/s  HBM2  memory  interface  
•  28-­‐56-­‐112  Gb/s  SerDes  links  (from  partner  Credo)  
•  Interlaken  chip-­‐chip  protocol  
•  High-­‐speed  40+Gb/s  Ethernet  

9 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  

 Freedom Revolution Platform Template
PCIe  Gen3/4  
SerDes  
Host   Custom  Compute  Array  
Interface   Compute  Tile  
Compute  Tile  
Debug/ ExecuQve  Tile   Compute  Tile  
Trace  
L1-­‐I$  
L1-­‐I$  
L1-­‐I$  
L1-­‐I$  
SPI,   U74  
U74  
UART,  
Digital   U74  
U7  Core   Compute  Tile   InterLaken  
I/O   L1-­‐D$  
L1-­‐D$   Chip-­‐Chip   SerDes  
GPIO   L1-­‐D$  
L1-­‐D$   S7   Custom  
DMA  
Core(s)   Accelerator  
Network   TileLink   TileLink  cache  
L2-­‐U$   TileLink  
SerDes   I/O   Serializer   coherent    
SRAM  
Ethernet   chip-­‐chip  
interconnect  
TileLink  Coherent  Cross-­‐Chip  Fabric  

HBM  Channel   HBM  Channel   HBM  Channel  

Controller   Controller   Controller  

10 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  

 HBM2 Phy + Controller
•  Silicon-­‐Proven  in  TSMC  16nm  
•  TSMC’s  OIP  Ecosystem  Forum  2017  
Customers’  Choice  Award  for  best  paper  
“HBM2”  

•  Total  bandwidth:  >300GB/s  

•  Data  transfer:  1.6-­‐2.4  Gb/s  
•  SiP  TSMC  CoWoS  (2.5D)  
•  Interposer  TSMC  65nm  
•  Interposer  trace  length  <  5mm  
•  Supports  all  HBM  stack  vendors  

•  IP  available  now  
•  Several  licensees  to  date  
11 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 Next-­‐GeneraSon  HBM2  IP  Subsystem    
Supports up to 3.2 Gbps/pin data rates and beyond
Supports up to 8 channels (16 pseudo channels)
AXI-based or TileLink-based HBM2 IP
subsystem development Supports up to >400GBytes of total bandwidth
Supports full DFI4.0 compliant controller and PHY interface
Targeting 3.2 Gbps per-pin data rates, Supports multi-port AXI interface or TileLink
and beyond, in TSMC’s latest 7nm Supports different schemes of arbitration and scheduling (QoS)
FinFET technologies
Supports different address mapping modes

12 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  

 Interlaken  IP  Subsystem  

Interlaken  IP  placement  in  the  chip  

ASIC/FPGA   PCB,  Backplane,   ASIC/FPGA  
High  Speed   Cable  

Customer  Logic  

Customer  Logic  
LLKN  FEC  
ILKN  FEC  
Channelized  Packet  

 SerDes  

 SerDes  
ILKN  

ILKN  
Interface  

Highly  Scalable  

Low  Latency  

Works  with  up  to  48  

Configurable  user  
parallel  physical  SerDes   Supports  bandwidth  of  
interface  of  128/256  bit  
lanes  3.125  Gbps  to  56   up  to  1.2  Tbps  
width  
Gbps  speeds  

Interlaken  IP    75+  licensees  to  date,  over  10+  years  

813 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 Ethernet  IP  Subsystem  
MAC  IP  +  PCS  IP  +  MCMR  FEC  IP  

Channelized  Flow  
MAC   IP  
Based   Flow-­‐Based  Client  Interface
Client  Interface
supports  
400/200/100/50/25/10GE  
client  port   PKT    /  FI

FlexE  IP  is  fully  compliant  to                                                                                              

OIF  Flex  Ethernet  Standard  v1.1   MCMR  
HIGH  LEVEL   FLEXE LOW  LEVEL   FEC  &  
PCS  &  RS   PCS   PHY
PCS  IP  supports  IEEE   PMA
standard  802.3  for  10G/25G/
40G/50G/100G/200G/400G  
data  rates   ODU  Interface
MCMR  FEC  (Forward  Error  
CorrecSon)  IP  supports  
Ethernet  standard  with  up  to   Flow-­‐Based  Client  
400G  data  rates  
Interface
14 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.  
 SiFive for IP components, or entire custom SoC
Available:  
–  RISC-­‐V  U7  and  S7  series  Core  IP    
–  TileLink  on-­‐chip  coherent  fabric  
–  TileLink  chip-­‐chip  coherent  serializaQon  (see  demo  with  WDC)  
–  2.4  Gb/s  HBM2  phy  and  controller  in  TSMC  16nm  FFC  
–  56-­‐112Gb/s  SerDes  in  TSMC  16nm  and  7nm  (from  partner  Credo)  
–  Interlaken  IP  
–  Ethernet  IP  
In  development:  
–  E7/U7  vector  and  custom  extensions  
–  3.2  Gb/s  HBM2  in  7nm  
–  Higher-­‐performance  RISC-­‐V  processors  

Please  come  talk  to  us  for  your  RISC-­‐V  AI  chip  needs!  

15 COPYRIGHT  2018  SIFIVE.    ALL  RIGHTS  RESERVED.