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Mega32C1)
8-bit
1. Introduction
Microcontrollers
The STK524 kit is made of the STK524 board, AVRCANAdapt and AVRLINAdapt
boards.
The STK524 board is a top module for the STK500 development board from Atmel Application Note
Corporation. It is designed to support the ATmega32M1, ATmega32C1 products and
future compatible derivatives.
AVRCANAdapt is a hardware driver for CAN network featuring the Atmel AT6660
CAN driver while the AVRLINAdapt is the hardware driver for LIN, featuring the Atmel
AT6661 LIN driver.
The STK524 includes connectors and hardware allowing full utilization of the new fea-
tures of the ATmega32M1 and ATmega32C1, while the Zero Insertion Force (ZIF)
socket allows easy to use of TQFP32 package for prototyping.
This user guide acts as a general getting started guide as well as a complete technical
reference for advanced users.
Notice that in this guide, the word AVR is used to refer to the target components
(ATmega32M1, ATmega32C1 and derivatives). ATmega32M1 and ATmega32C1 will
be also used to refer one of the products from this family.
Figure 1-1. STK524 Top Module for STK500 with LIN & CAN buses adapters
AVRLINAdapt AVRCANAdapt
2. Features
• STK524 is a New Member of the Successful STK500 Starter Kit Family.
• Supports the ATmega32M1 and ATmega32C1.
• CAN Interface thru Port using hardware bridge included
• LIN Interface thru Port using hardware bridge included
• Supported by AVR Studio® 4.
• Zero Insertion Force Socket for TQFP32 Package.
• High Voltage Parallell Programming.
• Serial Programming.
• 6 Pin Connector for On-chip Debugging using JTAGICE mkII or AVR Dragon emulators.
• Potentiometer for the Demo Application.
• Quick Reference to all Jumpers in the Silk-Screen of the PCB.
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Note: Connecting the STK524 with wrong orientation may damage the board.
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Figure 3-2. Pin1 on ZIF Socket
Pin1
Caution: Do not mount a ATmega32M1 or ATmega32C1 on the STK524 at the same time as an
AVR is mounted on the STK500 board. None of the devices might work as intended.
3.2.1 AVRLINAdapt
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3.2.2 AVRCANAdapt
See STK501CAN extension user’s guide for more detailed information
CAN AVR
port
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Figure 3-5. Connecting AVRLINAdapt & AVRCANAdapt to STK524
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To program the ATmega32M1 or ATmega32C1 using ISP Programming mode, connect the 6-
wire cable between the ISP6PIN connector on the STK500 board and the ISP connector on the
STK524 board as shown in Figure 4-1. The device can be programmed using the Serial Pro-
gramming mode in the AVR Studio4 STK500 software.
The STK500 & STK524 jumpers must follow the configuration:
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7780A–AVR–02/08
Table 4-1. In-System programming jumper settings for ATmega32M1/C1
STK500
VTARGET Mounted
AREF Optional
RESET Opened
XTAL1 Mounted
OSCSEL Mounted, pin 1 and 2
BSEL2 Optional
PJUMP Optional
STK524
VTG Mounted
Note: See STK500 User Guide for information on how to use the STK500 front-end software for ISP
Programming.
Note: Beware not having AVRLINAdapt connected to either J4 or J5 when doing In-System Program-
ming.
ISP and LIN share PD3 for MOSI_A & TXLIN, PE2 for SCK_A & RXLIN. Data received on
MOSI_A are output on TXLIN. RXLIN received data from TXLIN in regards of the LIN protocol,
then conflict occurs on SCK_A line.
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To program the AVR using High-voltage (Parallel) Programming, connect the PROGCTRL to
PORTD and PROGDATA to PORTB on the STK500 as shown in Figure 4-2. Make sure that the
TOSC-switch is placed in the XTAL position.
The STK500 & STK524 jumpers must follow the configuration :
Table 6-1. High-Voltage programming jumper settings for ATmega32M1/C1
STK500
VTARGET Mounted
AREF Optional
RESET Mounted
XTAL1 Mounted
OSCSEL Mounted, pin 1 and 2
BSEL2 Mounted
PJUMP Open
STK524
VTG Mounted
The device can now be programmed using the High-voltage Programming mode in AVR Studio
STK500 software.
Note: See the STK500 User Guide for information on how to use the STK500 front-end software in High-
voltage Programming mode.
Note: For the High-voltage Programming mode to function correctly, the target voltage must be higher
than 4.5V.
Figure 4-3 shows how to connect the JTAGICE mkII probe on the STK524 board.
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Figure 4-3. Connecting JTAGICE mkII to the STK524
The ISP connector is used for the ATmega32M1/C1 built-in debugWire interface. The pin out of
the connector is shown in Table 4-2 and is compliant with the pin out of the JTAG ICE available
from Atmel. Connecting a JTAGICE mkII to this connector allows On-chip Debugging of the
ATmega32M1/C1.
More information about the JTAGICE mkII and On-chip Debugging can be found in the AVR
JTAGICE mkII User Guide, which is available at the Atmel web site, www.atmel.com.
Note: Remove the RESET jumper on the STK500 to work run properly JTAGICE mkII.
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Note: MISO, MOSI & SCK lines can be disconnected when the product is in debugging mode. These
can be used then for application purpose.
(1)
: Let it opened if the address resistor of the AVRLINAdapt is selected.See “LIN bus adapter.”
on page 4
11
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4.6 Potentiometer
The STK524 includes a potentiometer. To use the potentiometer, please mount JP4 and use
JP5.2 line as Potentiometer output.
The potentiometer is supplied by AREF and it delivers a voltage to JP5.2. This line can be con-
nected to any Port lines or ADC input on the STK500.
The STK524 includes a footprint for a ZIF socket to evaluate QFN32 package. Socket is not
mounted but can be populated using the PN : QFN32 bt-0,65-01-00 from ENPLAS
5. Technical Specifications
System Unit
Physical Dimensions 56 x 119 x 27 mm
Weight 70 g
Operating Conditions
Voltage Supply 1,8V - 5,5V
Temperature 0°C - 50°C
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6. Technical Support
For Technical support, please contact avr@atmel.com. When requesting technical support,
please include the following information:
• Which target AVR device is used (complete part number).
• Target voltage and speed.
• Clock source and fuse setting of the AVR.
• Programming method (ISP or High-voltage).
• Hardware revisions of the AVR tools, found on the PCB.
• Version number of AVR Studio. This can be found in the AVR Studio help menu.
• PC operating system and version/build.
• PC processor type and speed.
A detailed description of the problem.
7. Complete Schematics
On the following pages the complete schematics and assembly drawing of the STK524 revision
A, AVRLINAdapt, AVRCANAdapt/STK501CAN extension are shown.
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14
5 4 3 2 1
PE1
D PE2 R1 D
AVR078
ID=0xCC 2K
R2
PE0 Q1 C2
Figure 6-1. Schematics, 1 of 4
BC847B 1nF
10K
VTG
VTG VTG VTG
J1 J2
100nF
1 GND GND 2 1 GND GND 2
3 AUXI1 AUXO1 4 3 AUXI0 AUXO0 4
C 5 6 5 6 C13 C
DATA7 DATA6 CT7 CT6 100nF
7 DATA5 DATA4 8 7 CT5 CT4 8
C1 9 DATA3 DATA0 10 9 CT3 CT2 10
11 DATA1 DATA9 12 11 CT1 BSEL2 12
13 14 13 14 REF AREFT
SI SO RESET (n.c.) REF PE2
15 SCK CS 16 15 NRST PE2 16
XT1 17 18 XT2 PE1 17 18 PE0
XT1 XT2 PE1 PE0
19 VTG VTG 20 19 GND GND 20
21 GND GND 22 21 VTG VTG 22
PB7 23 24 PB6 PC7 23 24 PC6
PB5
PB7 PB6 PB4 PC5
PC7 PC6 PC4
25 PB5 PB4 26 25 PC5 PC4 26
PB3 27 28 PB2 PC3 27 28 PC2
PB1
PB3 PB2 PB0 PC1
PC3 PC2 PC0
29 PB1 PB0 30 29 PC1 PC0 30
PD7 31 32 PD6 31 32
PD5
PD7 PD6 PD4
PA7 PA6
33 PD5 PD4 34 33 PA5 PA4 34
PD3 35 36 PD2 35 36
PD1
PD3 PD2 PD0
PA3 PA2 PE2
37 PD1 PD0 38 37 PA1 PA0 38
B
39 GND GND 40 39 GND GND 40 B
CON 2x20 CON 2x20
PE[2..0]
PE[2..0]
EXP. CON 1 EXP. CON 0
PD[7..0]
PD[7..0]
PC[7..0]
PC[7..0]
PB[7..0]
PB[7..0]
A A
STK524 MEZZANINE FOR STK500
Title
POWER & EXPANSION CONNECTORS
7780A–AVR–02/08
5 4 3 2 1
7780A–AVR–02/08
PD[7..0]
D D
PD3
PD[7..0]
TxD
J4
PC[7..0]
2 1 EXT1 EXT2 2
1 JP6 RXLIN 3 4 TXLIN PD3
EXT3 EXT4
Figure 6-2. Schematics, 2 of 4
PC3
PD4
C C
PE[2..0]
PE1
PD[7..0]
C3 J5
PC[7..0]
15pF Y1 1 2
RXLIN EXT1 EXT2 TXLIN PD3
8MHz 3 EXT3 EXT4 4
ISRC 5 6 TXCAN PC2
AREF_S EXT5 EXT6
PE2 RXCAN 7 8 NLSP PC7
EXT7 EXT8
9 GND VCC 10
C4
15pF PORT_COM2 C14 VTG
CON 2x5 100nF
B B
PC3
PD4
PD[7..0]
PD3
J3 VTG
PD2 1 2
PD4
PDO VCC
3 SCK PDI 4
PE0 5 6 C12
RESET GND 100nF
CON 2x3
A A
ISP CON STK524 MEZZANINE FOR STK500
PE[2..0]
Title
ISP, DebugWire, CAN, LIN, UART
15
AVR078
16
5 4 3 2 1
T2
AREFTP JP2
VTG 1 2 AREFT
JP1
L1 C7 ANA REF
1 2 10nF
BLM-21A102S C6 JP3
D D
VTG
AVR078
C5
100nF 100nF 1 2
ISRC
AVCC_S R3
Figure 6-3. Schematics, 3 of 4
VCC_S T1 1K
C8 AREF_S GND TP
100nF
PD0 PB7
PC0 PB6
PE0 PB5
PD1 PC7
C C
U101
32
31
30
29
28
27
26
25
PE0
PB7
PB6
PB5
PD1
PC0
PD0
PC7
1 24 PB4
PD2 PB4 PB3
2 PD3 PB3 23
PC1 3 22 PC6
PC1 PC6
4 VCC AREF 21
5 GND AGND 20
PC2 6 19
PC3
PC2 AVCC PC5
7 PC3 PC5 18
PB0 8 17 PC4
PB0 PC4
PB1
PE1
PE2
PD4
PD5
PD6
PD7
PB2
9
10
11
12
13
14
15
16
ATmega32M1_C1_tqfp32
B TQFP32 B
PB1 PB2
PE1 PD7
PE2 PD6
PD4 PD5
PE[2..0] PD[7..0]
PE[2..0] PD[7..0]
PC[7..0]
PC[7..0]
PB[7..0]
PB[7..0]
A A
STK524 MEZZANINE FOR STK500
Title
MICROCONTROLLER TQFP SOCKET
7780A–AVR–02/08
5 4 3 2 1
7780A–AVR–02/08
AREF_S
C10
D 10nF D
VCC_S
AVCC_S
C9 C11 2
100nF 100nF
JP4
Figure 6-4. Schematics, 4 of 4
P1 voltage
increases
when it is
turned in P1
PD0 PB7 the CW 100K
PC0 PB6 direction
PE0 PB5
PD1 PC7
C C
2
U102
32
31
30
29
28
27
26
25
JP5
1
PE0
PB7
PB6
PB5
PD1
PC0
PD0
PC7
PD2 1 24 PB4
PD3
PD2 PB4 PB3
2 PD3 PB3 23
PC1 3 22 PC6
PC1 PC6 (not connected)
4 VCC AREF 21
5 GND AGND 20
PC2 6 19
PC3
PC2 AVCC PC5
7 PC3 PC5 18
PB0 8 17 PC4
PB0 PC4
PB1
PE1
PE2
PD4
PD5
PD6
PD7
PB2
9
10
11
12
13
14
15
16
ATmega32M1_C1_qfn32
B QFN32 B
PB1 PB2
PE1 PD7
PE2 PD6
PD4 PD5
PE[2..0] PD[7..0]
PE[2..0] PD[7..0]
PB[7..0]
PB[7..0]
PC[7..0]
A A
STK524 MEZZANINE FOR STK500
Title
MICROCONTROLLER QFN32 SOCKET
17
AVR078
18
5 4 3 2 1
D D
AVR078
J1
1 2
Figure 6-5. ATAVRLINADAPT
3 4
5 6
7 8
JS2 GND 9 10 VTG
MASTER LIN
J2 CD075014 2X5 VTG
YMJ-02-O-BK CD075014 1X2 PORT
1
2
R1
D1
1k VTG
3 1 R2
C 10k C
R3 R4
1k BAS16W J3 1k
U1
J4 1 2
8 1 RxLIN 3 4 TxLIN
BAT INH RXD
3 7 VS EN 2 5 6
2 LIN 6 3 7 8
GND LIN WAKE
1 5 GND TXD 4 GND 9 10 VTG
CD075014 1X3 ATA6661-TAQJ CD075014 2X5
GND C1 PORT
LIN HEADER 100n
3
4
GND SW1
WUP LIN SKRAALE010 J6
J5
1 2
1
2
U2 2 1
3
B B
1 3 R5
2 4 2 JS6
3 ISRC GND CD075014 1X2 3266W-1-253_LF
4 MC 1,5/4-G-3,81
YMJ-02-O-BK
1
GND
<Variant Name>
ATMEL Nantes SA
La Chantrerie BP 70602
A 44306 Nantes Cedex 3 A
FRANCE
Title AVRLINADAPT
Size Document Number Rev
A PE020940 A
7780A–AVR–02/08
7780A–AVR–02/08
Figure 6-6. STK501 CAN Add On
OFF
CTRL
ON
JS5
J5
PH_2,54_3 X 1
SLOPE CTRL
3
2
1
SHUNT_CON_2,54
CAN2
2
Not mounted U2 Not mounted Not mounted
PD5 CANTx 1 R11 2 1 8 1 R13 2 CTRL CTRL R7
TXD RS
0R 0R 24K
1
VCC 2 7 CAN_H
GND CANH
J6
PD0 1 2 PD1 GND 3 6 CAN_L
VCC CANL
PD2 3 4 PD3
PD4 5 6 PD5 CANTx PD6 CANRx 1 R12 2 4 5 /SHDN GND
RXD SHDN
CANRx PD6 7 8 PD7 0R
9 10 Not mounted MAX3050ASA
VCC Not mounted
1
GND PH_2,54_5 X 2 C4 1 R2 2
2
2
4
6
8
10
1
VCC GND
C6 GND PH_2,54_5 X 2
2
1
3
5
7
9
2
100N_16V_X7R Not mounted
R6 Not mounted
GND 0R CAN_SHLDFLAT 1 R3 2
1
0R
GND
/SHDN
100N_16V_X7R
CAN_SHLDDB9 5
CAN1 GND CAN_V+ 9
U1 CAN_RES4 4 (4 res)
PD5 CANTx 1 R8 2 1 8 1 R10 2 CTRL CAN_RES8 8 (8 res)
TXD RS
CAN_GND 3
0R 0R
VCC 2 7 CAN_H CAN_H CAN_H 7
GND CANH
CAN_L CAN_L 2
GND 3 6 CAN_L CAN_GND 6
VCC CANL
2
2
J7 CAN_RES1 1 (1 res)
PD0 1 2 PD1 PD6 CANRx 1 R9 2 4 5 VREF R5 R4
RXD VREF
PD2 3 4 PD3 62R 62R 10
0R
1
1
2
2
1
CANRx PD6 PD7 R14 9_PIN_MALE
9 10 C3 0R 0R
VCC
2
1
1
1
AVR PORT D GND J4 J3
Not mounted C7 2 1 VSPLIT 2 1
2
1
100N_16V_X7R
C1 PH_2,54_2 X 1_B PH_2,54_2 X 1_B GND
2
SHUNT_CON_2,54 SHUNT_CON_2,54
19
AVR078
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7780A–AVR–02/08