VivadoLab-2018 1

Designing FPGAs Using the Vivado Design Suite 1
Lab Workbook
fpga-vdes1-2018.1-wkb-lab-rev1
Table of Contents
Lab 1: Vivado Design Suite Project-Based Flow ....................................... 3
Lab 2: Vivado Synthesis and Implementation ........................................ 35
Lab 3: Basic Design Analysis in the Vivado IDE ...................................... 61
Lab 4: Vivado Design Rule Checks ........................................................... 79
Lab 5: Vivado Design Suite I/O Pin Planning........................................ 101
Lab 6: Vivado IP Flow .............................................................................. 119
Lab 7: Introduction to Clock Constraints .............................................. 129
Lab 8: I/O Constraints and Virtual Clocks ............................................. 155
Lab 9: Timing Constraints Wizard .......................................................... 181
Lab 10: Xilinx Power Estimator Spreadsheet .......................................... 207
Lab 11: Introduction to Tcl ....................................................................... 227
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© Copyright 2018 Xilinx
Lab Workbook Lab 1: Vivado Design Suite Project-Based Flow
Lab 1: Vivado Design Suite Project-Based Flow

2018.1
Abstract
This lab provides a basic overview of the project-based design flow supported by, as well as the
simulation environment in, the Vivado® Integrated Design Environment (IDE).
This lab supports both Verilog and VHDL design files. However, the lab instructions and figures
show only Verilog usage.
This lab should take approximately 30 minutes.
Objectives
After completing this lab, you will be able to:
 Create a new project by using the New Project Wizard from the Vivado IDE
 Add design source files to the Vivado IDE project
 Add simulation source files to the Vivado IDE project
 Explore various Vivado IDE views and layouts
 Evaluate the project settings
 Simulate a design by using the Vivado simulator
Introduction
This lab guides you through the process of creating a new project and simulating it by using
existing RTL source files that describe a UART-based design called uart_led. The uart_led design
implements the RS-232 protocol, which receives serial data and displays its equivalent binary
value on LEDs.
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Lab 1: Vivado Design Suite Project-Based Flow Lab Workbook
A typical FPGA design flow is as follows:
1. Create a new project 10. Run DRC checker

2. Add/create source files 11. Synthesize
3. Integrate systems (embedded or DSP) 12. Add timing constraints and check timing
4. Add IP 13. Re-synthesize
5. Elaboration of RTL 14. Review design reports
6. RTL simulation 15. Implement
7. RTL analysis 16. Review design reports and perform static
timing analysis
8. Evaluate clocking resources
17. Evaluate design with routing resources
9. Plan I/O pin layout
and/or the Vivado logic analyzer
In order to get their design to work properly, many designers would say that they need to
backtrack in this process and repeat certain steps. Many designers would also lock their pins
earlier in the design flow. This flow is to illustrate the steps you will follow in this lab.
This lab explains how to create a new project, add existing design source files and design
constraints, add simulation source files (test benches) and simulate the design using the Vivado
simulator.
General Flow
Step 1: Step 2: Step 3: Step 4:
Creating Adding Exploring Simulating
a New Simulation the the
Project Source Files Vivado IDE Design
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Creating a New Project Step 1

You will begin the lab by launching the Vivado Design Suite to create a new
project using the New Project Wizard in the Vivado IDE.
The New Project Wizard in the Vivado IDE will create an XPR project file. The
Vivado IDE project file (.xpr) organizes your design files and saves the design
status whenever the processes are run from design entry through
implementation to programming the targeted Xilinx device.
There are a number of ways to launch the Vivado Design Suite. The two most
popular mechanisms are shown here.
1-1. Launch the Vivado Design Suite.

This can be done in two standard ways, use your preferred method.
1-1-1. For Windows 7: Select Start > All Programs > Xilinx Design Tools > Vivado 2018.1 >
Vivado 2018.1.
Figure 1-1: Launching the Vivado Design Suite from the Start Menu
For Windows 10: Select Start > Xilinx Design Tools > Vivado 2018.1.
-- OR --
Double-click the Vivado Design Suite shortcut icon ( ) on the desktop.
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The Vivado Design Suite opens to the Welcome window. From the Welcome window you
can create a new project, open an existing project, or enter Tcl commands directly into
the Vivado Design Suite as well as access documentation and examples.
Figure 1-2: Vivado Design Suite Welcome Screen
o Create Project opens the New Project Wizard to guide you through creating various
supported project types.
o Open Project opens Windows Explorer, allowing you to browse to an existing project
location and then open the project.
o Open Example Project allows you to open any of the provided example projects.
o Manage IP opens the IP catalog for customizing and managing IP.
o Open Hardware Manager opens the Vivado Design Suite hardware manager for
programming a design into a device. The Vivado logic analyzer and Vivado serial I/O
analyzer features of the tool enable users to debug a design.
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o Xilinx Tcl Store provides access to multiple scripts and utilities contributed from
different sources, which solve various issues and improve productivity. You can install
Tcl scripts and also contribute Tcl scripts to share your expertise with others.
o Documentation and Tutorials, Quick Take Videos, and Release Notes Guide in
the Information Center section open the Documentation Navigator. The
Documentation Navigator is integrated with the Vivado Design Suite, and it provides
a catalog of Xilinx documentation and videos. The Release Notes Guide link opens
the Release Notes, Installation documentation, and Licensing user guide. The Release
Notes provides information about what's new in this version of the Vivado Design
Suite.
Question 1
What are the different types of example projects provided by the Vivado Design Suite?
1-2. Create a new Vivado Design Suite project.

The project flow begins with the creation of a new project. The project contains
sources, IP, and other elements that are used to build a final bitstream.
1-2-1. Click Create Project (1).
Figure 1-3: Creating a New Vivado Design Suite Project
This will launch the New Project Wizard.

You can get help by clicking the ? icon in the bottom left of the dialog box.
1-2-2. Click Next to begin entering the specifics for this project (2).
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1-3. You will now encounter a series of dialog boxes asking you to enter
different pieces of information describing the project.
1-3-1. Enter uart_led in the Project name field.
1-3-2. Enter C:\training\Project_Flow\lab\[KCU105 | KC705]\[verilog | vhdl] in the Project
location field.
Alternatively, you can use the browse feature to navigate to where you want the project
to reside.
Note: If you prefer to use Verilog source files for creating the project, select Verilog in
the Project location directory. If you prefer to use VHDL source files, select VHDL. The
source files for creating the new project are provided in both Verilog and VHDL.
1-3-3. Deselect the Create Project Subdirectory option as leaving this checked will create an
unnecessary level of hierarchy for the lab.
Figure 1-4: Entering the Project Name and Location
1-3-4. Click Next to accept the selections and advance to selecting a type of project.
The Project type dialog box invites you to choose between different project types that
can be created.
Question 2
What are the various types of projects that can be made with the New Project Wizard?
Question 3
What is the purpose of the Do not specify sources at this time option?
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1-3-5. Select RTL Project since this project will be based on source code (rather than a netlist)
(1).
This enables you to add or create new HDL files and synthesize them, whereas a post-
synthesis project requires pre-synthesized files.
1-3-6. Since you will be adding RTL files in the next instruction, deselect the Do not specify
sources at this time option (2).
Figure 1-5: Setting the Project Type to RTL
1-3-7. Click Next to accept the selection and advance to the adding sources stage (3).
1-4. Add existing RTL source files.

Now that the project name, type, and location have been entered, the wizard asks
you to add source files to the project or directly write the RTL code. While adding
sources, you can add entire directories where the sources are located, add
specific files, or create new sources.
Begin by adding the sources to your project.
1-4-1. Click the Plus icon ( ) to begin adding objects to the project.
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1-4-2. Select Add Files from the pop-up menu to begin adding your source files to the project.
Figure 1-6: Adding Sources to the Project
After you add all the necessary files, the remainder of this dialog box will be addressed.
The Add Source Files dialog box opens.
1-4-3. Browse to the C:\training\Project_Flow\lab\[KCU105 | KC705]\[verilog | vhdl] directory (1).
Figure 1-7: Adding Source Files
1-4-4. Verilog users: Select or multi-select led_ctl.v, meta_harden.v, uart_baud_gen.v,

uart_led.v, uart_rx.v, and uart_rx_ctl.v (2).
VHDL users: Select or multi-select led_ctl.vhd, meta_harden.vhd, uart_baud_gen.vhd,
uart_led.vhd, uart_led_pkg.vhd, uart_rx.vhd, uart_rx_ctl.vhd (2).
1-4-5. Click OK to accept the selected files and add them as sources to the project (3).
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The Add Source Files dialog box closes and brings you back to the Add Sources dialog
box.
Figure 1-8: Setting Options in the Add Sources Window
1-5. Add any existing IP modules to the Vivado Design Suite project.
KCU105 users: Since there are no IP modules required for this design, click Next
and skip to the instruction that begins with "Add any existing constraints files to
the Vivado Design Project".
KC705 users: Add the clk_core IP in this design by using the steps below.
The clock_core IP is a clock management block (HDL code) that takes an input
clock of a certain frequency and generates output clock(s) with the desired
frequency using certain FPGA resources (MMCM and PLL). In the uart_led design
targeting the KC705, the clock core IP has been added so that the design meets
the timing requirements. When the design is targeting the KCU105, this IP is not
required to meet the timing requirements.
1-5-1. Click the Plus icon ( ) again to select the IP files.
1-5-2. Select Add Files to open the Add Source Files dialog box.
1-5-3. Select clk_core.xci.
1-5-4. Click OK to accept the selected files and add them as sources to the project.
If you have additional files located in other directories, you can repeat this instruction for
each directory.
1-5-5. Confirm that the Scan and add RTL include files into project option is selected (used
for Verilog only; it has no effect for VHDL) in the Add Sources dialog box (1).
This will automatically pull in any include files used by Verilog sources.
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1-5-6. Confirm that the Copy sources into project option is selected (1).
This will make a local copy of the source in the project space. Selecting this option
enables you to make changes to the local copy without affecting the original source file.
1-5-7. Make sure that your preferred language is selected from the Target Language drop-
down list (2).
This choice only affects which language is used for the generation of templates and
wrappers. You can add files in any language regardless of which target language is
selected. If you do not generate or use any templates or wrappers, this step is irrelevant
and you can select any language.
This will make a local copy of the sources in the project space. Selecting this option
1-5-8. Click Next to complete the adding of RTL sources and advance to adding any constraint
files (3).
1-6. Add any existing constraint files to the Vivado Design Suite project.
You will add uart_led.xdc to the project in the following instructions.
1-6-1. Click the Plus icon ( ) to select the type of object you want to import (1).
1-6-2. Select Add Files to open the Add Constraint Files dialog box.
The Add Constraint Files dialog box opens.

1-6-3. Browse to the C:\training\Project_Flow\lab\[KCU105 | KC705]\[verilog | vhdl] directory.
Figure 1-9: Adding Constraints
1-6-4. Select uart_led.xdc.

each directory.
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1-6-6. Confirm that the Copy constraints files into project option is selected (2).
Question 4
What are the different constraint types supported by the Vivado Design Suite?
1-6-7. Click Next to advance to selecting a target device (3).
1-7. Select the target part by first filtering by board and then by family. If you
are not using a supported board, you will need to filter by part.
1-7-1. Select Boards from the Select area (1).
1-7-2. Select All from the Vendor drop-down list in the Filter area (2).
This filters the available boards to those that are populated with any member of the
selected library.
1-7-3. Select Kintex UltraScale KCU105 Evaluation Platform | Kintex -7 KC705 Evaluation
platform from the board list.
Alternatively, you can select the board directly from the list at any time while in this
dialog box.
Figure 1-10: Selecting the Board for the Project
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Question 5
What are the device part numbers corresponding to the KCU105 and KC705 evaluation platform
boards?
1-7-4. Click Next to advance to the summary (3).
A summary of your project is displayed. If you want to change any of the information
that you entered, you can do that now by clicking Back until you reach the correct dialog
box and making the correction, or you can create the project now and edit the project
properties and add or remove files later.
1-7-5. Click Finish.
Your project is constructed and you are presented with the Vivado Design Suite main
workspace environment.
Adding Simulation Source Files to the Project Step 2

You have added design sources while creating the project. You will now add the
simulation source files from the working directory into the project.
The Add Sources Wizard allows you to add or create RTL source files, simulation
source files, constraint files, DSP modules, or embedded processors as well as
add existing IP.
2-1. Add simulation files to the design.

2-1-1. Select Add Sources under Project Manager in the Flow Navigator.
Figure 1-11: Selecting Add Sources
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2-1-2. Select Add or create simulation sources.
Figure 1-12: Add Sources Dialog Box
2-1-3. Click Next.
2-1-4. Click the Plus ( ) icon and select Add Files to open the Add Source Files dialog box,
which allows you to browse to the desired directory.
2-1-5. Browse to the C:\training\Project_Flow\lab\[KCU105 | KC705]\<language> directory.
2-1-6. Verilog users: Select the following simulation source files:
o tb_fifo.v
o tb_resetgen.v
o tb_resp_checker.v
o tb_uart_driver.v
o tb_uart_rx.v
o test_uart_rx.v
VHDL users: Select the following simulation source files:
o string_utilities_sim_pkg.vhd
o string_utilities_synth_pkg.vhd
o tb_fifo_pkg.vhd
o tb_resp_checker.vhd
o tb_uart_driver.vhd
o test_uart_rx.vhd
o time_utilities_pkg.vhd
2-1-7. Click OK.
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2-1-8. VHDL users only: Associate the VHDL package files to their corresponding libraries.
2-1-9. Double-click in the Library column in front of each VHDL file and type the library name
as given below.
The utilities_lib library should have the following package files:
o string_utilities_sim_pkg.vhd
o string_utilities_synth_pkg.vhd
o time_utilities_pkg.vhd
The specific_support_lib library should have the following package files:
o tb_fifo_pkg.vhd
The remaining files go into the default sim library (xil_defaultlib):
o tb_resp_checker.vhd
o tb_uart_driver.vhd
o test_uart_rx.vhd
Figure 1-13: Associating VHDL Package Files to Their Corresponding Libraries
2-1-10. Click Finish to add the simulation files to the project.
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2-2. Analyze the hierarchy of the design using the Hierarchy tab of the Sources
window.
The Sources window displays the design sources, constraint files, simulation
sources, and IP cores of the project.
The Design Sources folder helps you keep track of Verilog and VHDL design
source files and libraries. The Constraints folder helps you manage constraint
files. The Simulation Sources folder helps you organize Verilog and VHDL
simulation source files and libraries.
Notice that the design hierarchy is shown by default.
The Hierarchy tab of the Sources window displays the hierarchy of the design
modules and instances. The top module defines the hierarchy of the design for
compilation, synthesis, and implementation. The Vivado IDE automatically detects
the top module.
2-2-1. Select the Hierarchy tab in the Sources window.
2-2-2. Click the Expand All ( ) icon to view all the files.
Question 6
What is the name of the top module in the design?
In the Libraries tab, sources are grouped by file type, while the Compile Order tab shows the
compile order used for synthesis.
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2-3. VHDL users only: Make sure that you see the correct VHDL package files
available under the utilities_lib and specific_support_lib libraries.
You should see the following structure in the Libraries tab.
Figure 1-14: VHDL Package Files in the Libraries
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Exploring the Vivado IDE Step 3

In this step, you will explore the various views and layouts in the Vivado IDE.
By default, the Vivado IDE opens with the Default layout. Each docked window in
the Vivado IDE is called a view.
3-1. Explore the various views of the Vivado IDE.
Figure 1-15: Vivado IDE Default Layout- KCU105
The vertical toolbar present on the left of the Vivado IDE is the Flow Navigator. The
Flow Navigator view provides control over the major design process tasks, such as
project configuration, synthesis, implementation, and bitstream creation.
Note that the Flow Navigator reflects the typical FPGA design flow of design entry >
behavioral simulation > synthesis > implementation > static timing analysis >
bitstream generation. The Flow Navigator takes you from design construction (top) all
the way through implementation (middle) and ends with programming the FPGA
(bottom).
The Sources window displays the list of source files that have been added to the project.
The Sources window will automatically recognize your design’s hierarchy based on the
instantiation of components in your HDL. It also references your design constraints files
that store timing objectives and pin assignment information.
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The Compile Order tab in the Sources window displays the source files in the order in
which they will be compiled and the processing order for constraints.
The Project Summary view provides a brief overview of the status of different processes
executed in the Vivado IDE. It also provides access to the most common design reports,
such as DRC violations and timing and design information, including estimated power
consumption, design performance, device utilization, and power.
The Properties window provides the properties of a selected object. Every time you
select an element/instance from the design netlist, its information can be found here.
The Project Status (top-right corner) displays the current status of the active design.
Question 7
What is the current status of the project?
3-2. Explore the horizontal toolbar.

The horizontal toolbar provides options for creating a new project, opening an existing
project, running synthesis, etc.
Figure 1-16: Horizontal Toolbar
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3-3. Expand the layout selector drop-down list to see if any layouts are available.
Even though there is no layout available at this stage, the Vivado IDE provides
predefined window layouts to facilitate various tasks in the design process. The
layout selector enables you to easily change window layouts.
During the later stages of this lab, when these layouts will be available to you, the
Layout Selector drop-down menu will show the following selections:
o Default Layout: Analyze your design with a minimum set of windows.
o I/O Planning: Define I/O placement constraints and place ports.
o Clock Planning: Cross-probe between the Clock Resources window, Device window,
and I/O Port window to plan and place clock resources in the design.
o Floorplanning: Define Pblocks, manage partitions, and perform hierarchical
floorplanning.
o Debug: Define debug nets and configure debug cores.
o Timing Analysis: Run timing reports and analyze timing.
Question 8
Why are layouts not available at this stage?
3-4. Briefly explore the Project Summary view for the design.
The Vivado IDE includes an interactive project summary that updates dynamically
as design commands are run and as the design progresses through the design
flow. It provides project and design information, such as the project part, project
status, and state of synthesis and implementation.
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It also provides links to detailed information, such as links to the Messages, Log,
and Reports windows as well as the Settings dialog box. As synthesis and
implementation complete, DRC violations, timing values, utilization percentages,
and power estimates are also populated.
Figure 1-17: Project Summary View - KCU105
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3-5. Explore the Settings dialog box for the design.

The Settings dialog box displays the project name, device family, project part, and
top module.
Figure 1-18: Settings Dialog Box - General
Question 9
What settings can you configure in the Settings dialog box?
Question 10
What are the project name, project device, and target language for the design?
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3-6. Select the Simulation tab in the Settings dialog box.

The Simulation tab enables you to specify the target simulator and displays the
simulation set and simulation top module name.
Figure 1-19: Settings – Simulation
Question 11
What is the target simulator for the design? What third-party simulators are supported?
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3-7. Select the Synthesis tab in the Settings dialog box.

The Synthesis tab shows the default constraints set, synthesis strategies, and
synthesis options.
A strategy is a set of switches to the tools that are defined in a preconfigured set
of options for the synthesis application or the various utilities and programs that
run during implementation.
Figure 1-20: Settings – Synthesis
Question 12
What is the synthesis strategy for this design?
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3-8. Select the Implementation tab in the Settings dialog box.

The Implementation tab provides an options area for selecting an
implementation strategy and for selecting options during implementation. The
Run report ultrafast methodology after routing option checks for UltraFast
methodology guidelines after routing. Use Incremental Compile for last-minute
HDL changes and save time by only placing and routing logic that has changed.
Additionally, other options can be set individually as described by the following:
o opt_design: Optimizes the current netlist. This will perform the retarget,
propconst, sweep, and bram_power_opt optimizations by default.
o power_opt_design: Optimizes dynamic power using intelligent clock gating.
o phys_opt_design: Optimizes the current placed netlist.
o place_design: Automatically places ports and leaf-level instances.
Figure 1-21: Settings – Implementation
Question 13
What is the implementation strategy for this design?
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3-9. Close the Settings dialog box.

3-9-1. Click Cancel to exit the Settings without making any changes.
3-10. Explore the Design Runs window at the bottom of the GUI.
The Design Runs window allows you to view, configure, launch, and analyze
synthesis and implementation runs.
Note: If you do not see any particular columns in the Design runs window or
would like to see more columns, right-click any column header and select the
column name you would like to add.
Each column in the Design Runs tab is used to track information as described
below:
o Name: Displays run name.
o Constraints: Displays the constraint set used for the run.
o Status: Indicates run status as not started, running, complete, or error.
o Progress: Displays the percentage complete (0 to 100%).
o Start: Reports the start time for the run.
o Elapsed: Reports the elapsed time for the run.
o Strategy: Displays the strategy assigned to the run.
o Part: Indicates the target part selected for the run.
Timing Summary Data:
o WNS: Displays worst negative slack.
o TNS: Displays total negative slack.
o WHS: Displays worst hold slack.
o THS: Displays total hold slack.
o TPWS: Displays total pulse width negative slack.
o Failed Routes: Displays the number of nets that failed to route, are partially routed,
or have conflicts.
o Description: Displays the description associated with the run. This description is set
initially to a strategy description when that strategy is applied to the run.
The Create New Runs Wizard (select Flow > Create Runs) allows you to create multiple
runs for synthesis, implementation, or both with different synthesis and implementation
strategies and constraints sets.
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Question 14
How many synthesis and implementation runs have been created for this design?
3-11. Create a synthesis run with the Flow_ RuntimeOptimized strategy.

This step shows how new design runs for synthesis and implementation can be
created if required.
3-11-1. Right-click in the Design Runs window and select Create Runs or click the icon in the
Design runs window.
Figure 1-22: Creating a New Synthesis Run
The Create New Runs Wizard opens.

3-11-2. Select Synthesis as the type of run that you want to create.
3-11-3. Click Next to configure the synthesis run.
3-11-4. Select Flow_RuntimeOptimized as the strategy in the Configure Synthesis Runs
window.
3-11-5. Click Next to set the launch options.
3-11-6. Select Do not launch now in the Launch Options window and leave the other fields at
their default selections.
This option allows you to launch the runs later.
3-11-7. Click Next to view the summary of the run created.
3-11-8. Click Cancel to keep the Create New Runs wizard from proceeding, as it is not necessary
to create a new synthesis run at this point.
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Simulating the Design Step 4

The Vivado simulator, integrated with the Vivado IDE, enables you to run
behavioral and structural logic simulation at each stage of the design as well as
timing simulation at post implementation. The simulator supports Verilog and
VHDL mixed-mode simulation, and the results are displayed in a unified
waveform viewer. Third-party simulators (such as ModelSim, Questa Sim, Riviera
PRO, and Active HDL) can also be used.
Question 15
What is the current name of the simulation top module? Why does it have to be changed?
4-1. Set the testbench (test_uart_rx.v/vhd) as the top module for simulation.
4-1-2. Right-click test_uart_rx .v under Simulation Sources > sim_1 and select Set as Top.
Figure 1-23: test_uart_rx.v Set as Top under Simulation Sources
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4-2. Run behavioral simulation using the Vivado simulator.

4-2-1. Click Run Simulation in the Flow Navigator under Simulation and select Run Behavioral
Simulation.
The tool will compile the testbench and launch the Vivado simulator.
Note that the Vivado IDE view changes and is now populated with views required for
simulation.
By default, a waveform viewer called untitled1 will appear, displaying only the signals at
the top level of the testbench.
The simulation has already been run for 1 microsecond, which is the default run time
specified under Simulation Settings.
4-3. Verilog users: Add the signals of interest for simulation.

VHDL users: Skip ahead to the instruction below that begins with "Change
the radix of signals to ASCII."
The top-level testbench for this design includes only some parameters and the
character being sent to the UUT. In order for the actual inputs and outputs of the
UUT to be seen, they need to be added to the waveform viewer and the
simulation must be restarted.
4-3-1. Select the Scopes window.
4-3-2. Expand test_uart_rx > tb and select uart_rx_i0.
Figure 1-24: Browsing the Simulation Hierarchy
The signals in the uart_rx_i0 module that you will add to the waveform window are
displayed in the Objects window.
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4-3-3. Select clk_rx, and while pressing the <Shift> key, click baud_x16_en to select all of the
signals at this level of the hierarchy.
4-3-4. Right-click and select Add to Wave Window.
Figure 1-25: Adding Signals to the Waveform Window
Alternatively, you can drag-and-drop the signals into the waveform window.
The signals are added to the bottom of the waveform window, but no values are
displayed because the simulator only saves signal values for signals that are displayed
when the simulation is run. The simulation must be restarted for the values on the new
signals to be seen.
4-4. Change the radix of signals to ASCII.

4-4-1. Select the waveform window.
4-4-2. Right-click rx_data[7:0] and select Radix > ASCII.
4-4-3. Verilog users: Repeat the same for char_to_send[7:0] and string[0:343].
VHDL users: Repeat the same for data_to_send[7:0].

Now the transmitted data stream becomes much easier to read.
Question 16
How do you display an analog-style waveform in the waveform viewer?
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4-5. Restart and run simulation to see the results on the newly added signal in
the waveform window.
4-5-1. Click the Restart toolbar icon ( ) in the horizontal toolbar at the top (not the Go to
Time 0 icon) to restart the simulation.
4-5-2. Click the Run All toolbar icon ( ) to rerun the simulation.
The simulation terminates when the simulator reaches $stop in the Verilog testbench
code or in VHDL, severity failure.
4-6. Analyze the simulation results.

4-6-1. Scroll through the Tcl Console to ensure that the sending character and character
received are the same.
Figure 1-26: Tcl Console Showing Sent and Received Characters
4-6-2. Select the Waveform window.
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4-6-3. Zoom in to the waveform window to visually inspect the received characters.
4-6-4. Verify that rx_data[7:0] has the same value as char_to_send[7:0] (or data_to_send[7:0]
for VHDL) whenever rx_data_rdy is high.
Hint: Select the rx_data_rdy signal in the waveform window and examine whether the
char_to_send[7:0] (or data_to_send[7:0] for VHDL) and rx_data[7:0] signals have the
same value at each rising edge of the rx_data_rdy signal as shown in the figure below.
Figure 1-27: Analyzing Simulation Waveforms
4-7. Close the Vivado simulator.

4-7-1. Click the X on the right side of the Simulation window banner and click OK to close the
simulator.
The Save Waveform Configuration dialog box opens.
4-7-2. Click Discard in the dialog box as there is no need to save any changes in the waveform
configuration file.
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4-8. Close the project.

4-8-1. Select File > Close Project to close the project.
The Close Project dialog box opens.
Figure 1-28: Close Project Dialog Box
4-8-2. Click OK.
4-9. Close the Vivado Design Suite.

4-9-1. Select File > Exit.
The Exit Vivado dialog box opens.
Figure 1-29: Exit Vivado Dialog Box
4-9-2. Click OK.
Summary
In the lab, you created a project using the New Project Wizard. You added design and
simulation source files to complete the project. The various views in the Vivado IDE were
observed. You also explored and evaluated the project settings provided by the Vivado Design
Suite. Finally, you performed behavioral simulation of the design using the Vivado simulator.
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Lab Workbook Lab 2: Vivado Synthesis and Implementation
Lab 2: Vivado Synthesis and Implementation

2018.1
Abstract
This lab reviews the process of synthesizing, implementing, and generating a bitstream.
show only VHDL usage.
Objectives
 Synthesize a design by using the Vivado® IDE or Tcl Console
 Implement the design by using the Vivado IDE
 Generate the bitstream
 Program a Kintex® UltraScale™ or a Kintex-7 FPGA (optional)
Introduction
In this lab, you will explore synthesis, implementation settings and optionally download the
uart_led design onto a Kintex UltraScale FPGA KCU105 evaluation board or a Kintex-7 FPGA
KC705 evaluation board to verify that the design works correctly.
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Lab 2: Vivado Synthesis and Implementation Lab Workbook
The uart_led design receives data on a serial RX port and displays its binary equivalent value on
LEDs.
Figure 2-1: Block Diagram of the uart_led Design
This design implements an RS-232 protocol that receives serial data at 115200 baud rate (no
parity, 8 data bits, no handshaking). When a character is successfully received, its binary
equivalent displays on the LEDs. The eight significant bits are shown by default. Pressing a
button (btn_pin) on the board shows the swapping of the four most and least significant bits.
In this lab, the input serial data will be the ASCII characters you will enter using a Tera Term
terminal. The binary equivalent of all ASCII characters is provided in
C:\training\Synth_Impl\support\ascii_table.pdf. The eight LEDs on the evaluation board will be
used to show the binary equivalent of the ASCII character entered by you.
General Flow
Opening an Synthesizing Implement- [Optional]
Existing the ing the Downloading
Project Design Design Bitstream
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Opening an Existing Project Step 1

You will begin by launching the Vivado Design Suite and opening the uart_led
design in the Vivado IDE.

Vivado 2018.1.
-- OR --
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1-2. Open the existing Vivado Design Suite project uart_led.xpr.

1-2-1. Click Open Project from the Quick Start section (1).
The Open Project dialog box opens (2).

1-2-2. Browse to the C:\training\Synth_Impl\lab\[KCU105 | KC705]\vhdl directory in the Look in
field (3).
Note: The drop-down arrow shows the directory hierarchy.
1-2-3. Select uart_led.xpr (4).
Figure 2-4: Opening an Existing Project
1-2-4. Click OK to open the selected project (5).
The project now opens in the Vivado Design Suite.
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Exploring Synthesis Settings and Synthesizing the Design Step 2

Here you will explore some of the synthesis settings and run design synthesis
based on the settings selected.
2-1. Set the synthesis options.

2-1-1. Click Settings in the Flow Navigator under Project Manager and then select Synthesis.
Alternatively, you can select Flow > Settings > Synthesis Settings.
Figure 2-5: Selecting Synthesis Settings
The Settings dialog box opens, allowing you to set options such as -
flatten_hierarchy, -fanout_limit, -fsm_extraction, etc., to meet specific
needs of the design.
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The tcl.pre and tcl.post options allow you to provide pre-synthesis and post-
synthesis Tcl files. For example, a post-synthesis Tcl file may have Tcl commands for
generating various reports.
Figure 2-6: Settings – Synthesis
The options available in the Synthesis settings dialog box are listed below:
 –flatten_hierarchy: Determines how Vivado synthesis controls hierarchy.
 –gated_clock_conversion: Turns on and off the synthesis tool's ability to convert the
clocked logic with enables.
 –bufg: Controls how many BUFGs the tool infers in the design.
 –fanout_limit: Specifies the number of loads a signal must drive before it starts
replicating logic.
 –directive: Replaces the effort_level option. When specified, this option runs Vivado
synthesis with different optimizations. Values are Default and RuntimeOptimized,
which run synthesis quickly and with less optimization.
 –fsm_extraction: Controls how synthesis extracts and maps finite state machines.
You can choose from the following options to encode the state machine in a specific
encoding type: off, one_hot, sequential, johnson, gray, or auto.
 -keep_equivalent_registers: Prevents merging of registers with the same input logic.
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 -resource_sharing: Sets the sharing of arithmetic operators between different signals.

The values are auto, on, and off.
 -control_set_opt_threshold: Sets the threshold for clock enable optimization to the
lower number of control sets. The default is 1.
 -no_lc: When checked, this option turns off LUT combining.
 -shreg_min_size: Is the threshold for inference of SRLs. The default setting is 3.
Question 1
What are the values available for -flatten_hierarchy?
2-2. Select the rebuilt value for the -flatten_hierarchy option, if not already set.
Selecting this option is recommended because this allows the design hierarchy to
be flattened for optimizing combinatorial logic, then rebuilt, making it more
useful for design analysis since many logical references will be maintained.
2-3. Click OK in the Settings dialog box and click No in the Create New Run
dialog box.
2-4. Select a synthesis strategy.

A strategy is a set of switches to the tools that are defined in a preconfigured set
of options for the synthesis application or the various utilities and programs that
run during implementation.
The Vivado IDE provides predefined strategies and also allows you to create your
own strategies.
2-4-1. Select Tools > Settings.
2-4-2. Select Tool Settings > Strategies > Run Strategies in the Settings dialog box.
2-4-3. Select Vivado Synthesis 2018 from the Flow drop-down list, if it is not already selected.
Question 2
What are the available synthesis strategies?
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2-4-4. Select the Flow_RuntimeOptimized strategy.
Question 3
What are the assigned values of -flatten_hierarchy, -directive, and -
fsm_extraction for the Flow_RuntimeOptimized strategy?
2-5. Create a user-defined synthesis strategy.

2-5-1. Create a synthesis strategy named My_Synthesis_Strategy with the following options:
o -Type = Synthesize
o -flatten_hierarchy = Full
o -fsm_extraction = one_hot
o Rest all at their default settings
Question 4
How do you create a user-defined synthesis strategy?
2-5-2. Delete the user-defined synthesis strategy.
Note: Leaving this user-defined strategy as active will make it the default strategy
whenever you run synthesis the next time.
2-5-3. Close the Settings dialog box without saving any changes.
2-6. Apply the basic timing constraints.

2-6-1. Double-click uart_led.xdc under Constraints > constrs_1 in the Sources window.
2-6-2. Uncomment the create_clock constraint to apply clock constraints to the design.
This constraint creates the primary clock clk_pin_p with a frequency 125 MHz (KCU105)
or 200 MHz (KC705).
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2-6-3. Uncomment the set_input_delay and set_output_delay constraints to apply input and
output delays to the design.
These will constrain the design I/O ports with specified input and output delay values.
The delay value specified in the set_input_delay and set_output_delay constraints
corresponds to the delays outside the FPGA, such as board trace delay and clk-to-out
delay.
2-6-4. Select File > Save File.
2-6-5. Close the uart_led.xdc file.
2-7. Run synthesis.

2-7-1. Click Run Synthesis in the Flow Navigator under Synthesis
2-7-2. Click OK to launch the runs.
Alternatively, you can also select Flow > Run Synthesis or press <F11>.
Figure 2-7: Selecting Run Synthesis
2-7-3. Click Save if you are asked to save your files.
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After the synthesis process completes, the Synthesis Completed dialog box opens. The
dialog box prompts you to run implementation, open the synthesized design, or view
reports.
Figure 2-8: Synthesis Completed Dialog Box
2-8. Review the Utilization report.

2-8-1. Select Open Synthesized Design from the flow navigator.
The Vivado IDE opens the synthesized netlist, the active constraint set, and the target
device in the Synthesized Design environment, which allows you to perform I/O pin
planning, design analysis, and floorplanning.
2-8-2. Open the Utilization Report from the Reports tab at the bottom of the Vivado IDE.
Question 5
Fill in the following table with the total number of FPGA resources used by the design.
FPGA Resources Number of Resources Consumed by the Design
BUFGCTRL
CLB/Slice LUTs
CLB/Slice Registers
Bonded IOBs
2-8-3. Select Report Utilization under Open Synthesized Design from the flow navigator.
2-8-4. Select Summary from the Utilization tab at the bottom of the Vivado IDE.
Question 6
What is the utilization percentage of LUTs, flip-flops, and I/O for the design?
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2-9. Verify the constraint coverage in the design by using the report generated
by the check_timing command.
Hint: Select Reports > Timing > Check Timing.
The check_timing report identifies the missing timing checks in the design.
Some of the supported timing checks are the following:
o no_clock: Number of clock pins reached by a zero timing clock.
o constant_clock: Number of register/latch pins with constant_clock.
o pulse_width_clock: Number of register/latch pins which need pulse_width check.
o unconstrained_internal_endpoints: Number of path endpoints without a timing
requirement.
o no_input_delay: Number of input ports without at least one input delay constraint.
o no_output_delay: Number of output ports without at least one output delay
constraint.
o multiple_clock: Number of clock pins reached by more than one timing clock.
o generated_clocks: Number of missing generated clock definitions.
o loops: Number of timing loops found in the design.
o partial_input_delay: Number of input ports with partially defined input delay
constraints.
o partial_output_delay: Number of output ports with partially defined output delay
constraints.
o latch_loops: Number of combinatorial latch loops in the design.
The check_timing report provides the summary of any missing timing constraints
according to the timing engine.
Question 7
Why is the check_timing report important for complete sign-off?
2-10. Close the synthesized design.

2-10-1. Select File > Close Synthesized Design.
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The Confirm Close dialog box may open.
Figure 2-9: Confirm Close Dialog Box
2-10-2. Click OK to close the synthesized design if the Confirm Close dialog box opens.
Alternatively, you can also close the synthesized design by clicking the X in the
Synthesized Design status bar at the top, or entering the Tcl command close_design
in the Tcl Console.
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Exploring Implementation Settings and Implementing the

Design Step 3
In this step, you will explore implementation settings and run implementation.
Implementation in the Vivado Design Suite is a timing-driven flow. It supports
industry-standard Synopsys design constraints (SDC) commands to specify
design requirements and restrictions, as well as additional commands in the Xilinx
design constraints (XDC) format.
3-1. Open the Implementation Settings dialog box to explore the

implementation settings.
The Implementation Settings dialog box allows you to set options to meet
specific needs of the design. It allows you to change the options for the various
implementation steps, such as opt_design, power_opt_design,
place_design, phys_opt_design, route_design, and
write_bitstream.
Figure 2-10: Settings – Implementation
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Question 8
What are the implementation sub-processes? What does each sub-process do?
3-2. Close the Implementation Settings dialog box.

3-2-1. Click Cancel in the Settings dialog box.
3-3. Select an implementation strategy.

3-3-1. Select Tools > Settings.
3-3-2. Select Tool Settings >Strategies > Run Strategies in the Settings dialog box.
3-3-3. Select Vivado Implementation 2018 from the Flow drop-down list.
Question 9
What are the implementation strategies available for the Vivado Design Suite?
3-3-4. Select the Performance_Explore strategy from the list of strategies.
Question 10
What is the assigned value of -directive for opt_design, place_design, and
route_design?
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3-4. Create a user-defined implementation strategy.

3-4-1. Create an implementation strategy named My_Implementation_Strategy with the
following options:
o -directive = RuntimeOptimized in the opt_design, place_design, and
route_design stages
o Rest all at their default settings
Figure 2-11: Selecting the Implementation Type
Question 11
How do you create a user-defined implementation strategy?
3-4-2. Select the Flow_RuntimeOptimized strategy from the list of strategies.
Question 12
Does the Flow_RuntimeOptimized strategy have the same options as that of the user-defined
My_Implementation_Strategy strategy?
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3-4-3. Explore the values available for -directive of opt_design, place_design,

phys_opt_design, and route_design.
Question 13
What is the phys_opt_design stage?
3-4-4. Delete the user-defined implementation strategy as this strategy is not needed.
3-4-5. Close the Options dialog box without saving any changes.
3-5. Run implementation with the Vivado Implementation Defaults 2018

strategy.
3-5-1. Click Run Implementation under Implementation in the Flow Navigator.
3-5-2. Click OK to launch runs.
3-6. Open the implemented design.

When you open the implemented design, the Vivado IDE imports the netlist,
design constraints, the target part, and the results from the place and route into
the Vivado IDE for design analysis and further work as needed.
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3-7. Examine the options available under Open Implemented Design in the Flow
Navigator.
The Flow Navigator points to the most important reports, such as Timing
Summary Report, Utilization Report, etc.
Figure 2-12: Flow Navigator Options – Post Implementation
3-8. Examine the reports available in the Reports tab at the bottom of the
Vivado IDE.
The Reports tab contains several useful reports, including log files for synthesis
and implementation runs.
3-9. Open the Control Sets Report from the Reports tab within Place Design at
the bottom of the Vivado IDE.
This report describes the number of unique control sets in the design and also
provides information about how control signals are grouped.
Question 14
How many unique control sets are there in the design?
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Question 15
How many registers sites are lost due to control set restrictions?
The report determines the ability of the tools to reach high device utilization. The number of
controls signals in the design is determined by the designer's inference of sets, resets, and
clock enable signals. The number of control signals can be reduced if the designer attempts
to share controls signals throughout the design as much as possible.
Note: Xilinx recommends using synchronous sets/resets whenever possible and that
designers reduce the number of control signals in their design to improve device utilization.
[Optional] Generating and Downloading the Bitstream Step 4

In this step, you will generate the bitstream and download onto the KCU105 or
KC705 evaluation board.
Configuration is a process of loading the configuration data onto the FPGA. For
more information about configuration, you can view the Configuration Recorded
E-Learning (REL) at www.xilinx.com/training/fpga/basic-fpga-configuration-
video.htm.
4-1. Generate the bitstream.

4-1-1. Locate the Generate Bitstream entry under Program and Debug in the Flow Navigator.
Figure 2-13: Generate Bitstream in the Flow Navigator
4-1-2. Click Generate Bitstream to start the bitstream generation.
A .bit file will be generated in the working project under the uart_led.runs\impl_1
directory.
The status indicator in the upper right-hand corner of the workspace, as well as in the
design runs console, will indicate when bitstream generation is complete.
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4-2. Power on the evaluation board.

Connect a USB cable from a USB port on your computer to the USB UART
connector on the evaluation board.
Connect the USB cable to the Digilent USB JTAG interface.
Figure 2-14: KCU105 Evaluation Board
Figure 2-15: KC705 Evaluation Board
Note: You may be prompted to install drivers when the board is first connected. Do not allow
the driver installation to search the Web, but allow it to search for the drivers on your
computer.
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4-3. Ensure that all DIP switches are in the off position.
4-4. Program the FPGA on the evaluation board using the Vivado hardware
manager.
4-4-1. Click Open Hardware Manager in the Bitstream Completed dialog box and select OK.
4-4-2. Click Open Target > Open New Target.
4-4-3. Click Next in the Open Hardware Target window after reading how to connect to a
remote hardware target.
4-4-4. Select the server type you are connecting to in the Hardware Server Settings dialog box
and click Next.
4-4-5. Keep the default selection in the Select Hardware Target dialog box to choose your
device and click Next.
4-4-6. Click Finish after reviewing the Hardware Target Summary.
4-4-7. KCU105 users: Right-click xcku040_0 and select Program Device.
KC705 users: Right-click xc7k325t_0 and select Program Device.
Figure 2-16: Programming the Device in the Hardware Session
The Program Device dialog box will open.

Observe that the bitstream file that will be used to program the device has been
included in the Bitstream file field.
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4-4-8. Click Program.
A progress bar appears, and when FPGA programming is complete, the dialog box
closes.
Figure 2-17: Programming Status of the FPGA
4-5. Configure the Tera Term terminal.

4-5-1. Open the Tera Term terminal.
4-5-2. Select the Serial option.
4-5-3. KCU105 users: Select the COM port that has Silicon Labs CP210x USB to UART
Bridge: Standard COM Port written in it.
KC705 users: Select the COM port that has Silicon Labs CP210x USB to UART Bridge
written in it.
4-5-4. Click OK.
Figure 2-18: HyperTerminal Connection Description
Note: The COM port setting is specific to the computer being used and may need to be
different than shown.
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4-5-5. Click OK.

4-5-6. Select Setup > Serial port and select the following options.
o Baud rate: 115200
o Data: 8 bit
o Parity: none
o Stop: 1 bit
o Flow control: none
4-5-7. Click OK.
4-5-8. Select Setup > Terminal and enable Local echo.
4-5-9. Click OK.
4-6. Enter data into the terminal and observe the pattern of the LEDs on the
board.
4-6-1. Type any characters into the Tera Term window.
On the evaluation board, all eight bits of the character will appear on the LEDs.
For a list of ASCII characters and their hexadecimal representation, see the ascii_table.pdf
file in the C:\training\Synth_Impl\support directory.
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4-7. Close the Tera Term application.
4-8. Close the hardware manager.
4-9. Power off the Evaluation Board.
4-10. Close the implemented design.

4-11-2. Click OK.

4-12-2. Click OK.
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Summary
In this lab, you learned how to synthesize the design with the default settings, implement the
design with default settings, and finally download the bitstream onto the evaluation board.
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Lab Workbook Lab 3: Basic Design Analysis in the Vivado IDE
Lab 3: Basic Design Analysis in the Vivado IDE

2018.1
Abstract
This lab provides an introduction to analysis features of the Vivado® IDE such as the Schematic
viewer and Hierarchy viewer. This will enable you to analyze the design and cross-probe the
timing path back to the RTL source.
Objectives
 Use the Schematic viewer to analyze a design
 Use the Hierarchy viewer to show the design netlist hierarchy
 Cross-probe timing-critical paths by using the Schematic viewer
 Use the Device viewer to display the placement and routing resources of the design
Introduction
The Vivado IDE enables you to analyze, verify, and modify the design at each stage of the design
process. You can improve circuit performance by analyzing the interim results in the design
process. This analysis can be run after RTL elaboration, synthesis, and implementation.
The design used in this lab is a programmable waveform generator, also known as a signal
generator.
The waveform generator in this design is intended to be a “standalone” device that is controlled
via a PC (or other terminal device) using RS-232 serial communication. The design described
here implements the RS-232 communication channel, the waveform generator and connection
to the external DAC, and a simple parser to implement a small number of “commands” to
control the waveform generation. This design can be downloaded to any FPGA development
board with a DAC, either on the board or on a daughter card.
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Lab 3: Basic Design Analysis in the Vivado IDE Lab Workbook
The top level architecture of wave_gen is shown in the following figure.
Figure 3-1: Top-Level Architecture
General Flow
Step 2: Step 3:
Step 1:
Analyzing Analyzing
Opening an
the the
Existing
Synthesized Implemented
Project
Design Design
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In this step, you will open an existing project via the Open Project link in the
Getting Started Welcome page.

If you do not recall how to perform this task, refer to the "Launching the Vivado
Design Suite" section under Vivado Design Suite Operations in the Lab Reference
Guide.
1-2. Open the Vivado Design Suite project named wave_gen.xpr located in the
C:\training\Basic_Dsgn_Analysis\lab\[KCU105 | KC7xx]\verilog directory.
If you do not recall how to perform this task, refer to the "Opening a Vivado
Design Suite Project" section under Vivado Design Suite Operations in the Lab
Reference Guide.
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Analyzing the Synthesized Design Using the Schematic and Hierarchy

Viewers Step 2
2-1. Examine the HDL hierarchy of the design by using the Hierarchy viewer.
Hint: Select the Hierarchy tab of the Sources window to see the HDL hierarchy of
the design.
Figure 3-2: HDL Hierarchy Viewer
Note: The constraints files, schematic, and hierarchical views will vary a little based on
the target devices. The figures used in this lab correspond to the Kintex® UltraScale™
device. The same steps are applicable to users of the Kintex-7 device. The instructions
will focus on describing the different views available in the Vivado IDE and how to use
them.
2-2. Open the synthesized design.

When you click Open Synthesized Design, the Vivado IDE opens the synthesized
netlist and the target device into the Synthesized Design environment in which
you can perform I/O pin planning, design analysis, and floorplanning.
2-3. Select the Netlist window.

The Netlist window provides a hierarchical view of the elaborated or synthesized
logic design, including the nets, logic primitives, and hierarchical modules of the
design, starting with the currently defined top module.
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The Netlist window includes the Leaf Cells folder and Nets folder at the top
hierarchy and each level of hierarchy.
o Leaf Cells: Displays primitive logic for each level of the hierarchy. This folder
condenses the display of logic content and hierarchical modules in the Netlist
window.
o Nets: Displays nets, or wires, for each level of the hierarchy. All of the bits of a bus
are collapsed under the bus by default, but you can expand buses to show each
individual bit.
Figure 3-3: Netlist Window and Representation of Each Icon
Question 1
How many nets and leaf cells are there at the top-level of the design hierarchy?
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2-4. Generate the Timing Summary report.

In the synthesized Timing Summary report, the Vivado IDE timing engine
estimates the net delays based on connectivity and fanout.
2-5. Select the most timing-critical path from the Timing Summary report.
Hint: Clicking the Worst Hold Slack (WHS) value in Design Timing Summary will
display the most timing critical paths.
2-6. Generate the schematic for the worst path.

After synthesis, viewing the schematic is the easiest way to visualize the gates in a
timing path.
2-6-1. Select the timing-critical path (i.e., the path with the highest WHS value).
2-6-2. Enable "Select Clock Paths" icon ( ) in the Timing Summary window.
2-6-3. Right-click and select Schematic or press <F4>.
Question 2
What does the schematic look like for the timing-critical path?
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2-7. Select wave_gen in the netlist hierarchy.
2-8. Generate the hierarchy of the design netlist by using the Hierarchy viewer.
Hint: Select Tools > Show Hierarchy or right-click and select Show Hierarchy.
The Hierarchy viewer displays a graphical representation of the logic hierarchy for
the current design, based on the current top module. Viewing the design from
top to bottom, you can identify the relationship among hierarchical modules,
approximate module sizes, and module location within the design.
Figure 3-4: Hierarchy Viewer (KCU105) - Example (Numbers May Vary)
Question 3
How many hierarchy levels are there in the design? Hint: Switch to the Tree view by clicking the
icon for easy viewing.
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2-9. Select the samp_gen instance in the Netlist window and display the
hierarchy level of the instance in the design.
Question 4
What is the hierarchy level of the samp_gen instance in the design?
2-10. Select the Cell Properties window.

The Properties window displays information about selected logic objects or
device resources. When you select an object, its properties dynamically display in
the Properties window. The Properties window includes several views to organize
information under different categories. The available views and the information
they display depend on the type of object selected.
The name of the Properties window changes to reflect the selected object. For
example, the window is called the Cell Properties window when a Cell is selected
and Bus Net Properties window when a Bus Net is selected.
Figure 3-5: Properties Window (KCU105)

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2-11. Select the Statistics tab in the Cell Properties window.
2-12. Review the contents of the Statistics tab.
Question 5
What are the primitive counts in the cell?
Question 6
What are the names of the carry chains in the cell? Hint: Use the Children tab in Properties view
after selecting the cell in the Netlist window.
2-13. Select any instance in the Hierarchy window and notice that the same object
is selected in the Netlist window.
This feature is called cross-selection of objects.
Question 7
How would the cross-selection feature be useful during design analysis?
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Analyzing the Implemented Design with the Vivado IDE Cross-Probe

Feature Step 3
In this step, you will open the implemented design and analyze the design by
using the Device viewer and cross-probing the timing-critical path.

The Vivado IDE imports the netlist, design constraints, the target part, and the
results from place and route into the Vivado IDE for design analysis and further
work as needed.
3-2. Open the Device viewer if it is not open by default.

The Device viewer displays FPGA resources such as slices, CLBs, clock regions, I/O
pads, BUFGs, MMCMs, block RAMs, etc. The viewer also shows the net
connectivity if the Routing Resources icon ( ) is enabled.
Figure 3-6: Example of Device Viewer
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3-3. Explore the horizontal toolbar.

The toolbar contains several icons, such as Routing Resources, Fit Selection, Auto
Fit Selection, etc.
Figure 3-7: Device Viewer Horizontal Toolbar
Question 8
What does the Auto Fit Selection icon do?
Question 9
What does the Show Cell Connections icon do?
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3-4. Enable the Routing Resources icon ( )if it is not enabled.
Question 10
When would viewing Routing Resources be useful?
3-5. Zoom into the Device view so that device resources such as LUTs, FFs, and
block RAM tiles are visible.
Figure 3-8: Zoomed In View of the Device Viewer
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3-6. Select any LUT resource in the Device view to observe that the same object
is cross-selected in the Netlist window.
This is the cross-selection feature in the Vivado IDE.
Figure 3-9: Cross Selection of Objects in the Device View and Netlist Window
3-7. Select the Truth Table tab in the Properties window.
Question 11
What is the LUT equation for the selected LUT?
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3-8. Select the General tab in the Cell Properties window.
Question 12
What are the Site, Tile, and BEL values of the selected LUT?
Question 13
Which clock region is the LUT located in?
3-9. View the Timing Summary report.

In the implemented design, the net delays are based on the actual routing
information and the net delays are accurate. You must use the Timing Summary
report as the timing sign-off for the fully routed design.
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3-10. Select the Worst Negative Slack (WNS) timing-critical path from the Timing
Summary report.
3-11. Observe the timing-critical path in the Device view.
Question 14
What does the timing path look like in the Device view?
3-12. Generate the schematic for the timing-critical path.

Hint: Right-click the path and look for the Schematic option.
After implementation, the schematic is the easiest way to visualize the gates in a
timing path. The schematic also shows the slack and fanout on each pin of the
cell.
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Question 15
What is the schematic for the timing-critical path?
3-13. Click the Settings icon ( ) in the horizontal toolbar to enable the Slack and
Fanout values on each pin of the cell.
3-14. Select the Fanout for Scalar Pin check box.
Figure 3-10: Fanout on Each Pin of the Cell
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Question 16
When would the Schematic options be useful?
You can also cross-probe the timing-critical path to the RTL source.
3-15. Identify the logic-level instance of the selected timing path.

3-15-1. Right-click any cell in the Schematic window.
3-15-2. Select Select Leaf Cell Parents.
This will highlight the logic-level instance of the selected timing path in the Netlist
window.
3-16. View the HDL file corresponding to the timing-critical path.

3-16-1. Right-click any cell in the Schematic window.
3-16-2. Select Go To Source.
This will open the corresponding HDL file, enabling you to cross-probe the source of the
timing-critical path.
3-17. Close the Implemented design.
Summary
In this lab, you learned how to use the Schematic viewer, Hierarchy viewer, and Device viewer to
analyze the design. You also used the cross-probing feature of the Vivado IDE to cross-probe
the timing-critical path.
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Lab Workbook Lab 4: Vivado Design Rule Checks
Lab 4: Vivado Design Rule Checks

2018.1
Abstract
This lab guides you through the process of generating a Design Rule Check (DRC) report at the
elaboration stage and fixing some of the DRC violations early in the flow.
This lab supports only Verilog design files for a Kintex®-7 FPGA.
Objectives
 Run a DRC report to detect design issues
 Fix the DRC violations early in the flow
Introduction
DRC checks are run to detect common design issues and errors. DRC rules will vary depending
on stages of the design process.
Elaborated Design
 Checks for DRCs related to I/O and clock placement.
The RTL netlist does not typically have all the I/O buffers, clock buffers, and other primitives that
post-synthesis designs have. Elaborated design DRCs do not check for as many errors as
subsequent DRCs.
Synthesized Design and Implemented Design
 Checks for DRCs related to the post-synthesis netlist
 Checks for I/O, BUFG, and other placements
 Basic checks on the attribute wiring on MGTs, IODELAYs, and other primitives
 For implementation, the same DRCs run, taking into account any available placement and
routing
 DRCs have four severities: Informational, warning, critical warning, and error. Critical
warnings and errors do not block the design flow at this point
Certain messages have a lower severity depending on the stage. These are DRC-flagging
conditions that do not stop opt_design, place_design, or route_design from
completing, but which can lead to issues on the board.
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Lab 4: Vivado Design Rule Checks Lab Workbook
place_design
Before starting placement, Vivado® implementation runs DRCs, including user-selected DRCs
from report_drc, and built-in DRCs internal to the Vivado placer engine. Internal DRCs report
many issues, including memory interface generator (MIG) cells without LOC constraints and I/O
banks with conflicting I/O standards.
route_design
Before starting routing, the Vivado tools runs DRCs, user-selected DRCs from report_drc, and
built-in DRCs internal to the Vivado router engine.
Bitstream Generation
Writing the bitstream file includes a final DRC to ensure that the design does not violate any
hardware rules.
General Flow
Step 1: Step 2: Step 3:
Opening an Examining Analyzing
Example the the Modified
Design Design Design
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Opening an Example Project Step 1

In this step, you will open an example project via the Open Example Project link
from the Getting Started page.

Vivado 2018.1.
-- OR --
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1-2. Use the Open Example Project link in the Getting Started page to create a
large RTL project.
1-2-1. Click the Open Example Project in the Getting Started page.
1-2-2. Click Next in the Open Example Project window after reading how the Example Project
Wizard should be used.
1-2-3. Select CPU (HDL) to use the template for creating a large RTL project.
1-2-4. Click Next.
1-2-5. Enter project_cpu as the project name and locate the project in the
C:\training\Dsgn_Rule_Check\lab\KC7xx\project_cpu directory.
1-2-6. Click Select.
Note: The CPU example in the Vivado Design Suite 2018.1 is provided only in Verilog
RTL for a Kintex-7 FPGA. It does not have a version for UltraScale™ devices or VHDL.
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1-2-7. Click Next to move to the Default Part window.

1-2-8. Select the xc7k70tfbg676-2 part to create the project based on a Kintex-7 device.
1-2-9. Click Next to move to Project Summary window.
1-2-10. Review the project details and click Finish.
Examining the project_cpu Design and check DRC Step 2

The project_cpu design is included as part of the Vivado Design Suite installation
as a sample design for designers to work with while gaining knowledge of the
capabilities of the Vivado Design Suite. This project includes the OpenRISC 1200
project from opencores.org.
The OpenRISC 1200 processor core is a 32-bit RISC processor with a scalar, five-
stage integer pipeline, virtual memory management units (MMU), and basic DSP
capabilities.
Figure 4-3: OR1200 CPU
2-1. Open the elaborated design.

The elaborated RTL design enables various analysis views, including RTL Netlist,
Schematic, and Graphical Hierarchy. These views have a cross-select feature,
which allows you to debug and optimize the RTL.
2-1-1. Click Open Elaborated Design under RTL Analysis in the Flow Navigator and click OK.
2-1-2. Click Schematic under Elaborated Design to open the RTL Schematic window of the top
level of the design.
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The RTL design allows to analyze your design for logic correctness. You can make sure
that there are no logic compilation issues, missing modules, or interface mismatches.
Figure 4-4: RTL Schematic
2-2. Explore the options available in the horizontal toolbar of the RTL Schematic
window.
The horizontal toolbar provides one-click options for various actions, such as
Select Area, Regenerate the Schematic, etc.
Figure 4-5: Horizontal Toolbar of the Elaborated Design
2-2-1. Close the Schematic window.
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2-3. Generate the DRC report.

Running the DRC utility is one of the most critical steps in the design. DRCs
report any violations in the current design against a specified set of design rules.
The rule violations are categorized by severity and are color coded for quick
review:
o Informational only: Provides general status and feedback on design processing.
o Warning: Indicates that design results might be sub-optimal because constraints or
specifications might not be applied as intended.
o Critical warning: Indicates that certain user input or constraints will not be applied
or do not adhere to best practices. Examining these issues and making any necessary
changes is highly recommended.
o Error: Indicates an issue that renders design results unusable and cannot be resolved
without user intervention.
Note: It is recommended that you review the DRC messages early in the design flow and
fix any issues to prevent device utilization and timing problems later in the development
flow.
2-3-1. Click Report DRC under RTL Analysis > Open Elaborated Design to open the Report DRC
window.
Question 1
What DRC rules are checked at the elaborated design stage?
2-3-2. Click OK in the Report DRC window to run the default DRC checks.
2-4. Review the DRC report.

2-4-1. Click the Collapse All icon ( ) at the bottom of the horizontal toolbar for a better view
of the DRC report.
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Question 2
Summarize the violations in the DRC report.
2-5. Expand the Pin Planning folder under All Violations.
Question 3
Summarize the pin planning violations in the DRC report.
2-6. Select the UCIO-1 > UCIO #1 violation from the IOB violations.
Question 4
What is the UCIO #1 violation?
Question 5
Which ports are creating the violations?
From the answers to the above question, it is clear that the problem ports do not have
the pin location and I/O standard assignments. To fix these DRC violations, you will need
to assign these attributes to these ports.
The package pin location and I/O standard assignments can be made in two ways: using
the I/O Planning layout or writing XDC constraints to the XDC file.
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2-7. Change the Default Layout to I/O Planning Layout and notice that the
Vivado IDE layout changed from the Default layout to the I/O Planning
layout in the horizontal toolbar.
2-7-1. Select Layout > I/O Planning.
When the Vivado IDE layout changed to I/O Planning, the Package window and I/O
Ports tab open in the main workspace area and Results window, respectively.
2-8. Open the Package window (if it is not already opened).

The Package window displays the physical characteristics of the target Xilinx part. This
window is used primarily during the I/O planning process. Pin types display in different
colors and shapes for better visualization.
Figure 4-6: Package Window
The colored areas between the pins display the I/O banks and show differential pairs,
clock-capable pins ( ), VCC ( ), GND ( ), or no connection ( ).
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The display of each pin in the Package window includes the pin name (signal name, if
assigned), pin number (found by dragging over), site type (I/O), differential pair type (P
or N), and bank number (26, 12, etc.).
Figure 4-7: Pin in the Package Window
2-9. Explore the options in the I/O Ports tab at the bottom.
2-9-1. Expand Scalar Ports in the I/O ports tab to view the ports shown in the figure below.
Figure 4-8: I/O Ports Window
2-9-2. Observe how selecting a port in the I/O Ports tab (like TermSel_pad_1_o, for example)
will highlight the corresponding pin in the Package and Device views of the Vivado IDE.
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2-10. Assign the package pin location for the ports using the I/O Ports tab.
2-10-1. Assign the K6 package pin location for TILE0_REFCLK_PAD_P_IN.
Hint: Enter K6 in the Package Pin column of the TILE0_REFCLK_PAD_P_IN port in the
I/O Ports tab.
Observe that this will also assign the pin location for the corresponding differential pair
(i.e. for TILE0_REFCLK_PAD_N_IN).
2-10-2. Assign the H6 package pin location for TILE1_REFCLK_PAD_P_IN.
2-10-3. Assign the F6 package pin location for TILE2_REFCLK_PAD_P_IN.
2-10-4. Assign the D6 package pin location for TILE3_REFCLK_PAD_P_IN.
2-11. Select File > Constraints > Save to save the modified top_full.xdc file.
2-11-1. Click Yes if prompted to save the elaborated design.
2-12. Run the DRC report again.
2-13. Verify that UCIO pin planning violations are no longer reported.
This is expected because the site has been specified for each of the eight ports
reported previously. This in turn sets the I/O standards and LOC constraints for
those ports.
2-14. Select the CFGBVS-1 > CFGBVS #1 violation.
2-15. Examine the violation properties.

2-15-1. Select the Properties window and view the violation for CFGBVS #1.
To fix the violation, you will need to know about CFGBVS and CONFIG_VOLTAGE.
Information on CFGBVS and CONFIG_VOLTAGE can be found in the 7 Series FPGAs
Configuration User Guide (UG470), which is available in the C:\training\Dsgn_Rule_Check\
support directory.
Question 6
What is CFGBVS?
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Question 7
What is the CFGBVS #1 violation?
2-16. Enter the following XDC constraints in the Tcl Console to fix this DRC
violation.
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
2-17. Select File > Constraints > Save to save the constraints to the top_full.xdc
file.
2-18. Run the DRC report again.
2-19. Verify that CFGBVS pin planning violations are no longer reported.
This is expected because the configuration bank voltage select (CFGBVS) has
been set to GND, and CONFIG_VOLTAGE has been set to 1.8V via Tcl.
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2-20. Run synthesis.

2-20-1. Click Run Synthesis in the Flow Navigator under Synthesis.
reports.

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2-20-4. Click OK to continue with your preferred choice or Cancel to simply close the dialog box
and return to the normal view of the Vivado Design Suite.
2-21. Run a DRC check on the synthesized design.

2-21-1. Click Report DRC under Synthesis > Open Synthesized Design.
2-23. Expand All Violations > Netlist > Instance > Pipeline > DSP48E1 to view the
pipelining violations.
Question 8
How many DSP inputs are not pipelined?
Question 9
How many DSP outputs are not pipelined?
2-24. Expand All Violations > Netlist > Instance > Synchronous controls >
DSP48E1 to view the violations due to registers with asynchronous resets.
Question 10
How many DSP outputs are connected to registers with asynchronous resets?
Question 11
What are appropriate design changes for improving the reset structure?
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2-26. Open the elaborated design again.
2-27. Generate the Report Methodology.

2-27-1. Click Report Methodology under RTL Analysis > Open Elaborated Design.
2-27-2. Click OK in the Report Methodology window to run the default checks.
2-27-3. Expand the RTL folder under All Violations.
2-27-4. Select the RMOR #1 violation under RTL > Multipliers and DSP48 > RMOR-1.
2-27-5. Select Window > Properties to open the Properties window.
Question 12
What does the RMOR #1 violation say?
2-27-6. Select RMOR #1 violation and click p00_i in the Methodology window.
Notice that p00_i is also selected in the RTL Netlist window.

2-27-7. Right-click p00_i in the RTL Netlist window and select Go To Source.
Question 13
What source file has been opened?
Question 14
Is there an asynchronous reset in the code snippet? What is the signal name?
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2-28. Remove the asynchronous reset from the code.

2-28-1. Select or1200_gmultp2_32x32.v to open the file if it is not already open.
2-28-2. Remove the posedge RST from the code on lines 118 and 127.
2-28-3. Save the code and reload the elaborated design.
The code snippet should look like the following figure.
Figure 4-11: Removing the Asynchronous Reset
2-29. Run the Report Methodology again.
Question 15
Is there an asynchronous reset violation now?
2-30. Select RTL > Fanout and Replication > RFFH-1 violation under All Violations.
2-31. Select RFFH #1.
Question 16
What does the RFFH #1 advisory say? How it can be solved?
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Question 17
How many XDC violations are reported in the DRC report? What do these violations indicate?
Can they be ignored?
2-32. Close the elaborated design.

2-32-1. Click OK if prompted to close the design.
2-33. Run synthesis.

2-33-1. Click Run Synthesis in the Flow Navigator under Synthesis.
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reports.
2-33-4. Click OK to continue with your preferred choice or Cancel to simply close the dialog box
and return to the normal view of the Vivado Design Suite.
2-34. Run a DRC check on the synthesized design.

2-34-1. Click Report DRC under Synthesis > Open Synthesized Design.
2-36. Expand All Violations > Netlist > Instance > Synchronous controls >
DSP48E1 to view the violations due to registers with asynchronous resets.
Notice that the violations due to registers with asynchronous reset has been
fixed (Now this violation is fixed. All Violations > Netlist > Instance >
Synchronous controls > DSP48E1).
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Analyzing the Modified project_cpu Design Step 3

In this step, you will open the modified project_cpu_hdl project and examine the
DRC violations.
3-1. Open the project_cpu_revised.xpr project located in the C:\training\

Dsgn_Rule_Check\lab\KC7xx\project_cpu_revised directory.

3-2-1. Click Open Elaborated Design under RTL Analysis in the Flow Navigator and click OK.
3-3. Run a DRC report.

3-3-1. Click Report DRC under RTL Analysis > Open Elaborated Design to open the Report
DRC window.

In the previous project_cpu design, the DRC report showed the RTL violations
since there were asynchronous resets in the design. However, the asynchronous
resets are either converted to synchronous or removed in the modified
project_cpu_revised design, so the DRC report does not show RTL violations.
3-5. Examine the reset bridge added to the design.

3-5-2. Expand Design Sources > top.
3-5-3. Double-click reset_bridge.v to open the file.
Question 18
What is the purpose of the reset bridge module (reset_bridge.v)?
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3-6. Generate a schematic for the RESET_BRIDGE module.

3-6-1. Select the Netlist tab in the Sources window to view the RTL blocks used in this design.
3-6-2. Select and right-click RESET_BRIDGE_CPUCLK.
3-6-3. Select Schematic to open the schematic view corresponding to the selected module.
3-6-4. Click the + sign to expand the schematic.
Question 19
What does the schematic look like?
The modified project_cpu_hdl design includes a RESET_BRIDGE module at the top level
for each clock domain.
The following is a list of reset changes that were made to the design:
o mgtTop.v: Removed wb_reset because it is only used to initialize registers (INITs by
default are set to 0).
o fftTop.v: Removed asynchronous resets and replaced with INITs.
o bft.vhd: fftClk used for bft; reset_fftClk used for the few remaining resets in bft;
resets changed to INITs.
o Wb_conmax_top.v: Left the rst port but removed all asynchronous resets in all
modules.
o Wb_conmax_arb.v: For the FSM, change it to a synchronous reset.
o Or1200_top.v: Changed rst_i to reset_wbClk and reset_cpuClk; per clock domain
used.
3-7. Select the Hierarchy tab of the Sources window.
3-8. Expand Design Sources > top> fftEngine >fftInst.
3-9. Double-click bft.vhdl to open the file.
3-10. Verify the code for asynchronous reset.

3-10-1. Go to line 109 to verify that the asynchronous reset code has been removed.
There are many occurrences like this in other modules for removing asynchronous resets
in the design.
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3-11. Select File > Close to close the elaborated design.

3-12-2. Click OK.

3-13-2. Click OK.
Summary
In this lab, you utilized Report DRC and Report Methodology to identify issues in the HDL early
in the design flow. You then fixed the I/O ports by assigning pins and changed an asynchronous
reset to synchronous, allowing the DSP48E1 output to be registered in the DSP48E1 block. You
examined the DRC report to identify the remaining issues and fixed them. Finally, you ran a
Report DRC on a version of the code that fixed these issues to confirm that these issues were
indeed fixed.
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Lab Workbook Lab 5: Vivado Design Suite I/O Pin Planning
Lab 5: Vivado Design Suite I/O Pin Planning

2018.1
Abstract
This lab introduces the I/O planning capabilities of the Vivado® Design Suite for FPGA devices.
The lab supports both Verilog and VHDL design files. However, the lab instructions and figures
Objectives
 Use the basic design analysis features of the Vivado IDE to explore your design
 Step through the I/O pin planning process using the GUI
 Assign configured I/O ports to the physical package pins
Introduction
The Vivado IDE provides an I/O planning environment that enables I/O ports assignment to
package pins. In this environment, you can assign I/O locations, specify I/O banks and I/O
standards, or create legal pin assignments by reporting Design Rule Checks (DRC).
I/O planning can be performed at any stage of the design flow with any type of project. Some of
the most common methods are:
 Pre-RTL I/O planning
 RTL I/O planning
 Netlist I/O planning
 I/O validation with an Implemented design
You can also use the I/O planning layout view to see the relationship of the physical package
pins and banks with the corresponding I/O pads.
General Flow
Creating Analyzing Placing
a the I/O
Project Design Pins
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Lab 5: Vivado Design Suite I/O Pin Planning Lab Workbook
Creating a New Project Step 1

You will begin the lab by launching the Vivado Design Suite to create a new
project using the New Project Wizard in the Vivado IDE.
The New Project Wizard in the Vivado IDE will create an XPR project file. The
Vivado IDE project file (.xpr) organizes your design files and saves the design
status whenever the processes are run from design entry through
implementation to programming the targeted Xilinx device.

Vivado 2018.1.
-- OR --
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Projects begin with the creation of a new project. The project contains sources,
settings, graphics, IP, and other elements that are used to build a final bitstream.
1-2. Create a new Vivado Design Suite project.

1-2-1. Click Create Project (1).
Figure 5-3: Creating a New Vivado Design Suite Project
This will launch the New Project Wizard.

1-2-2. Click Next to begin entering the specifics for this project (2).
1-3. You will now encounter a series of dialog boxes asking you to enter
different pieces of information describing the project.
1-3-1. Enter uart_led in the Project name field(1).
1-3-2. Enter C:\training\IO_PinPlanning\lab\[KCU105 | KC705]\verilog in the Project
location field(2).
Select your preferred language to be either Verilog or VHDL.
Alternatively, you can use the browse feature to navigate to where you want the project
to reside.
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1-3-3. Deselect the Create Project Subdirectory option, as leaving this checked will create an
additional level of hierarchy in the lab (3).
Figure 5-4: Entering the Project Name and Location
1-3-4. Click Next to accept the selections and advance to selecting a type of project (4).
The Project Type dialog box invites you to choose between an RTL project or a post-
synthesis project. Simply put, an RTL project enables you to add or create new HDL files
and synthesize them, whereas a post-synthesis project requires pre-synthesized files.
1-3-5. Select RTL Project since this project will be based on source code (rather than a netlist)
(1).
1-3-6. Deselect the Do not specify sources at this time option (2), since you will be adding
RTL files in the next instruction.
Figure 5-5: Setting the Project Type to RTL
1-3-7. Click Next to accept the selection and advance to the adding sources stage (3).
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1-4. Now that the project name, type, and location have been entered, the
wizard invites you to add source files to the project. You can add entire
directories where the sources are located, add specific files, or create new
sources.
Begin by adding the sources to your project.
1-4-1. Click the Plus icon ( ) to begin adding objects to the project.
1-4-2. Select Add Files from the pop-up menu to begin adding your source files to the project.
Figure 5-6: Adding Sources to the Project
After you add all the necessary files, the remainder of this dialog box will be addressed.
The Add Source Files dialog box opens.
1-4-3. Browse to the C:\training\IO_PinPlanning\lab\[KCU105 | KC705]\verilog directory (1).
Figure 5-7: Adding Source Files
1-4-4. Verilog users: Select or multi-select led_ctl.v, meta_harden.v, uart_baud_gen.v,

uart_led.v, uart_rx.v, uart_rx_ctl.v (2).
VHDL users: Select or multi-select led_ctl.vhd, meta_harden.vhd, uart_baud_gen.vhd,
uart_led.vhd, uart_led_pkg.vhd, uart_rx.vhd, uart_rx_ctl.vhd.
1-4-5. Click OK to accept the selected files and add them as sources to the project (3).
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The Add Source Files dialog box closes and returns you to the Add Sources dialog box.
Figure 5-8: Setting Options in the Add Sources Window
1-5. In the Add Sources window, add any existing IP modules to the Vivado
Design Suite project.
KCU105 users: No IP is required for this design. Click Next and skip to the
step that begins with "Add any existing constraint files". KC705 users: Add
the clk_core IP to the design by using steps below.
1-5-1. Click the Plus icon ( ) again to select the IP files.
1-5-2. Select Add Files to open the Add Source Files dialog box.
1-5-3. Select clk_core.xci.
each directory.
1-5-5. Confirm that the Scan and Add RTL Include Files into Project option is selected (used
for Verilog, no effect for VHDL) in the Add Sources dialog box (1).
This will automatically pull in any include files used by Verilog sources.
1-5-6. Confirm that the Copy Sources into Project option is selected (1).
1-5-7. Select your preferred language from the Target Language drop-down list (2).
This choice only affects which language is used for the generation of templates and
wrappers. You can add files in any language regardless of which target language is
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selected. If you do not generate or use any templates or wrappers, this step is irrelevant
and you can select any language.
1-5-8. Click Next to complete the adding of RTL sources and advance to adding any XDC files.
1-6. Add any existing constraint files to the Vivado Design Suite project.
You will add uart_led.xdc to the project in the following instructions.
1-6-1. Click the Plus icon ( ) to select the type of object you want to import (1).
1-6-2. Select Add Files to open the Add Constraints Files dialog box.
1-6-3. Browse to the C:\training\IO_PinPlanning\lab\[KCU105 | KC705]\verilog directory.
Figure 5-9: Adding Constraints
1-6-4. Select uart_led.xdc.

If you have additional files located in other directories you can repeat this instruction for
each directory.
1-6-6. Confirm that the Copy constraints files into Project option is selected (2).
1-6-7. Click Next to advance to selecting a target device (3).
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1-7. Select the target part by first filtering by board and then by family. If you
are not using a supported board, you will need to filter by part.
1-7-1. Select Boards from the Select area (1).
1-7-2. Select All from the Vendor drop-down list in the Filter area (2).
This filters the available boards to those that are populated with any member of the
selected library.
1-7-3. Select Kintex UltraScale KCU105 Evaluation Platform | Kintex -7 KC705 Evaluation
Platform from the board list.
Alternatively you can select the board directly from the list at any time while in this
dialog box.
Figure 5-10: Selecting the Board for the Project
1-7-4. Click Next to advance to the summary (3).
A summary of your project is displayed. If you want to change any of the information
that you entered, you can do so now by clicking Back until you reach the correct dialog
box and making the correction, or you can create the project now and edit the project
properties, add or remove files, etc. later.
Your project is constructed and you are presented with the Vivado Design Suite main
workspace environment.
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Analyzing the Design Using the Schematic and Hierarchy Views Step 2
You will open the elaborated design and briefly explore the design with the RTL
Netlist, Schematic, and Hierarchy viewers.

2-1-1. Click Open Elaborated Design under RTL Analysis in the Flow Navigator to elaborate
the design.
The elaborated RTL design enables various analysis views, including RTL Netlist,
Schematic, and Graphical Hierarchy. These views have a cross-select feature, which allows
you to debug and optimize the RTL.
The Elaborate Design dialog box opens.
2-1-2. Click OK in the dialog box to open the elaborated design.
2-1-3. Click Schematic under RTL Analysis > Elaborated Design in the Flow Navigator to
open the RTL schematic of the design in the main window.
Figure 5-11: RTL Schematic of the uart_led Design (KCU105)
Figure 5-12: RTL Schematic of the uart_led Design (KC705)
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2-2. Explore the design with the Schematic view.

2-2-1. Select any logic instance in the Schematic view.
2-2-2. Right-click the instance and select Go To Source.
Notice that the RTL source file is opened in the text editor with the logic instance
highlighted.
Also notice that the logic instance is also highlighted in the RTL Netlist window.
2-2-3. Double-click the uart_rx_i0 logic instance in the Schematic view.
The subcomponents of the uart_rx_i0 are displayed.
Figure 5-13: Viewing the Submodules of the uart_rx_i0 Component
2-2-4. Explore the RTL Schematic view by expanding each of the submodules and viewing the
lowest level of the RTL schematic.
2-3. View the design hierarchy by using the Hierarchy view.

2-3-1. Select the uart_baud_gen_rx_i0 logic instance in the Schematic view.
2-3-2. Select Tools > Show Hierarchy.
The RTL hierarchy window opens, displaying the hierarchical block structure of the
selected uart_baud_gen_rx_i0 instance.
2-3-3. Enable the Show Tree View icon from the Hierarchy window horizontal toolbar.
This displays and highlights the structure of the uart_baud_gen_rx_i0 logic instance until
the bottom leaf cells are present in the hierarchy.
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2-3-4. Click the Go Up One Level icon until you are at the top level of the
uart_baud_gen_rx_i0 instance.
Figureb 5-14: RTL Hierarchy View with uart_baud_gen_rx_i0 Highlighted (KCU105) (Numbers
May Vary)
Figure 5-15: RTL Hierarchy View with uart_baud_gen_rx_i0 Highlighted (KC705) (Numbers May
Vary)
2-3-5. Explore the RTL Hierarchy view and see how the component selection in this view
automatically highlight the same module in other views (Schematic view or Netlist
window).
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Question 1
From the top level, how many levels of hierarchy did you go through before reaching the lowest
level? What you understood from the design tree?
2-4. Close both the RTL Hierarchy and Schematic views.
2-5. Run DRC checks on the elaborated design.

2-5-1. Click Report DRC under RTL Analysis > Open Elaborated Design in the Flow
Navigator.
The Report DRC dialog box opens.
2-5-2. Select default in the Vivado Rule Decks section.
2-5-3. Observe the categories in the Rules section.
2-5-4. Click OK to generate the DRC report.
2-5-5. Review the DRC violations in the DRC report.
Question 2
What are all the critical warnings reported by DRC? If so, what could be the reason(s)?
2-5-6. Right-click the DRC tab after reviewing the violations and select Close.
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Placing Pins Using the I/O Planning View Step 3

It is clear from the DRC report that there are three ports that do not have user-
assigned LOC constraints and have default IOSTANDARD values. Here you will
use the I/O Planning view to place the unplaced pins in the design.
3-1. Use the I/O Planning view to identify pins that do not have an assigned
location.
3-1-1. Select Layout > I/O Planning from the layout selector, if it is in any other layout view.
3-1-2. Select the Package view, if it is not already opened.
The main window of the I/O Planning view displays the Package view of the Kintex®
UltraScale™ or Kintex 7-series device.
Figure 5-16: I/O Planning View
3-1-3. Observe the I/O Ports tab, which displays the list of I/O ports of the design, and the
Package Pins tab, which displays the list of package pins available on the device
package.
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3-2. Assign the location and I/O standard for btn_pin.

3-2-1. Expand Scalar ports in the I/O Ports tab.
3-2-2. Select the btn_pin signal.
3-2-3. Select AE10 (KCU105) or Y29 (KC705) under the Package Pin column.
3-2-4. Explicitly select LVCMOS18 (KCU105) from under the I/O Std column, or LVCMOS25
(KC705) from the I/O Standard drop-down list.
Figure 5-17: I/O Port Properties for btn_pin (KCU105)
Figure 5-18: I/O Port Properties for btn_pin (KC705)
3-3. Assign the location and I/O standard for rxd_pin.

3-3-1. Select rxd_pin in the I/O Ports view.
3-3-2. Select G25 (KCU105) or M19 (KC705) from under the Package Pin column.
3-3-3. Enter the following in the I/O Port Properties view.
o I/O Standard: LVCMOS18 (KCU105) or LVCMOS25 (KC705).
o Leave the Drive Strength at its default value; drive strength does not apply to input
pins.
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3-4. Assign the location (using the Package view) and I/O standard for rst_pin.
3-4-1. Select rst_pin in the I/O Ports view.
3-4-2. Select LVCMOS18 (KCU105) or LVCMOS15 (KC705) from the I/O Standard drop-down
list and press <Enter>.
Rather than entering the package pin in the I/O Ports view, you can use the Package view
to assign the package pin for this pin.
3-4-3. Drag the rst_pin from the I/O ports view onto location AN8 (KCU105) or AK4 (KC705) in
the Package view.
3-5. Save the I/O pin assignments to the targeted XDC file.
3-5-1. Select File > Constraints > Save to save the constraints.
The Save Constraint dialog box opens.

3-5-2. Select the Select an existing file option.
Figure 5-19: Selecting uart_led.xdc as the Target Constraints File
3-5-3. Click OK.
All these placement constraints will be saved to the existing uart_led.xdc file.
3-6. Open the uart_led.xdc file to confirm that your new pin assignments have
been saved in the XDC file.
3-6-1. Select the Hierarchy tab of the Sources window.
3-6-2. Double-click the uart_led.xdc under Constraints > constrs_1 to open the file in the text
editor.
3-6-3. Scroll to the bottom of the file and validate the changes that you made in the Vivado
IDE.
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3-7. Rerun DRC to check for any violations.

This time, no IOB violations (Unconstrained Logical Ports) should be reported.
3-8. Close the elaborated design.

3-8-1. Select File > Close Elaborated Design to close the elaborated design.
The Confirm Close dialog box opens.
Figure 5-20: Confirm Close Dialog Box
3-8-2. Click OK.
Summary
In this lab, you checked DRC for violations and fixed the violations by using the I/O planning
capability of the Vivado IDE to assign ports to package pins.
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Lab Workbook Lab 6: Vivado IP Flow
Lab 6: Vivado IP Flow

2018.1
Abstract
In this lab, you will add the Xilinx Clocking Wizard IP using the IP flow, allowing you to configure
a clocking subsystem to provide various clock outputs and clock buffers to connect clock signals
to global clock networks.
This lab supports both Verilog and VHDL design files. However, the lab instructions and graphics
are limited to VHDL usage.
Objectives
 Create a clocking subsystem consisting of an MMCM and some internal buffers by using the
Clocking Wizard
 Instantiate the generated cores in a design
Introduction
The LogiCORE™ IP Clocking Wizard core simplifies the creation of HDL source code wrappers for
clock circuits customized to your clocking requirements. The wizard guides you in setting the
appropriate attributes for your clocking primitive, and allows you to override any wizard-
calculated parameter. In addition to providing an HDL wrapper for implementing the desired
clocking circuit, the Clocking Wizard also delivers a timing parameter summary generated by the
Xilinx timing tools for the circuit.
General Flow
Opening an Building and Implement-
Existing Instantiating ing the
Project the Core Design
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Lab 6: Vivado IP Flow Lab Workbook

You will begin the lab by launching the Vivado® Design Suite and opening the
wave_gen.xpr design in the Vivado IDE.

If you do not recall how to perform this task, refer to the "Launching the Vivado Design
Suite" section under Vivado Design Suite Operations in the Lab Reference Guide.
C:\training\IP_Flow\lab\[KCU105 | KC7xx]\vhdl directory.
If you do not recall how to perform this task, refer to the "Opening a Vivado Design Suite
Project" section under Vivado Design Suite Operations in the Lab Reference Guide.
Building and Instantiating the clk_core Core Step 2

Here you will open the IP catalog to access the Clocking Wizard in order to
customize the clock core IP and then instantiate it in the clk_gen.v/vhd module.
2-1. Launch the Clocking Wizard from the IP catalog in the Vivado IDE.
2-1-1. Click IP Catalog under Project Manager in the Flow Navigator.
Alternatively, you can select Window > IP Catalog.

The IP Catalog window opens in the main workspace area.
2-1-2. Expand FPGA Features and Design > Clocking in the IP catalog.
2-1-3. Double-click Clocking Wizard to customize the selected IP.
Alternatively, you can right-click and select Customize IP.

The Customize IP window opens.
Question 1
Why use the Clocking Wizard to create the core? That is, why not just instantiate the MMCM
primitive?
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2-2. Customize the Clocking Wizard IP with the following parameters:

 Component Name: clk_core
 Primitive: MMCM
 Input Frequency: 300 MHz (KCU105) or 200 MHz (KC7xx)
Two output clocks of 200 MHz frequency
2-2-1. Ensure that the Show disable ports option is not selected in the IP Symbol tab (left
side).
2-2-2. Enter clk_core in the Component Name field.
2-2-3. Ensure that MMCM is selected in the Clocking Options > Primitive field.
2-2-4. Ensure that the Frequency Synthesis and Phase Alignment options are selected.
2-2-5. Set the Primary Input Clock Frequency field to 300.000 MHz (KCU105) or 200.00 MHz
(KC7xx).
2-2-6. Set the Source field to Differential clock capable pin.
Note: The Primary Input Clock Frequency option specified for the core is used so that
the wizard can calculate the correct modes and parameters for the core to generate the
outputs specified in the following stages. If this frequency does not match the frequency
of the clock source of the board, then the outputs will not match the requested output
frequencies.
Figure 6-1: Clocking Features/Input Clocks (KCU105)
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Figure 6-2: Clocking Features/Input Clocks (KC7xx)
2-3. Generate two output clocks (clk_out1 and clk_out2) from the MMCM
module with an output frequency of 200 MHz each.
2-3-1. Select the Output Clocks tab in the Customize IP dialog box.
2-3-2. Enter 200 as the value in the Output Freq (MHz) Requested field of the clk_out1 output
clock.
2-3-3. Enable the clk_out2 output clock by using the check box.
2-3-4. Enter 200 as the value in the Output Freq (MHz) Requested field of the clk_out2 output
clock.
2-3-5. Ensure that the Duty Cycle field is set to 50% for both output clocks.
Figure 6-3: Output Clocks Settings Tab (KCU105)
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2-4. Leave all the other tabs in the Clocking Wizard at their default settings.
Review the clock summary and generate the core.
2-4-1. Select the Summary tab and review the settings.
2-4-2. Click OK in the Customize IP dialog box.
The Generate Output Products dialog box opens.

2-4-3. Click Generate in the Generate Output Products dialog box.
Note: In the OOC flow, the IP is synthesized alone and an OOC DCP is produced. The
produced DCP is a container file, and includes a netlist as well as constraints.
Notice that a new file is added to the Sources > Hierarchy view: clk_core.xci. This source
file will not be included in the design hierarchy until the component has been
instantiated into one of the HDL source files.
2-5. View the HDL functional model for clk_core and confirm that the core
implemented by the core generator has the expected architecture.
2-5-1. Select the IP Sources tab in the Sources view.
2-5-2. Expand IP > clk_core > Synthesis.
2-5-3. Double-click clk_core_clk_wiz.v to view the HDL functional model.
2-5-4. Examine the source code generated by the Clocking Wizard.
KCU105 users:
This file contains the following instantiated components: an IBUFDS, an MMCME3_ADV,
and three BUFGs.
The input clock clk_in1_p/n drives an IBUFDS, which in turn drives the CLKIN1 port of
MMCME3_ADV. The CLKOUT0 and CLKOUT1 output of MMCME3_ADV drives the BUFGs,
which connects to the clk_out1 and clk_out2 output port of the module.
The MMCM attributes are passed via in-line parameter assignments.
The functional model of this core is not solely a simulation model, but is, in fact, the
instantiation and interconnection of the required hardware primitives. The Clocking
Wizard does not generate a separate netlist file.
KC7xx users:
This file contains the following instantiated components: an IBUFDS, an MMCME2_ADV,
and three BUFGs.
The input clock clk_in1_p/n drives an IBUFDS, which in turn drives the CLKIN1 port of
MMCME2_ADV. The CLKOUT0 and CLKOUT1 output of MMCME2_ADV drives the BUFGs,
which connects to the clk_out1 and clk_out2 output port of the module.
The MMCM attributes are passed via in-line parameter assignments.
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The functional model of this core is not solely a simulation model, but is, in fact, the
instantiation and interconnection of the required hardware primitives. The Clocking
Wizard does not generate a separate netlist file.
Question 2
If the core is already created, is the MMCM already connected to the design? Why must the
MMCM core be instantiated into this design?
2-5-5. Right-click the clk_core_clk_wiz.v tab and select Close to close the source file when you
are finished viewing the HDL source.
Note: The design files for this IP are delivered in Verilog only.
2-6. Instantiate the clk_core component by copying-and-pasting the text from

the instantiation template into the clk_gen.vhd/v file after the comment
"Instantiate clk_core – generated by the Clocking Wizard".
2-6-1. Expand IP > clk_core > Instantiation Template in the IP Sources tab of the Sources
view.
2-6-2. Select and double-click clk_core.vho/veo to open the instantiation template in the text
editor.
The language that the template is provided in is set by your language choice when you
built the project. It can be changed at any time.
2-6-3. Copy the instantiation template for the clk_core core from the clk_core.veo/vho window
by selecting all the text between the "Begin Cut here for INSTANTIATION Template" and
"End INSTANTIATION Template" comment lines and right-clicking and selecting Copy.
2-6-4. Select the Hierarchy tab and expand the wave_gen hierarchy.
2-6-5. Double-click clk_gen.vhd/v to open the source code in the text editor.
2-6-6. Paste the copied text into the clk_gen.vhd/v file under the comment "Instantiate clk_core
– generated by the Clocking Wizard" by right-clicking and selecting Paste.
Note that normally the component declaration would need to be copied as well. For this
lab, the component declaration has already been added for you. This can be verified by
looking for the clk_core component under the architecture section of the clk_gen.vhd file
(line 96). So component declaration need not to be copied from the Instantiation
Template.
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2-7. Complete the instantiation by changing the instance name and filling in the
port connections.
2-7-1. Complete the instantiation by changing the instance name and filling in the port
connections as follows:
VHDL
clk_core_i0: clk_core
port Map
(
clk_in1_p => clk_pin_p,
clk_in1_n => clk_pin_n,
clk_out1 => clk_rx_internal,
clk_out2 => clk_tx_internal,
reset => rst_i,
locked => clock_locked
);
Verilog
clk_core clk_core_i0 (
.clk_out1 (clk_rx),
.clk_out2 (clk_tx),
.reset (rst_i),
.locked (clock_locked),
.clk_in1_p (clk_pin_p),
.clk_in1_n (clk_pin_n)
);
2-7-2. Select File > Save File to save clk_gen.vhd/v.
Note: In order to make sure that the clk_core IP is included in the wave_gen design,
refresh the Hierarchy from the Sources window before running the next proc in order to
use the Tcl completer script.
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Implementing the Design Step 3

Here you will verify that the clk_core IP is properly instantiated in the
clk_gen.vhd/v module and then implement the design to view what clocking
resources have been used by the Clocking Wizard IP.
3-1. Verify that clk_core is correctly instantiated in the clk_gen.vhd/v module.

3-1-1. Select the Hierarchy window.
3-1-2. Expand Design Sources > wave_gen > clk_gen_i0 to confirm that the clk_core.xci file is
located correctly.
You will need to expand clk_gen_i0 to see the correct location for the clk_core source.
Figure 6-4: Hierarchy View with clk_core Correctly Instantiated
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After making sure that the clk_core IP is instantiated properly, you will now
implement the design to view the clocking resources used by the Clocking
Wizard.
3-2. Implement the design.

3-2-1. Click Run Implementation in the Flow Navigator (under Implementation).
Alternatively, you can select Flow > Run Implementation.
Figure 6-5: Selecting Run Implementation
Note: If needed, click OK to launch synthesis first if prompted.

Notice that the tools run all of the processes required to implement the design. This
means that if the synthesized netlist is not available already, the Vivado Design Suite will
run synthesis before running implementation.
After implementation completes, the Implementation Completed dialog box opens. The
dialog box prompts you to open the implemented design, generate the bitstream, or
view reports.
3-2-2. Click OK again to launch the selected runs.
3-2-3. Select Open Implemented Design.
Figure 6-6: Implementation Completed Dialog Box
3-2-4. Click OK.
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3-3. Use the Utilization report to verify the number of clock resources used.
3-3-1. Click Implemented Design > Report Utilization under Implementation in the Flow
Navigator.
3-3-2. Click OK in the Report Utilization dialog box to accept the default results name.
The utilization report appears at the bottom of the Vivado IDE.

3-3-3. Examine the Utilization report and verify the number of clock resources used.
Question 3
How many MMCMs and global clock buffer resources were used in the finished design?
Summary
In this lab you explored a mechanism for accessing FPGA resources. You created the clock core
IP and instantiated it into the design. You also manually instantiated several device primitives in
order to access specific global clocking resources within the FPGA.
The final mechanism of accessing FPGA resources is through inference. This, of course, is the
primary mechanism used. It is used extensively throughout the rest of the wave_gen design.
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Lab Workbook Lab 7: Introduction to Clock Constraints
Lab 7: Introduction to Clock Constraints

2018.1
Abstract
This lab reviews the process of creating and generating clocks.
are limited to Verilog usage.
Objectives
 Create clocks by using the Timing Constraints window
 Associate jitter specification to a created clock
 Generate a clock report (report_clock)
 Implement the design
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Lab 7: Introduction to Clock Constraints Lab Workbook
Introduction
The wave_gen design used in this lab is a programmable waveform generator.
Figure 7-1: wave_gen Design Block Diagram
This design records specific information via RS-232 serial communication and stores this data in
memory. After data has been stored, it can be retrieved via the RS-232 communications channel,
or played out via a bank of LEDs or a DAC. The wave_gen design implements the RS-232
communication channel, the waveform generator and connection to the external DAC, and a
simple parser to implement a small number of "commands" to control the waveform generation.
This lab will show you how to create clocks and generate clock constraints using the Timing
Constraint window. You will use report_clocks to understand the clocks that are used in the
design. This lab will also review the process of generating and reading static timing analysis
reports.
The diagram below shows the systematic approach recommended for applying timing
constraints and incrementally progressing towards closure. There are three broad stages in the
Performance Baselining procedure recommended by Xilinx, which enables the designer to
achieve timing closure progressively.
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 This lab will focus on optimizing internal paths (Baseline) as explained in the below figure:
 Define all primary clocks and generated clocks. Check for the clocks in the design
(period, edge relationships).
 Specify asynchronous (unrelated) clock groups: All clocks are assumed to be related to
each other unless otherwise specified. The phases between any two clocks are derived
from their individual clock definitions; timing paths between such clock domains are
analyzed using these derived requirements. To avoid this redundant timing analysis and
reporting of timing failure, asynchronous clock groups need to be specified. When there
are such asynchronous inter-clock paths specified, the design must use appropriate
synchronization techniques to capture data reliably at the target clock domain.
Note: Specifying asynchronous clocks step is covered in "Applying Clock Groups
Constraints" topic.
 With a complete clock definition as above, all FPGA internal paths (single-cycle paths)
can be analyzed for timing. The feasibility of closing timing for the single-cycle internal
paths can be assessed with reasonable confidence.
Figure 7-2: Focus in this Lab
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General Flow
Step 3:
Creating the
Opening Generating Creating a Implement-
Clock &
the a Clock Generated ing the
Specifying
Project Report Clock Design
Jitter
Opening the wave_gen.xpr Project Step 1

The first step is to open the wave_gen.xpr project in the Vivado® IDE and then
open the synthesized design database to launch the Timing Constraints window.

Vivado 2018.1.
-- OR --
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1-2. Open the existing Vivado Design Suite project wave_gen.xpr.

1-2-1. Click Open Project from the Quick Start section (1).
The Open Project dialog box opens (2).

1-2-2. Browse to the C:\training\ClkConstr_Intro\lab\[KCU105 | KC7xx]\verilog directory in the
Look in field (3).
Note: The drop-down arrow shows the directory hierarchy.
1-2-3. Select wave_gen.xpr (4).
Figure 7-5: Opening an Existing Project
1-2-4. Click OK to open the selected project (5).
The project now opens in the Vivado Design Suite.
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1-3. Examine the provided XDC file.

1-3-1. Expand Constraints (1) > constrs_1 in the Hierarchy tab of the Sources view.
1-3-2. Double-click wave_gen_timing.xdc to open it in the text editor.
Question 1
Are there are any constraints currently in the design?
1-3-3. Click X in the text editor window to close the opened XDC file.

1-4-1. Click Open Synthesized Design under Synthesis in the Flow Navigator.
Alternatively, you can select Flow > Open Synthesized Design.
Figure 7-6: Opening the Synthesized Design
Generating a Clock Report Step 2

You will review the clock networks in the design to view the generated clocks
hierarchy and fanout of each clock defined in the design. All the clocks in the
design need to be identified through this step for applying clock constraints.
2-1. Generate a Clocks Networks report.

2-1-1. Click Report Clock Networks in the Flow Navigator under Synthesized Design.
Alternatively, you can select Reports > Timing > Report Clock Networks.
The Report Clock Networks dialog box opens.
2-1-2. Click OK.
Clock Networks report gives the network fanout of each clock net in the open design
and provides a hierarchical tree view of the clock network.
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2-2. Review the Clock Networks report.

2-2-1. Expand the Unconstrained folder in the Clock Networks report.
None of the clocks in the design has been constrained at this time and all clocks appear
as Unconstrained. If there were already constrained clocks, they will appear outside the
Unconstrained group.
2-2-2. Expand clk_pin_p.
This will expand the clock network tree up to mmcm(e3)_adv_inst.

2-2-3. Click the Maximize icon in the Clock Networks -network_1 window.
2-2-4. Follow the steps listed below to view a complete hierarchy of the clock network.
o KCU105 Verilog users:
 Expand mmcme3_adv_inst > CLKFBOUT > clkfbout_clk_core > CLKFBIN
 Expand mmcme3_adv_inst > CLK_OUT0 > clk_out1_clk_core > clk_out1
 Expand mmcme3_adv_inst > CLK_OUT1 > clk_out2_clk_core > clk_out2 >
BUFGCE > BUFGCE_clk_samp_i0 > CLK
Note: In the VHDL version of the lab, you will find the clk_samp signal instead of clk.
o KC7xx Verilog users:
 Expand mmcm_adv_inst > CLKFBOUT > clkfbout_clk_core > CLKFBIN
 Expand mmcm_adv_inst > CLK_OUT0 > clk_out1_clk_core > clk_out1
 Expand mmcm_adv_inst > CLK_OUT1 > clk_out2_clk_core > clk_out2 >
BUFHCE > BUFHCE_clk_samp_i0 > clk_samp
2-2-5. Observe the fanout of the clkout1, clkout0, and clk clock objects.
The Clock Networks window should look the figure below.
Figure 7-7: Clock Networks Report (KCU105, Verilog)
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Note: For 7 series users, the graphic will be slightly different with respect to the mmcm
primitive name, clock buffer names, and fanouts.
2-2-6. Click the Restore icon in the Clock Networks -report_1 window.
2-2-7. Close the Clock Networks tab.
Creating the Clock and Specifying Associated Jitter Step 3

The next thing is to define a clock object in the design. Now you will define
clk_pin_p as a clock object, associate jitter specification to the clock object, and
then use the report_clocks command to see all the clocks available in the
design.
3-1. Open the Timing Constraints window.

3-1-1. Select Window > Timing Constraints.
The Timing Constraints window can also be opened by clicking Edit Timing Constraints
under Synthesized Design in the Flow Navigator.
The Timing Constraints window opens in the main workspace area.
Figure 7-8: Timing Constraints Window in the Vivado IDE
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3-2. Launch the Create Clock dialog box.

3-2-1. Double-click Create Clock (0) in the Timing Constraints window.
The number in the parentheses represents the number of similar constraints in the
design. In this case, this is zero because there are no objects defined as clock objects in
the design provided; i.e., there are zero create_clock constraints in the design.
The Create Clock dialog box opens.
Figure 7-9: Create Clock Dialog Box
3-2-2. Click Reference to read the command reference about the selected command, i.e.,
create_clock.
3-2-3. Click Close in the Command Reference: create_clock dialog box.
3-2-4. Enter clk_pin_p in Clock name field.
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3-3. Associate the clock input port to the clock definition.
3-3-1. Click the icon next to the Source objects field.

The Specify Clock Source Objects dialog box opens.
3-3-2. Ensure that I/O ports is selected from the Find names of type drop-down list.
3-3-3. Specify the search options as NAME CONTAINS clk_pin* to search clocks with clk_pin in
the name.
3-3-4. Click Find to initiate the search.
3-3-5. Select clk_pin_p from the Results > Found window.
3-3-6. Click the icon to add clk_pin_p to the Selected section.
Figure 7-10: Specify Clock Source Objects Dialog Box
3-3-7. Click Set.
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3-4. Describe the period property and review the waveform details of the clock
object.
3-4-1. Enter the period value in the Period field under the Waveform section in the Create Clock
dialog box.
KCU105 users: Enter 3.333 ns to specify a clock of 300 MHz.
KC7xx users: Enter 5.000 ns to specify a clock of 200 MHz.
3-4-2. Ensure that the Rise at field is set to '0' and Fall at field is set to half of the given period
to have 50% duty cycle.
Figure 7-11: Create Clock Dialog Box after Defining clk_pin_p Port as a Clock Object
3-4-3. Click OK to create the clock.
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After the clock is created, the Timing Constraints window should look like the figure
below.
Figure 7-12: Timing Constraints Window after Entering create_clock
Notice the create_clock XDC command for the created clock in the All Constraints
section of the Timing Constraints window.
3-5. Assume the clock is ideal and enter the clock input jitter information.
3-5-1. Double-click Clocks (1) > Set Input Jitter using the Timing Constraints window.
The Set Input Jitter Dialog box opens.

3-5-2. Enter 0 in the Input Jitter field assuming that the clock is ideal.
Note: 0 is the default value for jitter; therefore, this specification is redundant. It is shown
here for completeness.
3-5-3. Click the icon next to the Clock field.

Specify the Input Jitter Clock dialog box opens.
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3-6. Set the jitter for the defined clock object.

3-6-1. Note that Clocks is selected for the Find names of type option.
3-6-2. Accept the default settings for the Options field.
3-6-3. Click Find in the Specify the Input Jitter Clock window to initiate the search.
3-6-4. Select clk_pin_p from the Results > Found section.
3-6-5. Click the icon to add clk_pin_p to the selected names.
Figure 7-13: Specify the Clock for Input Jitter Dialog Box
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3-6-6. Click OK.
Figure 7-14: Set Input Jitter Dialog Box
3-6-7. Click OK in the Set Input Jitter dialog box.
3-7. Generate the clocks report.

3-7-1. Select Window > Tcl Console if the Tcl Console is not already selected (at the bottom of
the Vivado GUI).
3-7-2. Enter the following command using the Tcl Console:
report_clocks
Note: report_clocks lists only the clock constraints that have been specified for timing.
This command does not list all the clock nets. To find the clock nets in a design, use
report_clock_networks.
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3-7-3. Click the Maximize icon in the Tcl Console window.
Figure 7-15: Reporting Clocks (KCU105)
Figure 7-16: Reporting Clocks (KC7xx)
Question 2
In addition to clk_pin_p, there are three more clocks (CLKFBOUT, CLK_OUT2, and CLKOUT1) in
the report. Are these clocks expected?
3-7-4. Click the Restore icon in the Tcl Console window.
Creating a Generated Clock Step 4

The design provided has a clock (clk_samp) that is generated using a clock buffer
(BUFGCE for UltraScale devices and BUFHCE for 7 series devices). You will define
the clock generated by the clock buffer by using the Create Generated Clock
command. The timing engine in the Vivado Design Suite does not automatically
derive the timing for such manually gated clocks and it needs to be specified
(unlike MMCM output clocks). If it is not specified, the same clock constraint at
the input of the buffer will be applied to clk_samp (like an un-gated buffer).
4-1. Launch the Create Generated Clock dialog box and associate the clock name
as clk_samp.
4-1-1. Double-click Clocks (2) > Create Generated Clock in the Timing Constraints Window.
The Create Generated Clock dialog box opens.

4-1-2. Enter clk_samp in the Clock name field.
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4-2. Associate the master pin to clk_samp.

When you are specifying manually created clocks, the source is specified at the
input pin of the clock generating element. In this case, it would be the BUFGCE I
pin/BUFHCE I pin.
4-2-1. Click the icon next to the Master pin (source) field.
The Specify Master Pin dialog box opens.
4-2-2. Ensure that Cell pins is selected from the Find names of type drop-down list.
4-2-3. Specify the search option as NAME CONTAINS BUF*CE_clk_samp_i0/* to search for the
pins of the clock buffer.
4-2-4. Enable the Search hierarchically option.
4-2-5. Click Find to initiate the search.
4-2-6. Select the input pin of the buffer from the Results > Found section.
KCU105 users: Select clk_gen_i0/BUFGCE_clk_samp_i0/I.

KC7xx users: Select clk_gen_i0/BUFHCE_clk_samp_i0/I.
4-2-7. Click the icon.
Figure 7-17: Specify Master Pin Dialog Box
4-2-8. Click OK.
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4-3. Specify clk_samp as a derived waveform with 1/32 frequency of the source
clock.
4-3-1. Select the By clock frequency option under the Derive from Source Clock Waveform
section, if it is not already selected.
4-3-2. Enter 32 as the division factor in the Divide source clock frequency by option.
4-4. Associate the source object to clk_samp.
4-4-1. Click the icon next to the Source objects field.

4-4-2. Ensure Cell Pins is selected from the Find names of type drop-down list.
4-4-3. Specify the search option as NAME CONTAINS BUF*CE_clk_samp_i0/* to search for the
pins of the clock buffer.
4-4-4. Click Find.
4-4-5. Select the output pin of the buffer from the Results > Found section.
KCU105 users: Select clk_gen_i0/BUFGCE_clk_samp_i0/O.

KC7xx users: Select clk_gen_i0/BUFHCE_clk_samp_i0/O.

4-4-7. Click Set.
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4-5. Create a clk_samp object and review the generated clock properties.
The Create Generated Clock dialog box should look like the figure below after
completing the above steps.
Figure 7-18: Create Generated Clock Dialog Box
4-5-1. Click OK to create the generated clock in the design.

4-5-2. Enter the following in the Tcl Console to generate a clock report:
report_clocks
4-5-3. Click the Maximize icon in the Tcl Console window.
Figure 7-19: Clock Report after Generating clk_samp (KCU105)
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Question 3
Is the period of clk_samp what you expected? Why or why not?
4-5-4. Click the Restore icon in the Tcl Console window.
4-6. Save the constraints to the XDC file.

4-6-1. Select the Window > Sources tab.
4-6-2. Expand Constraints (1) > constrs_1 using the Hierarchy tab of the Sources view.
4-6-3. Double-click the wave_gen_timing.xdc file to open it in the Sources view.
Question 4
Are there constraints in the XDC file? If not, where are the constraints that you specified?
4-6-4. Close the wave_gen_timing.xdc window.

4-6-5. Select File > Constraints > Save.
4-6-6. Click OK if the Out of Date Design dialog box opens.
The Save Constraints File dialog box opens.

4-6-7. Ensure that the Select an Existing File option is selected.
Note that wave_gen_timing.xdc is the only XDC file in this project; hence, it was selected
by default.
4-6-8. Click OK.
4-6-9. Reopen the wave_gen_timing.xdc file.
Notice that the constraints are now written to the XDC file.
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In this step, you will implement the design and analyze the timing paths and its
properties.
5-1. Implement the design.

5-1-1. Click Run Implementation in the Flow Navigator (under Implementation).
Alternatively, you can select Flow > Run Implementation.
Figure 7-20: Selecting Run Implementation
Note: If needed, click OK to launch synthesis first if prompted.

Notice that the tools run all of the processes required to implement the design. This
means that if the synthesized netlist is not available already, the Vivado Design Suite will
run synthesis before running implementation.
After implementation completes, the Implementation Completed dialog box opens. The
dialog box prompts you to open the implemented design, generate the bitstream, or
view reports.
5-1-2. Click OK again to launch the selected runs.
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5-1-3. Select Open Implemented Design.
Figure 7-21: Implementation Completed Dialog Box
5-1-4. Click OK.

5-1-5. Click Yes if asked to close the Synthesized design before opening the Implemented
design.
5-2. Analyze the Timing Summary Report.

The Timing Summary Report will be open by default in the implemented
design and run as a part of Implementation.
5-2-1. Select the first path in the clk_out1_clk_core under the Intra-Clock paths section of the
Timing Summary window.
Note: There may be timing errors in the setup paths.
Question 5
How many clock paths are constrained in this design?
Question 6
Are these timing errors expected? Why or why not?
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5-2-2. Press <F4> to create the schematic of the first timing path.
Note that the clock path is also visible, along with the data path in the schematic.
If the icon is not selected, the clock path is not shown in the schematic.
Figure 7-22: Schematic of the Timing Path (KCU105) - Example (Your Schematic May Differ)
Figure 7-23: Schematic of the Timing Path (KC7xx) - Example (Your Schematic May Differ)
The clock path and data path have been highlighted in the graphic for better
understanding.
5-2-3. Double-click the selected path in the Timing Summary window to view the detailed path
report.
5-2-4. Maximize or float the Path Report to look at the path details.
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Note: This is an example timing summary report. Your results may very depends on
which Vivado Design Suite version you are using.
Figure 7-24: Timing Path Report for First Path of clk_out1_clk_core (KCU105)
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Figure 7-25: Timing Path Report for First Path of clk_out1_clk_core (KC7xx)
Note: The timing may vary slightly in the above mentioned timing path reports.
The timing path report provides a detailed summary of the timing path covered by the
specific clock path group. When you click the links in the report, the logic objects are
selected in other views.
It provides the detailed information of the logic objects in the path and their associated
delays for the source clock path, data path, and the destination clock path. The details of
the timing path report are as follows.
o Summary: Provides brief information about the timing path and reports slack for the
timing path endpoints. The slack is the difference between the data required time
and the data arrival timing at the path endpoint.
o Source Clock Path: Provides the detailed information of the logic objects in the path
and their associated delays for the source clock path. This source clock path is the
path followed by the source clock from its source point to the clock pin of the
launching flip-flop.
o Data Path: Provides the detailed information of the logic objects in the path and
their associated delays for the internal circuitry, between the launching and capturing
flip-flops. The active clock pin of the launching flip-flop is called the path startpoint.
The data input pin of the capturing flip-flop is called the path endpoint.
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o Destination Clock Path: Provides the detailed information of the logic objects in the
path and their associated delays for the e destination clock path. The destination
clock path is the path followed by the destination clock from its source point,
typically an input port, to the clock pin of the capturing flip-flop.
5-2-5. Extract the information required for the table below.
Hint: Look in the Summary section of the path report.

5-2-6. Repeat the steps to extract information for the path covered by the clk_out2_clk_core
clock group. Make sure you choose the first path.
5-2-7. Examine the timing results. Verify the slowest paths for the two clock groups.
Question 7
Record and verify the startpoint, endpoint, slack, and data path delay of the slowest path for the
following clock groups.
Data Path
Clock Group Source Destination Slack
Delay
clk_out1_clk_core
clk_out2_clk_core
Static Timing Results
The timing analysis at this stage is only for the internal paths of the FPGA, and I/O timing
has not yet been specified for analysis. From the timing summary report, it can be seen
that only some clk_out1_clk_core domain paths under Intra-Clock Paths are failing as of
now. From the source and destination of these paths and an understanding of the
wave_gen design, it can be seen that these long paths are designed as multicycle paths.
You will apply multicycle paths in a later lab to close this timing.
5-2-8. Click the Restore icon or Dock icon in the window banner to restore the Path Properties
window.
Summary
Through this lab, you have learned how to use the Timing Constraints window to define clocks
in the design. You also learned how to view the clocks in the design by using the
report_clocks command from the Tcl Console and how to generate a timing report through
the GUI.
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Lab Workbook Lab 8: I/O Constraints and Virtual Clocks
Lab 8: I/O Constraints and Virtual Clocks

2018.1
Abstract
This lab will guide you through creating input and output XDC timing constraints by using the
Timing Constraints Editor. You will also utilize timing reports to verify the timing results.
Objectives
 Specify input delay requirements with respect to real and virtual clocks
 Define a virtual clock in a design
 Specify output delay requirements in a design
 Verify the timing reports to check that an implemented design has met timing
Introduction
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Lab 8: I/O Constraints and Virtual Clocks Lab Workbook
This lab will show you how to apply input and output delay requirements for an FPGA. This lab
will also review the process of generating and reading timing reports.
The diagram below shows the systematic approach recommended for applying timing
constraints and incrementally progressing towards closure. There are three broad stages in the
Performance Baselining procedure recommended by Xilinx, which enables the designer to
achieve timing closure progressively.
This lab will focus on second stage of the Performance Baselining flow (optimizing the entire
chip) as explained in the below figure.
Figure 8-2: Focus in this Lab
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General Flow
Opening Specifying Specifying Implement-
the the Input the Output ing the
Project Delays Delays Design
Opening the wave_gen Project Step 1

The first step is to open the wave_gen project in the Vivado® IDE and then open
the synthesized design database to launch the Timing Constraints window.

Guide.
C:\training\IOConstr_Intro\lab\[KCU105 | KC7xx]\netlist directory.
If you do not recall how to perform this task, refer to the "Opening a Vivado Design Suite
Project" section under Vivado Design Suite Operations in the Lab Reference Guide.

1-3-1. Click Open Synthesized Design under NETLIST ANALYSIS in the Flow Navigator.
Alternatively, you can select Flow > Open Synthesized Design.
Figure 8-3: Set Input Delay Dialog Box
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The basic timing constraints are create_clock, set_input_delay, and

set_output_delay. Timing constraints must be passed to the synthesis engine
by means of the XDC file. In this lab, you will specify the input and output delay
constraints by using the figure below.
Figure 8-4: Timing Objectives of the Design
Note: The timing constraints will vary based on the chosen FPGA device. The
following table lists the delay values for both the KCU105 and KC705 boards.
There are three input pins in the design. You will apply an input max delay
constraint of 1.25 ns and input min delay of 1 ns for the input pins. Details on
each input are listed below:
Upstream Device Delay Values
Maximum Clk to out delay (tco_max) = 0.35 ns
Minimum Clk to out delay (tco_min) = 0.2 ns
Maximum board trace delay (trce_dly_max)= 0.9 ns
Minimum board trace delay (trce_dly_min) = 0.8 ns
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Similarly, identify the system-synchronous output pins and specify an output max
delay of 1.25 ns and min delay 0.5 ns constraints for all the output pins clocked
by the system clock.
Downstream Device Delay Values for led_pins[*] and

txd_pin
Setup delay requirement destination flip-flop (tsu) = 0.35 ns
Hold time requirement of destination flip-flops (thd) = 0.3 ns
Maximum board trace delay (trce_dly_max) = 0.9 ns
Since the design clocks an external DAC, identify the source-synchronous output
pins clocked by spi_clk_pin and specify output max delay constraint of 1 ns and
min delay of -1 ns for all the output pins clocked by spi_clk_pin. spi_clk_pin is
already defined in the XDC.
Downstream Device Delay Values for spi_mosi_pin,

dac_cs_n_pin, and dac_clr_n_pin
Setup delay requirement destination flip-flop (tsu) = 0.1 ns
Hold time requirement of destination flip-flops (thd) = 1.8 ns
Maximum board trace delay (trce_dly_max) = 0.9 ns
The set input delay value for the maximum delay (setup analysis) = tco_max +
maximum board trace delay (trce_dly_max).
The set input delay value for the minimum delay (hold analysis) = tco_min +
minimum board trace delay (trce_dly_min).
The set output delay value for the maximum delay (setup analysis) = maximum
board trace delay (trce_dly_max) + setup requirement of the destination flip-flop
(tsu).
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The set output delay value for the minimum delay (hold analysis) = minimum
board trace delay (trce_dly_min) - hold requirement of the destination flip-flop
(thd).
1-4. Examine the tables above and answer the following questions.
Question 1
The data from the upstream device arrives at the FPGA pin with a maximum delay value
specified in the table above (upstream clock to out delay and trace delay), and the device has a
setup requirement. The data arrives at the FPGA with a minimum delay value, and the device has
a hold requirement.
How will you specify the input timing requirements at the FPGA for setup and hold analysis?
Assume an ideal system-synchronous interface with 0 skew.
Hint: Enter set_input_delay -help in the Tcl Console to view information on how to apply
an input delay constraint.
Question 2
The data output from the FPGA arrives at the downstream device with a maximum delay value
specified in the table above, and the device has setup requirement. FPGA data arrives at the
downstream device with a minimum delay value, and the downstream device has a hold
requirement value.
How will you specify the output delay requirements for the FPGA? Assume an ideal system-
synchronous interface with 0 skew.
Hint: Enter set_output_delay -help in the Tcl Console to view information on how to
apply an output delay constraint.
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Specifying the Input Delays Step 2

In addition to differential clock input ports, there are three more input signals in
the wave_gen design:
o rst_pin: Asynchronous reset input for MMCM; asynchronous preset for reset
bridge; asynchronous reset for char_fifo.
o rxd_pin: Serial receiver port
o lb_sel_pin: Loopback switch input that the lb_sel net generates, which is the
debounced output of the switch using tx_clk.
In this step, you will specify an input max delay constraint of 1.25 ns and input
min delay of 1 ns for these input pins.
2-1. Open the Timing Constraints Editor window.

2-1-1. Select Window > Timing Constraints.
This window can also be opened by clicking Edit Timing Constraints under Synthesized
Design in the Flow Navigator.
The Timing Constraints window opens in the main workspace area.
2-2. Launch the Set Input Delay dialog box from the Timing Constraints window
to specify delay requirements on the input ports.
2-2-1. Double-click Set Input Delay (0) under the Inputs category in the Timing Constraints
window.
The Set Input Delay dialog box opens.
Figure 8-5: Set Input Delay Dialog Box
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The Specify Clock dialog box opens.
Note that Clocks is selected for the Find names of type drop-down list.
2-2-3. Click Find.
2-2-4. Select clk_pin_p from the Results > Found section.
Figure 8-6: Specifying Delay Requirements on the Input Ports
2-2-6. Click OK.
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2-3. Select the port objects to set the input delays.
2-3-1. Click the icon next to the Objects (ports) field.

The Specify Delay Objects dialog box opens.
Note that I/O ports is selected for the Find names of type drop-down list.
2-3-2. Specify the search option as NAME CONTAINS r*pin.
2-3-3. Click Find.
2-3-4. Select rst_pin from the Results > Found section.
Figure 8-7: Setting the Input Delays on the Port Objects
2-3-6. Click Set.
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2-4. Specify the input setup delay value.

2-4-1. Enter the delay value as 1.25 ns in the Delay value field.
This design assumes 1.25 ns as the max delay requirement.

2-4-2. Make sure rise is selected from the Delay value is relative to clock edge drop-down list.
2-4-3. Confirm that the Add delay information to the existing delay (no overwrite) option is
deselected.
2-4-4. Leave all other options at their defaults.
Figure 8-8: Specifying the Input Setup Delay Value
Note the set_input_delay XDC command at the bottom of the Set Input Delay
dialog box. This will create a set_input_delay with a 1.25 ns setup time requirement
on the rst_pin port in relationship to clk_pin_p.
2-4-5. Click OK.
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The Timing Constraints window should look like the figure below with the newly created
command.
Figure 8-9: Timing Constraints Window with Newly Created Command
2-5. Specify 1 ns min delay requirement on the rst_pin port with respect to
clk_pin_p.
2-5-1. Double-click Set Input Delay (1) in the Timing Constraints window under the Inputs
category.
The Set Input Delay dialog box opens with the recently entered data.
If the fields in the dialog box are different from the above figure, repeat the instructions
that you completed at the beginning in which you found and specified clk_pin_p.
2-5-2. Enter 1 in the Delay value field of the Set Input Delay dialog box.
2-5-3. Enable the Delay value specifies <min/max> delay option.
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2-5-4. Select min from the Delay value specifies drop-down list.
Figure 8-10: Selecting Delay Value Specifies Min
2-5-5. Click OK.
This will create a set_input_delay with a 1 ns min delay requirement on the input
ports rst_pin.
2-5-6. Enter the following reporting command using the Tcl Console:
check_timing -verbose -override_defaults no_input_delay
This will check whether all input ports in the design are specified with the
set_input_delay constraint.
Figure 8-11: check_timing in the Tcl Console
Note that lb_sel_pin and rxd_pin do not have input delay specifications.
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2-6. Create a virtual clock named clk_tx_virtual with a period property of

[get_clocks clk_out2_clk_core].
2-6-1. Enter the following command using the Tcl Console:
get_property PERIOD [get_clocks clk_out2_clk_core]
Note down the return value. When creating the virtual clock, you will use this value to
define the period of the virtual clock.
2-6-2. Double-click Create Clock (1) under the Clocks category using the Timing Constraints
window.
2-6-3. Enter clk_tx_virtual in the Clock name field.
2-6-4. Clear the Source objects field if required.
You are creating a virtual clock; i.e., there is no source object (port/pin/net) with the
constraint.
2-6-5. Enter 5.161 in the Period field.
Figure 8-12: Creating a Virtual Clock
2-6-6. Click OK to create the virtual clock.
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2-7. Specify 1.25 ns max delay requirement on the lb_sel_pin port relative to
clk_tx_virtual.
2-7-1. Double-click Set Input Delay (2) under the Inputs category using the Timing Constraints
Window.

The Specify Clocks window opens.
2-7-3. Click Find.
2-7-4. Select clk_tx_virtual from the Results > Found section.
Figure 8-13: Specifying the Input Delay Requirement on the Virtual Clock
2-7-6. Click OK.
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2-8. Specify the ports to the input delay specification.

2-8-2. Ensure that the search option is specified as NAME CONTAINS *.
2-8-3. Click Find.
2-8-4. Select lb_sel_pin from Results > Found section.

2-8-6. Click Set.
2-8-7. Set the Delay value to 1.25 ns.
2-8-8. Deselect the Delay value specifies <min/max> delay option.
Figure 8-14: Specifying the Ports to the Input Delay Specification for the Virtual Clock
2-8-9. Click OK.
2-9. Specify 1 ns min delay requirement on lb_sel_pin relative to clk_tx_virtual.

window.
2-9-2. Enter 1 ns in the Delay value field.
2-9-3. Select the Delay value specifies <min/max> delay option.
2-9-4. Select min from the Delay value specifies <min/max> delay drop-down list.
2-9-5. Click OK.
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2-10. KCU105 users only: Create a virtual clock named clk_rx_virtual with a period
property of [get_clocks clk_out1_clk_core].
2-10-1. Repeat the steps that you had previously followed to create the clk_tx_virtual virtual
clock to now create a virtual clock with the name clk_rx_virtual and a period of 5.00 ns.
2-11. Specify 1.25 ns max delay requirement on rxd_pin port.

Window.

2-11-3. Click Find in the Specify Clocks window.
2-11-4. Select the appropriate option for your board from the Results > Found section:
KCU105 users: Select clk_rx_virtual.

KC705 users: Select clk_pin_p.

2-11-6. Click OK.
2-12. Specify the ports to the input delay specification

2-12-2. Enter the search option as NAME CONTAINS r*.
2-12-3. Click Find.
2-12-4. Select rxd_pin from the Results > Found section.

2-12-6. Click Set.
2-12-7. Set the delay value to 1.25 ns.
2-12-8. Deselect the Delay value specifies <min/max> delay option.
2-12-9. Click OK.
This creates a 1.25 ns max delay constraint on rxd_pin port.
2-13. Specify a 1 ns hold time requirement on rxd_pin.

window.
2-13-3. Select the Delay value specifies <min/max> delay option.
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2-13-5. Click OK.
This specifies a 1 ns min delay requirement on the rxd_pin port with respect to
clk_rx_virtual/clk_pin_p.
The unsaved constraints section of the Timing Constraints window should look like the
figure below.
Figure 8-15: Unsaved Constraints Section of the Timing Constraints Window (KCU105)
Figure 8-16: Unsaved Constraints section of Timing Constraint Window (KC7xx)
2-13-6. Enter the following reporting command using the Tcl Console:
check_timing -verbose -override_defaults no_input_delay
This will check whether all input ports in the design are specified with the
set_input_delay constraint.
Question 3
Were all the input ports specified with input delay requirements?
2-14. The All Constraints Section of the Timing Constraints window displays the
timing commands that have been run and that are applied to the design
that is loaded in the memory.
Commit the constraints to the design so that they are applied to the design. The
applied constraints can be saved by writing them to a Xilinx design constraints
(XDC) file.
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2-14-2. Make sure that Select an existing file with wave_gen_timing.xdc is selected.
2-14-3. Click OK.
Specifying the Output Delays Step 3

Here, you will specify the output delay for txd_pin and led_pins[*] with respect to
the clk_tx_virtual clock that you created previously.
3-1. Associate the clock to the set output delay.

3-1-1. Double-click Set Output Delay (0) under the Outputs category in the Timing Constraints
window.

The Specify Clock dialog box opens.
Note that Clocks is selected for the Find names of type drop-down list.
3-1-3. Click Find.
3-1-4. Select clk_tx_virtual from the Results > Found section.
3-1-5. Click to select clk_tx_virtual.
Figure 8-17: Specifying the Output Delay to the Virtual Clock
3-1-6. Click OK.
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3-2. Associate the led_pins[*] and txd_pin objects to the output delay
specification.

The Specify Delay Objects dialog box opens.
3-2-2. Ensure I/O Ports is selected from the Find names of type drop-down list.
3-2-3. Click Find.
3-2-4. Select led_pins[0], led_pins[1], led_pins[2], led_pins[3], led_pins[4], led_pins[5],
led_pins[6], led_pins[7] and txd_pin in the Find results section by pressing <Ctrl> and
clicking.
3-2-5. Click to select the ports.
Figure 8-18: Specify Delay Objects Dialog Box
3-2-6. Click Set.
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3-3. Specify the delay value to the set output delay command.
3-3-1. Enter 1.25 ns in the Delay value field.
3-3-2. Leave the other fields at their defaults.
Figure 8-19: Specifying the Delay Value to the Set Output Delay Command
3-3-3. Click OK to create the set output delay constraint.
3-4. Specify the minimum delay value to the set output delay command.
3-4-1. Double-click Set Output Delay (1) in the Timing Constraints window under the Outputs
category.
The Set Output Delay dialog box opens with the recently entered data.
If the fields in the dialog box are different from the above figure, repeat the instructions
that you completed at the beginning in which you found and specified clk_tx_virtual.
3-4-2. Enter 0.5 ns in the Delay value field of the Set Output Delay dialog box.
3-4-4. Select min from the Delay value specifies drop-down list.
3-4-5. Click OK.
This will create a set_output_delay with a 0.5 ns min delay requirement on the
output ports led_pins[*] and txd_pin.
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3-5. Specify the output delay for spi_mosi_pin, dac_cs_n_pin, and dac_clr_n_pin
with a max delay requirement of 1 ns with respect to spi_clk.
window.
3-5-2. Enter [get_clocks {spi_clk}] in the Clock field.
3-5-3. Enter [get_ports {dac_clr_n_pin dac_cs_n_pin spi_mosi_pin}] in the
Objects (ports) field.
3-5-6. Select max from the Delay value specifies <min/max> delay list.
Figure 8-20: Specifying Ports Setup Time Requirement for spi_clk
3-5-7. Click OK.
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3-6. Specify a min delay requirement of -1 ns to the spi_mosi_pin, dac_cs_n_pin,

and dac_clr_n_pin ports using the real clock named spi_clk.
window.
3-6-2. Make sure that [get_clocks {spi_clk}] is entered in the Clock field.
3-6-3. Make sure that [get_ports {dac_clr_n_pin dac_cs_n_pin spi_mosi_pin}]
is entered in the Objects (ports) field.
3-6-4. Enter -1 ns in the Delay Value field.
3-6-6. Click OK.
3-7. Confirm that all output ports in the design were specified with output delay
requirements.
3-7-1. Enter the following command in the Tcl Console:
check_timing -verbose -override_defaults no_output_delay
spi_clk_pin is not constrained with the set_output_delay command because it is a
source-synchronous pin that goes to the clk pin of any sequential element in the
downstream device.
Notice that all other output ports were specified with output delay requirements.
4-1. Save the constraints to the XDC file.

All the constraints created so far were saved just in memory, so the created
constraints need to be saved to the XDC file before closing the database (in
this case, synthesized design database).
4-1-2. Click Yes if prompted to commit the constraints to the design.
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4-3. Run implementation and open the implemented design.

4-3-1. Review the Timing Summary that opened with the implemented design.
The paths in Intra-Clock Paths section and Other Path Groups section have failed to meet
timing.
Note: Click OK in the Critical Messages dialog box.
4-4. Generate the Timing Report to view specific timing paths.

4-4-1. Select Reports > Timing > Report Timing.
The Report Timing dialog box opens.
Figure 8-21: Report Timing Dialog Box: Targets Tab
4-4-2. Click OK to generate the timing report with the default options.
The generated timing report opens in the Timing tab at the bottom.
4-4-3. Click to display the failing paths.
4-4-4. Click to also select clock paths when the timing path is selected.
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This adds clock path visibility to the timing paths.
Figure 8-22: Timing Report Results (KCU105)
Note: The timing values generated by the Timing Report may vary slightly.
Notice that there are timing errors in the design.
4-4-5. Enter the report_timing_summary command in the Tcl console.
4-4-6. Select the first path under the clk_out1_clk_core group and press <F4>.
This creates the schematic of the timing path selected.

Note: Schematic may vary from the one below.
Figure 8-23: Schematic of the Timing Path with Data Path and Clock Path (KCU105)
Question 4
Are these timing errors expected? Why or why not?
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With the I/O timing specifications added, timing analysis has accounted for the FPGA's
interface level and internal timing. The few paths that are failing for I/O timing are
related to asynchronous reset input. The timing failures in the clk_out1_clk_core domain
are multicycle paths. These timings will be closed in the Fine Tuning stage of timing
specification and analysis.
4-5. Close the Vivado Design Suite project.

If you do not recall how to perform this task, refer to the "Closing the Vivado
Reference Guide.

Design Suite" section under Vivado Design Suite Operations chapter in the Lab
Reference Guide.
Summary
This lab illustrated how the input and output delay requirements are specified to the design by
using the Timing Constraints window.
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Lab Workbook Lab 9: Timing Constraints Wizard
Lab 9: Timing Constraints Wizard

2018.1
Abstract
This lab introduces you to the Timing Constraints Wizard in the Vivado® IDE. The Timing
Constraints Wizard helps you create timing constraints in a design, such as clock and I/O
constraints.
are limited to Verilog usage.
Objectives
 Use the Timing Constraints Wizard in the Vivado IDE to enter timing constraints
 Review the timing report to determine if the constraints are attainable
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Lab 9: Timing Constraints Wizard Lab Workbook
Introduction
Prior to implementation, there are timing and physical constraints that need to be
defined. The Vivado IDE enables you to interactively enter these timing and
physical constraints to the design.
The wave_gen design has a 300-MHz clock (KCU105 users) or 200-MHz clock
(KC7xx) supplied through differential clock input ports on the FPGA. You will first
define the primary clock object for the design and define a create_clock
constraint for the clock object.
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In addition to differential clock input ports, there are three more input signals in
the wave_gen design:
o rst_pin: Asynchronous reset input for MMCM
o rxd_pin: Serial receiver port
o lb_sel_pin: Loopback switch input that generates the lb_sel net, which is the
debounced output of the switch using tx_clk
You will specify input delay requirements on rst_pin, rxd_pin, and lb_sel_pin.
An input_delay constraint for the above pins needs to be specified. Later an
output_delay constraint needs to be specified from the output flip-flops to the
led_pins ports, which are the outputs for the design.
You will use the Timing Constraints Wizard to apply timing constraints to the
design.
General Flow
Step 2: Step 3:
Step 1: Step 4:
Entering Entering
Opening Implement-
Timing Timing
an Existing ing and
Constraints Constraints
Project Analyzing
[UltraScale] [7 Series]

You will begin the lab by launching the Vivado Design Suite and opening the
wave_gen.xpr design in the Vivado IDE.

Guide.
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C:\training\Constr_Wizard\lab\[KCU105 | KC7xx]\verilog directory.
If you do not recall how to perform this task, refer to the "Opening a Vivado
Reference Guide.
In order to apply the constraints to the design, the synthesized design has to be
opened. Therefore, you will start the lab by opening the synthesized design.
1-3. Open the wave_gen.xdc file to view any existing constraints.

1-3-1. Select the Hierarchy tab in the Sources view.
1-3-2. Expand the Constraints folder.
1-3-3. Double-click the wave_gen_timing.xdc file to open the file.
Note that there are no constraints in the XDC file.

1-3-4. Close the wave_gen_timing.xdc file.

If you do not recall how to perform this task, refer to the "Opening the
Synthesized Design" section under Vivado Design Suite Operations in the Lab
Reference Guide.
1-5. Generate the timing summary report to view any missing constraints in the
design.
1-5-1. Click Report Timing Summary under Synthesis > Open Synthesized Design.
1-5-2. Click OK to run the default Timing Summary report.
1-5-3. Review the Check Timing section of the Timing Summary report.
Notice that there are warnings under the no_clock, no_input_delay, and no_output_delay
section of the report.
This means that there are no clocks defined and that no input and output delay
constraints are applied to the design.
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1-6. Set the target constraints file.

1-6-1. Click Constraints Wizard under Synthesis > Open Synthesized Design in the Flow
Navigator.
This will open the Timing Constraints Wizard in the main workspace area.
1-6-2. Click Define Target in the No Target Constraints File dialog box that opens.
1-6-3. Select wave_gen_timing.xdc in the Define Constraints and Target dialog box.
1-6-4. Click OK.
This sets wave_gen_timing.xdc as the target file for entering constraints.
1-7. Open the Constraints Wizard and enter timing constraints.

1-7-1. Click Constraints Wizard under Synthesis > Open Synthesized Design in the Flow
Navigator to open the Timing Constraints Wizard.
The Timing Constraints Wizard appears in the main window of the Vivado IDE.
1-7-2. Click Next in the Identify and Recommend Missing Timing Constraints dialog box.
Figure 9-2: Identify and Recommend Missing Timing Constraints Dialog Box
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Question 1
What effect do timing constraints have on the implementation tools? What do the tools do if
there are no constraints applied?
KCU105 users: Continue with the "UltraScale Users Only: Entering Timing Constraints"
step.
KC7xx users: Proceed to the "7 Series Users Only: Entering Timing Constraints" step.
UltraScale Users Only: Entering Timing Constraints Step 2

In this step, you will define the clock object and specify the input and output
delays for the design.
2-1. Define the primary clocks with a specified period.

The Recommended Constraints section shows the primary clocks that the wizard
has identified and you need to define their period.
The Constraints for Pulse Width Check Only section shows clocks in the design
that are ultimately constrained by a pulse width only check. You may or may not
want to define their period.
The Tcl Command Preview section shows you the Tcl commands that will be
issued when you continue with the wizard. Finally, the Existing Constraints section
shows you pertinent existing constraints in the design.
Most pages of the wizard adhere to this general format. If a row is checked, then
the constraint corresponding to that row will be issued when you continue with
the wizard. You can opt out of any constraint by unchecking a row in the table.
Additionally, when you select a row in the top table, the corresponding Tcl
commands will be selected in the Tcl preview pane.
2-1-1. Examine the Primary Clocks dialog box of the Timing Constraints Wizard and notice that
a constraint on the clk_pin_p object is recommended in the Primary clocks dialog box of
the Timing Constraints Wizard.
2-1-2. Click the question mark icon on the left-bottom side of the page.
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This will open the Quick Help dialog box and more information is provided on the
Primary Clocks page.
2-1-3. Review the information in the Quick Help dialog box.
Figure 9-3: Quick Help Dialog Box for Primary Clocks
2-1-4. Click X to close the Quick Help dialog box and get back to the Primary Clocks page.
2-1-5. Enter 300 in the Frequency (MHz) column.
2-1-6. Observe that the Frequency, Rise At, and Fall At values are automatically generated
based on Period.
Note: The create_clock XDC command is also displayed under the Tcl Command
Preview tab.
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You can also view existing create clock constraints (if any) in the design under the
Existing Create Clock Constraints tab.
Figure 9-4: Creating a Constraint on the Object clk_pin_p
2-1-7. Click Next.

2-1-8. Click Next three times since there are no generated clocks, forwarded clocks, or external
feedback delays.
Note: You can click the question mark icon (?) in each page to get more information on
forwarded clocks, generated clocks, and external feedback delays respectively.
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You will now specify the input delay requirements on rst_pin, rxd_pin, and
lb_sel_pin with respect to the virtual clock by using the Set Input Delay command
in the Timing Constraints Wizard.
In the Input Delays dialog box of the Timing Constraints Wizard, notice that a
constraint on rxd_pin, rst_pin, and lb_sel_pin is recommended.
2-2. Specify 1.25 ns as the input delay value for maximum (setup) analysis on the
rxd_pin ports with respect to the virtual clock.
2-2-1. Select rxd_pin and on the right side under Delay Parameters so that you can find various
parameters to define the setup and hold requirements.
2-2-2. Enter 0.35 (ns) in the tco_max field.
2-2-3. Enter 0.9 (ns) and trce_dly_max field.
This specifies an input delay value of 1.25 ns (i.e., tco_max + trce_dly_max) on rxd_pin for
setup (maximum delay) analysis.
Note: The virtual clock, in this case VIRTUAL_clock_out2_clk_core, is used for I/O timing
and is automatically generated in the Input Delays window of the Timing Constraints
Wizard.
Figure 9-5: Specifying Input Delay Value on rxd_pin for Setup Analysis
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2-3. Specify a 1 ns input delay value for minimum (hold) analysis on the rxd_pin
port with respect to the virtual clock.
2-3-1. Enter 0.2 (ns) in the tco_min column.
2-3-2. Enter 0.8 (ns) in the trce_dly_min column.
Figure 9-6: Specifying Input Delay Value on rxd_pin for Hold Analysis
This specifies an input delay value of 1 ns (i.e., tco_min and trce_dly_min) on the rxd_pin
port for hold analysis.
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2-4. Specify the input delay values 1.25 ns and 1 ns for maximum (setup) and
minimum (hold) analysis respectively on the rst_pin and lb_sel_pin ports
with respect to the virtual clock.
2-4-1. Repeat the above steps for rst_pin and lb_sel_pin.
Note: The XDC command set_input_delay under the Tcl Command Preview tab can
also be run from the Tcl Console to create a set_input_delay constraint with a 1 ns
input delay value for hold analysis and 1.25 ns input delay value for setup analysis on the
rst_pin, rxd_pin, and lb_sel_pin ports.
2-4-2. Click Apply.
Figure 9-7: Tcl Command Preview of set_input_delay Command
2-4-3. Click Next.
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2-5. Specify the output delay value of 1.25 ns for setup and 0.5 ns for hold
analysis on the following with respect to the virtual clock by using the Set
Output Delay command in the Timing Constraints Wizard
o led_pins[*]
o spi_mosi_pin
o txd_pin
o dac_clr_n_pin
o dac_cs_n_pin
2-5-1. Uncheck the spi_clk_pin in the Output Delays dialog box of the Timing Constraints
Wizard.
downstream device.
2-5-2. Select the led_pins[*] in the Output Delays Dialog box.
2-5-3. Enter 0.9 ns in the trce_dly_max column.
2-5-4. Enter 0.35 ns in the tsu column.
This sets an output delay of 1.25 ns for setup analysis on led_pins[*].

2-5-5. Enter 0.8 ns in the trce_dly_min column.
2-5-6. Enter 0.3 ns in the thd column.
This sets an output delay of 0.5 ns for hold analysis on led_pins[*].
Figure 9-8: Specifying Output Delay on led_pins
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2-5-7. Repeat the above steps for:

o txd_pin
o spi_mosi_pin
o dac_clr_n_pin
o dac_cs_n_pin
Note: The XDC command set_output_delay under the Tcl Command Preview tab
can also be run from the Tcl Console to create a set_output_delay constraint with a
1.25 ns (setup) and 0.5 ns (hold) output delay value.
2-5-8. Click Apply.
Figure 9-9: Tcl Command Preview of set_output_delay Command
2-5-9. Click Next.
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2-6. Write the timing constraints to the target XDC file.

All the timing commands that have been run are applied to the design that
is loaded in the memory. The applied constraints can be saved by writing
them to a Xilinx design constraints (XDC) file.
2-6-1. Click Next until you get to the Constraints Summary dialog box.
2-6-2. Verify the number of create_clock, set_input_delay, and set_output_delay
constraints applied.
2-6-3. Select the View Timing Constraints option.
Figure 9-10: Constraints Summary Dialog Box
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2-7. Verify that the timing constraints have been applied to the
wave_gen_timing.xdc file.
2-7-1. Observe the constraints applied in the Timing Constraints window that is opened.
2-7-2. Select the Sources > Hierarchy view.
Figure 9-11: Timing Constraints Written to the wave_gen_timing.xdc File
You should see that the timing constraints were saved to the XDC file.
2-7-6. Close the Timing Constraints window.
Jump to Step 4 - Verifying Constraints Coverage and Implementing the Design.
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7 Series Users Only: Entering Timing Constraints Step 3

In this step, you will define the clock object and specify the input and output
delays for the design.
3-1. Define the primary clock constraint with a specified period.

Notice that a constraint on the clk_pin_p object is recommended in the Primary Clocks
dialog box of the Timing Constraints Wizard.
3-1-1. Enter 200 in the Frequency (MHz) column.
3-1-2. Observe that the Frequency, Rise At, and Fall At values are automatically generated
based on Period.
Note: The create_clock XDC command is also displayed under the Tcl Command
Preview tab.
You can also view existing create clock constraints (if any) in the design under the
Existing Create Clock Constraints tab.
Figure 9-12: Creating a Constraint on the Object clk_pin_p
3-1-3. Click Next.

3-1-4. Click Next three times since there are no generated clocks, forwarded clocks, or external
feedback delays.
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You will now specify the input delay requirements on rst_pin, rxd_pin, and
lb_sel_pin with respect to clk_pin_p by using the Set Input Delay command in the
Timing Constraints Wizard.
In the Input Delays dialog box of the Timing Constraints Wizard, notice that a
constraint on rxd_pin, rst_pin, and lb_sel_pin is recommended.
3-2. Specify 1.25 ns as the input delay value for maximum (setup) analysis on the
rxd_pin port with respect to clk_pin_p.
3-2-1. Select rxd_pin on left side and on the right side under Delay Parameters, you can find
various parameters to define the setup and hold requirements.
3-2-2. Enter 0.35 (ns) in the tco_max field.
3-2-3. Enter 0.9 (ns) and trce_dly_max field.
This specifies an input delay value of 1.25 ns (i.e., tco_max and trce_dly_max) on rxd_pin
for setup analysis.
Figure 9-13: Specifying Input Delay Value on rxd_pin for Setup Analysis
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3-3. Specify 1 ns as input delay value for minimum (hold) analysis on the rxd_pin
port with respect to clk_pin_p.
3-3-1. Enter 0.2 (ns) in the tco_min column.
3-3-2. Enter 0.8 (ns) in the trce_dly_min column.
Figure 9-14: Specifying Input Delay Value on rxd_pin for Hold Time Analysis
This specifies an input delay of 1 ns (i.e., tco_min and trce_dly_min) on the rxd_pin port
for hold analysis.
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3-4. Specify the input delay values 1.25 ns and 1 ns for maximum (setup) and
minimum (hold) analysis on the rst_pin and lb_sel_pin ports with respect to
clk_pin_p.
3-4-1. Repeat the above steps for rst_pin and lb_sel_pin.
Note: The XDC command set_input_delay under the Tcl Command Preview tab can
also be run from the Tcl Console to create a set_input_delay constraint with a 1 ns
input delay for hold analysis and 1.25 ns input delay for setup analysis on the rst_pin,
rxd_pin, and lb_sel_pin ports.
3-4-2. Click Apply.
Figure 9-15: Tcl Command Preview of set_input_delay Command
3-4-3. Click Next.
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3-5. Specify the output delay of 1.25 ns on the following with respect to
clk_pin_p by using the Set Output Delay command in the Timing Constraints
Wizard:
 led_pins[*]
 spi_mosi_pin
 txd_pin
 dac_clr_n_pin
 dac_cs_n_pin
3-5-1. Uncheck the spi_clk_pin in the Output Delays dialog box of the Timing Constraints
Wizard.
downstream device.
3-5-2. Select led_pins[*] in the Output Delays dialog box.
3-5-3. Enter 0.9 ns in the trce_dly_max column.
3-5-4. Enter 0.35 ns in the tsu column.
This sets an output delay of 1.25 ns for setup analysis on led_pins[*].

3-5-5. Enter 0.8 ns in the trce_dly_min column.
3-5-6. Enter 0.3 ns in the thd column.
This sets an output delay of 0.5 ns on led_pins[*].
Figure 9-16: Specifying Output Delay on led_pins
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3-5-7. Repeat the above steps for:

o txd_pin
o spi_mosi_pin
o dac_clr_n_pin
o dac_cs_n_pin
Note: The XDC command set_output_delay under the Tcl Command Preview tab
can also be run from the Tcl Console to create a set_output_delay constraint with a
1.25 ns (setup) and 0.5 ns (hold) output delay value.
3-5-8. Click Apply.
Figure 9-17: Tcl Command Preview of set_output_delay Command
3-5-9. Click Next.
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3-6. Write the timing constraints to the target XDC file.

All the timing commands that have been run are applied to the design that
is loaded in the memory. The applied constraints can be saved by writing
them to a Xilinx design constraints (XDC) file.
3-6-1. Click Next until you get to the Constraints Summary dialog box.
3-6-2. Verify the number of create_clock, set_input_delay, and set_output_delay
constraints applied.
3-6-3. Select the View Timing Constraints options.
Figure 9-18: Constraints Summary Dialog Box
3-7. Verify that the timing constraints have been applied to the
wave_gen_timing.xdc file.
3-7-1. Observe the constraints applied in the Timing Constraints window that is opened.
3-7-2. Select the Sources > Hierarchy view.
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Figure 9-19: Timing Constraints Written to the wave_gen_timing.xdc File
You should see that the timing constraints were saved to the XDC file.
3-7-6. Close the Timing Constraints window.
Verifying Constraints Coverage and Implementing the Design Step 4

In this step, you will generate the Timing Summary report to verify the constraints
coverage and then implement the design.
4-1. Generate a Timing Summary report.

If you do not recall how to perform this task, refer to the "Generating a Timing
Summary Report" section under Vivado Design Suite Operations in the Lab
Reference Guide.
4-1-1. Expand the Check Timing section of the Timing Summary report.
4-1-2. Click no_output_delay under Check Timing.
This section shows that spi_clk_pin is the port with no output delay. All other ports are
constrained.
spi_clk_pin is a source-synchronous pin that goes to the clk pin of any sequential element
in the downstream device. Hence it is not constrained with set_output_delay.
4-1-3. Close the Timing Summary report.
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If you do not recall how to perform this task, refer to the "Closing the Synthesized
Design" section under Vivado Design Suite Operations in the Lab Reference
Guide.
4-3. Run implementation.

Refer to the "Running Implementation" section under Vivado Design Suite
Operations chapter in the Lab Reference Guide if you do not recall how to
perform this task.

If you do not recall how to perform this task, refer to the "Opening the
Implemented Design" section under Vivado Design Suite Operations in the Lab
Reference Guide.
4-5. Review the Timing Summary report that is automatically generated.

Note: If there are failing timing paths, they will be indicated in red.
Question 2
Are these timing errors expected?
Question 3
If timing was not met after the timing constraints were applied, what could be done?
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Question 4
Are the worst paths the same in the estimated timing report and implemented timing reports? If
not, why?
Question 5
What information can you obtain from the timing report?
4-5-1. Close the Timing Summary report.

If you do not recall how to perform this task, refer to the "Closing the
Implemented Design" section under Vivado Design Suite Operations in the Lab
Reference Guide.
4-7. Close the Vivado Design Suite project.

Reference Guide.

Design Suite" section under the Vivado Design Suite Operations in the Lab
Reference Guide.
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Summary
In this lab, you used the Timing Constraints Wizard in the Vivado Design Suite to enter
create_clock, set_input_delay, and set_output_delay constraints. You also reviewed
the estimated and final timing reports.
Timing constraints are the best way to communicate your performance expectations to the
implementation tools. However, do not forget about pin placement. Good placement can make
it easier for the tools to meet timing.
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Lab Workbook Lab 10: Xilinx Power Estimator Spreadsheet
Lab 10: Xilinx Power Estimator Spreadsheet

2018.1
Abstract
This lab introduces the Xilinx Power Estimator (XPE) spreadsheet, which is power estimation tool
typically used in the pre-design and pre-implementation phases of the project.
Objectives
 Estimate the resources required for a design, based on the high-level design description
 Enter the amount of resources required for the design into the XPE
 Enter the default activity rates for the components used
 Evaluate the estimated power calculated by the XPE
Introduction
The Xilinx Power Estimator (XPE) assists with architecture evaluation, device selection,
appropriate power supply components, and thermal management components specific to your
application.
The XPE considers your design resource usage, toggle rates, I/O loading, and many other factors
which it combines with the device models to calculate the estimated power distribution. The
device models are extracted from measurements, simulation, and/or extrapolation.
The accuracy of the XPE is dependent on two primary sets of inputs:
 Device utilization, component configuration, clock, enable, and toggle rates, and other
information you enter into the tool
 Device data models integrated into the tool
For accurate estimates of your application, enter realistic information that is as complete as
possible. Modeling a certain aspect of the design conservatively or without sufficient knowledge
of the design can result in unrealistic estimates.
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Lab 10: Xilinx Power Estimator Spreadsheet Lab Workbook
The design used in this lab will communicate with the UCD9248 power supply controller chip
(which monitors and controls the voltage rails) available on the KC705 board.
Figure 10-1: Block Diagram of the kc705_power_test Module
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The design also has power consuming modules instantiated 128 times and a UART module that
sends/receive commands with the host PC at a 115200 baud rate.
Figure 10-2: Power Consuming Module
clk_gen module: This modules generates two clocks: 100 MHz and 50 MHz. The input clock to
this module is from the clk200_p and clk200_n differential clock pair on the KC705 board. The
differential clock inputs are supplied to the MMCM, which generates clk100 and clk50 using the
MMCM. The clk100 is used by the Power Consuming Module (PCM) while the remaining
modules in design are driven by clk50.
uart_control module: This module consists of UART_RX, UART_TX, and the PicoBlaze processor.
UART_RX is used to receive the command from the host. UART_TX will send the information
corresponding to the host command decoded by the processor.
Power Consuming Module (power_sink): This module consists of a pseudo-random number
generator, 16-bit accumulator, 16-bit toggle shift register and another PicoBlaze processor. The
program executed by the PicoBlaze processor (KCPSM6) can therefore be written to emphasize
the use of certain features at different times either to adjust power consumption in general or to
evaluate the relative power consumption of different resources.
power_test_control module: The PicoBlaze processor (KCPSM6) implements a PMBus protocol
to communicate with the UCD9248 power supply controller (Texas Instruments) on the KC705
board. This will be used to read the die temperature, power consumed by the device, and supply
voltages.
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General Flow
Opening Estimating Entering Evaluating
the XPE Required Each the Power
Spreadsheet Resources Resource Estimates
Opening the XPE Spreadsheet Step 1
1-1. Open the spreadsheet targeted for the Kintex-7 device and make sure that
your Microsoft Excel settings allow macro extensions.
1-1-1. Open the 7_Series_XPE_2018_1.xls XPE spreadsheet located in the C:\training\
XPE\lab\KC705 directory.
The latest updated spreadsheets for various FPGAs will be available at
www.xilinx.com/products/technology/power/xpe.html.
In Excel, the macro security level is set to High by default, which disables macros.
1-1-2. Change the macro security level if needed:
Microsoft Excel 2003 users:

o Select Tools > Macro > Security.
o Select the Security Level tab in the Security dialog box.
o Select Medium and then click OK.
o Re-open the XPE spreadsheet.
o Click Enable Macros when prompted whether to enable or disable macros.
Microsoft Excel 2007 users:
o Click Options from the Security Warning.
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o Select Enable this content and then click OK.
Figure 10-3: Enabling the Macro Settings in Excel
Microsoft Excel 2010 or 2013 users:

o Select File > Options > Trust Center > Trust Center Settings.
o Select the Macro Settings category. Under Macro Settings, select Enable all macros
and click OK.
o Click OK.
1-1-3. Review all the available worksheets in the Xilinx Power Estimator (XPE) spreadsheet.
o Summary
o Snapshot
o Graphs
o IP_Manager
o Clock
o Logic
o IO
o BRAM
o DSP
o CLKMGR
o GTX
o Other
o User
o Release
Question 1
What information is provided in the Clock, Logic, IO, BRAM, DSP, CLKMGR, and GTX worksheets?
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Estimating the Resources Required from the High-Level Design Step 2

Power estimation for programmable devices like FPGAs is a complex process,
since it is highly dependent on the amount of logic in the design and the
configuration of that logic. To supply the minimum input that will allow XPE to
estimate power with reasonable accuracy, you need the following:
o A target device-package-grade combination
o A good estimate of resources you expect to use in the design (for example,
flip-flops, look-up tables, I/Os, block RAMs, MMCMs, and PLLs)
o A clock frequency or frequencies for the design
o An estimate of the data toggle rates for the design
o The external memory and transceiver-based interfaces with their data rates for
the design
o The thermal environment in which the design will be operating
As a general rule, input as much information about your design as available, then
leave the remaining settings to default values. This strategy will allow you to
determine the device power supply and heat dissipation requirements.
Based on the lab design description, you will be estimating the resources
required for this design.
2-1. Configure the Device and Environment settings.

2-1-1. Enter early_stage_estimate as the Project in the Summary worksheet.
2-1-2. Note down the default On-Chip Power and Junction Temperature in the Summary
section.
2-1-3. Update the device and environment settings in the Summary worksheet with the
following values:
o Device
 Family: Kintex-7
 Device: XC7K325T
 Package: FFG900
 Temp Grade: Commercial
 Speed Grade: -2
 Process: Typical
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o Environment
 Ambient Temp: 30° C
 Airflow: 250 LFM
 Heat Sink: Medium Profile
 # of Board Layers: 16 or more
Figure 10-4: Device and Environment Settings for the Board
Note: FPGA quiescent power is highly affected by environment settings, so it is

important to match your board’s environment with the board data as precisely as
possible. The Xilinx power tools can be very useful to perform the analysis and define the
best thermal strategy for the board.
2-2. Configure the implementation setting.

2-2-1. Set the implementation setting to Power Optimization.
The power optimization option in the Implementation setting minimizes the core
dynamic power.
2-2-2. Save the file.
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Question 2
Based on the Device characterization under settings (Production, Advance, and Preliminary),
what are your expectations about the quality of power estimation?
2-3. Estimate the resources required for this design.

Estimates in the early stages of design may change because the specifications
and algorithms may change frequently. Generally, prior knowledge about device
architecture, design modules, and IPs used in the design is helpful when
estimating the resources.
From the block diagram of the Power Consuming Module, you may observe that
the PCM is composed of one PicoBlaze processor and flip-flops. To obtain the
resource estimation for PicoBlaze processor, you can refer to the PicoBlaze user
guide available at www.xilinx.com/picoblaze.
PicoBlaze processor: 26 slices (104 LUTs and 82 FFs)
LFSR/Toggle FFs/ACC: 48 FFs
Processor memory: 16 distributed RAM and 16 FFs
Approximate additional/glue logic (control signals to handles LFSR/Toggle
FFs/ACC, reading/writing data of processor): 140 LUTs, 80 FFs
Total number of resources for one PCM: 274 FFs, 244 LUTs, and 16 distributed
RAMs
In this design, the total number of resources for 128 PCMs (approximately) is
35072 FFs, 31232 LUTs (includes LUTs and distributed ROM), and 2048 distributed
RAMs
In addition to PCMs, the design has uart_control and power_test_control
modules, which use approximately 1000 FFs, 1000 LUTs, and 64 distributed RAMs.
Note: The device usage is around 90% LUTs and 40% FFs, so this example is a
realistic scenario of power consumption for CLB logic. However, clocking
resources, block RAM, and DSP slice resources are at a minimum.
2-3-1. Select the Logic worksheet tab.
2-3-2. Enter 100 MHz in E12 and 50 MHz in E13.
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2-3-3. Enter the calculated data as shown in the figure below.
Figure 10-5: Entering Estimated Logic Resources

2-3-5. Switch to Summary worksheet and review the increase in On-chip Power and Junction
Temperature after adding the resources.
Figure 10-6: Summary Section After Adding Resources
Entering the Amount of Each Resource Step 3

Enter the number of resources required, such as clock, block RAM, and MMCM.
For an accurate XPE estimation, you will have to estimate the amount of device
resources that your design will use. Providing accurate toggle rates in the various
XPE sheets is essential to obtain quality power estimates. This information,
however, might not be readily available at the stage in the design cycle where
you enter data in XPE. Activity might be refined as the design gets more defined.
The following guidelines can help you enter design toggle activity:
o For synchronous paths, the toggle rate reflects how often an output changes
relative to a given clock input and can be modeled as a percentage between
0–100%. The max data toggle rate of 100% means that the output toggles
every active clock edge. When data changes twice per clock cycle, enter 200%
for the toggle rate.
 For example, consider a free running binary counter with a 100-MHz clock.
For the least significant bit you would enter 100% in the Toggle Rate
column because this bit toggles every rising edge of the clock. For the
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second bit you would enter 50% because this bit toggles every other rising
edge of the clock.
o For non-periodic or event-driven portions of designs, toggle rates cannot be
easily predicted. An effective method of estimating average toggle rates for a
given design is to segregate the different sections of the design based on
their functionality or hierarchy and estimate the toggle rates for each of the
sub-blocks. An average toggle rate can then be arrived at by calculating the
average for the entire design or hierarchy. Most logic-intensive designs work
at around 12.5% average toggle rate, which is the default toggle rate setting
in XPE.
o It has been observed that designs with random data patterns as input
generally have toggle rates between 10%–30%. However, designs with a lot of
glitch logic can have toggle rates as high as or even higher than 50%. Glitch
logic is generally classified as combinatorial functions which have a high
probability of the output changing when any one input changes, such as XOR
gates or unregistered arithmetic logic (i.e., adders). Functions that use large
amounts of such logic, such as error detection/correction circuitry, might
exhibit higher toggle rates due to this. Designs with large amounts of control
path logic, such as embedded designs, on average have lower toggle rates
due to large sections of logic being inactive at any given time during
operation.
3-1. Enter the activity rates and clock frequency.

3-1-1. Select the Summary worksheet and click the Set Default Rates button.
Figure 10-7: Set Default Rates Button
The details entered here are the default values for the LOGIC, I/O, BRAM, DSP, and other
worksheets.
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3-1-2. Set the Toggle rate to 20% in the Logic field (for worst-case analysis). Set the rate to 100
MHz in the All Clock Nets field.
3-1-3. Enter the default toggle rates for others as shown in the figure below and click OK.
Figure 10-8: Setting the Toggle Rates and Clock Frequency
3-1-4. Review the Logic page after changing these parameters and verify that the toggle rate
has changed from 12.5% to 20%. Update the clock in the E13 cell to 50 Mhz.
3-1-5. Record the changes in On-Chip Power and Junction Temperature in the Summary
worksheet.
The Total On-Chip Power has been increased to 0.426W from 0.332W
3-1-6. Alter the toggle rate value to see the impact on power consumption.
Note: Typically, logic-intensive designs work at around 12.5% of the synchronizing clock
(12.5% is the default value used in XPE). For a worst-case estimate, a toggle rate of 20%
can be used. Average toggle rates greater than 20% are not very common. Arithmetic-
intensive modules of a design seem to take toggle rates of up to 50%, which is
representative of the absolute worst case. An example of this would be a multiply-
accumulate operation. It is also common to model toggle rate for random input data at
50%. To appreciate what 100% toggle rate means, think of a constantly enabled toggle
flip-flop (TFF) whose data input is tied High. The T-output of this flip-flop toggles every
clock edge. Very few designs could have an average rate that high (100%).
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3-2. Enter the clock information.

3-2-1. Select the Clock sheet.
3-2-2. Enter clk100 in the B10 cell (Name column) and enter the corresponding frequency and
fanout in the respective cells.
3-2-3. Enter clk50 in the B11 cell (Name column) and enter the corresponding frequency and
fanout in the respective cells as shown below.
Figure 10-9: Entering Clock Information
3-2-4. Review the Total On-Chip Power and Junction Temperature in the Summary worksheet
after adding clock information.
Figure 10-10: Summary Section After Adding Clock Information
3-3. Enter the input, output, and bidirectional pin details.
Signal Name Direction Size I/O Standard
clk200_p Input 1 LVDS_18
clk200_n Input 1 LVDS_18
cpu_rst Input 1 LVCMOS18
led Output 7:0 LVCMOS18
lcd_rs Output 1 LVCMOS18
lcd_rw Output 1 LVCMOS18
lcd_e Output 1 LVCMOS18
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Signal Name Direction Size I/O Standard
lcd_d Inout 7:4 LVCMOS18
uart_tx Output 1 LVCMOS25
uart_rx Input 1 LVCMOS25
pmbus_clk Inout 1 LVCMOS18
pmbus_data Inout 1 LVCMOS18
pmbus_control Output 1 LVCMOS18
pmbus_alert Input 1 LVCMOS18
fan_tach In 1 LVCMOS25
fan_pwm Out 1 LVCMOS25
Top-Level Input/Output Signals
The table does not include all the information like I/O Bank, I/O Settings, and
Clock Frequency. Fill the data in spreadsheet as shown in the figure below.
3-3-1. Select the IO worksheet.
3-3-2. Enter the number of input pins, output pins, and I/O standards from the Top-Level
Input/Output ports table.
3-3-3. Enter the clock as 200 MHz for clk200.
The top-level input/output ports are shown in the following figure.
Figure 10-11: Entering LVDS Pair Clock Frequency
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The On-Chip power and Junction Temperature increases again by applying the I/O Pin
details.
Figure 10-12: Summary Section After Adding I/O Pin Details
3-4. Provide the block RAM usage.

3-4-1. Select the BRAM worksheet.
3-4-2. Enter 1 in the Block RAMs column, select RAMB36 from the Mode column, and 18 from
the Bit Width column.
3-4-3. Select WRITE_FIRST from the drop-down list of Write Mode column as shown below
for both Port A and Port B.
Figure 10-13: Entering Block RAM Information
Note: Since there are no DSP resources in the design, skip the DSP sheet.
3-5. Provide the MMCM usage and parameter information.

3-5-1. Select the CLKMGR worksheet.
3-5-2. Enter the information as shown in the following figure.
Figure 10-14: Entering MMCM Information
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3-6. Review the IP Manager worksheet.

3-6-1. Select the IP_Manager worksheet.
3-6-2. Click the Manage_IP button and go through the Create IP tabs.
There is no need to add any IPs now. Just review the worksheet to create IP and close the
XPE IP Manager tab.
Evaluating the Power Estimates Step 4
4-1. Review the estimated power calculated by the tool.

4-1-1. Select the Summary sheet.
4-1-2. Review the On-Chip Power, Power Supply, and Summary sections.
Figure 10-15: Summary of XPE Power Estimation
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Question 3
Enter the data in the following tables:
Summary XPE
Junction Temperature (C)
Effective JA (C/W)
Total On-Chip Power (W)
Summary of XPE
On-Chip Power (W) XPE
CLOCK
LOGIC
BRAM
DSP
MMCM
IO
Device Static
On-Chip Power of XPE
You should note that the logic (CLB) resources use the highest percentage of total
power. Remember that their power consumption can be altered by redesigning so that
more resources map to dedicated hardware (which uses less power) instead of logic.
You should also remember that this example provides only a rough estimate. The
estimation improves with every step, as shown below.
o As the actual system is built and the amount of logic resources is actually known, the
power estimate will get more accurate.
o Likewise, after the design has been routed, the power estimate will be more accurate.
o Finally, after implementation has been done and simulation data has been loaded (to
estimate dynamic power consumption with an SAIF file) the power estimate will be
the best.
222 www.xilinx.com
You should also be able to verify (from the Summary) that dynamic power consumes a
lot more power than static power. So if the clock frequencies used were slower, power
consumption would decrease.
Power Supply XPE

Total Current (A)
Vccint
Vccbram
Vccaux
Vcco2.5v
Vcco1.8v
Vccadc
Power Supply of XPE
4-1-3. Select the Graphs worksheet.

4-1-4. Review the graphs.
Figure 10-16: Graphical Summary of Estimated Power
4-2. Set up a power comparison using the Snapshots sheet.

4-2-1. Select the Snapshot worksheet.
4-2-2. Click the Snapshot button.
4-2-3. Change Snapshot_1 to Typical in cell C3.
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4-2-5. Select the Summary worksheet.

4-2-6. Change the Process to Maximum in the Settings section.
4-2-7. Select the Snapshot worksheet and click the Snapshot button.
4-2-8. Change Snapshot_2 to Maximum in cell E3.
Figure 10-17: Viewing the Snapshot Worksheet
This helps with more easily comparing the different configuration results.
224 www.xilinx.com
Question 4
The project manager decides to add additional logic and make other changes to the design.
How will you make the changes outlined below? Determine if there is sufficient thermal margin.
 The design needs to be estimated as more DSP-like and the effective clock rates have to
double.
 More block RAMs will be needed (30) and they will be clocked at 200 MHz.
 DSP slice resources will need to be added as well (40) and they will be clocked at 200 MHz.
 Increase the Logic and Registers to 150000 and fanout to 160000 for the clock with 200MHz.
 If all options are assumed to run in the worst-case scenario (except the ambient temperature
can be 50 degrees Celsius).
Question 5
Modify the environment (heat sink use and airflow) so that the FPGA can operate as the project
manager needs.
Summary
You entered the estimated resources for the design by using the outline of the design in the
Xilinx Power Estimator (XPE) spreadsheet and reviewed the estimated power of the design.
www.xilinx.com 225
Lab Workbook Lab 11: Introduction to Tcl
Lab 11: Introduction to Tcl

2018.1
Abstract
In this lab, you will learn some basic ways of interfacing with the operating system so that you
can perform file and directory management, and you will explore a number of commonly used
Tcl commands.
Objectives
After exercising this lab, you will be able to:
 Maneuver through a file system
 Use three very commonly accessed Tcl commands: puts, set, and source
 Create variables using set
 Use the created variables
Introduction
Tcl interfaces natively with the C language due to the way it was originally written. However, the
Tcl shell enables common operating system (OS) commands (like cd, pwd, dir, etc.) to be
handled successfully.
If the Tcl interpreter is unable to handle an OS command, it will pass the command to the OS
shell for execution. On such occasions, a warning message will be issued, indicating that the
command is an unknown Tcl command and that it has been sent to the OS shell for execution.
The common OS commands are essential for file and directory management and for interfacing
with other languages.
General Flow
Accessing Working Intro to
the with the Tcl Program-
Tcl Shell OS ming
www.xilinx.com 227
Lab 11: Introduction to Tcl Lab Workbook
Accessing the Vivado IDE Tcl Shell Step 1
1-1. Launch the Vivado Design Suite Tcl shell.

Vivado 2018.1 Tcl Shell.
Figure 11-1: Vivado Design Suite Tcl Shell
OR
For Windows 10: Select Start > Xilinx Design Tools > Vivado 2018.1 Tcl Shell.
This opens the Tcl interactive shell.
Figure 11-2: Vivado Tcl Interactive Shell
228 www.xilinx.com
Working with the Operating System Step 2

Tcl interfaces with the operating system in a consistent fashion so that it is
transparent to you whether you are working on a Windows or Linux system.
Here are the commands that you will be using:
Operating System-Related Tcl Commands
Command What it Does
cd <path> Changes directory to the specified path. The path may

include the drive, such as cd e:
cls Clears the Tcl Console
dir [<path>] Lists the files and directories under <path>. Note that
backslashes are used with this command, which is a Tcl
keyword; therefore, when specifying a path you must
use two backslashes. Example:
dir\\training\\Tcl_Intro\\lab
pwd Prints the working directory; displays the full path of the
current location in the file system hierarchy of the OS
file <command> [<options>] Performs a number of basic file manipulation

commands, such as copying, making/removing
directories, etc.
See www.tcl.tk/man/tcl8.6/TclCmd/file.htm
exit Closes the Tcl shell
2-1. Clear the Tcl window of all of the startup messages.

2-1-1. Enter cls in the Vivado® Design Suite Tcl shell.
www.xilinx.com 229
The Tcl shell clears all content on the screen.
Figure 11-3: Clear Interactive Shell Screen
2-2. Determine the current directory when the Tcl shell opens.
2-2-1. Enter pwd (1).
2-3. The working files for this lab are located in C:\training\Tcl_Intro\lab. Move
to this directory so that you are not required to enter the full path for every
file access.
2-3-1. Enter cd c:/training/Tcl_Intro/lab (2).
2-3-2. Enter pwd again, or press the Up Arrow key twice (2).
The Up Arrow key enables you to re-execute previous commands.

Confirm that you are at pwd command.
2-3-3. Enter dir (4).
View the files in this directory.

Note: Since dir is an OS command but not a native Tcl command, you will see a
warning message indicating that the command has been sent to the OS shell for
execution.
230 www.xilinx.com
2-4. Create a new directory to work from for this lab named Intro_Tcl.
2-4-1. Enter file mkdir Intro_Tcl (5).
2-4-2. Enter dir to confirm that the Intro_Tcl directory was created (6).
Ensure that Intro_Tcl directory is present.

Here is what things should look like at this point.
Figure 11-4: Step 2 Operations
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Introduction to Tcl Programming Step 3

Here, you will be setting variables and writing commands in a Tcl Shell to figure
out how long it takes a separate Tcl script to run (a simple for loop counter from
1 to 10). This will help you realize how to utilize the Tcl Shell and a Tcl script. You
will then evaluate a Tcl script which has all the commands you entered into the
Tcl Shell.
The following is the flowchart for the program that you will be writing.
Figure 11-5: Flowchart for the timer.tcl Script
232 www.xilinx.com
3-1. The first step is to provide the name and location of the count_to_10.tcl
script.
3-1-1. Clear the window with the cls command in the Tcl shell.
3-1-2. Display a message to the user asking for the name of the Tcl function to time.
Enter puts "Enter script to time: " (1).

puts is a function that places a string on the stdout device, usually the monitor. This is
very useful for debugging especially when determining the values of various variables.
Here it immediately echoed the string back to the console. This is not of much use right
now, but in a few moments you will see the value in this.
3-1-3. When the user enters the name of the Tcl script, assign it to a variable so it can be used
later.
Here stdin refers to the keyboard, whereas stdout refers to the monitor (typically).
Enter set tcl_script_name [gets stdin] (2).
At this point, the Tcl environment is waiting for you to enter a Tcl script name.
3-1-4. Open and observe the file count_to_10.tcl located at C:\training\Tcl_Intro\support using
your preferred text editor.
Observe how a simple for loop is executed 10 times to serve as a counter to count up to
10.
3-1-5. Enter c:/training/Tcl_Intro/support/count_to_10.tcl in the Tcl shell.
3-2. Get the current system time (before the script is run) and save it for later.
3-2-1. Enter set TIME_start [clock milliseconds] (3).
The square brackets ([ and ]) wrap a standalone instruction so that it is executed or

evaluated first, then assigned to the variable TIME_start. clock milliseconds
returns a high-resolution time value as a system-dependent integer value. The unit of the
value is system-dependent such as a CPU cycle counter.
3-3. Run the script.

3-3-1. Enter source $tcl_script_name (4).
Note that count_to_10.tcl is executed and that its output is visible on the console.
The source command is useful for running existing scripts.
3-4. Get the current system time (after the script is run) and save it for later.
3-4-1. Enter set TIME_end [clock milliseconds] (5).
Note that first the clock command is executed, then the result is assigned to TIME_end.
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3-5. Compute the amount of time elapsed and inform the user.
3-5-1. Enter set TIME_taken [expr $TIME_end - $TIME_start] (6).
3-5-2. Enter puts "Script $tcl_script_name took $TIME_taken milliseconds
to run" (7).
Question 1
Is this amount of time reasonable for a Tcl script to count to 10? Why or why not?
Question 2
How can we make the measurement of time for the script to run more accurate?
3-6. These commands have been collected for you in a script file so that there is
no typing delay time when running the script. Run the timer.tcl script file.
3-6-1. Open and observe the timer.tcl file located at C:\training\Tcl_Intro\support using your
preferred text editor.
Observe how the commands above have been included in a file to eliminate delays
caused by user interaction.
3-6-2. Enter source c:/training/Tcl_Intro/support/timer.tcl (8).
3-6-3. Enter c:/training/Tcl_Intro/support/count_to_10.tcl when the script asks
for a Tcl script to time.
Note the output from count_to_10.tcl as well as the displayed comments (lines beginning
with '#').
Question 3
Is the amount of time reasonable for a Tcl script to count to 10? Why or why not?
234 www.xilinx.com
Question 4
If you were looking to count to 10 as fast as possible, is Tcl a good choice? Why or why not?
Here is what things should look like so far.
Figure 11-6: Step 3 Operations
Note: Your timing values may vary slightly, but they should be in the range of 10-100
ms.
3-7. Close the Vivado Tcl shell.

3-7-1. Enter exit in the Tcl Command console.
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Summary
You have just completed two important steps in the process of becoming familiar with Tcl and
the Vivado Design Suite Tcl shell: talking to the operating system (for file and directory
management), and seeing how the puts, set, and source commands can be used. While far
from the only list, or even the most important, these capabilities are used frequently for both
debugging and increasing productivity.
236 www.xilinx.com

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Designing FPGAs Using the Vivado Design Suite 1

Lab 1: Vivado Design Suite Project-Based Flow ....................................... 3

Lab 2: Vivado Synthesis and Implementation ........................................ 35

Lab 3: Basic Design Analysis in the Vivado IDE ...................................... 61

Lab 4: Vivado Design Rule Checks ........................................................... 79

Lab 5: Vivado Design Suite I/O Pin Planning........................................ 101

Lab 6: Vivado IP Flow .............................................................................. 119

Lab 7: Introduction to Clock Constraints .............................................. 129

Lab 8: I/O Constraints and Virtual Clocks ............................................. 155

Lab 9: Timing Constraints Wizard .......................................................... 181

Lab 10: Xilinx Power Estimator Spreadsheet .......................................... 207

Lab 11: Introduction to Tcl ....................................................................... 227

Lab 1: Vivado Design Suite Project-Based Flow

A typical FPGA design flow is as follows:

1. Create a new project 10. Run DRC checker

Creating a New Project Step 1

1-1. Launch the Vivado Design Suite.

Double-click the Vivado Design Suite shortcut icon ( ) on the desktop.

Figure 1-2: Vivado Design Suite Welcome Screen

1-2. Create a new Vivado Design Suite project.

Figure 1-3: Creating a New Vivado Design Suite Project

This will launch the New Project Wizard.

Figure 1-4: Entering the Project Name and Location

Figure 1-5: Setting the Project Type to RTL

1-4. Add existing RTL source files.

Figure 1-6: Adding Sources to the Project

Figure 1-7: Adding Source Files

1-4-4. Verilog users: Select or multi-select led_ctl.v, meta_harden.v, uart_baud_gen.v,

Figure 1-8: Setting Options in the Add Sources Window

The Add Constraint Files dialog box opens.

Figure 1-9: Adding Constraints

1-6-4. Select uart_led.xdc.

1-6-7. Click Next to advance to selecting a target device (3).

Figure 1-10: Selecting the Board for the Project

1-7-4. Click Next to advance to the summary (3).

Adding Simulation Source Files to the Project Step 2

2-1. Add simulation files to the design.

Figure 1-11: Selecting Add Sources

2-1-2. Select Add or create simulation sources.

Figure 1-12: Add Sources Dialog Box

2-1-3. Click Next.

Figure 1-13: Associating VHDL Package Files to Their Corresponding Libraries

2-1-10. Click Finish to add the simulation files to the project.

Figure 1-14: VHDL Package Files in the Libraries

Exploring the Vivado IDE Step 3

3-1. Explore the various views of the Vivado IDE.

Figure 1-15: Vivado IDE Default Layout- KCU105

3-2. Explore the horizontal toolbar.

Figure 1-16: Horizontal Toolbar

Figure 1-17: Project Summary View - KCU105

3-5. Explore the Settings dialog box for the design.

Figure 1-18: Settings Dialog Box - General

3-6. Select the Simulation tab in the Settings dialog box.

Figure 1-19: Settings – Simulation

3-7. Select the Synthesis tab in the Settings dialog box.

Figure 1-20: Settings – Synthesis

3-8. Select the Implementation tab in the Settings dialog box.

Figure 1-21: Settings – Implementation

3-9. Close the Settings dialog box.

3-11. Create a synthesis run with the Flow_ RuntimeOptimized strategy.

Figure 1-22: Creating a New Synthesis Run

The Create New Runs Wizard opens.

Simulating the Design Step 4