SUNESH N.

V
#57, 8th cross, Maruthi Nagar, Madiwala, Bangalore-68
Contact: 08792664878; Email: nvsunesh@gmail.com; Date of Birth: 30/09/1986

VLSI DESIGN ENGINEER

Seeking a good opportunity in chip design in the areas of ASIC, FPGA design and Custom layout design with an organization which
recognizes and utilizes my technical skills.

PROFILE
 M.Tech (VLSI DESIGN) from Amrita school of Engineering affiliated to Amrita Vishwa Vidyapeetham University; Cultured in
a time bound and target oriented atmosphere, perfectly capable to coordinate with the organization and thrive to utilize my
legerdemain skills and knowledge for the amplification and augmentation of the firm.
 Knowledge in Digital design, Verilog, System verilog,Dft,Testing.

Technical Skills
Design Tools:
 Cadence Encounter RTL Compiler tool
 Synopsys Design Compiler (90 nm)
 Xilinx
ISE design Suit
Worked on Spartan 3E, Spartan 6
 Mentor Graphics
Model Sim SE PLUS 6.5
Worked on Model Sim for RTL coding
 Verilog
Worked on Verilog as the part of the academic project
 System Verilog
 C
 C++

EDUCATIONAL CREDENTIAL

M.Tech VLSI Design 2012-2014

Amrita School of Engineering Bangalore, Amrita Vishwa Vidyapeetham University, CGPA 6.65/10

B.Tech Electronics & Communication 2008

Royal College of Engineering and Technology, Calicut University Kerala, 62%

HSC 2004
St.Thomas Higher Secondary School, Thope, Thrissur, State Board, 73%

SSLC 2002
NSS English Medium Higher Secondary School,Thrissur, State Board, 81.5%

EXPERIENCE
DUKESOFT SOFTWARE CONSULTANTS
Technical Support Executive (2 year 6 months)
 Attend customer calls
 Accounts correction
 Training

ACHIEVEMENTS
 Won in Analog Design contest conduct by Texas instrument at amrita school of Engineering, Bangalore 2014.
 Member of cricket and football team in college and school.
 Class Representative at M-Tech and B-Tech class.
 Coordinator of many technical and cultural events in college.

PROJECT UNDERTAKEN AS A PART OF ACADEMIC CURRICULUM

 Project: “Design and implementation of Fast Floating Point Multiplier Unit”, Fall 2014
Tools used:-Design Compiler,Xilinx,modelsim
Language:-verilog
Description: This project proposes architecture for multiplying floating point numbers faster by decreasing the delay. Multiplier unit
can make faster by placing faster adders.The floating point multipliers are widely used in DSP processors where speed are very
important.
 Project: “Comparison of various Adders and Multipliers using Synopsys tool”, Fall 2014
Tools used:-Design Compiler,Xilinx,modelsim
Language:-verilog
Description: This project has compared various adders and multipliers using synopsys design compiler tool.In this project fast
adders and multipliers had been found and compared there area ,delay and power with others also

 Project: “Secure Speed Limiter Using GPS”, Fall 2008

 Language:- Embedded C
This secure speed limiter using GPS is a device in which the speed of a vehicle is controlled on the basis of location. The
microcontroller 16F877A is the brain of the project. If our vehicle is in front of hospitals, schools then the speed should be reduced
to a particular limit [eg: 20 km/hr] set by the user. If in a normal place the maximum speed can be controlled to a particular value
[eg: 60 km/hr].This reduction of speed is done by this device. So this reduces the number of accidents occurring in our country
.
 Project : “Moving Message Display” , Fall 2010
 Embedded C
Description:This is mainly used to convey messages or information to a large crowd. This scrolling message display finds a wide
variety of applications in TV advertising, broadcasting, educational institutions etc. we are using a microcontroller 16F84A with a
led display. We are using 5*7 led matrix display. So there are 35 leds arranged to form a letter. We use seven such letters for reading
words clearly

References: Available on Request