Low Power- Upf

UPF
Provides the power-regions, power behavior & associated cells involved.
1. Power & Ground nets.
2. Power switches --> the ones which controls the on/off of a region, there would be multiple power
switches across the entire voltage area just like vias & the count depends on area & IR numbers.
Comes from APR, generally in Floorplan.
The syn stage requires the upf to pass, in case control & ack ports not defined in rtl, create_ports
in syn stage where the rtl is read in.
3. Various Power domains - switching domain, Always ON, different voltages levels, (diff voltages
come in through bumps)
4. Level shifters - connections & locations, needed for the signal/data lines. Comes from synthesis,
only when different voltages exists.
The Isolation Cells hence used the Level Shifters are needed in order to Clamp the output of
powered down voltage going to the

5. State tables- definition of each power domain, which is when ON/OFF

6. ISOLATION cells - Are needed for switching a signal from switching-power domain to a always on-
domain as the always ON domain needs to see some voltage from line to avoid going into
metastable state.
Have seen comes from syn, Where ??, added in APR was the earlier understanding.
This is a Gate type.

Iso cells are always used with level-shifters.

Difference between Retention flops & Isolation cells are that iso cells are of two types always 1 or
always 0 no other type, whereas retention flops should be based on the rtl logic.

 Tie cells are different, as gates are not connected directly with the Power - ground supply to
protect the gate from fluctuations, hence through tie-low or tie high cells which ideally should
have diodes or other protections.

1. Retention flops - Are such data holders which hold the data even when the power supply is off,
how is it Done ? The flop sits in power switching domain but has vcc from always ON domain.
Another important point is the retention flop Is for the logic sitting in the switching domain, as this
retains the logic.
This has to come from rtl as which ever signals are important needs to have this, based on the
design.
This is a Register.

7. There are other power buffer cells which are like always on needed for supporting any other
feedthrough signals passing through the power domain.

9. What is power clamp?

 Video Tutorials
http://videos.accellera.org/upflowpower/upf38msn6y9/index.html

Design type power consumption, decreasing order

CPU
Modem
GPU
Video
display

Addition to the netlist for upf runs

At Synthesis stage -->
iso cells, retention flops, level shifters

At floorplan stage-->
power switches

Power Domain:
Level shifters Not needed

Power switches --> yes, to control the on/off of the areas.

Retention flops --> Comes from the Rtl
Isolation cells --> Yes needed

CLP - Conformal Low power check

Syn Upf vs Pnr Upf

1. Power switches are added only in the PnR.

Power Domain vs voltage Domain --> Power domain is when the some regions exists which has a
switching supply.

Voltage domain - when there are multiple voltages operating.

FLAT VS HIERARCHICAL CONFIGURATION - uscpc dual supply hierarchical implementation.

########
# Power Domains

create_power_domain PD_TOP -include_scope

create_power_domain PD_ADV -elements { i_rgx_uscpc_av }

########
# Supply Ports & Supply Nets
# vcc always-on supply
####
create_supply_port vcc -domain PD_TOP
create_supply_net vcc -domain PD_TOP

#ADV
create_supply_net vcc -domain PD_ADV -reuse
connect_supply_net vcc -ports {vcc}

####
# svcc_adv switchable supply
create_supply_net svcc_adv -domain PD_ADV -resolve parallel

####
# vss always-on supply
####
create_supply_port vss -domain PD_TOP
create_supply_net vss -domain PD_TOP

#ADV
#create_supply_port vss -domain PD_ADV
create_supply_net vss -domain PD_ADV -reuse

connect_supply_net vss -ports {vss}

########
# Primary Power and Ground Supplies

set_domain_supply_net PD_TOP -primary_power_net vcc -primary_ground_net vss

set_domain_supply_net PD_ADV -primary_power_net svcc_adv -primary_ground_net vss

########
# Power Switches

create_power_switch psw_adv -domain PD_ADV \

-input_supply_port {in vcc} \
-output_supply_port {out svcc_adv} \
-control_port {ctrl0 iso_en_adv} \
-ack_port {ack0 i_rgx_uscpc_av/ack_adv} \
-on_state {on in { !ctrl0 }}
########
# Isolations

set_isolation iso_uscpc_adv -domain PD_ADV -isolation_power_net vcc -applies_to outputs -

clamp_value 0
set_isolation_control iso_uscpc_adv -domain PD_ADV -isolation_signal iso_en_adv -isolation_sense low
-location self

set_isolation iso_uscpc_adv_no -domain PD_ADV -no_isolation -elements {i_rgx_uscpc_av/ack_adv}

########
# Power State Table
# Voltages of port states must match those of operating conditions in libraries.
# Legend: Rv = regular voltage, Lv = low voltage, Wc = worst case opcond, Bc = best case opcond.

add_port_state vcc -state {Rv_Wc 0.900} -state {Rv_Bc 0.900} // This number signifies the Best
corner & the Worst corner voltages.

add_port_state vss -state {Gnd 0.0}

add_port_state psw_adv/out -state {Off off} -state {Rv_Wc 0.900} -state {Rv_Bc 0.900}

create_pst pst_uscpc -supplies {

vcc
vss
psw_adv/out
}

add_pst_state stt_all_on_wc -pst pst_uscpc -state { Rv_Wc Gnd Rv_Wc }

add_pst_state stt_all_off_wc -pst pst_uscpc -state { Rv_Wc Gnd Off }

add_pst_state stt_all_on_bc -pst pst_uscpc -state { Rv_Bc Gnd Rv_Bc }

add_pst_state stt_all_off_bc -pst pst_uscpc -state { Rv_Bc Gnd Off }

## --------------------------------------------------------------------------
## End of file
## --------------------------------------------------------------------------
Files to update the voltages in LP runs:
1. Set voltage --> apr & syn
2. Upf --> apr & syn
3. Mcmm.tcl --> only in apr

Case1: wc=0.9 V, BC= 1.1 V

update the set voltage to 0.9
upf & mccm with both the numbers
Case2: wc=bc=1.4V
Update the set voltage, upf, mcmm =1.4V
Defining proper corners are very important. Else big failure.