LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

component bcdadd is
port(X,Y:in std_logic_vector(3 downto 0);
CIN:in std_logic;
S:out std_logic_vector(3 downto 0);
COUT:out std_logic);
end component;

--Inputs
signal X,Y : std_logic_vector(3 downto 0);
signal CIN: std_logic :='0';

-- outputs
signal S : std_logic_vector(3 downto 0);
signal COUT: std_logic;

-- Clock period definitions

constant CLOCK_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: bcdadd PORT MAP (X,Y,CIN,S,COUT);

-- Clock process definitions

CLOCK_process :process
begin
X<="0000";
Y<="0000";
wait for 50 ps;
X<="0001";
Y<="0001";
wait for 50 ps;
X<="0010";
Y<="0010";
wait for 50 ps;
X<="0011";
Y<="0011";
wait for 50 ps;
X<="0100";
Y<="0000";
wait for 50 ps;
X<="0101";
Y<="0101";
wait for 50 ps;
X<="0110";
Y<="0110";
wait for 50 ps;
X<="0111";
Y<="0111";
wait for 50 ps;
X<="1000";
Y<="0010";
wait for 50 ps;
X<="0001";
Y<="1000";
wait for 50 ps;
X<="1010";
Y<="1100";
wait for 50 ps;
X<="1111";
X<="1100";
end process;

END;