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Journal of Power Electronics, to be published 1

A New Method for Elimination of Zero-sequence


Voltage in Dual Three-level Inverter Fed Open-end
Winding Induction Motors
Yi-Wen Geng, Chen-Xi Wei, Rui-Cheng Chen, Liang Wang, Jia-Bin Xu, and Shuang-Cheng Hao

School of Information and Electrical Engineering, China University of Mining and Technology, Xuzhou, China

Abstract
Due to the excessive zero-sequence voltage in dual three-level inverter fed open-end winding induction motor systems, zero-
sequence circumfluence which is harmful to switching devices and insulation is then formed when operating in a single DC
voltage source supplying mode. Traditionally, it is the mean value instead of instantaneous value of the zero-sequence voltage
that is eliminated, through adjusting the durations of the operating vectors. A new strategy is proposed for zero-sequence voltage
elimination, which utilizes unified voltage modulation and a decoupled SVPWM strategy to achieve two same-sized equivalent
vectors for an angle of 120°, generated by two inverters independently. Both simulation and experimental results have verified its
efficiency in the instantaneous value elimination of zero-sequence voltage.

Key words: dual three-level inverter-fed open-end winding induction motor, unified pulse width modulation, zero-sequence
voltage, space-vector decoupling PWM

series at either end of the open-end winding induction motor.


I. INTRODUCTION
However, with two extra isolated DC power supplies, the
Multilevel inverters have been popular in recent years due system cost will be excessively high and the implementation
to their advantages such as reduced output harmonics and of four-quadrant operation is difficult to achieve. Somasekhar
reduced voltage derivatives (dv/dt)[1,2], which are commonly V. T. et.al proposed two methods aiming at eliminating zero-
applied in medium and high voltage situations. In the case of sequence voltages. The first one used the unified voltage
an equal number of switching devices, compared with NPC modulation strategy [18] and the 180° decoupled PWM
(Neutral Point Clamped) [3,4], Flying Capacitor [5] as well strategy [19] to adjust the duration of the small vectors so that
as H-bridge cascaded [6] inverters, inverters cascaded at the mean zero-sequence voltage is zero during each switching
either end driving an open-end winding induction motors cycle. Then the zero-sequence voltage is dynamically
provide more voltage levels and less output harmonics [7]. eliminated [20]. The other way is the biasing inverter PWM
Therefore, this topology is gaining popularity in multilevel strategy [6] where the mean value of summation of three-
inverter application and electric driving fields. However, in phase voltage is zero. Nevertheless, these two methods are
the case of one single DC power supply operating, zero- without two isolated DC power supplies. However, it is only
sequence circumfluence resulting from zero-sequence voltage the average value of the zero-sequence voltage that is
generated by inverters cascaded at either end of open-winding eliminated while the instantaneous value is still high. The
induction motors still attracts the interest of many researchers, authors of [21] implemented the biasing inverter PWM
which mainly focus on dual two-level inverters and dual strategy and the 180° decoupled PWM strategy to eliminate
three-level inverters. To solve this problem, many zero- zero-sequence voltage as well as common-mode voltage.
sequence voltage elimination methods and modulation However, the instantaneous value is not completely
strategies have been proposed based on dual two-level and eliminated.
dual three-level inverters [8-16]. Thus, the unified voltage modulation strategy and the 120°
In [17] Srinivasan P et.al proposed an effective method decoupled PWM strategy are applied to resolve the reference
using two isolated DC power supplies to eliminate zero- voltage vector into two vectors generated by each inverter,
sequence circumfluence when these two two-level inverters with equal size but an angle of 120°, which can completely
eliminate instantaneous zero-sequence voltage. The zero-
Journal of Power Electronics, to be published

sequence circulating current, which increases the amplitude II. DUAL THREE-LEVEL INVERTER FED OPEN
of the current and brings a lot of damage to the insulation of WINDING INDUCTION MOTOR DRIVE
the winding, can also be eliminated by the method proposed The topology of a dual three-level inverter fed open-end
in this paper. Both simulation and experimental results have winding induction motor drive operated with a single power
verified the correctness and effectiveness of this method. supply is shown in Fig. 1. It should be noted from this figure

Fig. 1 Topology of dual three-level inverter-fed open-end winding induction-motor with a single DC power supply
120 020 120
020 220 220
S=3 K J I S=2 K J I

010 221 U ref1 010 221


021 021
210 210
L C B H L C B H
Ubase1 110
022 011 121 110 Uref1 S=1 022
011 121
111 222 100 Uref2 111 222 100
M D O A G M D O A
211
G
211 200
S=4 122 001 000 101 200 122 001 000 101
N E F S N E F S
201
012 212 201 012 212
112 112

P Q R S=6 P Q R
002 S=5 102 202 002 102 202

Udc/3 Udc/3

2(a) Space vector diagram of inverter-1 2(b) Space vector diagram of inverter-2

45
1 44 2 43 3 42
2
41
1

E D C

2 6 10 10 6 2
46 25 24 23 22 40

3
47 26
10
11
20
10
24
9
20
21
10 39 3
F B
Uref1
2 10 24 36 36 2 10 2
48 27 12 3 8 24 20 38
Uref2
Uref
O 30° 1
1 G 6 20 45 36 20 A 37
49 28 13 4 36 0 α 1 7 19 6

Uref2
10 24 10 2
2
50 29 14 5 36 36 6 18
24 36 60

20 20 10
3 51 H 30 10 15 16 24 17 35 L
59
3

6
2 52 31 6 32 10 33 10 34 58
2

J
I K
53 1 2 3 56 2 57 1
54 55

2Udc/3
2(c) Space vector diagram of dual inverter

Fig. 2 Principle of space voltage vector 120° decoupling


that inverter-1 and inverter-2 are in series at either end of the independent control of two inverters. Another advantage of
motor. Since both inverters are NPC three-level inverters, such a strategy is that when a fault happens to one of the two
each inverter has 27 switching states as shown in Figs. 2(a) inverters, the system can smoothly switch to single inverter
and 2(b), respectively. States ‘0’, ‘1’ and ‘2’ in Fig. 2 supply mode. Thus, the five-level inverter is converted to a
represent the output voltage level including ‘-Vdc/4’, ‘0’ and three-level inverter. As a result, the induction motor does not
‘Vdc/4’, from which 729 switching states are achieved in dual have to shut down and stability as well as reliability are
three-level inverters. The corresponding vector diagram is increased. It should be noted that the voltage is reduced by
shown in Fig. 2(c) where the uppercase figures are voltage 1/ 3 and the system is running under a full load at low speed,
vector number while the superscripts represent the number of when the system operates in a fault-tolerant situation.
redundant switching states. In the meantime, it is also noted U ref  U ref1  U ref2
that Fig. 2 is same as a vector diagram of a traditional five-
U ref (2)
level NPC inverter. The only difference is that there are more U ref1  U ref2 
3
redundant states in the former case.
Let uzs be the zero-sequence voltage of a dual three-level B. Zero-sequence Voltage Elimination
inverter system and their mathematical relation is [19]: Suppose that the voltage vector Uref is located in the
uzs  ucm1  ucm2 (1) position shown in Fig. 2(c). Uref1 and Uref2 are achieved by
ucm1 and ucm2 are the common-mode voltages of inverter-1 resolving Uref with an angle of 120°, as shown in Figs. 2(a)
and inverter-2 respectively, where ucm1=(uao+ubo+uco)/3 and and 2(b). From the NTV (Nearest Triangle Vector)
ucm2 =(ua'o+ub'o+uc'o)/3. theory[22], Uref1 is composed of three vectors including B H I,
When operating in a two isolated DC voltage source mode, while Uref2 is composed of D'L'M'. To achieve the operating
even the zero-sequence voltage uzs is excessively large. The time of each vector, two equivalent vectors need to be
DC sources of two inverters are isolated, among which the converted to basic vectors and two-level sub-vectors. Then
zero-sequence current is zero due to no circuit. This is a unified voltage modulation is applied to determine the
harmless mode and no extra solution is needed for the zero- operating vectors and to calculate the operating time of each
sequence voltage suppression. However, a closed circuit in vector, which is the same as the two-level SVPWM. To
the system generates excessive zero-sequence current when simplify this case, take the example of Uref1, which is shown
operating in a single DC voltage source. Thus, a large in Fig. 2(a).
circumfluence is formed. As a result, the phase-current Let:
harmonics then increase causing insulation damage [17]. In U ref1  urefa1 urefb1 urefc1  (3)
the latter case, the zero-sequence voltage should be
Where urefa1, urefb1, and urefc1 are components of Uref1 under the
suppressed for good operation of the system.
abc coordinate system.
Ⅲ. THE 120° DECOUPLED PWM STRATEGY The three-level vector diagram can be seen as a
combination of six two-level vector diagrams, where the six
A. Principles of the 120° Decoupled PWM Strategy large sectors are named S, and among each large sector there
Based on the principles of the decoupled PWM strategy is a two-level vector diagram. However, the overlapping part
[16], the voltage vector is resolved into two vectors generated of the two-level vector diagram is split evenly into the
by inverter-1 and inverter-2, respectively. As a result, the two neighboring parts.
inverters are controlled individually. As shown in Fig. 2, the The specific sector judgment rules are shown in TABLE 1.
reference voltage vector is Uref (|Uref|∠α) and two equivalent
vectors of the same size but with an angle of 60°, Uref1(|Uref1| TABLE I
∠(α+30°)) and U '
ref2 (| U '
ref2 |∠(α-30°)), are achieved using DISCRIMINATION RULES OF SECTOR
parallelogram law. More specificly, Uref1 is generated by
Sector(S) Criteria
inverter-1 while U ref2
'
is generated by inverter-2. Among
1 urefa1>0&urefb1<0&urefc1<0
these the vector Uref2 that is actually needed is in the opposite
2 urefa1>0&urefb1>0&urefc1<0
direction of U ref2
'
since the directions at either end of the
3 urefa1<0&urefb1>0&urefc1<0
motor are opposite. Thus, Uref1 and Uref2 actually have a phase
difference of 120° and the relations between Uref 、 Uref1 、 4 urefa1<0&urefb1>0&urefc1>0
Uref2 are shown in (2). 5 urefa1<0&urefb1<0&urefc1>0
It can be noted from the above analysis that the 120° 6 urefa1>0&urefb1<0&urefc1>0
decoupled PWM strategy is an effective way for the
Journal of Power Electronics, to be published

A basic vector Ubase is introduced to map the space vector Let Tmax1 = max(Tas1, Tbs1, Tcs1) and Tmin1 = min(Tas1, Tbs1,
to the two-level space-vector plane. The new basic vector is Tcs1). Teff1 is the effective time of inverter-1. From Fig. 3, it
the central vector of each sector as shown in Fig. 2(a). can be achieved that:
Take Uref1 in Fig. 2(a) as an example. Fig. 2(a) shows Teff1  Tmax1  Tmin1 (7)
the position of the equivalent reference voltage vector Uref1, U dc 4
'
where Ubase1=U110 among inverter-1. The adjusted vector U' urefa1

ref1 in the two-level case is: '


urefb1
'
U ref1 =U ref1  U base1
(4) '
urefc1
U base1  ubasea1 ubaseb1 ubasec1 
U dc 4 1
Thus: 1 0
1 0
' 0
urefa1  urefa1  ubasea1
Tcs1 Tmin1  Tbs1 Tas1  Tmax1 
'
urefb1  urefb1  ubaseb1 Teff1
'
urefc1  urefc1  ubasec1 (5) Toffset1
' ' '
urefa1  urefb1  urefc1
Teff1
'
U ref1 = urefa1
' '
urefb1 '
urefc1  Tgc1 Tgb1 Tga1
  A phase 1 1 1
1 1 0
Similarly, the corrected equivalent voltage vectors under B phase
1 0 0
C phase 0
the two-level space-vector plane among the other sectors can 0 0
be analysed, and the components of central vector of each T01 2 T21 T11 T01 2
sector in the abc coordinate system are presented in TABLE 2. Ts 2

Fig. 3 Functional principle of the unified PWM for Uref1


TABLE Ⅱ
THE THREE-PHASE VAULE OF BASE VECTORS IN DIFFERENT SECTOR The actual switching time can be achieved by adding a
shifted time Toffset1 to the imaginary switching time. In the
Sector(S) ubasea1 ubaseb1 ubasec1
SVPWM effective time Teff1 is put at the centre of a half cycle.
1 Udc/6 -Udc/12 -Udc/12 Thus, the shifted time Toffset1 is:
2 Udc/12 Udc/12 -Udc/6 T01  Ts 2  Teff1
(8)
Toffset1  T01 2  Tmin1
3 -Udc/12 Udc/6 -Udc/12
Therefore, the actual switching times are:
4 -Udc/6 Udc/12 Udc/12
Tgx1  Txs1  Toffset1 (9)
5 -Udc/12 -Udc/12 Udc/6
6 Udc/12 -Udc/6 Udc/12 Where x ∈ (a, b, c), Tga1, Tgb1 and Tgc1 are the actual
switching instants of the bridge.
The corrected vectors are two-level vectors. Therefore, the Only two switching states (0,1) are achieved through the
operating time corresponding to the switching states can be above strategy. Thus, an inverse-process to map the two-level
calculated by the unified voltage modulation strategy. vectors to three-level vectors is implemented to drive the
Coupled with modified u ' refa1, u ' refb1, u ' refc1 and the DC NPC three-level inverter. That is to say, the real switching
states can be obtained by adding a two-level vector to the
voltage Udc/2, the relation between the modulated signal and
equivalent central vector of each sector. The switching states
the output voltage is:
of the central vector in each sector are shown in TABLE 3.
'
2urefx1 Fig. 3 represents the gating pulses of the two level inverter,
Txs1   Ts (6)
U dc which is achieved by decomposing the reference vector into
the small vector of a two level inverter. Fig. 4 represents the
Where x∈(a, b, c), Tas1, Tbs1 and Tcs1 are the imaginary
actual states and it can be obtained by the following method.
switching times for the bridge.
As shown in Fig. (2), it can be find that the reference vector
To get the actual switching time of each bridge, define the
Uref1 is located in sector 2. The central vector in sector 2 is
effective time Teff, which refers to the durations of the
110. Therefore, the actual switching states of Uref1 are
different voltage level outputs of the inverter, as is illustrated
achieved by adding the state 110, to the original two-level
in Fig. 3.
states as presented in Fig. 3. For example, the actual state
Journal of Power Electronics, to be published

(220) is achieved by adding (110) to (110). 1 U U  U


ucm1  221    dc  dc  0   dc
TABLE Ⅲ 3  2 2  3
1 U U U  U
SWITCH STATUS OF THE INNER VECTOR OF DIFFERENT SECTOR ucm1  220     dc  dc  dc   dc
3  2 2 2  6
(10)
Sector(S) Switching states of the central vector 1 U U 
ucm1  210     dc  0  dc   0
1 100 3  2 2 
2 110 1  U dc  U dc
ucm1 110     0  0  
3 010 3  2  6

4 011 The switching states corresponding to Uref2 are 122-022-


012-011, which correspond to the common-mode voltage of
5 001
inverter-2:
6 101
1  U U  U
ucm2 122     0  dc  dc   dc
3  2 2  3
Teff1 1  U U U  U
ucm2  022      dc  dc  dc   dc
3  2 2 2  6
(11)
1  U U 
ucm2  012      dc  0  dc   0
3  2 2 
1  U  U
ucm2  011     dc  0  0    dc
3  2  6
Based on the mathematical relationship between Uref1 and
Uref2, shown in Figs. 2(a) and 2(b), it is known that:
Fig. 4 Instantaneous mapped three-phase reference signals for
T01  T02
Uref1, corresponding gating pulses and effective switching time
T11  T12 (12)
Similarly, Uref2 can be achieved through this method, T21  T22
where the relations between the switching states and the In the meantime, the operating vectors are achieved
effective time are shown in Fig. 5. through (1) and the zero-sequence voltage among the 4
Teff2 operating durations, T01/2(T02/2)、T21 (T22)、T11 (T12)、T01/2
Tga2 Tgc2 Tgb2 (T02/2), which are presented in (13).
T  u u
uzs  01   cm1 cm2
 2  3
U dc 3  U dc 3
 0
3
T02 2 T02 2 u u
uzs T21   cm1 cm2
T22 T12
3
U dc 6  U dc 6
Fig. 5 Instantaneous mapped three-phase reference signals for  0
3
Uref2, corresponding gating pulses and effective switching time (13)
u u
uzs T11   cm1 cm2
3
The switching states corresponding to Uref1 are 221-220-
00
210-110, based on the relations between the common-mode  0
3
voltage and the phase voltage of the inverter. The common-
T  u u
mode voltage of inverter-1 is achieved as (10). uzs  01   cm1 cm2
 2  3
U dc 6   U dc 6 
 0
3
From the above discussion, the zero-sequence voltage of an
open-end winding induction motor during each duration of a
half cycle is zero. Additionally, due to the symmetry of
seven-segment modulation, it can be concluded that during
one cycle the instantaneous value of the zero-sequence
Journal of Power Electronics, to be published

voltage is zero. Similarly, when the reference voltage Uref A simulation model in MATLAB/Simulink is established
arrives at other positions, as shown in Fig. 2(c), the to verify the effectiveness of the proposed zero-sequence
instantaneous value of the zero-sequence voltage during each elimination method. The induction motor is controlled by the
operating period among each cycle is zero. V/F, and the DC voltage of the inverter is set to 200V while
It can be concluded that with the implementation of the the carrier frequency is 5kHz. TABLE 4 presents the specific
120° decoupled PWM strategy, the instantaneous value of the parameters of the simulation.
zero-sequence voltage in an open-end winding induction Define the modulation ratio as ma=2Uref/Udc. When ma is
motor can be completely eliminated. Compared with the 180° 0.9, the phase current ia and voltage uaa waveforms, supplied
decoupled PWM strategy proposed in [20], the method by a single DC source, are shown in Fig. 6. When ma is 0.4
presented in this paper is essentially different since it is the and the system is operating under a single DC source, the
instantaneous value that is eliminated while [20] aimed at phase current ia and voltage uaa' waveforms are shown in Fig.
eliminating the mean value. Thus, when operating in the 7.
single DC source mode, the harmonics content is not affected
and good performance of the system is achieved by the TABLE Ⅳ
strategy proposed in this paper.
SIMULATION PARAMETERS SETTING FOR OPEN-END WINDING
C. Modulation Range Analysis INDUCTION-MOTOR

Strategies implemented to eliminate zero-sequence voltage


Parameters Value
will have certain effects on the linear modulation range.
Rated power of motor 5.5 kW
Let |OA|=2Udc/3, as shown in Fig. 2(c), then |OG|=|O'G'
Rated voltage of motor 380 V
|=Udc/3, which is shown in Fig. 2(a) and Fig. 2(b). The
modulation range of the system without the 120° decoupled Rated current of motor 12.1 A
PWM strategy corresponds to the regular hexagon ACEGIK, Rated frequency of motor 50 Hz
among which the maximum amplitude of the phase voltage Rated speed of motor 1460 rpm
generated by the dual three-level inverters is Udc / 3 . Stator resistance of motor 1.844Ω
When the 120° decoupled PWM strategy is applied to the
Stator inductance of motor 11.31 mH
system, each basic vector of the vector diagrams of the dual
three-level inverter is composed of two three-level vectors, Rotor resistance of motor 1.826 Ω
with a maximum amplitude of |OG|=Udc/3, with an angle of Rotor inductance of motor 11.31 mH
120°. Thus, the maximum amplitude of the basic vector is Mutual inductance between stator
104.83 mH
|OB|=Udc/ 3 . As can be seen from Fig. 2(c), the modulation and rotor
area is reduced to an inscribed regular hexagon BDFHJL, Moment of Inertia 0.021 kg.m2
among which the maximum amplitude of the modulated Number of pole-pairs 2
phase-voltage is Udc/2. As a result, the linear modulation
range of the system implementing zero-voltage elimination is 250 3
200
reduced by: 150 2
100 1
3  U dc 2
uaa'/V

U dc 50
 100%  13.4% (14)
ia/A

0 0
U dc 3 -50
-100 -1
As shown in (15), the DC voltage then needs to be -150 -2
-200
increased to obtain the same maximum output phase-voltage -250 -3
amplitude as the traditional five-level NPC inverter. 1.8 1.82 1.84 1.86 1.88 1.8 1.82 1.84 1.86 1.88
t/s t/s
2U dc 3  U dc Fig. 6 Simulation result of motor phase current and phase
 100%  15.5% (15)
U dc voltage for modulation indices of ma = 0.9
Originally the DC bus voltage of dual three-level inverters
is only half that of a five-level NPC inverter. Thus, even the
same maximum output phase-voltage as a five-level inverter
is achieved, and the dual three-level inverters’ DC voltage is
only 57.75% of that for a five-level NPC inverter.

Ⅳ. SIMULATION AND EXPERIMENT RESEARCH

A. Simulation Research
Journal of Power Electronics, to be published

the strategy in [20] mainly eliminates the mean value while


the high-frequency zero-sequence voltage still exists, with a
large amplitude. Therefore, it can concluded that there is an
uaa'/V

ia/A
essential difference between the strategies proposed in this
paper and in [20].

B. Experiment Research
A 5.5kW dual three-level inverter fed open-end winding
Fig. 7 Simulation result of motor phase current and phase induction motor experiment is implemented to verify the
voltage for modulation indices of ma = 0.4 effectiveness of the proposing strategy. Two NPC three-level
inverters are series connected at either end of the induction
To further demonstrate the effectiveness of the 120° PWM motor and an open-looped V/F is applied to the control motor.
strategy, simulation results of the zero-sequence voltage are The controller utilizes a TMS320F28335 to produce 12 PWM
shown when operating on a single DC source, with ma values pulses. Then a XC3S400 FPGA is used for the inversion of
of 0.9 and 0.4 respectively, the waveforms of which are the generated pulses. In total, 24 PWM pulses are generated
shown in Fig. 8. Then let the dual three-level inverters to drive the dual three-level inverters. The experiment
operate on high and low modulation depths and implement parameters are identical to those of the simulation.
the 180° decoupled space vector PWM strategy presented in Fig. 10 presents the experimental phase-current ia and
[20]. Thus, the simulation waveforms of the zero-sequence phase-voltage uaa' waveforms under a single DC source when
voltage are finally achieved in Fig. 9. ma is 0.9. Similarly, when ma is 0.4 the output phase-current
and phase-voltage waveforms are shown in Fig. 11. To
observe the zero-sequence voltage waveforms, experiments in
the single DC source mode are conducted with two different
ma values of 0.9 and 0.4, the waveforms of which are shown
uzs/V
uzs/V

in Figs. 12.
uaa'(100V/div) ia(2.5A/div)

Fig. 8 Simulation result of zero-sequence voltage in dual three-


level inverter-fed open-end winding motor for modulation
indices of ma = 0.9 and ma = 0.4 with a single DC power supply

Fig. 10 Experimental result of motor phase current and phase


voltage for modulation indices of ma = 0.9
Upper trace: motor phase current ia
uzs/V
uzs/V

Lower trace: motor phase voltage uaa'

Fig. 9 Simulation result of zero-sequence voltage in dual three-


level inverter-fed open-end winding motor for modulation
indices of ma = 0.9 and ma = 0.4 by using space voltage vector
t(10ms/div)
180° decoupling
Fig. 11 Experimental result of motor phase current and phase
voltage for modulation indices of ma = 0.4
From Figs. 6, 7 and 8, it can be seen that with the
Upper trace: motor phase current ia
implementation of the 120° decoupled PWM strategy,
Lower trace: motor phase voltage uaa'
operating on different modulation ratios, the output phase-
voltage is five-level during the high modulation range, and it
turns into three-level during the low modulation range. The
good thing is that in both cases the output current waveforms
are quite favorable and the instantaneous value of the zero-
sequence is zero. However, the results from Fig. 9 show that
Journal of Power Electronics, to be published

technique,” Journal of Power Electronics, Vol. 11, No. 1, pp.


21-27, January. 2011.

uaa'(50mV/div)
uaa'(50mV/div)

[3] J. Liu, X. G. Yi, Z. Zhang, et al. “Key technologies of main


circuit topology improvement and PWM security and stability of
high-voltage,” Transactions of China Electrotechnical Society,
Vol. 27, No. 8, pp. 28-34, August. 2012.
[4] H. B. Hu, W. X. Yao, Z. Y. Lu. “Realization of three- level
SVPWM using FPGA,” Transactions of China Electrotechnical
Fig. 12 Experimental result of zero-sequence voltage in dual Society,Vol. 25, No. 5, pp. 116-122, May. 2010.
three-level inverter-fed open-end winding motor for modulation [5] T. A. Maynard, H. Foch. “Multi-level conversion: high
indices of ma = 0.9 and ma = 0.4 with a single DC power supply voltage choppers and voltage source inverters,” in Proceedings
of Power Electronics Specialists Conference, pp. 397-403, 1992.
The results from the experiments verify that, under either [6] L. M. Tolbert, F. Z. Peng, T. G. Habetler. “Multilevel
mode, when operating in the high modulation area the output converters for large electric drives,” IEEE Transactions on
phase-voltage is five level, otherwise a three-level phase- Industrial Applications, Vol. 35, No. 1, pp. 36-44,
voltage is achieved. This is similar to the results of the January/February. 1999.
simulation, which show that the instantaneous value of the [7] P. Srinivasan. “A new SVPWM for dual-inverter fed three-
zero-sequence voltage is zero in either the high or low level induction motor drive,” in Proceedings of International
modulation area. Therefore, the strategy proposed in this Conference on Green Computing, Communication and
paper is effective for completely eliminating zero-sequence Conservation of Energy, pp. 514-518, 2013.
voltage. [8] V. T. Somasekhar, K. Gopakumar, A. Pittet, et al. “PWM
Ⅴ. CONCLUSIONS inverter switching strategy for a dual two-level inverter fed
open-end winding induction motor drive with a switched
A new and effective strategy was proposed for the zero-
neutral,” Electric Power Applications, Vol. 149, No. 2, pp. 152-
sequence elimination of dual three-level inverter fed open-
160, May. 2001.
end winding induction motors, which is achieved by
[9] V. T. Somasekhar, M. R. Baiju, K. Gopakumar. “Dual two
suppressing the instantaneous value. Simulation and
level inverter scheme for an open-end winding induction motor
experimental results confirm that:
drive with a single DC power supply and improved DC bus
(1) The 120° decoupled PWM strategy can achieve
utilization,” IEEE Transactions on Industrial Electronics, Vol.
independent control of two inverters and eliminate the
151, No. 2, pp. 230-238, March. 2004.
instantaneous value of the zero-sequence voltage, which
ensure the good performance of systems operating in the [10] V. T. Somasekhar, K. Gopakumar, E. G. Shivakumar, et al.
single DC source mode. “A space vector modulation scheme for a dual two level inverter
(2) Compared with the traditional modulation strategy, the fed an open-end winding induction motor drive for the
linear modulation range of a system implementing zero- elimination of zero sequence currents”. European Power
voltage elimination is obviously reduced by 13.4%. However, Electronics and Drives, Vol. 12, No. 2, pp. 26-36, December.
the DC bus voltage of dual three-level inverters is only half 2002.
that of a five-level NPC inverter. Thus, even if the same [11] M. R. Baiju, K. K. Mohapatra, K. Gopakumar. “A dual two-
maximum output phase-voltage as a five-level inverter is level inverter scheme with common mode voltage elimination
achieved, the dual three-level inverters’ DC voltage is only for an induction motor drive,” IEEE Transactions on Power
57.75% of that of a five-level NPC inverter. Electronics, Vol. 19, No. 3, pp. 794-805, May. 2004.
(3) To suppress the mean value of zero-sequence voltage, [12] V. Oleschuk, B. K. Bose, A. M. Stankovic. “Phase shift
the 180° decoupled space vector PWM strategy needs to based synchronous modulation of dual-inverters for an open-end
calculate and analyze the shifted time, which is more complex winding induction motor drive with elimination of zero sequence
than the strategy proposed in this paper. currents,” IEEE Power Electronics and Drive Systems, Vol. 6,
No. 3, pp. 325-330,May. 2005.
REFERENCES
[13] V. T. Somasekhar, S. Srinivas. “Switching algorithms for a
[1] A. Nabae, I. Takahash, H. Akagi. “A new neutral point
dual inverter fed open-end winding induction motor drive,” in
clamped PWM inverter,” IEEE Transactions on Industrial
Proceedings of IEEE India International Conference on Power
Applications, Vol. 17, No. 5, pp. 518-523, September. 1981.
Electronics, 2004.
[2] M. M. Renge, H. M. Suryawanshi, “Multilevel inverter to
[14] V. T. Somasekhar, S. Srinivas, K. Gopakumar. “A space
reduce common mode voltage in AC motor drives using SPWM
vector based PWM switching scheme for the reduction of
Journal of Power Electronics, to be published

common-mode voltages for a dual inverter fed open-end winding Chen-Xi Wei was born in Shandong
induction motor drive,” in Proceedings of Power Electronics Province, China, in 1993. She received her
B.S. degree in Electrical Engineering from
Specialists Conference, pp. 816-821, 2005.
the China University of Mining and
[15] S. Srinivas, V. T. Somasekhar. “A new alternate-inverter Technology, Xuzhou, China, in 2015. She is
PWM switching strategy for reducing the common-mode presently working towards her M.S. degree
voltages for a dual-inverter fed open-end winding induction in Electrical Engineering in School of
Information and Electrical Engineering,
motor drive,” in Proceedings of Power Electronics Specialists
China University of Mining and Technology. Her current
Conference, pp. 1460-1465, 2005. research interests include the advanced control of ac machines,
[16] V. T. Somasekhar, S. Srinivas, B. P. Reddy, et al. “PWM the modulation of multi-level inverters, and power electronics.
switching strategy for the dynamic balancing of zero-sequence
Rui-Cheng Chen was born in Jiangsu
current for a dual-inverter fed open-end winding induction motor
Province, China, in 1992. He received his
drive,” IEEE Electric on Power Applications, Vol. 1, No. 4, pp. B.S. degree in Electrical Engineering from
591-600, July. 2007. the China University of Mining and
[17] P. Srinivasan, B. L. Narasimharaju, N. V. Srikanth. “Two- Technology, Xuzhou, China, in 2015. He is
presently working towards his M.S. degree in
quadrant Clamping Inverter Scheme for Three-level Open-end
Electrical Engineering in School of
Winding Induction Motor Drive,” in Proceedings of IEEE Information and Electrical Engineering,
International Conference on Power Electronics, Drives and China University of Mining and Technology. His current
Energy Systems, pp. 1-4, 2014. research interests include the control of double three-
phase permanent magnet synchronous motors, the modulation of
[18] D. W. Chung, J. S. Kim, S. K. Sul, et al. “Unified voltage
multi-level inverters, and power electronics.
modulation technique for real-time three-phase power
conversion,” IEEE Transactions on Industrial Applications, Vol. Liang Wang was born in Jiangsu Province,
34, No. 2, pp. 374-380, March/April. 1998. China, in 1992. He received his B.S. degree
in Electrical Engineering from the China
[19] S. Srinivas, V. T. Somasekhar, et al. “Switching Algorithms
University of Mining and Technology,
for the Dual Inverter fed Open-end Winding Induction Motor Xuzhou, China, in 2014. He is presently
Drive for 3-level Voltage Space Phasor Generation,” Asian working towards his M.S. degree in
Power Electronics Journal, Vol. 1, No. 1, pp. 96-110, Journal, Electrical Engineering in School of
Information and Electrical Engineering,
2007.
China University of Mining and Technology. His current
[20] V. T. Somasekhar, S. Srinivas, K. K. Kumar, et al. “Effect research interests include power electronics and electrical drives.
of Zero-Vector Placement in a Dual-Inverter Fed Open-End
Winding Induction-Motor Drive With a Decoupled Space-Vector Jia-Bin Xu was born in Jiangsu Province,
China, in 1991. He received his B.S. degree
PWM Strategy,” IEEE Transactions on Industrial
in Electrical Engineering from the China
Electronics,Vol. 55, No. 6, pp. 2497-2505, June. 2008. University of Mining and Technology,
[21] D. Wu, L, C Su, X. J. Wu, et al. “An optimized control Xuzhou, China, in 2014. He is presently
method based on dual three-level inverters for open-end winding working towards his M.S. degree in
Electrical Engineering in the Department of
induction motor drives,” Journal of Power Electronics, Vol. 14,
Information and Electrical Engineering,
No. 2, pp. 315-323, March. 2014 China University of Mining and Technology. His current
research interests include the advanced control of ac machines,
the modulation of multi-level inverters, and power electronics.
Yi-Wen Geng was born in Jiangsu Province,
China, in 1977. He received his B.S. and Shuang-Cheng Hao was born in Jiangsu
M.S. degrees in Electrical Engineering from Province, China, in 1991. He received his
the China University of Mining and B.S. degree in Electrical Engineering from
Technology, Xuzhou, China, in 2000 and the China University of Mining and
2004, respectively. He has been with the Technology, Xuzhou, China, in 2014. He is
Department of Information and Electrical presently working toward his M.S. degree in
Engineering, China University of Mining Electrical Engineering in the Department of
and Technology, where he is presently working as an Associate Information and Electrical Engineering,
Professor. His current research interests include PV inverters, China University of Mining and Technology. His current
harmonic control and power electronics. research interests include power electronics and electrical drives.